CN115206989A - Three-dimensional memory and preparation method thereof - Google Patents
Three-dimensional memory and preparation method thereof Download PDFInfo
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The invention provides a three-dimensional memory and a preparation method thereof. The three-dimensional memory includes: a stacked first insulating layer, a source layer, and a stacked structure, the source layer being between the first insulating layer and the stacked structure, the stacked structure including conductive layers and interlayer insulating layers that are alternately stacked; a channel structure passing through the stacked structure; the connecting layer is positioned on one side, away from the stacking structure, of the first insulating layer and is provided with a protruding portion, and the protruding portion penetrates through the first insulating layer and is electrically connected with the source electrode layer; the first insulating layer is a single-layer insulating layer, and the first insulating layer is in contact with both the connection layer and the source electrode layer. The invention solves the technical problems of complex preparation process and higher cost of the three-dimensional memory.
Description
The application is a divisional application of Chinese patent application with the application date of 2021, 05 and 27, and the application number of 202110588023.9, and the application name of "three-dimensional memory and preparation method thereof".
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a three-dimensional memory and a preparation method thereof.
Background
The three-dimensional memory comprises a stacked insulating layer, a source layer and a stacked structure, wherein the source layer is positioned between the insulating layer and the stacked structure. However, the existing insulating layer is a composite multilayer, which not only makes the thickness and volume of the three-dimensional memory larger, but also makes the preparation process of the three-dimensional memory complex and increases the cost.
Disclosure of Invention
The invention aims to provide a three-dimensional memory and a preparation method thereof, and aims to solve the technical problems of complex preparation process and high cost of the three-dimensional memory.
The present invention provides a three-dimensional memory, comprising: a stacked first insulating layer, a source layer, and a stacked structure, the source layer being between the first insulating layer and the stacked structure, the stacked structure including conductive layers and interlayer insulating layers that are alternately stacked; a channel structure through the stacked structure; the connecting layer is positioned on one side, away from the stacking structure, of the first insulating layer and is provided with a protruding portion, and the protruding portion penetrates through the first insulating layer and is electrically connected with the source electrode layer; the first insulating layer is a single-layer insulating layer, and the first insulating layer is in contact with both the connection layer and the source layer.
Wherein the material of the first insulating layer comprises silicon oxide.
Wherein, still include: and the grounding structure is positioned on one side of the source layer, which is back to the stacking structure, penetrates through the first insulating layer, and two ends of the grounding structure are respectively and electrically connected with the source layer and the connecting layer.
Wherein the grounding structure and the source electrode layer are made of the same material.
Wherein, still include: a second insulating layer covering the stacked structure and the source layer; a first contact passing through the second insulating layer, the source layer, and the first insulating layer and electrically connected to the connection layer.
Wherein, still include: a second contact connected to the conductive layer of the stacked structure through the second insulating layer.
Wherein, still include: an interconnect structure on a side of the stack structure facing away from the source layer, the interconnect structure electrically connected to the channel structure.
Wherein, still include: and the peripheral circuit is positioned on one side of the interconnection structure, which is far away from the stacking structure, and is electrically connected with the interconnection structure.
The invention provides a preparation method of a three-dimensional memory, which comprises the following steps: providing a first insulating layer, a source layer and a stacked structure which are arranged in a stacked mode, wherein the source layer is located between the first insulating layer and the stacked structure, the first insulating layer is a single-layer insulating layer, and the stacked structure comprises conducting layers and interlayer insulating layers which are stacked alternately; forming a channel structure on the stacked structure through the stacked structure; forming a connecting layer on a side of the first insulating layer facing away from the stacked structure, wherein the connecting layer has a protruding portion electrically connected with the source layer through the second insulating layer; the first insulating layer is in contact with both the connection layer and the source layer.
Wherein, a functional layer is stacked on a side of the first insulating layer facing away from the source layer, and before the forming the connection layer, the preparation method further comprises: covering a second insulating layer on the source layer and the stacked structure; forming a first contact within the second insulating layer, the source layer, and the first insulating layer, wherein the first contact does not extend into the functional layer.
The functional layer is a substrate, and the first contact does not extend into the substrate.
The functional layer comprises a substrate and an etching stop layer, the substrate is formed on one side, away from the source electrode layer, of the first insulating layer, the etching stop layer is formed between the first insulating layer and the substrate, and the first contact does not extend into the etching stop layer.
The functional layer further comprises an oxide layer, and the oxide layer is stacked between the etching stop layer and the substrate.
Wherein "the first contact does not extend into the functional layer" includes: the first contact and the first insulating layer face the surface of the functional layer in a flush manner, or the first contact and the first insulating layer face the surface of the functional layer in a preset distance.
Wherein the preset distance is between 30nm and 40 nm.
Wherein forming a first contact within the second insulating layer, the source layer, and the first insulating layer comprises: selectively etching the second insulating layer, the source electrode layer and the first insulating layer to form a contact hole, wherein the contact hole does not extend into the functional layer; forming a contact material within the contact hole to form the first contact.
Wherein after forming the first contact, the method of making further comprises: removing a part of the substrate from the surface of the substrate facing away from the first insulating layer to form a reference substrate, wherein the thickness of the reference substrate is smaller than that of the substrate; removing the reference substrate.
Wherein "removing the reference substrate" comprises: when the reference substrate is removed, removing part of the first contact so that the first contact does not protrude from the surface of the first insulating layer far away from the source electrode layer.
Wherein "removing the reference substrate" comprises: and removing the reference substrate by adopting a chemical mechanical polishing method.
An initial grounding structure is arranged on one side, back to the stacking structure, of the source layer, and the initial grounding structure penetrates through the first insulating layer and then extends into the functional layer; "removing the reference substrate" includes: when the reference substrate is removed, removing a part of the initial grounding structure to form a grounding structure, wherein the grounding structure is flush with the first insulating layer.
Wherein after removing the substrate, the preparation method further comprises: forming a via on the first insulating layer, the via exposing the source layer; the "forming a connection layer on a side of the first insulating layer facing away from the stacked structure" includes: and forming the connecting layer, and forming a convex part in the via hole, wherein the convex part is connected with the source layer.
Wherein forming a first contact within the second insulating layer, the source layer, and the first insulating layer comprises: forming a second contact within the second insulating layer while forming the first contact, wherein the second contact is connected to a conductive layer of the stacked structure.
The first contact and the second contact are made of tungsten, and the connecting layer is made of aluminum; the substrate is made of polycrystalline silicon; the etching stop layer is made of silicon nitride; the first insulating layer and the second insulating layer are made of silicon dioxide.
Wherein, before removing the substrate, the preparation method further comprises: and forming an interconnection structure on the side of the stacking structure, which faces away from the source layer, wherein the interconnection structure is electrically connected with the channel structure.
Wherein after forming the interconnect structure, the method further comprises: and forming a peripheral circuit on the side of the interconnection structure, which faces away from the stacking structure, wherein the peripheral circuit is electrically connected with the interconnection structure.
In summary, the first insulating layer is arranged to be the single-layer insulating layer, so that the thickness of the three-dimensional memory is greatly reduced, the size of the three-dimensional memory is small, the preparation process flow of the three-dimensional memory is reduced, and the cost is reduced. The application solves the technical problems that the existing insulating layers are composite multilayer, so that the thickness and the size of the three-dimensional memory are large, the preparation process of the three-dimensional memory is complex, and the cost is increased.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present invention.
Fig. 2 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of an initial structure of another three-dimensional memory.
Fig. 4 is a schematic structural diagram of thinning the substrate in fig. 3 to obtain a reference substrate.
Fig. 5 is a schematic diagram of a structure in which the reference substrate in fig. 4 is removed.
Fig. 6 is a schematic diagram of a structure of forming a via hole on the etch stop layer and the oxide layer in fig. 5.
Fig. 7 is a schematic diagram of a structure in which a connection layer is formed on the oxide layer in fig. 6.
Fig. 8 is a schematic diagram of an initial structure of the three-dimensional memory of fig. 1.
Fig. 9 is a schematic structural diagram of thinning the substrate in fig. 8 to obtain a reference substrate.
Fig. 10 is a schematic view of a structure in which the reference substrate in fig. 9 is removed.
Fig. 11 is a schematic structural view of via holes formed on the first insulating layer in fig. 10.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
Referring to fig. 1, fig. 1 is a three-dimensional memory according to the present invention. According to the three-dimensional memory, the first insulating layer 202 is a single-layer insulating layer, so that the thickness of the three-dimensional memory is greatly reduced, the size of the three-dimensional memory is small, the preparation process flow of the three-dimensional memory is reduced, and the cost is reduced.
The three-dimensional memory includes:
a stacked first insulating layer 202, a source layer 101, and a stacked structure, the source layer 101 being between the first insulating layer 202 and the stacked structure, the stacked structure including conductive layers 103 and interlayer insulating layers which are alternately stacked; the interlayer insulating layer may be made of silicon oxide.
A channel structure 107 through the stacked structure; the channel structure 107 includes a charge storage layer including a blocking insulating layer, a charge trapping layer, and a tunneling insulating layer along sidewalls of the channel hole toward the center of the hole, and a channel layer. An exemplary material of the blocking insulating layer and the tunneling insulating layer is silicon oxide, an exemplary material of the charge trapping layer is silicon nitride, and the charge storage layer forms a stacked structure of silicon oxide-silicon nitride-silicon oxide (ONO). An exemplary material of the channel layer is silicon (Si). Other materials may be selected for the blocking insulating layer, the charge trapping layer and the tunneling insulating layer, and are not limited herein.
A connection layer 270 located on a side of the first insulating layer 202 facing away from the stacked structure and having a protrusion 280, wherein the protrusion 280 penetrates through the first insulating layer 202 and is electrically connected to the source layer 101; the first insulating layer 202 is a single-layer insulating layer, and the first insulating layer 202 is in contact with both the connection layer 270 and the source layer 101. The connecting layer 270 is made of aluminum.
In the application, the first insulating layer 202 is a single-layer insulating layer, so that the thickness of the three-dimensional memory is greatly reduced, the size of the three-dimensional memory is small, the preparation process flow of the three-dimensional memory is reduced, and the cost is reduced. The application solves the technical problems that the existing insulating layer is a composite multilayer, so that the thickness and the size of the three-dimensional memory are large, the preparation process of the three-dimensional memory is complex, and the cost is increased.
In a specific embodiment, the material of the first insulating layer 202 includes silicon oxide.
In a specific embodiment, the three-dimensional memory further comprises: the ground structure 240 is located on a side of the source layer 101 opposite to the stacked structure, the ground structure 240 penetrates through the first insulating layer 202, and two ends of the ground structure are electrically connected to the source layer 101 and the connecting layer 270, respectively.
In the present application, the grounding structure 240 is electrically connected to the source layer 101 and the connecting layer 270, respectively, so that the charges on the source layer 101 can be led out to the outside through the connecting layer 270.
In one embodiment, the ground structure 240 and the source layer 101 are the same material. In the present application, by setting the grounding structure 240 to be made of the same material as the source layer 101, the charges on the source layer 101 can be quickly derived, and the charges are prevented from being punctured into the three-dimensional memory. Alternatively, the ground structure 240 may be a co-molded structure with the source layer 101. The grounding structure 240 and the source layer 101 may be made of polysilicon.
In a specific embodiment, the three-dimensional memory further comprises:
a second insulating layer 102 covering the stack structure and the source layer 101;
the first contact 40 penetrates the second insulating layer 102, the source layer 101, and the first insulating layer 202, and is electrically connected to the connection layer 270. It is understood that the first contact 40 is flush-connected to the connection layer 270, or the first contact 40 is spaced apart from the connection layer 270 by a predetermined distance, and a portion of the connection layer 270 extends within the contact hole 30 in which the first contact 40 is located to connect to the first contact 40. Optionally, the material of the second insulating layer 102 is silicon oxide. The material of the first contact 40 may be tungsten (W).
In the present application, the first contact 40 is disposed to connect with the connection layer 270, so that the connection layer 270 can be connected with other structures of the three-dimensional memory through the first contact 40.
In a specific embodiment, the three-dimensional memory further comprises:
and a second contact 104 connected to the conductive layer 103 of the stacked structure through the second insulating layer 102. It is to be understood that the conductive layer 103 is formed in a stepped shape, the second contact 104 is plural, and the plural second contacts 104 are connected to the stepped conductive layer 103. The material of the second contact 104 may be tungsten (W).
In this application, by providing the second contact 104 to be connected to the conductive layer 103, the conductive layer 103 can be connected to another structure of the three-dimensional memory through the second contact 104.
In a specific embodiment, the three-dimensional memory further comprises:
and an interconnect structure 290 located on a side of the stacked structure facing away from the source layer 101, the interconnect structure 290 being electrically connected to the channel structure 107. It is understood that an interconnect structure 290 is also formed within second insulating layer 102. Interconnect structure 290 includes pads 70, conductive vias 80, and routing 50 connected in series. The pad 70 is connected to the channel structure 107, and the wiring 50 is electrically connected to other structures of the three-dimensional memory, such as peripheral circuits to be described later.
In the present application, by providing the interconnect structure 290, the channel structure 107 is electrically connected to other structures of the three-dimensional memory, such as peripheral circuits below.
In a specific embodiment, the three-dimensional memory further comprises:
and peripheral circuitry 60 located on a side of interconnect structure 290 facing away from the stacked structure and electrically connected to interconnect structure 290. Peripheral circuitry 60 provides power to channel structure 107 through interconnect structure 290 in this application.
Referring to fig. 2, in addition to the three-dimensional memory, an embodiment of the invention further provides a method for manufacturing the three-dimensional memory. The three-dimensional memory and the preparation method of the three-dimensional memory in the embodiments of the present invention can achieve the advantages of the present invention, and the two can be used together or separately, which is not particularly limited by the present invention. In one specific embodiment, the three-dimensional memory is fabricated as follows.
Referring to fig. 2, fig. 2 is a method for fabricating a three-dimensional memory according to the present invention. According to the three-dimensional memory, the first insulating layer 202 is a single-layer insulating layer, so that the thickness of the three-dimensional memory is greatly reduced, the size of the three-dimensional memory is small, the preparation process flow of the three-dimensional memory is reduced, and the cost is reduced. The application solves the technical problems that the existing insulating layer is a composite multilayer, so that the thickness and the size of the three-dimensional memory are large, the preparation process of the three-dimensional memory is complex, and the cost is increased.
A method of fabricating a three-dimensional memory is shown in fig. 2. As shown in fig. 2, the method can be broadly summarized as the following process: a first insulating layer 202, a source layer 101 and a stack structure arranged in a stacked manner are provided (S1), a channel structure 107 is formed through the stack structure on the stack structure (S2), and a connection layer 270 is formed on a side of the first insulating layer 202 facing away from the stack structure (S3). As will be described separately below.
Referring to fig. 2, the method first performs operations S1-S3:
s1, providing a first insulating layer 202, a source layer 101 and a stacked structure which are stacked, wherein the source layer 101 is located between the first insulating layer 202 and the stacked structure, the first insulating layer 202 is a single-layer insulating layer, and the stacked structure comprises a conducting layer 103 and an interlayer insulating layer which are stacked alternately; the first insulating layer 202 and the interlayer insulating layer may be made of silicon oxide.
S2, forming a channel structure 107 penetrating through the stacked structure on the stacked structure; the channel structure 107 includes a charge storage layer including a blocking insulating layer, a charge trapping layer, and a tunneling insulating layer along sidewalls of the channel hole toward a center of the hole, and a channel layer. An exemplary material of the blocking insulating layer and the tunneling insulating layer is silicon oxide, an exemplary material of the charge trap layer is silicon nitride, and the charge storage layer forms a stacked structure of silicon oxide-silicon nitride-silicon oxide (ONO). An exemplary material of the channel layer is silicon (Si). Other materials may be selected for the blocking insulating layer, the charge trapping layer and the tunneling insulating layer, which are not limited herein.
S3, forming a connection layer 270 on a side of the first insulating layer 202 away from the stacked structure, wherein the connection layer 270 has a protrusion 280, and the protrusion 280 penetrates through the second insulating layer 102 to be electrically connected to the source layer 101; the first insulating layer 202 contacts both the connection layer 270 and the source layer 101. The connecting layer 270 may be aluminum.
In the application, the first insulating layer 202 is a single-layer insulating layer, so that the thickness of the three-dimensional memory is greatly reduced, the size of the three-dimensional memory is small, the preparation process flow of the three-dimensional memory is reduced, and the cost is reduced. The application solves the technical problems that the existing insulating layer is a composite multilayer, so that the thickness and the size of the three-dimensional memory are large, the preparation process of the three-dimensional memory is complex, and the cost is increased.
In a specific embodiment, a functional layer is stacked on a side of the first insulating layer 202 facing away from the source layer 101, and before forming the connection layer 270, the method further includes:
covering a second insulating layer 102 on the source layer 101 and the stacked structure;
a first contact 40 is formed within the second insulating layer 102, the source layer 101, and the first insulating layer 202, wherein the first contact 40 does not extend into the functional layer. It will be appreciated that the end of the first contact 40 may be located between two opposing surfaces of the first insulating layer 202, or the first contact 40 may be flush with the surface of the first insulating layer 202 remote from the source layer 101. The material of the first contact 40 is typically tungsten (W). The material of the first insulating layer 202 is typically silicon dioxide (SiO) 2 )。
In the application, by arranging the first contact 40 not to extend into the functional layer, after the functional layer is removed, when a subsequent structure is formed on the first insulating layer 202, the subsequent structure is smooth, the structure of the three-dimensional memory is smooth, and the yield of the three-dimensional memory is good.
In one embodiment, "forming the first contact 40 within the second insulating layer 102, the source layer 101, and the first insulating layer 202" includes:
selectively etching the second insulating layer 102, the source layer 101 and the first insulating layer 202 to form a contact hole 30, wherein the contact hole 30 does not extend into the functional layer;
a contact material is formed within the contact hole 30 to form a first contact 40.
It can be understood that the material properties of the first insulating layer 202 and the functional layer are different, so that the contact hole 30 stops extending after penetrating through the first insulating layer 202, and the functional layer is not etched. The etching process of the second insulating layer 102, the source layer 101, and the first insulating layer 202 may be an anisotropic dry etching process, and a selective etchant, such as an etching gas, for example, SF6, NF3, COS, cl2, HBr, fluorocarbon (CF 4, CHF 3) with a small fluorocarbon content, or the like, may be used; of course, the present application may also use a high carbon/fluorine ratio gas (C/F ratio) and/or a hydrocarbon gas (CHx) to etch the functional layer, the first insulating layer 202 and the second insulating layer 102 to avoid the etching gas from etching the functional layer. The etching ratio of the first insulating layer 202 to the functional layer may be greater than 5, for example, the etching ratio may be 6, 10, 15, 100, 200, 1000, and the like, and the present application does not specifically limit the etching ratio of the first insulating layer 202 to the functional layer, as long as the etching gas does not etch or substantially does not etch the functional layer after etching the first insulating layer 202. In the present application, since the contact hole 30 does not extend into the functional layer, the first contact 40 does not extend into the functional layer, that is, the first contact 40 is not present in the functional layer. After the functional layer is removed, the first contact 40 does not protrude out of the first insulating layer, and when a subsequent structure is formed on the first insulating layer 202, the subsequent structure is also flat, the structure of the three-dimensional memory is flat, and the yield of the three-dimensional memory is good.
In a particular embodiment, the "first contact 40 does not extend into the functional layer" includes:
the first contact 40 is flush with the surface of the first insulating layer 202 facing the functional layer, or the first contact 40 is at a predetermined distance from the surface of the first insulating layer 202 facing the functional layer.
It can be understood that when the first contact 40 is flush with the surface of the first insulating layer 202 facing the functional layer, the first contact 40 does not protrude from the first insulating layer 202, which facilitates connection with the first contact 40 in a subsequent structure stacked on the first insulating layer 202. When the first contact 40 and the surface of the first insulating layer 202 facing the functional layer have a predetermined distance therebetween, the predetermined distance between the first contact 40 and the surface of the first insulating layer 202 away from the source layer 101 is a reserved space of the contact hole 30, and the reserved space can be filled with the subsequent structure. By the method, the first contact 40 does not protrude out of the first insulating layer 202, the reserved space is arranged, the reserved space can be filled by a subsequent structure as required, the subsequent structure can be in good contact with the first contact 40, and the structure of the three-dimensional memory is more flexible.
In a specific embodiment, the predetermined distance is between 30nm and 40 nm. The headspace between 30nm and 40nm may allow the subsequent structure to better fill the headspace, and the subsequent structure may make good contact with the first contact 40.
Referring to fig. 3, in one embodiment, the functional layers include a substrate 90 and an etch stop layer 210, the substrate 90 is formed on a side of the first insulating layer 202 away from the source layer 101, the etch stop layer 210 is formed between the first insulating layer 202 and the substrate 90, and the first contact 40 does not extend into the etch stop layer 210.
It can be understood that the material of the etching stop layer 210 is different from the material of the first insulating layer 202, when the contact hole 30 accommodating the first contact 40 is formed by etching, the first insulating layer 202 is selectively etched without etching the etching stop layer 210, after the first contact 40 is formed in the contact hole 30, the first contact 40 does not extend into the etching stop layer 210, and after the etching stop layer 210 is subsequently removed, the first contact 40 does not protrude out of the first insulating layer 202, and the first contact 40 does not need to be separately ground, so that the preparation flow of the three-dimensional memory is reduced, the process is saved, and the cost is saved. Optionally, the material of the etch stop layer 210 is silicon nitride (SiN).
In a specific embodiment, the functional layer further includes an oxide layer 220, and the oxide layer 220 is stacked between the etch stop layer 210 and the substrate 90. It is understood that oxide layer 220 is used to planarize etch stop layer 210.
Referring to fig. 4, after the first contact 40 is formed, the manufacturing method further includes:
removing a portion of the substrate 90 from a surface of the substrate 90 facing away from the first insulating layer 202 to form a reference substrate 110, wherein a thickness of the reference substrate 110 is less than a thickness of the substrate 90;
referring to fig. 5, the reference substrate 110 is removed.
In this embodiment, after removing the substrate 90, the preparation method further includes:
referring to fig. 6, a via 20b is formed on the first insulating layer 202, the via 20b exposing the source layer 101;
in this embodiment, the "forming the connection layer 270 on the side of the first insulating layer 202 facing away from the stacked structure" includes:
referring to fig. 7, the forming of the connection layer 270 on the side of the first insulating layer 202 away from the stacked structure includes:
after the connection layer 270 is formed, a protrusion 280 is formed in the via hole 20b, and the protrusion 280 is connected to the source layer 101. It is understood that the number of the via holes 20b may be plural.
Referring to fig. 8, in one embodiment, the functional layer is a substrate 90 and the first contact 40 does not extend into the substrate 90. The substrate 90 may be polysilicon.
It can be understood that the material of the substrate 90 is different from the material of the first insulating layer 202, when the contact hole 30 accommodating the first contact 40 is formed by etching, the first insulating layer 202 is selectively etched without etching the substrate 90, after the first contact 40 is formed in the contact hole 30, the first contact 40 does not extend into the substrate 90, and after the substrate 90 is subsequently removed, the first contact 40 does not protrude out of the first insulating layer 202, and the first contact 40 does not need to be separately ground, so that the preparation process of the three-dimensional memory is reduced, the process is saved, and the cost is saved. Optionally, the substrate 90 is made of polysilicon.
In this embodiment, after forming the first contact 40, the preparation method further includes:
referring to fig. 9, a portion of the substrate 90 is removed from a surface of the substrate 90 away from the first insulating layer 202 to form a reference substrate 110, wherein a thickness of the reference substrate 110 is smaller than a thickness of the substrate 90;
referring to fig. 10, the reference substrate 110 is removed. Alternatively, "removing the reference substrate 110" includes: the reference substrate 110 is removed by Chemical Mechanical Polishing (CMP).
It is understood that the three-dimensional memory is formed by the following method: a layer structure of the three-dimensional memory is formed on the substrate 90, and then the substrate 90 is removed. In the present application, a portion of the substrate 90 is first removed from a surface of the substrate 90 away from the first insulating layer 202, that is, the substrate 90 is thinned from a surface of the substrate 90 away from the first insulating layer 202, and a method for thinning the substrate 90 may be chemical mechanical polishing. Because the substrate 90 is thicker, the process of removing part of the substrate 90 can be fast grinding and rough grinding, that is, the process from the substrate 90 to the reference substrate 110 is fast grinding, so as to accelerate the thinning speed of the substrate 90 and save time; after the reference substrate 110 is formed, the method for removing the reference substrate 110 may also be chemical mechanical polishing, and the process for removing the reference substrate 110 may be slow polishing and fine polishing, so that the reference substrate 110 may be polished to a desired thickness and the first insulating layer 202 is not polished. In this embodiment, the reference substrate 110 is completely polished, and the first insulating layer 202 is not polished. The entire substrate 90 may be removed by chemical mechanical polishing.
In a particular embodiment, "removing the reference substrate 110" includes:
when the reference substrate 110 is removed, a portion of the first contact 40 is removed, so that the first contact 40 of the removed portion does not protrude beyond the surface of the first insulating layer 202 away from the source layer 101.
It is understood that chemical mechanical polishing is to add chemical reagent to react with the member to be polished while the member to be polished is being polished mechanically. In the present application, the chemical reagent may react with the first contact 40, and thus, when the substrate 90 is chemically and mechanically polished, a part of the structure of the first contact 40 is removed by reaction, for example, a part of the structure of the first contact 40 in the contact hole 30 is removed by reaction, so that the first contact 40 does not protrude from the surface of the first insulating layer 202 away from the substrate 90. When the subsequent structure is formed on the first insulating layer 202, the subsequent structure can be formed on the first insulating layer 202 in a flat manner, the structure of the three-dimensional memory is flat, and the yield of the three-dimensional memory is high. This also applies to the first contact 40 protruding into the substrate 90, and the cmp process can also remove the structure of the first contact 40 protruding into the substrate 90.
Referring to fig. 8-9, in one embodiment, an initial ground structure 230 is disposed on a side of the source layer 101 opposite to the stacked structure, and the initial ground structure 230 penetrates through the first insulating layer 202 and then extends into the functional layer;
referring to fig. 10, "removing the reference substrate 110" includes: when the reference substrate 110 is removed, a portion of the initial ground structure 230 is removed to form a ground structure 240, and the ground structure 240 is flush with the first insulating layer 202.
It is understood that when the substrate 90 is polished by chemical mechanical polishing, the initial ground structure 230 in the substrate 90 is polished at the same time, so that the initial ground structure 230 forms the ground structure 240. After the substrate 90 is removed, when the connection layer 270 is formed on the first insulating layer 202, the connection layer 270 is connected with the ground structure 240. Also, since the ground structure 240 is flush with the first insulating layer 202, the connection layer 270 may be formed flat on the first insulating layer 202.
In a specific embodiment, after removing the substrate 90, the method further comprises:
referring to fig. 11, a via 20b is formed on the first insulating layer 202, and the via 20b exposes the source layer 101;
"forming the connection layer 270 on the side of the first insulating layer 202 facing away from the stacked structure" includes:
after the connection layer 270 is formed, a protrusion 280 is formed in the via hole 20b, and the protrusion 280 is connected to the source layer 101. It is understood that the number of the via holes 20b may be plural.
In the present application, the via hole 20b is used to expose the source layer 101, the protrusion 280 for leading out the source layer 101 is formed in the via hole 20b, and when the connection layer 270 is formed on the first insulating layer 202, the protrusion 280 may be flatly accommodated in the via hole 20 b.
In one embodiment, "forming the first contact 40 within the second insulating layer 102, the source layer 101, and the first insulating layer 202" includes:
when forming the first contact 40, a second contact 104 is formed within the second insulating layer 102, wherein the second contact 104 is connected with the conductive layer 103 of the stacked structure. Optionally, the material of the first contact 40 and the second contact 104 is tungsten.
In this application, the second contact 104 is connected to the conductive layer 103, so that the connection layer 270 can be connected to other structures of the three-dimensional memory through the second contact 104.
In a specific embodiment, prior to removing the substrate 90, the method of making further comprises:
an interconnect structure 290 is formed on a side of the stack structure facing away from the source layer 101, wherein the interconnect structure 290 is electrically connected to the channel structure 107. It will be appreciated that the interconnect structure 290 includes the pads 70, the conductive vias 80, and the wiring 50 connected in series. The pad 70 is connected to the channel structure 107, and the wiring 50 is electrically connected to other structures of the three-dimensional memory, such as peripheral circuits to be described later.
In the present application, by providing the interconnect structure 290, the channel structure 107 is electrically connected to other structures of the three-dimensional memory.
In a specific embodiment, after forming the interconnect structure 290, the method further comprises:
In the present application, peripheral circuitry 60 provides power to channel structure 107 through interconnect structure 290.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (24)
1. A three-dimensional memory, comprising:
a first insulating layer, a source layer and a stacked structure, the source layer being between the first insulating layer and the stacked structure, the stacked structure including conductive layers and interlayer insulating layers which are alternately stacked;
a channel structure passing through the stacked structure;
the connecting layer is positioned on one side, away from the stacking structure, of the first insulating layer and is provided with a protruding portion, and the protruding portion penetrates through the first insulating layer to be electrically connected with the source electrode layer;
the first insulating layer is a single-layer insulating layer, and the first insulating layer is in contact with the connecting layer and the source electrode layer;
and a ground structure electrically connected to the source layer and the connection layer.
2. The three-dimensional memory according to claim 1, wherein a material of the first insulating layer comprises silicon oxide.
3. The three-dimensional memory according to claim 1, wherein the ground structure is located on a side of the source layer facing away from the stacked structure, the ground structure penetrates through the first insulating layer, and two ends of the ground structure are electrically connected to the source layer and the connecting layer, respectively.
4. The three-dimensional memory of claim 1, wherein the ground structure and the source layer are the same material.
5. The three-dimensional memory according to claim 1, further comprising:
a second insulating layer covering the stack structure and the source layer;
a first contact passing through the second insulating layer, the source layer, and the first insulating layer and electrically connected to the connection layer.
6. The three-dimensional memory according to claim 5, further comprising:
a second contact connected to the conductive layer of the stacked structure through the second insulating layer.
7. The three-dimensional memory according to claim 1, further comprising:
and the interconnection structure is positioned on one side of the stacking structure, which is far away from the source electrode layer, and is electrically connected with the channel structure.
8. The three-dimensional memory according to claim 7, further comprising:
and the peripheral circuit is positioned on one side of the interconnection structure, which is far away from the stacking structure, and is electrically connected with the interconnection structure.
9. A method for preparing a three-dimensional memory is characterized by comprising the following steps:
providing a first insulating layer, a source electrode layer and a stacked structure which are arranged in a stacked mode, wherein the source electrode layer is located between the first insulating layer and the stacked structure, the first insulating layer is a single-layer insulating layer, and the stacked structure comprises a conducting layer and an interlayer insulating layer which are stacked alternately;
forming a channel structure on the stacked structure through the stacked structure;
forming a grounding structure on one side of the source layer, which is far away from the stacking structure, wherein the grounding structure is electrically connected with the source layer;
forming a connection layer on a side of the first insulating layer facing away from the stacked structure, wherein the connection layer is electrically connected to the ground structure, and the connection layer has a protruding portion electrically connected to the source layer through the first insulating layer; the first insulating layer is in contact with both the connection layer and the source layer.
10. The method of manufacturing of claim 9, wherein prior to forming the tie layer, the method further comprises:
forming a functional layer on one side of the first insulating layer, which is far away from the source electrode layer;
forming an initial grounding structure on one side of the source layer, which is far away from the stacking structure, wherein the initial grounding structure penetrates through the first insulating layer and then extends into the functional layer;
covering a second insulating layer on the source layer and the stacked structure;
forming a first contact within the second insulating layer, the source layer, and the first insulating layer, wherein the first contact does not extend into the functional layer.
11. The method of manufacturing of claim 10, wherein the functional layer is a substrate and the first contact does not extend into the substrate.
12. The method according to claim 10, wherein the functional layer includes a substrate and an etch stop layer, the substrate is formed on a side of the first insulating layer facing away from the source layer, the etch stop layer is formed between the first insulating layer and the substrate, and the first contact does not extend into the etch stop layer.
13. The production method according to claim 12, wherein the functional layer further includes an oxide layer laminated between the etch stop layer and the substrate.
14. The method of claim 10, wherein the "the first contact does not extend into the functional layer" comprises:
the first contact and the surface of the first insulating layer facing the functional layer are flush, or a preset distance is reserved between the first contact and the surface of the first insulating layer facing the functional layer.
15. The method of claim 14, wherein the predetermined distance is between 30nm and 40 nm.
16. The method of claim 10, wherein forming a first contact within the second insulating layer, the source layer, and the first insulating layer comprises:
selectively etching the second insulating layer, the source electrode layer and the first insulating layer to form a contact hole, wherein the contact hole does not extend into the functional layer;
forming a contact material within the contact hole to form the first contact.
17. The method of manufacturing of claim 11, wherein after forming the first contact, the method of manufacturing further comprises:
removing a part of the substrate from the surface of the substrate facing away from the first insulating layer to form a reference substrate, wherein the thickness of the reference substrate is smaller than that of the substrate;
and removing the reference substrate.
18. The method of manufacturing of claim 17, wherein "removing the reference substrate" comprises:
when the reference substrate is removed, part of the first contact is removed, so that the first contact of the removed part of the structure does not protrude out of the surface of the first insulating layer far away from the source layer.
19. The method of claim 17, wherein removing the reference substrate comprises: when the reference substrate is removed, removing a part of the initial grounding structure to form the grounding structure, wherein the grounding structure is flush with the first insulating layer.
20. The manufacturing method according to claim 17, characterized in that after removing the substrate, the manufacturing method further comprises:
forming a via on the first insulating layer, the via exposing the source layer;
the "forming a connection layer on a side of the first insulating layer facing away from the stacked structure" includes:
and forming a bulge in the via hole when the connecting layer is formed, wherein the bulge is connected with the source layer.
21. The method of claim 12, wherein forming a first contact within the second insulating layer, the source layer, and the first insulating layer comprises:
forming a second contact within the second insulating layer while forming the first contact, wherein the second contact is connected to a conductive layer of the stacked structure.
22. The method of claim 21, wherein the first contact and the second contact are made of tungsten, and the connection layer is made of aluminum; the substrate is made of polycrystalline silicon; the etching stop layer is made of silicon nitride; the first insulating layer and the second insulating layer are made of silicon dioxide.
23. The method of manufacturing according to claim 17, further comprising, before removing the substrate:
and forming an interconnection structure on one side of the stacking structure, which is far away from the source layer, wherein the interconnection structure is electrically connected with the channel structure.
24. The method of claim 23, wherein after forming the interconnect structure, the method further comprises:
and forming a peripheral circuit on one side of the interconnection structure, which faces away from the stacking structure, wherein the peripheral circuit is electrically connected with the interconnection structure.
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| US10916556B1 (en) * | 2017-12-12 | 2021-02-09 | Sandisk Technologies Llc | Three-dimensional memory device using a buried source line with a thin semiconductor oxide tunneling layer |
| US10629611B2 (en) * | 2018-04-24 | 2020-04-21 | Sandisk Technologies Llc | Three-dimensional memory device and methods of making the same using replacement drain select gate electrodes |
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| CN111370411B (en) * | 2020-03-12 | 2023-04-18 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN111566816B (en) * | 2020-04-14 | 2021-06-08 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory device with backside source contact |
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