CN111785681B - Memory device and method of manufacturing the same - Google Patents
Memory device and method of manufacturing the same Download PDFInfo
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- CN111785681B CN111785681B CN202010640621.1A CN202010640621A CN111785681B CN 111785681 B CN111785681 B CN 111785681B CN 202010640621 A CN202010640621 A CN 202010640621A CN 111785681 B CN111785681 B CN 111785681B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The application discloses a memory device and a method of manufacturing the same. The manufacturing method comprises forming at least one through hole penetrating through the substrate, the through hole extending along the second surface of the substrate to the first surface of the substrate; sequentially forming an insulating layer and a conductive material layer on the second surface of the substrate and inside the through hole; forming a metal material layer on the surface of the conductive material layer; and removing part of the metal material layer, part of the conductive material layer and part of the insulating layer, so that the conductive material layer positioned inside the through hole and positioned on the second surface of part of the substrate is used as a silicon through interconnection structure, the metal material layer positioned on the surface of the silicon through interconnection structure is used as a back side interconnection conductive layer, and the back side interconnection conductive layer is in contact with and electrically connected with the silicon through interconnection structure. According to the method, redundant conductive material layers and metal material layers are removed by one-time etching to simultaneously form the silicon through interconnection structure and the back side interconnection conductive layer, so that the back side interconnection conductive layer and a contact part between the silicon through interconnection structures are closely matched, and the stability of the storage device is improved.
Description
Technical Field
The present invention relates to memory technology, and more particularly, to memory devices and methods of fabricating the same.
Background
The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, memory devices of three-dimensional structure have been developed. In order to ensure the bit density of the memory device, a through silicon interconnect structure is introduced in the memory device to achieve electrical connection between the memory array and peripheral circuits.
In the current memory device, during the process of forming the through silicon interconnect structure, a conductive material layer in the through silicon via may have a dishing (divot) defect, which may result in a poor contact at the intersection of the through silicon interconnect structure and the backside interconnect conductive layer, and may affect the performance of the memory device.
It is desirable to further improve the structure of the memory device and the method of manufacturing the same to simplify the process flow for manufacturing the memory device and to improve the performance of the memory device.
Disclosure of Invention
The invention aims to provide an improved memory device and a manufacturing method thereof, which simplify the process flow for manufacturing the memory device and improve the performance of the memory device.
According to an aspect of the present invention, there is provided a method of manufacturing a memory device, including: forming at least one via through a substrate, the via extending along a second surface of the substrate to a first surface of the substrate; sequentially forming an insulating layer and a conductive material layer on the second surface of the substrate and inside the through hole; forming a metal material layer on the surface of the conductive material layer; and removing part of the metal material layer, part of the conductive material layer and part of the insulating layer, so that the conductive material layer positioned inside the through hole and on the second surface of the part of the substrate is used as a silicon through interconnection structure, and the metal material layer positioned on the surface of the silicon through interconnection structure is used as a back side interconnection conductive layer, wherein the back side interconnection conductive layer is in contact with and electrically connected with the silicon through interconnection structure.
Optionally, the step of forming the backside interconnect conductive layer and the through-silicon interconnect structure includes: forming a patterned optical mask on the surface of the metal material layer; and etching along the surface of the metal material layer according to the optical mask, and taking the substrate as a stop layer.
Optionally, the metal material layer shielded by the optical mask covers the through hole and a part of the substrate.
Optionally, the method further comprises: forming a memory cell layer on the first surface of the substrate, the memory cell layer including a gate stack formed on the first surface of the substrate and at least one first interconnect structure extending through the gate stack and to the first surface of the substrate.
Optionally, the first interconnect structure is in communication with the via.
Optionally, the step of forming the at least one through hole further comprises: and thinning the second surface of the substrate.
According to another aspect of the present invention, there is provided a memory device including: a substrate; at least one via through the substrate; an insulating layer located at the via sidewall and on a second surface of a portion of the substrate; the silicon through interconnection structure is positioned in the through hole and on the surface of the insulating layer, and is provided with a conductive material layer; and a backside interconnect conductive layer on a surface of the conductive material layer, the backside interconnect conductive layer being in contact with and electrically connected to the conductive material layer.
Optionally, the insulating layer isolates the substrate from the layer of conductive material.
Optionally, the memory device further comprises: the memory cell layer is positioned on the first surface of the substrate and comprises a gate stack positioned on the first surface and a first interconnection structure penetrating through the gate stack to reach the first surface.
Optionally, the silicon is contacted and connected through the interconnect structure.
Optionally, the through silicon interconnect structure covers the first interconnect structure.
Optionally, the conductive material layer is a tungsten layer, and the backside interconnect conductive layer is an aluminum layer.
According to the memory device and the manufacturing method thereof provided by the embodiment of the invention, the metal material layer is directly deposited after the conductive material layer is deposited, and then the redundant conductive material layer and the metal material layer are removed by adopting one-time etching to simultaneously form the silicon through interconnection structure and the back side interconnection conductive layer, so that the contact part between the back side interconnection conductive layer and the silicon through interconnection structure is tightly matched, a concave area is prevented from being formed between the back side interconnection conductive layer and the silicon through interconnection structure in the manufacturing process, and the quality of the back side interconnection conductive layer in the silicon through interconnection structure area is improved. And the stability of the memory device is improved through the simplified manufacturing flow.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic cross-sectional view of a partial structure of a memory device.
Fig. 2 is a flow chart illustrating a method for manufacturing a memory device according to an embodiment of the present invention.
Fig. 3 through 8 are schematic cross-sectional views of a memory device provided in accordance with an embodiment of the present invention at various stages in the fabrication process.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The inventors of the present application have noticed that the memory device structure is currently unstable and the manufacturing process is complex, and thus propose a further improved memory device and a method of manufacturing the same.
In order to improve the memory density and the integration of the memory device, the memory device includes a plurality of memory cells stacked in a vertical direction. The effect of the electrical connection between the plurality of memory cells and the external circuit directly affects the stability of the memory device.
Fig. 1 shows a schematic cross-sectional view of a partial structure of a memory device.
As shown in fig. 1, a memory cell layer (not shown) of a memory device is formed on a first surface of a substrate 510, at least one via hole penetrating the substrate 510 is formed to extend downward along a second surface of the substrate 510, an insulating layer 512 is formed on an inner sidewall of the via hole, a conductive material layer 513 is formed inside the via hole to be in contact with the first surface of the substrate 510, and the insulating layer 512 separates the conductive material layer 513 from the substrate 510. The insulating layer 512 and the conductive material layer 513 inside the through silicon via constitute a through silicon interconnect structure. A backside interconnect conductive layer 514 on the first surface of the substrate 510 and the through silicon interconnect structure for electrically connecting the memory cell to an external interconnect structure. A recess 600 exists between the backside interconnect conductive layer 514 and the through-silicon interconnect structure, so that the backside interconnect conductive layer 514 and the through-silicon interconnect structure have poor contact, thereby affecting the stability of the memory device.
According to the memory device and the manufacturing method thereof, the contact between the back side interconnection conductive layer in the memory device and the silicon through interconnection structure is good, the stability of the memory device is improved, and the manufacturing process of the memory device is simple.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 2 shows a flow chart of a method for manufacturing a memory device according to an embodiment of the present invention, and fig. 3 to 8 show cross-sectional views of the memory device provided according to an embodiment of the present invention at various stages in the manufacturing process. The present application mainly solves the problem of electrical connection between the memory cell layer and the external circuit, so the manufacturing method starts with forming the memory cell layer on the surface.
As shown in fig. 2, the method of manufacturing a memory device includes the steps of:
step S10: a memory cell layer is formed on a first surface of a substrate. For example, in a 3D memory device of a NAND structure, the memory cell layer mainly includes a gate stack structure, a channel pillar penetrating the gate stack structure, the gate stack structure is used to provide gate conductors of the select transistor and the memory transistor, and the channel pillar is used to provide channel layers and gate dielectric stacks of the select transistor and the memory transistor. The memory cell also comprises a conductive channel for realizing interconnection of the memory cell string. As shown in fig. 3, a memory cell layer 120 is formed on a first surface of a substrate 110. Specifically, for example, a gate stack formed by alternately stacking a plurality of interlayer insulating layers and a plurality of gate conductor layers is formed on the first surface of the substrate 120, and preferably, the material of the interlayer insulating layers is selected from oxide and the material of the gate conductor layers is selected from tungsten. A plurality of channel pillars (not shown) penetrating through the gate stack and reaching the first surface of the substrate 110 and the first interconnect structure 121 are formed as conductive paths along the surface of the gate stack. The first interconnect structure 121 has one end reaching the first surface of the substrate 110 and the other end reaching the gate stack surface. Preferably, an end of the first interconnect structure 121 close to the substrate 110 is embedded in a partial region of the substrate 110 along the first surface of the substrate 110 to serve as a stopper when a through-silicon via is subsequently formed. Wherein the first interconnect structure 121 includes an insulating layer and a conductive layer, the insulating layer isolating the conductive layer from the gate stack in the memory cell layer 120 layer. The conductive layer in the first interconnect structure 121 includes, for example, copper, tungsten, cobalt, or other conductive material.
Preferably, a circuit structure 200 is also included that forms a bond connection with the gate stack in the memory cell layer 120. A peripheral circuit 201 is formed within the circuit structure 200, and the peripheral circuit 201 is connected to the first interconnect structure 121, thereby forming an electrical connection with the memory cell to supply a control voltage, etc. to the memory cell.
Preferably, after the semiconductor structure is turned over, the substrate 110 is thinned along the second surface of the substrate 110, and then the thinned second surface of the substrate 110 is processed, for example, by using a mechanical polishing process, so as to obtain a flat surface, which is beneficial for implementing the subsequent manufacturing process. Wherein the first surface and the second surface of the substrate 110 are opposite.
Step S20: at least one via is formed along the second surface of the substrate. Specifically, as shown in fig. 4, at least one via hole 111 extending downward and reaching the first surface of the substrate 110 is formed along the second surface of the substrate 110. Wherein a sacrificial layer is deposited on the second surface of the substrate 110, and then a patterned optical mask is disposed on the surface of the sacrificial layer. Photolithography is then followed by a photomask to form at least one via 111 in the substrate 110. Specifically, the semiconductor structure is lithographically patterned through the window pattern of the photomask and stopped at the surface of the memory cell layer 120 in contact with the first surface of the substrate 110 to form at least one via hole 111 through the substrate 110. Thereby exposing at least an end portion of the first interconnect structure 121 in the via hole 111. The first interconnect structure 121 plays a role of limiting during the process of forming the via hole 111.
Further, after the photolithography is completed, the optical mask and the sacrificial layer on the second surface of the substrate 110 are removed.
Step S30: and forming an insulating layer and a conductive material layer on the second surface of the substrate and inside the through hole. Specifically, as shown in fig. 5, an insulating layer is deposited on the second surface of the substrate 110 and inside the through hole 111, and then the insulating layer at the bottom of the through hole 111 is removed to obtain an insulating layer 301 at the second surface of the substrate 110 and the sidewall of the through hole 111. Next, a conductive material layer 302 is formed on the surface of the insulating layer 301 and inside the via hole 111, and the conductive material layer 302 at the bottom of the via hole 111 is in contact with and connected to the first interconnect structure 121. The layer 302 of conductive material covers the second surface of the substrate 110 and reaches the first surface of the substrate 110. The insulating layer 301 is, for example, a silicon oxide layer or a silicon nitride layer, and the conductive material layer 302 is selected from a tungsten layer, alternatively, the conductive material layer 302 may also be a copper, cobalt or other conductive material layer.
Step S40: and forming a metal material layer on the surface of the conductive material layer. Specifically, as shown in fig. 6, a metallic material layer 303 is deposited on the surface of the conductive material layer 302 away from the substrate 110, the metallic material layer 303 being selected from an aluminum layer. The layer of metallic material 303 covers the layer of conductive material 303 and is used to form a backside interconnect conductive layer in a subsequent flow.
Step S50: and removing part of the insulating layer, part of the conductive material layer and part of the metal material layer to form a back side interconnection conductive layer and a silicon through interconnection structure. Specifically, as shown in fig. 7 and 8, an optical mask 401 is formed on the surface of the metal material layer 303, the optical mask 401 is patterned to block a portion of the metal material layer 303 above the through hole 111 and on the second surface of the substrate 110, and the rest of the metal material layer 303 is exposed. And etching along the surface of the metal material layer 303 away from the conductive material layer according to the optical mask 401, stopping on the second surface of the substrate 110, removing part of the insulating layer, part of the conductive material layer, and part of the metal material layer, leaving the insulating layer 112 on the sidewall of the through hole 111 and part of the second surface of the substrate 110, and enabling the conductive material layer 113 in the through hole 111 and on the second surface of the substrate 110 to serve as a through silicon interconnection structure, and the metal material layer 114 on the surface of the through silicon interconnection structure to serve as a back side interconnection conductive layer. Further, the silicon through interconnect structure is connected with the first interconnect structure 121. The backside interconnection conductive layer is in contact with and connected to the silicon through interconnection structure in preparation for interconnecting the silicon through interconnection structure in the memory device with an external circuit structure, expanding the function of the memory device and improving the performance of the memory device. Next, the optical mask 401 is removed. According to the manufacturing method, after the conductive material layer and the metal material layer are deposited in sequence, the redundant conductive material layer and the redundant metal material layer are removed by adopting one-time etching to simultaneously form the back side interconnection conductive layer and the silicon through interconnection structure, so that the contact part between the back side interconnection conductive layer and the silicon through interconnection structure is tightly matched, the recess between the back side interconnection conductive layer and the silicon through interconnection structure is avoided, the quality of the back side interconnection conductive layer in the silicon through interconnection structure area is improved, and the stability of the storage device is further improved.
Further, as shown in fig. 8, a memory cell layer 120 of a memory device and a first interconnect structure 121 penetrating the memory cell layer 120 are formed on the first surface of the substrate 110. At least one through hole 111 penetrating the substrate 110 and communicating with the first interconnect structure 121, an insulating layer 112 located at the sidewall of the through hole 111 and on the second surface of the portion of the substrate 110, and a conductive material layer 113 located inside the through hole 111 and on the second surface of the portion of the substrate 110 are formed to extend downward on the second surface of the substrate 110 as a through silicon interconnect structure. The metal material layer 114 on the surface of the conductive material layer 113 serves as a backside interconnect conductive layer. The through silicon interconnect structure electrically connects the first interconnect structure 121 of the memory cell with the backside interconnect conductive layer. A backside interconnect conductive layer is located over the second surface of the substrate 110 for connecting to external circuit structures. The back side interconnection conducting layer is in close contact with the silicon through interconnection structure, so that the quality of the back side interconnection conducting layer deposited on the silicon through interconnection structure is guaranteed, and the stability of the storage device is further improved.
The manufacturing method of the memory device reduces the process flow, saves the cost and can obtain the memory device with improved stability.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (12)
1. A method of manufacturing a memory device, comprising:
sequentially forming a storage unit layer and a circuit structure on the first surface of the substrate, wherein a peripheral circuit is formed in the circuit structure, and the storage unit layer comprises at least one first interconnection structure connected with the peripheral circuit;
forming at least one via through a substrate, the via extending along a second surface of the substrate to a first surface of the substrate;
sequentially forming an insulating layer and a conductive material layer on the second surface of the substrate and inside the through hole;
forming a metal material layer on the surface of the conductive material layer; and
removing part of the metal material layer, part of the conductive material layer and part of the insulating layer, so that the conductive material layer positioned in the through hole and positioned on the second surface of part of the substrate is used as a silicon through interconnection structure, the metal material layer positioned on the surface of the silicon through interconnection structure is used as a back side interconnection conductive layer,
wherein the backside interconnect conductive layer is in contact with and electrically connected to the through-silicon interconnect structure, which is connected to the first interconnect structure.
2. The manufacturing method according to claim 1, wherein the step of forming the backside interconnect conductive layer and the through-silicon interconnect structure comprises:
forming a patterned optical mask on the surface of the metal material layer;
and etching along the surface of the metal material layer according to the optical mask, and taking the substrate as a stop layer.
3. The manufacturing method according to claim 2, wherein the metal material layer blocked by the optical mask covers the through hole and a part of the substrate.
4. The manufacturing method according to claim 1,
the memory cell layer further includes a gate stack formed on the substrate first surface, the at least one first interconnect structure extending through the gate stack and to the substrate first surface.
5. The manufacturing method according to claim 4, wherein the first interconnect structure communicates with the via.
6. The manufacturing method of claim 4, wherein the step of forming the at least one via further comprises:
and thinning the second surface of the substrate.
7. A memory device, comprising:
a substrate;
the memory cell layer and the circuit structure are sequentially positioned on the first surface of the substrate, a peripheral circuit is formed in the circuit structure, and the memory cell layer comprises at least one first interconnection structure connected with the peripheral circuit;
at least one via through the substrate;
an insulating layer located at the via sidewall and on a second surface of a portion of the substrate;
the silicon through interconnection structure is positioned in the through hole and on the surface of the insulating layer, and is connected with the first interconnection structure; and
a backside interconnect conductive layer on a surface of the conductive material layer, the backside interconnect conductive layer in contact with and electrically connected to the conductive material layer,
the memory deviceFormed by the manufacturing method of any one of claims 1 to 6。
8. The memory device of claim 7, wherein the insulating layer isolates the substrate from the layer of conductive material.
9. The memory device of claim 7, wherein the memory cell layer further comprises a gate stack at the first surface, the at least one first interconnect structure extending through the gate stack to the first surface.
10. The memory device of claim 9, wherein the first interconnect structure is in contact with and connected to the through silicon interconnect structure.
11. The memory device of claim 10, wherein the through silicon interconnect structure overlies the first interconnect structure.
12. The memory device of claim 7, wherein the conductive material layer is a tungsten layer and the backside interconnect conductive layer is an aluminum layer.
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| KR20070020919A (en) * | 2005-08-17 | 2007-02-22 | 삼성전자주식회사 | Recess channel array transistor and method for fabricating the same |
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| CN103890940A (en) * | 2011-10-28 | 2014-06-25 | 英特尔公司 | 3d interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach |
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