CN112864093B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112864093B CN112864093B CN201911175511.6A CN201911175511A CN112864093B CN 112864093 B CN112864093 B CN 112864093B CN 201911175511 A CN201911175511 A CN 201911175511A CN 112864093 B CN112864093 B CN 112864093B
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- 238000005530 etching Methods 0.000 description 9
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- 239000010703 silicon Substances 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 6
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a substrate and an initial fin part separated from the substrate, and the initial fin part comprises an initial bottom fin part and an initial top fin part; forming an initial isolation structure covering the side wall of the initial fin part on the substrate exposed by the initial fin part; doping oxygen ions in the initial isolation structure to form an oxidation doped region; removing part of the thickness initial isolation structure to form a residual initial isolation structure exposing part of the side wall of the initial top fin part; annealing treatment is carried out, so that partial thickness materials of the side wall, which is in contact with the oxidation doping region, in the initial fin part are consumed and converted into an oxide layer, the rest initial bottom fin part is used as a bottom fin part, and the rest initial top fin part is used as a top fin part; and removing the residual initial isolation structure and the oxide layer which are higher than the bottom fin part to form an isolation structure. The embodiment of the invention is beneficial to improving the performance of the device.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pinchoff) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (Subthreshold leakage), namely so-called Short Channel Effects (SCE), is more likely to occur.
Accordingly, to reduce the impact of short channel effects, semiconductor processes are gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of a device.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and an initial fin part separated from the substrate, the initial fin part comprises an initial bottom fin part and an initial top fin part positioned on the initial bottom fin part, and the direction perpendicular to the extending direction of the initial fin part and perpendicular to the side wall of the initial fin part is transverse; forming an initial isolation structure on the substrate exposed by the initial fin part, wherein the initial isolation structure covers the side wall of the initial fin part; doping oxygen ions in the initial isolation structure to form an oxidation doped region, wherein the oxidation doped region is in contact with the side wall, close to the junction between the initial bottom fin part and the initial top fin part, of the initial top fin part along the transverse direction; removing part of the initial isolation structure with the thickness to form a residual initial isolation structure, wherein part of the side wall of the initial top fin part is exposed by the residual initial isolation structure; after removing the initial isolation structure with partial thickness, carrying out annealing treatment to consume partial thickness materials of the side wall, which is in contact with the oxidation doping region, in the initial fin part and convert the partial thickness materials into an oxidation layer, wherein the rest initial bottom fin part is used as a bottom fin part, the rest initial top fin part is used as a top fin part, and the bottom fin part and the top fin part are used for forming a fin part; and after the fin parts are formed, removing the residual initial isolation structures higher than the bottom fin parts to form isolation structures.
Optionally, in the step of providing the substrate, a fin mask layer is further formed on top of the initial fin; in the step of forming the initial isolation structure, the top surface of the initial isolation structure is higher than the top surface of the initial fin portion and lower than the top surface of the fin portion mask layer; doping oxygen ions in the initial isolation structure by taking the fin mask layer as a mask to form the oxidation doped region; after forming the oxidation doped region and before removing part of the thickness of the initial isolation structure, the method for forming the semiconductor structure further comprises the following steps: and removing the fin part mask layer.
Optionally, the step of forming the initial isolation structure includes: forming an isolation material layer on the substrate exposed by the initial fin part, wherein the isolation material layer also covers the fin part mask layer; taking the top surface of the fin part mask layer as a stop position, and carrying out planarization treatment on the isolation material layer to enable the top surface of the isolation material layer to be flush with the top surface of the fin part mask layer; and removing part of the isolation material layer with the thickness, so that the top surface of the isolation material layer is lower than the top surface of the fin mask layer, and forming the initial isolation structure.
Optionally, in the step of forming the initial isolation structure, a distance from a top surface of the initial isolation structure to a top surface of the fin mask layer is 200 to 300 a m along a normal direction of the substrate.
Optionally, in the step of forming the oxidation doped region, the oxidation doped region is in contact with the initial fin sidewall at the junction of the initial bottom fin and the initial top fin along the lateral direction.
Optionally, in the step of removing the initial isolation structure with a partial thickness, the height of the initial top fin covered by the remaining initial isolation structure is 5% to 15% of the total height of the initial top fin.
Optionally, an ion implantation process is used to dope oxygen ions into the initial isolation structure.
Optionally, the parameters of the ion implantation process include: the angle of implantation is 0 degrees to the normal of the substrate surface, the implantation energy is 10KeV to 100KeV, and the implantation dose is 1E13 atoms per square centimeter to 5E14 atoms per square centimeter.
Optionally, the annealing treatment is performed at a temperature of 500 ℃ to 750 ℃.
Optionally, a furnace tube annealing process is adopted for the annealing treatment.
Optionally, in the step of performing the annealing treatment, a consumption of the single-sided sidewall in the initial fin is 5 to 20 a.
Optionally, after forming the remaining initial isolation structures, before performing the annealing treatment, the method for forming the semiconductor structure further includes: forming a protective layer on the top surface and the side wall of the initial top fin part; after the annealing treatment, the method for forming the semiconductor structure further comprises the following steps: and removing the protective layer.
Optionally, the thickness of the protective layer is 30 to 80 a.
Optionally, the protective layer is removed by a wet etching process.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: the substrate comprises a substrate and a fin part separated from the substrate, wherein the fin part comprises a bottom fin part and a top fin part positioned on the bottom fin part, and the direction along the direction perpendicular to the extending direction of the fin part and the direction perpendicular to the side wall of the fin part is transverse; the side wall of the top fin part is recessed along the transverse direction at one side close to the junction of the bottom fin part and the top fin part; and the isolation structure is positioned on the substrate exposed by the fin part, covers the side wall of the bottom fin part and exposes the top fin part.
Optionally, the side wall of the fin portion is recessed in the transverse direction at the junction of the bottom fin portion and the top fin portion; the semiconductor structure further includes: and the oxide layer is positioned between the side wall of the bottom fin part along the transverse recess and the isolation structure, and is formed by converting partial thickness materials of the side wall of the fin part.
Optionally, the material of the oxide layer is the same as the material of the isolation structure.
Optionally, in the bottom fin, a height of the portion of the sidewall recessed in the lateral direction is 20 to 30 a.
Optionally, in the top fin portion, a sidewall near a junction of the bottom fin portion and the top fin portion is recessed 5 to 20 a in a lateral direction.
Optionally, in the top fin, a height of the portion of the sidewall recessed in the lateral direction is 5% to 15% of a total height of the top fin.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure of the embodiment of the invention, oxygen ions are doped in the initial isolation structure to form an oxidation doped region, the oxidation doped region is in contact with the side wall of the initial top fin part, which is close to the junction between the initial bottom fin part and the initial top fin part, along the transverse direction, then part of the initial isolation structure with partial thickness is removed to expose part of the side wall of the initial top fin part, so that part of the side wall of the initial top fin part is in contact with the oxidation doped region, and then annealing treatment is carried out, wherein in the annealing treatment process, the oxygen ions in the oxidation doped region diffuse into the initial fin part through the side wall of the initial fin part, so that part of the thickness material of the side wall of the initial fin part, which is in contact with the oxidation doped region, is consumed, so that an oxidation layer is formed, and the transverse dimension of the side of the initial top fin part, which is close to the junction between the initial bottom fin part and the initial top fin part, is reduced along the transverse direction, namely, the side wall of the top fin part, which is close to the junction between the bottom fin part and the top part is recessed along the transverse direction. In the semiconductor field, the initial fin portion is generally of a trapezoid structure with a small top and a large bottom, and the top fin portion is generally used as an effective fin portion of the device, so that the lateral wall of the top fin portion, which is close to one side of the junction between the bottom fin portion and the top fin portion, is recessed in the lateral direction, so that the lateral dimension difference between the bottom of the effective fin portion (i.e., the top fin portion) and the top of the effective fin portion is reduced, and the perpendicularity of the lateral wall of the effective fin portion and the lateral dimension uniformity of the bottom and the top of the effective fin portion are improved, and the performance of the device is improved.
Drawings
Fig. 1 to 9 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
Currently, the fin formed by the SAQP process is generally a trapezoid structure with a small top and a large bottom, and the side wall of the fin is not generally perpendicular to the substrate, that is, the side wall of the fin part has a certain included angle with the normal line of the surface of the substrate, the top of the fin part points to the substrate along the direction of the substrate, and the width of the fin part is gradually increased along the extending direction perpendicular to the fin part.
Furthermore, after forming the fin portion, the method for forming the semiconductor structure generally further includes: and forming an isolation layer on the substrate exposed by the fin part, wherein the isolation layer covers part of the side wall of the fin part, and the top surface of the isolation layer is lower than the top surface of the fin part.
The part of the fin portion exposed by the isolation layer is an effective fin portion, and after a gate structure is formed subsequently, the gate structure spans the effective fin portion and covers part of the top and part of the side wall of the effective fin portion.
The side wall of the fin portion has a certain included angle with the normal line of the substrate, the verticality of the side wall of the fin portion is poor, that is, the difference in size between the top of the effective fin portion and the bottom of the effective fin portion is large, the size of the bottom of the effective fin portion is larger than the size of the top of the effective fin portion, the uniformity of the width size of the effective fin portion is poor, which easily results in poor performance of the device, for example: leakage current at the bottom of the effective fin is large, etc.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and an initial fin part separated from the substrate, the initial fin part comprises an initial bottom fin part and an initial top fin part positioned on the initial bottom fin part, and the direction perpendicular to the extending direction of the initial fin part and perpendicular to the side wall of the initial fin part is transverse; forming an initial isolation structure on the substrate exposed by the initial fin part, wherein the initial isolation structure covers the side wall of the initial fin part; doping oxygen ions in the initial isolation structure to form an oxidation doped region, wherein the oxidation doped region is in contact with the side wall, close to the junction between the initial bottom fin part and the initial top fin part, of the initial top fin part along the transverse direction; removing part of the initial isolation structure with the thickness to form a residual initial isolation structure, wherein part of the side wall of the initial top fin part is exposed by the residual initial isolation structure; after removing the initial isolation structure with partial thickness, carrying out annealing treatment to consume partial thickness materials of the side wall, which is in contact with the oxidation doping region, in the initial fin part and convert the partial thickness materials into an oxidation layer, wherein the rest initial bottom fin part is used as a bottom fin part, the rest initial top fin part is used as a top fin part, and the bottom fin part and the top fin part are used for forming a fin part; and after the fin parts are formed, removing the residual initial isolation structures higher than the bottom fin parts to form isolation structures.
In the method for forming the semiconductor structure of the embodiment of the invention, oxygen ions are doped in the initial isolation structure to form an oxidation doped region, the oxidation doped region is in contact with the side wall of the initial top fin part, which is close to the junction between the initial bottom fin part and the initial top fin part, along the transverse direction, then part of the initial isolation structure with partial thickness is removed to expose part of the side wall of the initial top fin part, so that part of the side wall of the initial top fin part is in contact with the oxidation doped region, and then annealing treatment is carried out, wherein in the annealing treatment process, the oxygen ions in the oxidation doped region diffuse into the initial fin part through the side wall of the initial fin part, so that part of the thickness material of the side wall of the initial fin part, which is in contact with the oxidation doped region, is consumed, so that an oxidation layer is formed, and the transverse dimension of the side of the initial top fin part, which is close to the junction between the initial bottom fin part and the initial top fin part, is reduced along the transverse direction, namely, the side wall of the top fin part, which is close to the junction between the bottom fin part and the top part is recessed along the transverse direction. In the semiconductor field, the initial fin portion is generally of a trapezoid structure with a small top and a large bottom, and the top fin portion is generally used as an effective fin portion of the device, so that the lateral wall of the top fin portion, which is close to one side of the junction between the bottom fin portion and the top fin portion, is recessed in the lateral direction, so that the lateral dimension difference between the bottom of the effective fin portion (i.e., the top fin portion) and the top of the effective fin portion is reduced, and the perpendicularity of the lateral wall of the effective fin portion and the lateral dimension uniformity of the bottom and the top of the effective fin portion are improved, and the performance of the device is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 to 9 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1, a base is provided, the base comprising a substrate 100 and an initial fin 110 separated from the substrate 100, the initial fin 110 comprising an initial bottom fin 101 and an initial top fin 102 on the initial bottom fin 101, the direction being transverse along a direction perpendicular to the extension direction of the initial fin 110 and perpendicular to the sidewalls of the initial fin 110.
The substrate provides a process platform for a process.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
The initial fin 110 is used for forming a fin later.
Wherein, the initial bottom fin 101 is used for forming a bottom fin subsequently; the initial top fin 102 is used to subsequently form a top fin that is used as an active fin of the device.
In this embodiment, the initial fin 110 is a unitary structure.
In this embodiment, the material of the initial fin portion 110 is the same as the material of the substrate 100, and the material of the initial fin portion 110 is silicon. In other embodiments, the material of the initial fin may be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the initial fin may be different from the material of the substrate.
In this embodiment, in the step of providing the substrate, a fin mask layer 130 is further formed on top of the initial fin 110.
The fin mask layer 130 is used as an etching mask for forming the initial fin 110 and the substrate, the fin mask layer 130 is further used for protecting the top of the initial fin 110, and the fin mask layer 130 is further used as a mask for doping oxygen ions in the initial isolation structure later, so as to prevent the oxygen ions from being doped to the top of the initial fin 110.
In this embodiment, the fin mask layer 130 is made of silicon nitride.
In this embodiment, a Pad oxide layer (Pad oxide) 120 is further formed between the initial fin 110 and the fin mask layer 130.
The pad oxide layer 120 is used for playing a role of stress buffering when the fin mask layer 130 is formed and the fin 110 and the substrate 100 are formed by taking the fin mask layer 130 as a mask, so that the adhesiveness between the fin mask layer 130 and the fin 110 is improved, and the problem that dislocation is generated when the fin mask layer 130 is in direct contact with the fin 110 is avoided.
In this embodiment, the pad oxide layer 120 is made of silicon oxide.
Referring to fig. 2-3, an initial isolation structure 135 (shown in fig. 3) is formed on substrate 100 where initial fin 110 is exposed, initial isolation structure 135 covering the sidewalls of initial fin 110.
The initial isolation structure 135 is used for subsequent formation of isolation structures, and the initial isolation structure 135 is also used to prepare for subsequent formation of oxide doped regions.
In this embodiment, the material of the initial isolation structure 135 is silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the initial isolation structure 135; in addition, the smaller dielectric constant of the silicon oxide is also beneficial to improving the function of the subsequent isolation structure for isolating adjacent devices. In other embodiments, the material of the initial isolation structure may be silicon nitride, silicon oxynitride, or other insulating materials.
In this embodiment, in the step of forming the initial isolation structure 135, the top surface of the initial isolation structure 135 is higher than the top surface of the initial fin 110 and lower than the top surface of the fin mask layer 130.
Doping oxygen ions into the initial isolation structure 135 by an ion implantation process, wherein the top surface of the initial isolation structure 135 is higher than the top surface of the initial fin 110, so that the doping of oxygen ions onto the initial fin 110 is prevented; by having the top surface of initial isolation structure 135 lower than the top surface of fin mask layer 130, the thickness of initial isolation structure 135 is made smaller, thereby making the implantation energy for subsequent ion implantation into initial isolation structure 135 smaller, thereby facilitating a reduction in the risk of ion implantation into the top of initial fin 110.
In the step of forming the initial isolation structure 135, the distance from the top surface of the initial isolation structure 135 to the top surface of the fin mask layer 130 should not be too small or too large along the normal direction of the substrate 100. If the distance is too small, the effect of reducing the risk of implanting ions on top of the initial fin 110 is not obvious; if the distance is too large, the initial isolation structure 135 is exposed to the initial fin 110 at a greater risk, and the subsequent doping of oxygen ions to the initial fin 110 is also at a greater risk. For this reason, in this embodiment, the distance from the top surface of the initial isolation structure 135 to the top surface of the fin mask layer 130 is 200 to 300 a.
This embodiment illustrates an example where the top surface of initial isolation structure 135 is higher than the top surface of initial fin 110 and lower than the top surface of fin mask layer 130. In other embodiments, the top surface of the initial isolation structure may also be flush with the top surface of the fin mask layer, depending on the actual process.
In this embodiment, the step of forming the initial isolation structure 135 includes: as shown in fig. 2, an isolation material layer 131 is formed on the substrate 100 exposed by the initial fin 110, and the isolation material layer 131 covers the sidewalls of the fin mask layer 130.
In this embodiment, the isolation material layer 131 is formed by a flowable chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD) process. The flowable chemical vapor deposition process has good filling capability, is suitable for filling the openings with high aspect ratio, is beneficial to reducing the probability of forming defects such as cavities in the isolation material layer 131, and is correspondingly beneficial to improving the film forming quality of the follow-up initial isolation structure.
With continued reference to fig. 2, the top surface of the fin mask layer 130 is taken as a stop position, and the isolation material layer 131 is planarized, so that the top surface of the isolation material layer 131 is flush with the top surface of the fin mask layer 130.
In this embodiment, a chemical mechanical planarization (Chemical Mechanic Planarization, CMP) process is used to planarize the isolation material layer 131.
By using a chemical mechanical planarization process, the top surface flatness of the isolation material layer 131 after the planarization process is advantageously improved.
As shown in fig. 3, a portion of isolation material layer 131 is removed to form initial isolation structure 135, such that the top surface of isolation material layer 131 is lower than the top surface of fin mask layer 130.
In this embodiment, a wet etching process is used to remove a portion of the thickness of the isolation material layer 131.
Specifically, the wet etching process is performed using a hydrofluoric acid solution.
Referring to fig. 4, oxygen ions are doped in initial isolation structure 135 (as shown by circles in fig. 4) to form an oxide doped region that laterally contacts a sidewall of initial top fin 102 that is adjacent to a boundary between initial bottom fin 101 and initial top fin 102.
By making the oxidized doped region laterally contact with the sidewall of the initial top fin 102, which is close to the junction between the initial bottom fin 101 and the initial top fin 102, in the subsequent annealing step, oxygen ions in the oxidized doped region can consume a part of the thickness material of the sidewall of the initial top fin 102, which is close to the junction between the initial bottom fin 101 and the initial top fin 102, so that the size of the bottom of the initial top fin 102 can be reduced, thereby being beneficial to improving the uniformity of the lateral width and the size of the top fin.
In this embodiment, in the step of forming the oxide doped region, the oxide doped region is in contact with the sidewalls of the initial fin 110 at the junction between the initial bottom fin 101 and the initial top fin 102 in the lateral direction, that is, the oxide doped region is in contact with not only the sidewalls of the initial top fin 102 near the junction between the initial bottom fin 101 and the initial top fin 102 but also the sidewalls of the initial bottom fin 101 near the junction between the initial bottom fin 101 and the initial top fin 102 in the lateral direction, so that after the initial isolation structure 135 with a partial thickness is removed, the oxide doped region can still be in contact with the sidewalls of the initial top fin 102 near the junction between the initial bottom fin 101 and the initial top fin 102, which is favorable for reducing the process risk and improving the process stability.
In this embodiment, a fin mask layer 130 is further formed on top of the initial fin 110, so that the oxide doping region is formed by doping oxygen ions in the initial isolation structure 135 with the fin mask layer 130 as a mask, which is beneficial to prevent oxygen ions from being doped on top of the initial fin 110.
In this embodiment, an ion implantation process is used to dope oxygen ions into the initial isolation structure 135.
In this embodiment, the angle between the implantation angle of the ion implantation process and the normal to the surface of substrate 100 is 0 °, that is, the ion implantation process implants oxygen ions into initial isolation structure 135 along the direction perpendicular to the surface of substrate 100, so that the risk of implanting oxygen ions onto the sidewalls of initial fin 110 is advantageously reduced.
The implantation energy of the ion implantation process is not too small nor too large. If the implantation energy of the ion implantation process is too small, the implantation depth of the oxygen ions in the initial isolation structure 135 is too shallow, which easily results in that the oxide doped region is difficult to contact along the sidewall of the lateral initial top fin 102, which is close to the junction between the initial bottom fin 101 and the initial top fin 102, and further, in the subsequent annealing process, it is difficult to consume a portion of the thickness material of the sidewall of the initial top fin 102, which is close to the junction between the initial bottom fin 101 and the initial top fin 102, and accordingly, it is difficult to reduce the lateral dimension of the bottom of the initial top fin 102; if the implantation energy of the ion implantation process is too high, the oxygen ions are easily implanted through the fin mask layer 130 to the top of the initial fin 110, and also easily increase the risk of implanting oxygen ions into the substrate 100. For this reason, in this embodiment, the implantation energy of the ion implantation process is 10KeV to 100KeV.
The implantation dose of the ion implantation process is not too small or too large. If the implantation dose of the ion implantation process is too small, the oxygen content in the oxidation doped region is correspondingly too small, and during the subsequent annealing treatment, oxygen ions consume too little material on the side wall of the initial top fin 102, which is close to the junction between the initial bottom fin 101 and the initial top fin 102, so that the effect of reducing the lateral dimension of the bottom of the initial top fin 102 is not obvious; if the implantation dose of the ion implantation process is too large, the oxygen content in the oxide doped region is correspondingly too large, which easily results in excessive consumption of the material on the sidewall of the initial top fin 102, which is close to the junction between the initial bottom fin 101 and the initial top fin 102, in the subsequent annealing process, so that the lateral size of the bottom of the top fin is too small, thereby being difficult to play a supporting role, and easily increasing the risk of collapse of the top fin. For this reason, in the present embodiment, the implantation dose of the ion implantation process is 1E13 atoms per square centimeter to 5E14 atoms per square centimeter.
In this embodiment, in the step of forming the oxide doped region, a distance from the bottom of the oxide doped region to the junction between the initial bottom fin portion 101 and the initial top fin portion 102 is 20 to 30 a.
In this embodiment, after forming the oxide doped region, the method for forming the semiconductor structure further includes: the fin mask layer 130 is removed.
The fin mask layer 130 is removed, so that the top of the initial fin 110 is exposed, and preparation is made for forming a functional layer such as a gate structure on the fin later.
In this embodiment, a phosphoric acid solution is used to remove the fin mask layer 130.
After removing the fin mask layer 130, the pad oxide layer 120 is exposed.
In this embodiment, after doping the initial isolation structure 135 with oxygen ions, before removing the fin mask layer 130, the method for forming the semiconductor structure further includes: portions of the initial isolation structures 135 are etched back, and the remaining initial isolation structures 135 expose portions of the sidewalls of fin mask layer 130.
By etching back the initial isolation structure 135 with a partial thickness, more sidewalls of fin mask layer 130 are exposed by the remaining initial isolation structure 135, so that fin mask layer 130 is easier to remove, and the process difficulty of removing fin mask layer 130 is reduced.
In this embodiment, a diluted hydrofluoric acid solution is used to etch back a portion of the thickness of the initial isolation structure 135.
Referring to fig. 5, a portion of the initial isolation structure 135 is removed to form a remaining initial isolation structure 140, the remaining initial isolation structure 140 exposing a portion of the sidewalls of the initial top fin 102.
The remaining initial isolation structure 140 exposes a portion of the sidewalls of the initial top fin 102, that is, the top surface of the remaining initial isolation structure 140 is higher than the boundary between the initial bottom fin 101 and the initial top fin 102 and lower than the top of the initial fin 110, and the remaining initial isolation structure 140 also covers a portion of the sidewalls of the initial top fin 102, so that the oxidized doped region can still laterally contact the sidewalls of the initial top fin 102, which are close to the boundary between the initial bottom fin 101 and the initial top fin 102, and oxygen ions in the oxidized doped region consume a portion of the thickness material of the boundary between the initial top fin 102, which is close to the boundary between the initial bottom fin 101 and the initial top fin 102, in preparation for the subsequent annealing process.
In this embodiment, a sicon process is used to remove a portion of the thickness of the initial isolation structure 135.
The sicon etching process is a chemical etching method, and compared with the traditional dry etching process, the sicon etching process etches the thin film in an environment without plasma and plasma bombardment, so that the damage to the initial fin portion 110 is reduced; compared with the traditional wet etching process, although the SiCoNi etching process also adopts a chemical etching mode to etch, a higher etching selection ratio can be obtained, the probability of damage of the initial fin portion 110 is reduced, the top surface height uniformity and the top surface morphology quality of the residual initial isolation structure 140 can be improved, and the etching load effect can be improved.
In the step of removing a portion of the thickness of initial isolation structure 135, the height of initial top fin 102 covered by remaining initial isolation structure 140 should not be too small or too large as a percentage of the total height of initial top fin 102. If the height of the initial top fin 102 covered by the remaining initial isolation structure 140 is too small as a percentage of the total height of the initial top fin 102, then in the case where the total height of the initial top fin 102 is certain, the initial top fin 102 covered by the remaining initial isolation structure 140 is too small, and the subsequent height of the initial top fin 102 consumed by oxygen ions is correspondingly too small, which easily results in an insignificant effect of reducing the size of the bottom of the initial top fin 102, and thus in an insignificant effect of improving the uniformity of the lateral dimensions of the bottom and top of the top fin; if the initial top fin 102 covered by the remaining initial isolation structures 140 has a too large percentage of the total height of the initial top fin 102, then in the case where the initial top fin 102 has a certain total height, the initial top fin 102 covered by the remaining initial isolation structures 140 is too large, the subsequent initial top fin 102 consumed by oxygen ions has a correspondingly large height, and the subsequently formed top fin serves as an effective fin, which tends to affect the electrical performance of the device, for example: carrier mobility, and the like. For this reason, in the present embodiment, the height of the initial top fin 102 covered by the remaining initial isolation structure 140 is 5% to 15% of the total height of the initial top fin 102, for example: 10%,12%, etc.
Specifically, in this embodiment, the height of the initial top fin 102 covered by the remaining initial isolation structures 140 is 2 nm to 3 nm.
In this embodiment, in the step of removing a portion of the thickness of the initial isolation structure 125, the pad oxide layer 120 is also removed.
Referring to fig. 6 in combination, after forming the remaining initial isolation structures 140, the method for forming a semiconductor structure further includes: a protective layer 150 is formed on the top surface and sidewalls of the initial top fin 102.
The subsequent step further includes performing an annealing process, where the protective layer 150 is formed before the annealing process is performed, and the protective layer 150 can protect the initial top fin 102 exposed by the remaining initial isolation structure 140 during the subsequent annealing process, so as to prevent the portion of the initial top fin 102 exposed by the remaining initial isolation structure 140 from being consumed.
In this embodiment, the protection layer 150 is further formed on the surface of the remaining initial isolation structure 140.
In this embodiment, the material of the protection layer 150 is silicon oxide. Silicon oxide is a common material in the field of semiconductors, and the silicon oxide is selected, so that the process compatibility is improved; in addition, the subsequent step of removing the protection layer 150 is further included, the silicon oxide material is easy to be removed, and the silicon oxide has a larger etching selectivity ratio to silicon, so that the silicon oxide is selected as the material of the protection layer 150, which is beneficial to preventing the damage to the initial top fin 102 caused by the subsequent process of removing the protection layer 150.
In other embodiments, the material of the protective layer may be other suitable materials.
The thickness of the protective layer 150 is not too small nor too large. If the thickness of the protection layer 150 is too small, the protection effect of the protection layer on the initial top fin 102 in the subsequent annealing process is easily reduced; if the thickness of the protective layer 1509 is too large, not only is process time and material easily wasted, but also the difficulty in subsequent removal of the protective layer 150 is easily increased. For this purpose, in the present embodiment, the thickness of the protective layer 150 is 30 to 80 a, for example: 40, 50, etc.
In this embodiment, the passivation layer 150 is formed by an atomic layer deposition process. The atomic layer deposition process includes performing multiple atomic layer deposition cycles to form a film layer of a desired thickness. By selecting an atomic layer deposition process, the thickness uniformity of the protective layer 150 is improved, the thickness of the protective layer 150 can be precisely controlled, and the protective layer 150 with smaller thickness is formed; in addition, the gap filling performance and the step coverage of the atomic layer deposition process are good, which is beneficial to improving the conformal coverage capability of the protective layer 150; in addition, by choosing an atomic layer deposition process, it is also advantageous to reduce the consumption of the initial top fin 102.
Referring to fig. 7, after removing a portion of the thickness of the initial isolation structure 135, an annealing process 160 is performed, so that a portion of the thickness material of the sidewall of the initial fin 110, which contacts the oxide doped region, is consumed and converted into an oxide layer 170, the remaining initial bottom fin 101 serves as a bottom fin 201, the remaining initial top fin 102 serves as a top fin 202, and the bottom fin 201 and the top fin 202 are used to form a fin 200.
In this embodiment, during the annealing process 160, oxygen ions in the oxide doped region diffuse into the initial fin 110 through the sidewall of the initial fin 110, so as to consume a part of the thickness material of the sidewall of the initial fin 110, which contacts the oxide doped region, to form the oxide layer 170, so that the lateral dimension of the initial top fin 102 near the junction between the initial bottom fin 101 and the initial top fin 102 is reduced, that is, the sidewall of the top fin 202 near the junction between the bottom fin 201 and the top fin 202 is recessed in the lateral direction; in the semiconductor field, the initial fin 110 is generally a trapezoid structure with a small top and a large bottom, and the top fin 202 is generally used as an effective fin of the device, so that by laterally recessing the sidewall of the top fin 202 near the junction between the bottom fin 201 and the top fin 202, the difference between the lateral dimensions of the bottom of the effective fin (i.e., the top fin 202) and the top of the effective fin is reduced, thereby being beneficial to improving the verticality of the sidewall of the effective fin and the uniformity of the lateral dimensions of the bottom and the top of the effective fin, and further being beneficial to improving the performance of the device.
Furthermore, by doping oxygen ions in the initial isolation structure 135 to form an oxidized doped region and converting the sidewall of the portion of the thickness of the initial fin 110 in contact with the oxidized doped region into the oxide layer 170, the reduction of the lateral dimension difference between the bottom and top of the effective fin (i.e., the top fin 202) is combined with the step of forming the isolation structure, which is advantageous for simplifying the process steps and for improving the process compatibility and process integration.
In this embodiment, the oxide doped region is in contact with the sidewall of the initial fin 110 at the junction between the initial bottom fin 101 and the initial top fin 102 in the lateral direction, so that the oxide layer 170 is formed by consuming a portion of the thickness material on the top of the initial bottom fin 101 and a portion of the thickness material on the bottom of the initial top fin 102 in the step of performing the annealing process 160.
In this embodiment, the oxide layer 170 is formed by transforming a portion of the thickness of the initial fin portion 110, and the material of the oxide layer 170 is silicon oxide.
In this embodiment, the material of the oxide layer 170 is the same as that of the remaining initial isolation structure 140, so that in the step of forming an isolation structure by subsequently removing the remaining initial isolation structure 140 higher than the bottom fin 201, a portion of the oxide layer 170 may be removed, exposing the bottom of the top fin 202; moreover, the oxide layer 170 is an insulating material, and can jointly play a role of isolating the adjacent fin portions 200 with the isolation structure, and the oxide layer 170 does not need to be removed, so that the process compatibility is improved.
In this embodiment, the annealing process 160 is performed by a furnace tube annealing process.
The temperature of the annealing treatment 160 is not too low nor too high. If the temperature of the annealing process 160 is too low, the consumption of the single-sided sidewall of the initial fin 110 is easily reduced, which may further easily result in a less obvious effect of reducing the lateral dimension of the bottom of the initial top fin 102, or may easily reduce the consumption rate of the sidewall of the initial fin 110; if the temperature of the annealing process 160 is too high, damage to the structure of the initial fin 110 is easily caused, or when a doped region is formed in the initial fin 110 and the substrate 100, activation of ions in the doped region, doping profile, etc. are easily affected, and too high a temperature of the annealing process 160 may also easily cause excessive consumption of the single-sided sidewalls of the initial fin 110. For this purpose, in the present embodiment, the temperature of the annealing treatment 160 is 500 ℃ to 750 ℃.
In this embodiment, the consumption of the single-sided sidewall of the initial fin 110 is 5 to 20 a/m in the step of performing the annealing process 160 according to the temperature of the annealing process 160 and the actual time of the annealing process 160.
Referring to fig. 8 in combination, in this embodiment, after the annealing process 160 is performed, the method for forming a semiconductor structure further includes: the protective layer 150 is removed.
The protection layer 150 is removed to prepare for the subsequent formation of functional layers such as a gate oxide layer, a gate electrode layer, etc. on the fin 200.
In this embodiment, a wet etching process is used to remove the protective layer 150. The wet etch process has the property of isotropic etching, so that the protective layer 150 on the top surface and sidewalls of the top fin 202 and on the surface of the remaining initial isolation structure 140 can be removed.
Referring to fig. 9, after forming the fin 200, the remaining initial isolation structure 140 and the oxide layer 170, which are higher than the bottom fin 201, are removed to form an isolation structure 180.
The remaining initial isolation structures 140 and oxide layer 170 above the bottom fin 201 are removed, exposing the bottom of the top fin 202, exposing the lateral recessed portion of the sidewalls of the top fin 202, so that the top fin 202 can act as an active fin.
The isolation structure 180 serves as a Shallow Trench Isolation (STI) structure for isolating adjacent fins 200 from each other.
The remaining oxide layer 170 is located between the isolation structure 180 and the bottom fin 201, and can serve to isolate the adjacent fins 200 together with the isolation structure 180.
In this embodiment, the material of the oxide layer 170 and the remaining initial isolation structure 140 is the same, so the remaining initial isolation structure 140 and the oxide layer 170 above the bottom fin 201 can be removed in the same step.
In this embodiment, the remaining initial isolation structure 140 and oxide layer 170 above the bottom fin 201 are removed using a sicomin process.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 9, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a base, wherein the base comprises a substrate 100 and a fin portion 200 separated from the substrate 100, the fin portion 200 comprises a bottom fin portion 201 and a top fin portion 202 positioned on the bottom fin portion 201, the direction perpendicular to the extending direction of the fin portion 200 and perpendicular to the side wall of the fin portion 200 is transverse, and the side wall of the top fin portion 202 is recessed along the transverse direction at one side close to the junction of the bottom fin portion 201 and the top fin portion 202; the isolation structure 180 is located on the substrate 100 exposed by the fin 200, the isolation structure 180 covers sidewalls of the bottom fin 201 and exposes the top fin 202.
In the semiconductor structure of the embodiment of the present invention, the side wall of the top fin 202 is recessed along the lateral direction at the side close to the junction between the bottom fin 201 and the top fin 202, so that the lateral dimension of the side of the top fin 202 close to the junction between the bottom fin 201 and the top fin 202 is reduced; in the semiconductor field, the top fin 202 is generally used as an effective fin of the device, so that by making the sidewall of the top fin 202 near the junction between the bottom fin 201 and the top fin 202 recessed in the lateral direction, the difference between the lateral dimensions of the bottom of the effective fin (i.e., the top fin 202) and the top of the effective fin is reduced, thereby being beneficial to improving the verticality of the sidewall of the effective fin and the uniformity of the lateral dimensions of the bottom and the top of the effective fin, and further being beneficial to improving the performance of the device.
The substrate provides a process platform for a process.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
In this embodiment, the fin 200 is of an integral structure.
The top fin 202 serves as an active fin to provide a conductive channel during device operation.
In this embodiment, the material of the fin portion 200 is the same as the material of the substrate 100, and the material of the fin portion 200 is silicon. In other embodiments, the material of the fin portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin portion may be different from the material of the substrate.
In the top fin 202, the lateral wall near the boundary between the bottom fin 201 and the top fin 202 should not be too small or too large in the lateral recess. If the lateral recess distance is too small, the effect of the lateral dimension reduction of the bottom of the top fin 202 is not significant, making it difficult to improve the uniformity of the lateral dimensions of the bottom and top of the top fin 202; if the lateral recess is too large, it may easily cause the lateral dimension of the bottom of the top fin 202 to be too small, so that it may be difficult to support the top fin 202, and the risk of collapse of the top fin 202 may easily increase. For this purpose, in the embodiment, in the top fin 202, a sidewall near a boundary between the bottom fin 201 and the top fin 202 is recessed by 5 to 20 a in a lateral direction.
In the top fin 202, the height of the laterally recessed portion of the sidewall should not be too small or too large as a percentage of the total height of the top fin 202. If the height of the laterally recessed portion of the sidewall in the top fin 202 is too small as a percentage of the total height of the top fin 202, then, in the case of a certain total height of the top fin 202, the height of the laterally recessed portion of the sidewall in the top fin 202 is too small, which tends to result in an insignificant effect of reducing the lateral dimension of the bottom of the top fin 202 and thus an insignificant effect of improving the uniformity of the lateral dimension of the bottom and top of the top fin 202; if the height of the laterally recessed portion of the sidewalls in the top fin 202 is too large as a percentage of the total height of the top fin 202, then in the case of a certain total height of the top fin 202, the laterally recessed portion of the sidewalls in the top fin 202 is too large, and the laterally reduced portion of the top fin 202 is too large, the top fin 202 serves as an effective fin, which tends to affect the electrical performance of the device, for example: carrier mobility, and the like. For this reason, in the embodiment, in the top fin 202, the height of the portion of the sidewall recessed in the lateral direction is 5% to 15% of the total height of the top fin 202, for example: 10%,12%, etc.
Specifically, in the present embodiment, in the top fin 202, the height of the portion of the sidewall recessed along the lateral direction is 2 nm to 3 nm.
In this embodiment, the sidewalls of the fin 200 are recessed laterally at the interface between the bottom fin 201 and the top fin 202. The semiconductor structure further includes: an oxide layer 170 is located between the lateral recessed sidewalls of the bottom fin 201 and the isolation structure 180, the oxide layer 170 being formed by partial thickness material conversion of the sidewalls of the fin 200.
The sidewalls of the fin 200 are recessed laterally at the interface between the bottom fin 201 and the top fin 202, i.e., the bottom of the top fin 202 and the top of the bottom fin 201 are both recessed laterally, and the semiconductor structure further includes an oxide layer 170, since the bottom of the top fin 202 is recessed laterally by converting a portion of the thickness sidewall of the bottom of the original top fin to form an oxide layer and removing the oxide layer higher than the bottom fin 201. By laterally recessing the sidewalls of the fin 200 at the interface of the bottom fin 201 and the top fin 202, it is advantageous to ensure that the sidewalls of the bottom of the top fin 202 are laterally recessed during formation of the fin 200.
In this embodiment, the material of the oxide layer 170 is the same as that of the isolation structure 180, and the material of the oxide layer 170 is silicon oxide.
The oxide layer 170 is made of the same material as the remaining initial isolation structures 140, so that the oxide layer 170 can remain in the semiconductor structure, and the oxide layer 170 and the isolation structures can jointly serve to isolate the adjacent fin portions 200, which is beneficial to improving process compatibility.
In this embodiment, in the bottom fin 201, the height of the portion of the sidewall recessed in the lateral direction is 20 to 30 a.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (14)
1. A method of forming a semiconductor structure, comprising:
Providing a substrate, wherein the substrate comprises a substrate and an initial fin part separated from the substrate, the initial fin part comprises an initial bottom fin part and an initial top fin part positioned on the initial bottom fin part, and the direction perpendicular to the extending direction of the initial fin part and perpendicular to the side wall of the initial fin part is transverse;
forming an initial isolation structure on the substrate exposed by the initial fin part, wherein the initial isolation structure covers the side wall of the initial fin part;
doping oxygen ions in the initial isolation structure to form an oxidation doped region, wherein the oxidation doped region is in contact with the side wall, close to the junction between the initial bottom fin part and the initial top fin part, of the initial top fin part along the transverse direction;
removing part of the thickness of the initial isolation structure and the oxide layer to form a residual initial isolation structure, wherein part of the side wall of the initial top fin part is exposed by the residual initial isolation structure;
after removing the initial isolation structure with partial thickness, carrying out annealing treatment to consume partial thickness materials of the side wall, which is in contact with the oxidation doping region, in the initial fin part and convert the partial thickness materials into an oxidation layer, wherein the rest initial bottom fin part is used as a bottom fin part, the rest initial top fin part is used as a top fin part, and the bottom fin part and the top fin part are used for forming a fin part;
And after the fin parts are formed, removing the residual initial isolation structures higher than the bottom fin parts to form isolation structures.
2. The method of claim 1, wherein in the step of providing a substrate, a fin mask layer is further formed on top of the initial fin;
in the step of forming the initial isolation structure, the top surface of the initial isolation structure is higher than the top surface of the initial fin portion and lower than the top surface of the fin portion mask layer;
doping oxygen ions in the initial isolation structure by taking the fin mask layer as a mask to form the oxidation doped region;
after forming the oxidation doped region and before removing part of the thickness of the initial isolation structure, the method for forming the semiconductor structure further comprises the following steps: and removing the fin part mask layer.
3. The method of forming a semiconductor structure of claim 2, wherein forming the initial isolation structure comprises: forming an isolation material layer on the substrate exposed by the initial fin part, wherein the isolation material layer also covers the fin part mask layer;
taking the top surface of the fin part mask layer as a stop position, and carrying out planarization treatment on the isolation material layer to enable the top surface of the isolation material layer to be flush with the top surface of the fin part mask layer;
And removing part of the isolation material layer with the thickness, so that the top surface of the isolation material layer is lower than the top surface of the fin mask layer, and forming the initial isolation structure.
4. The method of claim 2, wherein in the step of forming the initial isolation structure, a distance from a top surface of the initial isolation structure to a top surface of the fin mask layer is 200 to 300 a along a normal direction of the substrate.
5. The method of claim 1, wherein the step of forming the oxidized doped region laterally contacts the initial fin sidewall at an interface between the initial bottom fin and the initial top fin.
6. The method of forming a semiconductor structure of claim 1, wherein in the step of removing a portion of the initial isolation structure, a height of the initial top fin covered by the remaining initial isolation structure is from 5% to 15% of a total height of the initial top fin.
7. The method of forming a semiconductor structure of claim 1, wherein oxygen ions are doped in said initial isolation structure using an ion implantation process.
8. The method of forming a semiconductor structure of claim 7, wherein the parameters of the ion implantation process comprise: the angle of implantation is 0 degrees to the normal of the substrate surface, the implantation energy is 10KeV to 100KeV, and the implantation dose is 1E13 atoms per square centimeter to 5E14 atoms per square centimeter.
9. The method of forming a semiconductor structure of claim 1, wherein the annealing treatment is at a temperature of 500 ℃ to 750 ℃.
10. The method of forming a semiconductor structure of claim 1, wherein said annealing is performed using a furnace tube annealing process.
11. The method of claim 1, wherein in the annealing step, a consumption of the single-sided sidewall in the initial fin is 5 to 20 a.
12. The method of forming a semiconductor structure of claim 1, wherein after forming the remaining initial isolation structures, prior to the annealing process, the method of forming a semiconductor structure further comprises: forming a protective layer on the top surface and the side wall of the initial top fin part;
after the annealing treatment, the method for forming the semiconductor structure further comprises the following steps: and removing the protective layer.
13. The method of forming a semiconductor structure of claim 12, wherein a thickness of the protective layer is between 30 and 80 angstroms.
14. The method of forming a semiconductor structure of claim 12, wherein the protective layer is removed using a wet etching process.
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| CN102446972A (en) * | 2010-10-08 | 2012-05-09 | 台湾积体电路制造股份有限公司 | Transistor having notched fin structure and method of making the same |
| CN104752186A (en) * | 2013-12-30 | 2015-07-01 | 台湾积体电路制造股份有限公司 | Semiconductor Liner Of Semiconductor Device |
| CN107919284A (en) * | 2016-10-10 | 2018-04-17 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
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| US9093531B2 (en) * | 2013-06-11 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of semiconductor device |
| US9966313B2 (en) * | 2016-08-05 | 2018-05-08 | Globalfoundries Inc. | FinFET device and method of manufacturing |
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| CN102446972A (en) * | 2010-10-08 | 2012-05-09 | 台湾积体电路制造股份有限公司 | Transistor having notched fin structure and method of making the same |
| CN104752186A (en) * | 2013-12-30 | 2015-07-01 | 台湾积体电路制造股份有限公司 | Semiconductor Liner Of Semiconductor Device |
| CN107919284A (en) * | 2016-10-10 | 2018-04-17 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
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