CN112864247B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112864247B
CN112864247B CN201911175343.0A CN201911175343A CN112864247B CN 112864247 B CN112864247 B CN 112864247B CN 201911175343 A CN201911175343 A CN 201911175343A CN 112864247 B CN112864247 B CN 112864247B
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initial
fin
forming
layer
isolation structure
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CN112864247A (en
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渠汇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a first device region, and the substrate comprises a substrate and an initial fin part protruding out of the substrate; forming an isolation structure on the substrate exposed by the initial fin part; forming an initial protection layer on the isolation structure, the top surfaces of the initial fin parts and the side walls of the initial fin parts exposed by the isolation structure; performing annealing treatment to convert the initial protective layer contacted with the isolation structure into a sacrificial layer, wherein the unconverted initial protective layer positioned on the top surface and the side wall of the initial fin part is used as a protective layer; removing the sacrificial layer of the first device region, and exposing a part of the side wall of the initial fin part, which is close to the isolation structure; the part of the initial fin part exposed by the protective layer and the isolation structure is used as an initial neck fin part; and thinning the initial neck fin portion side wall of the first device region along the direction perpendicular to the extending direction of the initial neck fin portion and perpendicular to the initial neck fin portion side wall to form the neck fin portion. The embodiment of the invention is beneficial to improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pinchoff) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (Subthreshold leakage), namely so-called Short Channel Effects (SCE), is more likely to occur.
Accordingly, to reduce the impact of short channel effects, semiconductor processes are gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of a device.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device region for forming a first device, and the substrate comprises a substrate and an initial fin protruding out of the substrate; forming an isolation structure on the substrate exposed by the initial fin part, wherein the isolation structure covers part of the side wall of the initial fin part, and the top surface of the isolation structure is lower than the top surface of the initial fin part; forming an initial protection layer on the isolation structure, the top surface of the initial fin portion and the side wall of the initial fin portion exposed by the isolation structure; performing annealing treatment to convert the initial protection layer contacted with the isolation structure into a sacrificial layer, wherein the unconverted initial protection layer positioned on the top surface and the side wall of the initial fin part is used as a protection layer; removing the sacrificial layer of the first device region, and exposing a part of the side wall of the initial fin part, which is close to the isolation structure; the part of the initial fin part exposed by the protective layer and the isolation structure is used as an initial neck fin part, and the part covered by the protective layer is used as a top fin part; and thinning the initial neck fin portion side wall of the first device region along the direction perpendicular to the extending direction of the initial neck fin portion and perpendicular to the initial neck fin portion side wall to form the neck fin portion.
Optionally, after the thinning treatment, the method for forming the semiconductor structure further includes: and oxidizing the protection layer and the neck fin part of the first device region to convert the protection layer and the neck fin part with partial thickness into a first gate oxide layer.
Optionally, the method for forming the semiconductor structure further includes: forming an oxide layer on the initial protective layer after forming the initial protective layer and before annealing treatment; in the step of annealing treatment, converting an initial protection layer between the oxide layer and the isolation structure and an initial protection layer with partial thickness which is positioned on the top and the side wall of the initial fin part and is in contact with the oxide layer into a sacrificial layer; and in the step of removing the sacrificial layer of the first device region, the oxide layer of the first device region is also removed.
Optionally, the substrate further includes a second device region for forming a second device, the second device having an operating frequency that is less than an operating frequency of the first device; in the step of forming the initial protection layer, the initial protection layer is further formed on the top surface of the isolation structure of the second device region, the side wall of the initial fin portion and the top surface; in the step of forming the oxide layer, the oxide layer is further formed on the initial protection layer of the second device region; and in the step of annealing treatment, converting a part of the initial protection layer which is positioned on the second device region and is in contact with the oxide layer into a first part of the gate dielectric layer, wherein the oxide layer, the first part of the gate dielectric layer and the rest of the initial protection layer which are positioned on the second device region are used for forming a second gate oxide layer.
Optionally, in the step of forming the initial protection layer, the thickness of the initial protection layer is a first thickness; in the step of forming the protective layer, the thickness of the protective layer on the side wall of the initial fin portion is a second thickness, and the second thickness is one third to two thirds of the first thickness.
Optionally, in the step of forming the oxide layer, the oxide layer on the initial protection layer on the top surface of the isolation structure has a third thickness, and the third thickness is 20 to 40 a.
Optionally, in the step of forming the oxide layer, a material of the oxide layer includes silicon oxide.
Optionally, the material of the isolation structure includes silicon oxide.
Optionally, in the step of forming the initial protection layer, a material of the initial protection layer includes silicon nitride, amorphous silicon, or silicon oxynitride.
Optionally, in the step of forming the initial protection layer, a thickness of the initial protection layer is 10 to 40 a.
Optionally, the process parameters of the annealing treatment include: the annealing temperature is 620 ℃ to 1020 ℃ and the annealing time is 0.5 hours to 6 hours.
Optionally, the method for forming the semiconductor structure further includes: and removing the isolation structure with partial thickness of the first device region before the thinning treatment of the initial cervical fin part of the first device region after the sacrificial layer of the first device region is removed.
Optionally, a wet etching process is used to remove the sacrificial layer of the first device region.
Optionally, a wet etching process is used to thin the sidewall of the initial cervical fin portion of the first device region.
Optionally, the material of the initial protection layer is silicon nitride, the material of the sacrificial layer is silicon oxide, the material of the isolation structure is silicon oxide, and the material of the oxide layer is silicon oxide.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: the substrate comprises a first device region for forming a first device, the substrate comprises a substrate and a device fin portion protruding out of the substrate of the first device region, the device fin portion comprises a bottom fin portion, a neck fin portion located on the bottom fin portion and a top fin portion located on the neck fin portion, and the side wall of the neck fin portion is retracted relative to the side wall of the top fin portion; the isolation structure is positioned on the substrate exposed by the device fin part, covers the side wall of the bottom fin part and exposes the neck fin part and the top fin part; and the protection layer is positioned on the top surface and the side wall of the top fin part and exposes the neck fin part.
Optionally, the material of the protective layer includes silicon nitride, amorphous silicon or silicon oxynitride.
Optionally, the thickness of the protective layer is 10 to 20 a.
Optionally, the height of the cervical fin is 5 nm to 10 nm along a direction perpendicular to the substrate.
Optionally, the sidewalls of the neck fin are recessed 20 to 60 angstroms relative to the sidewalls of the top fin on the same side.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure of the embodiment of the invention, the position of the initial cervical fin part is defined by the position of the sacrificial layer, the forming position of the sacrificial layer is defined by the position of the top surface of the isolation structure, and in the semiconductor field, the process for forming the isolation structure is mature, the position of the top surface of the isolation structure is easy to accurately control, and the height consistency of the top surface of the isolation structure is good, so that the method is beneficial to accurately controlling the position of the initial cervical fin part, further is beneficial to accurately controlling the position of the cervical fin part, and the height consistency of the bottom of the cervical fin part is good; moreover, the height of the initial cervical fin portion is defined by the thickness of the sacrificial layer, and the sacrificial layer is formed by converting an initial protection layer in contact with the isolation structure, so that the height of the initial cervical fin portion is easy to accurately control by controlling the thickness of the initial protection layer, and further the height of the cervical fin portion is easy to accurately control, and the height consistency of the cervical fin portion is improved.
Drawings
Fig. 1 to 4 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 5 to 11 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1 to 4, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a base is provided, the base comprising a first device region 1A forming a first device and a second device region (not shown) for forming a second device, the base comprising a substrate 1 and an initial fin 2 protruding from the substrate 1.
With continued reference to fig. 1, an isolation structure 3 is formed on the substrate exposed by the initial fin 2, the isolation structure 3 covers a portion of the sidewall of the initial fin 2, and the top surface of the isolation structure 3 is lower than the top surface of the initial fin 2.
Referring to fig. 2, a first oxidation treatment is performed on the initial fin portion 2 exposed by the isolation structure 3, so that a portion of the exposed sidewall and top of the initial fin portion 2 with a thickness of the isolation structure 3 is converted into a first gate oxide layer 4, and the remaining unconverted initial fin portion 2 located in the second device region is used as a first fin portion (not shown).
Referring to fig. 3, the first gate oxide layer 4 of the first device region 1A is removed.
Referring to fig. 4, after the first gate oxide layer 4 of the first device region 1A is removed, a second oxidation treatment is performed on the initial fin portion 2 exposed by the isolation structure 3 of the first device region 1A, so that the sidewall and the top of the portion of the thickness initial fin portion 2 exposed by the isolation structure 3 of the first device region 1A are converted into a second gate oxide layer 6, and the remaining unconverted initial fin portion 2 located in the first device region 1A is used as a second fin portion 5.
In the forming method, a Dual Gate Oxide (DGO) layer process is adopted, that is, two devices are formed on a substrate: the first device and the second device have different working frequencies so as to meet different design requirements.
The working frequencies of the first device and the second device are different, and the thicknesses of the gate oxide layers of the first device and the second device are correspondingly different, so that the gate oxide layers of the first device and the gate oxide layers of the second device are respectively formed in different steps in the forming method.
In the semiconductor field, the exposed portion of the second fin 5 by the isolation structure 3 is used as an effective fin. However, in the forming method, the initial fin portion of the first device region 1A is subjected to two oxidation treatments, and the entire initial fin portion 2 exposed by the isolation structure 3 is oxidized by both oxidation treatments, so that it is difficult to reduce the width dimension of the bottom of the effective fin portion of the first device region 1A, and further, the leakage current generated by the formed first device at the bottom of the effective fin portion is larger, and the performance of the formed device is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device region for forming a first device, and the substrate comprises a substrate and an initial fin protruding out of the substrate; forming an isolation structure on the substrate exposed by the initial fin part, wherein the isolation structure covers part of the side wall of the initial fin part, and the top surface of the isolation structure is lower than the top surface of the initial fin part; forming an initial protection layer on the isolation structure, the top surface of the initial fin portion and the side wall of the initial fin portion exposed by the isolation structure; performing annealing treatment to convert the initial protection layer contacted with the isolation structure into a sacrificial layer, wherein the unconverted initial protection layer positioned on the top surface and the side wall of the initial fin part is used as a protection layer; removing the sacrificial layer of the first device region, and exposing a part of the side wall of the initial fin part, which is close to the isolation structure; the part of the initial fin part exposed by the protective layer and the isolation structure is used as an initial neck fin part, and the part covered by the protective layer is used as a top fin part; and thinning the initial neck fin portion side wall of the first device region along the direction perpendicular to the extending direction of the initial neck fin portion and perpendicular to the initial neck fin portion side wall to form the neck fin portion.
In the method for forming the semiconductor structure of the embodiment of the invention, the position of the initial cervical fin part is defined by the position of the sacrificial layer, the forming position of the sacrificial layer is defined by the position of the top surface of the isolation structure, and in the semiconductor field, the process for forming the isolation structure is mature, the position of the top surface of the isolation structure is easy to accurately control, and the height consistency of the top surface of the isolation structure is good, so that the method is beneficial to accurately controlling the position of the initial cervical fin part, further is beneficial to accurately controlling the position of the cervical fin part, and the height consistency of the bottom of the cervical fin part is good; moreover, the height of the initial cervical fin portion is defined by the thickness of the sacrificial layer, and the sacrificial layer is formed by converting an initial protection layer in contact with the isolation structure, so that the height of the initial cervical fin portion is easy to accurately control by controlling the thickness of the initial protection layer, and further the height of the cervical fin portion is easy to accurately control, and the height consistency of the cervical fin portion is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 5 to 11 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5, a base is provided, the base comprising a first device region I for forming a first device, the base comprising a substrate 100 and an initial fin 110 protruding from the substrate 100.
The substrate provides a process platform for a process.
In this embodiment, the first device is a Core device (Core device). The core device mainly refers to a device used in the chip, usually adopts a lower voltage, and has a higher working frequency.
In this embodiment, the substrate further includes a second device region (not shown) for forming a second device, where the second device has a lower operating frequency than the first device, so that two different types of devices are subsequently formed on the substrate to meet the requirements of forming the different types of devices.
In this embodiment, the second device is an Input/Output device (Input/Output device). The input/output device generally refers to a device used when the chip interacts with the external interface, the operating voltage of such a device is generally higher, the operating voltage of the input/output device is generally greater than the operating voltage of the core device, and the operating frequency of the input/output device is generally less than the operating frequency of the core device.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
The initial fin 110 is used for forming a device fin later.
In this embodiment, the material of the initial fin portion 110 is the same as the material of the substrate 100, and the material of the initial fin portion 110 is silicon. In other embodiments, the material of the initial fin may be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the initial fin may be different from the material of the substrate.
With continued reference to fig. 5, an isolation structure 120 is formed on the substrate 100 where the initial fin 110 is exposed, the isolation structure 120 covers a portion of the sidewall of the initial fin 110, and a top surface of the isolation structure 120 is lower than a top surface of the initial fin 110.
The isolation structure 120 acts as a Shallow Trench Isolation (STI) to isolate adjacent devices.
An initial protection layer is formed on the top surfaces of the isolation structure 120 and the initial fin portion 110, and on the sidewalls of the initial fin portion 110 exposed by the isolation structure 120, and the isolation structure 120 is further used for oxidizing the initial protection layer in contact with the isolation structure 120 into a sacrificial layer in the subsequent annealing process.
Therefore, in this embodiment, the position of the top surface of the isolation structure 120 is also used to define the formation position of the subsequent sacrificial layer.
In this embodiment, the material of the isolation structure 120 is silicon oxide. By selecting the silicon oxide material, the silicon oxide is able to oxidize the initial protective layer in contact with the isolation structure 120 to a sacrificial layer during a subsequent anneal process.
In other embodiments, the material of the isolation structure may be other suitable materials, depending on the actual process.
Referring to fig. 6, an initial protection layer 130 is formed on the isolation structure 120 and the top surface of the initial fin 110, and on the sidewalls of the initial fin 110 where the isolation structure 120 is exposed.
After the subsequent annealing treatment, a part of the initial protection layer 130 is used to be converted into a sacrificial layer, and the remaining unconverted initial protection layer 130 is used to form a protection layer.
In this embodiment, the material of the initial protection layer 130 includes silicon nitride.
The silicon nitride material is a material commonly used in a semiconductor process, the process compatibility is high, the process cost is low, and the silicon nitride material can be converted into a silicon oxide material to be used as a sacrificial layer through a subsequent annealing process, so that the sacrificial layer is easy to remove subsequently; and the remaining unconverted initial protection layer 130 can be used as a protection layer, and the protection layer can protect the portion of the initial fin 110 covered by the protection layer in the subsequent thinning process of the sidewall of the initial cervical fin.
In other embodiments, the material of the initial protection layer may be amorphous silicon or silicon oxynitride.
In this embodiment, the initial protection layer 130 is formed by an atomic layer deposition process. The atomic layer deposition process includes performing multiple atomic layer deposition cycles to form an initial protective layer 130 of a desired thickness. The atomic layer deposition process is adopted, so that the thickness uniformity of the initial protective layer 130 is improved, and the thickness of the initial protective layer 130 can be accurately controlled; in addition, the gap filling performance and the step coverage of the atomic layer deposition process are good, and the conformal coverage capability of the initial protection layer 130 is correspondingly improved.
In this embodiment, in the step of forming the initial protection layer 130, the initial protection layer 130 is further formed on the top surface of the isolation structure 120 of the second device region, the sidewalls and the top surface of the initial fin 110.
The initial protective layer 130 formed in the second device region is used to prepare for the subsequent formation of the gate oxide layer of the second device.
In this embodiment, in the step of forming the initial protection layer 130, the thickness of the initial protection layer 130 is a first thickness.
The thickness of the initial protective layer 130 is not too small nor too large. If the thickness of the initial protection layer 130 is too small, after the subsequent annealing treatment, the thickness of the unconverted initial protection layer 130 located on the top surface and the side wall of the initial fin 110 is too small, that is, the thickness of the protection layer is too small, which easily causes that the protection layer is difficult to play a role in protecting the side wall of the initial neck fin in the subsequent thinning treatment, and the initial protection layer 130 contacting with the isolation structure 120 is subsequently converted into a sacrificial layer, and the height of the initial fin 130 exposed after the sacrificial layer of the first device region I is removed is too small, that is, the height of the initial neck fin is too small, which easily increases the difficulty of reducing the lateral dimension of the initial neck fin in the subsequent thinning treatment, and also easily causes that the height of the neck fin is too small, thereby causing that the neck fin is difficult to play a role in improving the leakage current; if the thickness of the initial protection layer 130 is too large, it is difficult to fully convert the initial protection layer 130 in contact with the isolation structure 120 into a sacrificial layer in the subsequent annealing process, so that the exposed initial fin 110 is too small after the sacrificial layer is subsequently removed, and the subsequent fin neck is too small. In this embodiment, the thickness of the initial protection layer 130 is 10 to 40 a.
Referring to fig. 7 in combination, in this embodiment, the method for forming a semiconductor structure further includes: after the initial protection layer 130 is formed, an oxide layer 140 is formed on the initial protection layer 130.
By forming the oxide layer 140 on the initial protection layer 130, the initial protection layer 130 on the surface of the isolation structure 120 is further covered by the oxide layer 140, which is beneficial to improving the oxidation rate of the initial protection layer 130 on the surface of the isolation structure in the subsequent annealing treatment step, so as to ensure that the initial protection layer 130 on the surface of the isolation structure 120 can be completely oxidized.
In this embodiment, in the step of forming the oxide layer 140, the oxide layer 140 is further formed on the initial protection layer 130 of the second device region.
The oxide layer 140 and the initial protection layer 130 located in the second device region are further used to form a gate oxide layer of the second device, and the thickness of the gate oxide layer of the second device is generally greater than that of the gate oxide layer of the first device, and by forming the oxide layer 140, it is also beneficial to make the thickness of the gate oxide layer of the second device meet the process requirements.
In this embodiment, in the step of forming the oxide layer 140, the material of the oxide layer 140 is silicon oxide. The silicon oxide is a commonly used material in the semiconductor process, which is beneficial to improving the process compatibility and reducing the process cost, and the silicon oxide material is selected so that the material of the oxide layer 140 is the same as that of the isolation structure 120, which is beneficial to improving the process compatibility and the oxidation effect of the initial protection layer 130 on the surface of the isolation structure 120; in addition, the subsequent step further includes a step of removing the oxide layer 140 of the first device region I, where a material of the oxide layer 140 is the same as a material of the subsequent sacrificial layer, so that the oxide layer 140 and the sacrificial layer located in the first device region I can be removed in the same step, thereby improving process integration.
In other embodiments, the material of the oxide layer may be other suitable materials, depending on the actual process.
In this embodiment, the oxide layer 140 is formed by an atomic layer deposition process. By selecting an atomic layer deposition process, the thickness uniformity of the oxide layer 140 is improved, and the conformal coverage capability of the oxide layer 140 is also improved.
In this embodiment, in the step of forming the oxide layer 140, the oxide layer 140 on the initial protection layer 130 on the top surface of the isolation structure 120 has a third thickness, which is not too small or too large. If the third thickness is too small, the risk that the initial protection layer 130 on the surface of the isolation structure 120 is not completely oxidized is easily increased, and the thickness of the gate oxide layer of the second device may be too small, so that it is difficult to meet the design requirement; if the third thickness is too large, the difficulty and risk of the subsequent process of removing the oxide layer 140 of the first device region I are easily increased. For this purpose, in this embodiment, the third thickness is 20 to 40 a.
Referring to fig. 8, an annealing process is performed to convert the initial protection layer 130 in contact with the isolation structure 120 into the sacrificial layer 150, and the unconverted initial protection layer 130 located on the top surface and the sidewall of the initial fin 110 is used as the protection layer 160.
The initial protection layer 130 in contact with the isolation structure 120 is converted into the sacrificial layer 150, so that after the sacrificial layer 150 is removed, the side wall of the initial fin portion 110 close to the isolation structure 120 can be exposed, and the exposed initial fin portion 110 serves as an initial neck fin portion, so that preparation is made for subsequent thinning treatment of the initial neck fin portion.
Moreover, the unconverted initial protection layer 130 located on the top surface and the sidewalls of the initial fin 110 is used as the protection layer 160, so that the protection layer 160 can protect the portion of the initial fin 110 covered by the protection layer 160 and prevent the sidewalls of the entire initial fin 110 exposed by the isolation structure 120 from being thinned in the subsequent thinning process.
In this embodiment, the oxide layer 140 is further formed on the sidewall of the initial protection layer 130, so that in the annealing process, the initial protection layer 130 between the oxide layer 140 and the isolation structure 120 and the initial protection layer 130 with a partial thickness on the top and the sidewall of the initial fin 110 and in contact with the oxide layer 140 are converted into the sacrificial layer 150.
Since the initial protection layer 130 on the surface of the isolation structure 120 contacts both the isolation structure 120 and the oxide layer 140, the initial protection layer 130 on the surface of the isolation structure 120 is oxidized at a higher rate than the initial protection layer 130 on the top of the initial fin 110 and the exposed sidewall of the isolation structure 120, and thus, after the initial protection layer 130 contacting the isolation structure 120 is completely converted into the sacrificial layer 150, a part of the unconverted initial protection layer 130 remains on the top and the sidewall of the initial fin 110 as the protection layer 160.
The annealing temperature of the annealing treatment is not too low nor too high. If the annealing temperature is too low, it is easy to convert the initial protection layer 130 on the surface of the isolation structure 120 into the sacrificial layer 150, or it is easy to reduce the rate of converting the initial protection layer 130 on the surface of the isolation structure 120 into the sacrificial layer 150, thereby wasting the residual productivity; if the annealing temperature is too high, not only is it easy for the initial protection layer 130 on the sidewalls and top of the initial fin 110 to be entirely oxidized, thereby making it difficult to form the protection layer 160, but also the structure of the initial fin 110 is easily damaged. For this reason, in this embodiment, the annealing temperature of the annealing treatment is 620 ℃ to 1020 ℃.
The annealing time of the annealing treatment is not too short nor too long. If the annealing time is too short, it is also easy to cause difficulty in converting the entirety of the initial protective layer 130 located on the surface of the isolation structure 120 into the sacrificial layer 150; if the annealing time is too long, after the initial protection layer 130 contacting the isolation structure 120 is converted into the sacrificial layer 150, the initial protection layer 130 on the top and the sidewalls of the initial fin 110 is also easily oxidized, and the structure of the initial fin 110 is also easily damaged. For this reason, in this embodiment, the annealing time of the annealing treatment is 0.5 hours to 6 hours.
In this embodiment, after the annealing treatment and the forming of the sacrificial layer 150 and the protective layer 160, the thickness of the protective layer 160 on the sidewall of the initial fin 110 is a second thickness, and the second thickness is one third to two thirds of the first thickness, so as to ensure that the protective layer 160 can protect the top of the initial fin 110 and the sidewall close to the top in the subsequent thinning process.
In this embodiment, in the annealing step, a portion of the initial protection layer 130 that is located on the second device region and is in contact with the oxide layer 140 is further converted into a first portion of the gate oxide layer (not shown), and the oxide layer 140, the first portion of the gate oxide layer, and the remaining initial protection layer 130 located on the second device region are used to form the second gate oxide layer.
Therefore, in the present embodiment, the step of forming the sacrificial layer 150 and the protective layer 160 of the first device region I is integrated with the step of forming the second gate oxide layer, which is beneficial to improving the process compatibility and the process integration.
Referring to fig. 9, the sacrificial layer 150 in the first device region I is removed, and a portion of the sidewall of the initial fin 110, which is close to the isolation structure 120, is exposed; the portion of the initial fin 110 exposed by the protective layer 160 and the isolation structure 120 serves as the initial cervical fin 12, and the portion covered by the protective layer 160 serves as the top fin 13.
The sacrificial layer 150 of the first device region I is removed, exposing a portion of the sidewalls of the initial fin 110 near the isolation structure 120, in preparation for subsequent thinning of the sidewalls of the initial cervical fin 12.
In this embodiment, the position of the initial cervical fin 12 is defined by the position of the sacrificial layer 150, and the forming position of the sacrificial layer 150 is defined by the position of the top surface of the isolation structure 120, so that in the semiconductor field, the process of forming the isolation structure 120 is mature, the position of the top surface of the isolation structure 120 is easy to be precisely controlled, and the height consistency of the top surface of the isolation structure 120 is better, therefore, in this embodiment, the position of the initial cervical fin 12 is favorable to be precisely controlled, and further, the position of the cervical fin is favorable to be precisely controlled, and the height consistency of the bottom of the cervical fin is better; moreover, the height of the initial cervical fin 12 is defined by the thickness of the sacrificial layer 150, and the sacrificial layer 150 is formed by transforming the initial protection layer 130 in contact with the isolation structure 120, so that the embodiment is easy to precisely control the height of the initial cervical fin 12 by controlling the thickness of the initial protection layer 130, thereby being beneficial to precisely controlling the height of the cervical fin and improving the uniformity of the height of the cervical fin.
In this embodiment, the portion of the initial fin 110 covered by the isolation structure 120 is used as the bottom fin 11.
In this embodiment, a wet etching process is used to remove the sacrificial layer 150 in the first device region I. The wet etching process has the characteristic of isotropic etching, so that the sacrificial layer 150 on the protective layer 160 and on the surface of the isolation structure 120 can be removed, and the wet etching process is simple to operate and low in process cost.
In this embodiment, the material of the sacrificial layer 150 is silicon oxide, and the etching solution of the wet etching process is diluted hydrofluoric acid (DHF) solution. The DHF solution is a material commonly used for etching silicon oxide in a semiconductor process, which is beneficial to improving process compatibility and reducing cost.
In this embodiment, the material of the oxide layer 140 is the same as that of the sacrificial layer 150, so in the step of removing the sacrificial layer 150 of the first device region I, the oxide layer 140 of the first device region I is also removed. By removing the sacrificial layer 150 and the oxide layer 140 of the first device region I, provision is made for the thickness of the gate oxide layer subsequently formed on the first device region I to be different from that of the gate oxide layer of the second device region.
In this embodiment, the height of the initial fin neck portion 12 is 5 nm to 10 nm along the direction perpendicular to the substrate 100, so that the process difficulty of the subsequent thinning treatment is reduced, and meanwhile, the height of the fin neck portion meets the process requirement, and further, the effect of the fin neck portion for reducing the leakage current of the device is more remarkable.
In this embodiment, the portion of the initial cervical fin 12 exposed by the sacrificial layer 150 in the first device region I after the removal of the initial cervical fin 110 is taken as an example.
In other embodiments, the method for forming the semiconductor structure further includes: and removing the isolation structure with partial thickness of the first device region before the thinning treatment of the initial cervical fin part of the first device region after the sacrificial layer of the first device region is removed.
The material of the isolation structure is the same as that of the sacrificial layer, so that the isolation structure with partial thickness of the first device region can be removed by adopting the wet etching process, and the process compatibility is improved.
Referring to fig. 10, the initial neck-fin portion 12 sidewall of the first device region I is thinned along a direction perpendicular to the extension direction of the initial fin portion 110 and perpendicular to the initial neck-fin portion 12 sidewall, so as to form the neck-fin portion 14.
In this embodiment, the position of the bottom of the initial cervical fin 12 is defined by the position of the top surface of the isolation structure 120, and the height of the initial cervical fin 12 is defined by the position of the sacrificial layer 150, so that the position of the initial cervical fin 12 is easy to be precisely controlled, thereby being beneficial to precisely controlling the position and the height of the cervical fin 14, and the height consistency of the bottom of the cervical fin 14 is better; moreover, the sidewalls of the initial fin portion 110 exposed by the protective layer 160 and the isolation structure 120 are thinned, so that the height of the initial neck fin portion 12 is smaller, and the thinning range is smaller, thereby being beneficial to reducing the difficulty of precisely controlling the thinning process, further being beneficial to improving the thickness uniformity of the thinning of the sidewalls of the initial neck fin portion 12, and correspondingly being beneficial to improving the width dimension uniformity of the neck fin portion 14.
In particular, in this embodiment, the first device is a core device, and the sidewall of the initial fin neck portion 12 in the first device region I is thinned, so that the effect of improving the leakage current of the core device by the fin neck portion 14 is facilitated, and further, the performance of the core device is facilitated to be significantly improved.
In this embodiment, after the thinning process, the bottom fin 11, the neck fin 14 located on the bottom fin 11, and the top fin 13 located on the neck fin 14 are used to form the device fin 170.
In this embodiment, a wet etching process is used to thin the sidewall of the initial fin neck portion 12 of the first device region I.
The wet etching process has the characteristic of isotropic etching, so that the side wall of the initial neck fin portion 12 can be etched along the direction perpendicular to the side wall of the initial neck fin portion 12, the effect of thinning the width of the initial neck fin portion 12 is achieved, the operation of the wet etching process is simple, and the process cost is low; in addition, compared with the reduction of the initial neck fin size achieved by oxidation treatment, the embodiment is also beneficial to reducing the influence on the size of the top fin 13 by adopting a wet etching process.
In this embodiment, the etching solution of the wet etching process is a mixed solution of hydrofluoric acid and ozone (FOM solution). The FOM solution has a larger etching selection ratio to silicon and silicon nitride, and the FOM solution has a larger etching selection ratio to silicon and silicon oxide, so that the protective layer 160 can play a corresponding role in protecting the top fin 13 in the thinning process, and the thinning process has small loss to the isolation structure 120, so that the control precision of the height of the neck fin 14 is improved; in addition, the FOM solution has good fluidity, which is beneficial to improving the transverse etching rate of the wet etching process to the initial cervical fin 12.
In the step of thinning, the thickness of the thinned single-sided sidewall of the initial cervical fin portion 12 is not too small or too large. If the thickness of the single-sided sidewall of the initial cervical fin portion 12 is too small, the effect of the width dimension reduction of the cervical fin portion 14 is not obvious; if the thickness of the thinned single-sided side wall of the initial neck fin portion 12 is too large, the width of the neck fin portion 14 is too small, the neck fin portion 14 is difficult to support the top fin portion 13, and the risk of collapse of the top fin portion 14 is easily increased. For this reason, in this embodiment, the thickness of the thinned single-sided sidewall of the initial cervical fin 12 is 20 to 60 a.
Referring to fig. 11 in combination, after the thinning process, the method for forming the semiconductor structure further includes: and oxidizing the protection layer 160 and the cervical fin portion 14 of the first device region I to convert the protection layer 160 and the cervical fin portion 14 with partial thickness into a first gate oxide layer 180.
The first gate oxide layer 180 is used to form a gate dielectric layer of a first device (i.e., a core device). In this embodiment, the thickness of the first gate oxide layer 180 is smaller than the thickness of the second gate oxide layer.
By converting the protection layer 160 and the partial thickness of the fin neck portion 14 into the first gate oxide layer 180, the process is simple, and the step of removing the protection layer 160 is not needed, which is beneficial to simplifying the process and improving the process compatibility.
Therefore, in this embodiment, the material of the first gate oxide layer 180 is silicon oxide.
In this embodiment, the protection layer 160 and the fin neck portion 14 of the first device region I are subjected to oxidation treatment by using a thermal oxidation growth process, for example: the thermal oxidation growth process may be an in situ steam generation process (ISSG).
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 10, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a base including a first device region I for forming a first device, the base including a substrate 100 and a device fin 170 protruding from the first device region I substrate 100, the device fin 170 including a bottom fin 11, a neck fin 14 on the bottom fin 11, and a top fin 13 on the neck fin 14, sidewalls of the neck fin 14 being recessed relative to sidewalls of the top fin 13; an isolation structure 120 on substrate 100 exposed by device fin 170, said isolation structure 120 covering sidewalls of said bottom fin 11 and exposing said neck fin 14 and top fin 13; and a protective layer 160 on top and sidewalls of the top fin 14 and exposing the neck fin 14.
The sidewalls of the neck-fin portion 14 are recessed relative to the sidewalls of the top-fin portion 13, i.e., the width dimension of the neck-fin portion 14 is smaller than the width dimension of the top-fin portion 13, which is advantageous for reducing leakage current of the device at the location of the neck-fin portion 14, thereby improving the performance of the device,
the substrate provides a process platform for a process. In this embodiment, the first device is a core device. The core device mainly refers to a device used in the chip, usually adopts a lower voltage, and has a higher working frequency.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
The device fin 170 is used to provide a conductive channel when the device is in operation.
In this embodiment, the material of device fin 170 is the same as the material of substrate 100, and the material of device fin 170 is silicon. In other embodiments, the material of the fin portion of the device may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin portion of the device may be different from the material of the substrate.
In this embodiment, device fin 170 is a unitary structure.
The height of the cervical fin 14 in the direction perpendicular to the substrate 100 is not too small nor too large. If the height of the cervical fin portion 14 is too small, the effect of the cervical fin portion 14 for improving the leakage current is not obvious; the neck fin 14 and the top fin 13 are used to form an effective fin of the device, and if the height of the neck fin 14 is too large, the effective fin tends to be reduced in size, thereby affecting the performance of the device. In this embodiment, the height of the cervical fin 14 is 5 nm to 10 nm in a direction perpendicular to the substrate 100.
The distance by which the sidewalls of the neck fin 14 are recessed relative to the sidewalls of the top fin 13 on the same side should not be too small nor too large. If the sidewall of the neck-fin portion 14 is too small in the retracted distance relative to the sidewall of the top-fin portion 13 on the same side, the effect of reducing the size of the neck-fin portion 14 is not obvious, and it is difficult to reduce the leakage current; if the sidewall of the neck fin 14 is too far from the sidewall of the top fin 13 on the same side, the neck fin 14 is difficult to support the top fin 13, and the risk of collapse of the top fin 14 is easily increased. For this purpose, in this embodiment, the sidewalls of the neck fin 14 are recessed 20 to 60 a/m with respect to the sidewalls of the top fin 13 on the same side.
The isolation structure 120 acts as a Shallow Trench Isolation (STI) to isolate adjacent devices.
In this embodiment, the top surface of the isolation structure 120 also serves to define the location of the bottom of the cervical fin 14.
In the semiconductor field, the process of forming the isolation structure 120 is mature, the position of the top surface of the isolation structure 120 is easy to be accurately controlled, and the height consistency of the top surface of the isolation structure 120 is good, so that the position of the neck fin portion 14 is beneficial to be accurately controlled, the height consistency of the bottom of the neck fin portion 14 is good, and the performance of the device is correspondingly improved.
In this embodiment, the material of the isolation structure 120 is silicon oxide. In other embodiments, the material of the isolation structure may also be other suitable materials.
The neck fin 14 is formed by thinning the sidewall of the initial neck fin, and the protective layer 160 is used to protect the top fin 13 during the thinning process, so as to prevent the width dimension of the top fin 13 from being affected.
The protective layer 160 is further used for forming a first gate oxide layer through a subsequent oxidation process.
In this embodiment, the material of the protective layer 160 includes silicon nitride. The silicon nitride material is a material commonly used in a semiconductor process, the process compatibility is high, the process cost is low, and the etching selectivity of the silicon nitride material and the silicon material is relatively large, so that the protection layer 160 can protect the top fin portion 13 in the thinning process.
In other embodiments, the material of the protective layer may be amorphous silicon or other suitable materials such as silicon oxynitride.
The thickness of the protective layer 160 is not too small nor too large. If the thickness of the protective layer 160 is too small, the protective layer 160 is easily consumed prematurely during the thinning process, thereby making it difficult to protect the top fin 13; if the thickness of the protective layer 160 is too large, the protective layer 160 is further oxidized to form a first gate oxide layer, and the thickness of the protective layer 160 is too large, which easily results in the thickness of the first gate oxide layer being too large, so that the thickness of the first gate oxide layer is difficult to meet the design requirement. In this embodiment, the thickness of the protective layer 160 is 10 to 20 a.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first device region for forming a first device, and the substrate comprises a substrate and an initial fin protruding out of the substrate;
forming an isolation structure on the substrate exposed by the initial fin part, wherein the isolation structure covers part of the side wall of the initial fin part, and the top surface of the isolation structure is lower than the top surface of the initial fin part;
forming an initial protection layer on the isolation structure, the top surface of the initial fin portion and the side wall of the initial fin portion exposed by the isolation structure;
performing annealing treatment to convert the initial protection layer contacted with the isolation structure into a sacrificial layer, wherein the unconverted initial protection layer positioned on the top surface and the side wall of the initial fin part is used as a protection layer;
removing the sacrificial layer of the first device region, and exposing a part of the side wall of the initial fin part, which is close to the isolation structure; the part of the initial fin part exposed by the protective layer and the isolation structure is used as an initial neck fin part, and the part covered by the protective layer is used as a top fin part;
and thinning the initial neck fin portion side wall of the first device region along the direction perpendicular to the extending direction of the initial neck fin portion and perpendicular to the initial neck fin portion side wall to form the neck fin portion.
2. The method of forming a semiconductor structure of claim 1, wherein after the thinning process, the method of forming a semiconductor structure further comprises: and oxidizing the protection layer and the neck fin part of the first device region to convert the protection layer and the neck fin part with partial thickness into a first gate oxide layer.
3. The method of forming a semiconductor structure of claim 1, further comprising: forming an oxide layer on the initial protective layer after forming the initial protective layer and before annealing treatment;
in the step of annealing treatment, converting an initial protection layer between the oxide layer and the isolation structure and an initial protection layer with partial thickness which is positioned on the top and the side wall of the initial fin part and is in contact with the oxide layer into a sacrificial layer;
and in the step of removing the sacrificial layer of the first device region, the oxide layer of the first device region is also removed.
4. The method of forming a semiconductor structure of claim 3, wherein the substrate further comprises a second device region for forming a second device, the second device having an operating frequency that is less than an operating frequency of the first device;
In the step of forming the initial protection layer, the initial protection layer is further formed on the top surface of the isolation structure of the second device region, the side wall of the initial fin portion and the top surface;
in the step of forming the oxide layer, the oxide layer is further formed on the initial protection layer of the second device region;
in the step of annealing, a portion of the initial protective layer on the second device region in contact with the oxide layer is further converted into a first portion of the gate oxide layer, and the oxide layer, the first portion of the gate oxide layer, and the remaining initial protective layer on the second device region are used to form a second gate oxide layer.
5. The method of forming a semiconductor structure of claim 3, wherein in the step of forming the initial protective layer, a thickness of the initial protective layer is a first thickness;
in the step of forming the protective layer, the thickness of the protective layer on the side wall of the initial fin portion is a second thickness, and the second thickness is one third to two thirds of the first thickness.
6. The method of forming a semiconductor structure of claim 3, wherein in the step of forming the oxide layer, the oxide layer on the initial protective layer on the top surface of the isolation structure has a third thickness, the third thickness being 20 to 40 a.
7. The method of forming a semiconductor structure of claim 3, wherein in the step of forming the oxide layer, the material of the oxide layer comprises silicon oxide.
8. The method of forming a semiconductor structure of claim 1, wherein the material of the isolation structure comprises silicon oxide.
9. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the initial protective layer, the material of the initial protective layer comprises silicon nitride, amorphous silicon, or silicon oxynitride.
10. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the initial protective layer, a thickness of the initial protective layer is from 10 to 40 angstroms.
11. The method of forming a semiconductor structure of claim 1, wherein the process parameters of the annealing process comprise: the annealing temperature is 620 ℃ to 1020 ℃ and the annealing time is 0.5 hours to 6 hours.
12. The method of forming a semiconductor structure of claim 1, further comprising: and removing the isolation structure with partial thickness of the first device region before the thinning treatment of the initial cervical fin part of the first device region after the sacrificial layer of the first device region is removed.
13. The method of forming a semiconductor structure of claim 1, wherein a wet etch process is used to remove the sacrificial layer of the first device region.
14. The method of forming a semiconductor structure of claim 1, wherein a wet etching process is used to thin sidewalls of an initial cervical fin of the first device region.
15. The method of claim 3, wherein the material of the initial protection layer is silicon nitride, the material of the sacrificial layer is silicon oxide, the material of the isolation structure is silicon oxide, and the material of the oxide layer is silicon oxide.
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