CN111048417B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN111048417B
CN111048417B CN201811191867.4A CN201811191867A CN111048417B CN 111048417 B CN111048417 B CN 111048417B CN 201811191867 A CN201811191867 A CN 201811191867A CN 111048417 B CN111048417 B CN 111048417B
Authority
CN
China
Prior art keywords
layer
forming
dummy gate
gate
gate layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811191867.4A
Other languages
Chinese (zh)
Other versions
CN111048417A (en
Inventor
王楠
王颖倩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201811191867.4A priority Critical patent/CN111048417B/en
Publication of CN111048417A publication Critical patent/CN111048417A/en
Application granted granted Critical
Publication of CN111048417B publication Critical patent/CN111048417B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a substrate and discrete fin parts protruding on the substrate; forming a pseudo gate structure crossing the fin part, wherein the pseudo gate structure comprises a first pseudo gate layer and a second pseudo gate layer positioned on the first pseudo gate layer, the width of the first pseudo gate layer gradually increases from bottom to top, and the side wall of the second pseudo gate layer is perpendicular to the top surface of the substrate; forming source-drain doping layers in fin parts on two sides of the pseudo gate structure; forming a dielectric layer on the source-drain doped layer, wherein the dielectric layer exposes the top of the pseudo gate structure; removing the pseudo gate structure and forming an opening in the dielectric layer; and forming a metal gate structure filling the opening. According to the invention, the included angle between the side wall of the first pseudo gate layer and the top wall of the fin part is smaller than 90 degrees, so that the process space is large when the first pseudo gate layer is removed later, the residue is not easy to occur, on the basis, the side wall of the second pseudo gate layer is vertical to the top surface of the substrate, the transverse space of the top surface of the fin part is saved, the size of a device is further reduced, and the performance of a semiconductor structure is optimized.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short-channel effect (SCE), is more likely to occur.
Accordingly, to reduce the impact of short channel effects, semiconductor processes are gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
In the FinFET device, a dummy gate structure covering part of the top wall and part of the side wall of the fin part is formed, and the dummy gate structure occupies space for forming a metal gate structure in a subsequent process, but the performance of the formed semiconductor structure is poor.
Disclosure of Invention
The problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are used for optimizing the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and discrete fin parts protruding on the substrate; forming a dummy gate structure crossing the fin part, wherein the dummy gate structure covers part of the top wall and part of the side wall of the fin part, the dummy gate structure comprises a first dummy gate layer and a second dummy gate layer positioned on the first dummy gate layer, the width of the first dummy gate layer gradually increases from bottom to top, and the side wall of the second dummy gate layer is perpendicular to the top surface of the substrate; forming source-drain doped layers in the fin parts at two sides of the pseudo gate structure; forming a dielectric layer on the source-drain doped layer, wherein the dielectric layer exposes the top of the pseudo gate structure; removing the pseudo gate structure and forming an opening in the dielectric layer; and forming a metal gate structure filling the opening.
Optionally, the forming step of the dummy gate structure includes: forming a first pseudo gate material layer covering the fin part and a second pseudo gate material layer positioned on the first pseudo gate material layer; patterning the first pseudo gate material layer and the second pseudo gate material layer to form a transition first pseudo gate layer and a second pseudo gate layer positioned on the transition first pseudo gate layer, wherein the side wall of the transition first pseudo gate layer is perpendicular to the top surface of the fin part; and etching the side wall of the transition first pseudo gate layer by adopting a wet etching process to form the first pseudo gate layer.
Optionally, the material of the first dummy gate layer is silicon germanium, and the material of the second dummy gate layer is silicon; the etching solution adopted in the wet etching process is tetramethyl ammonium hydroxide solution.
Optionally, the forming step of the dummy gate structure includes: forming a first pseudo gate material layer covering the fin part and a second pseudo gate material layer positioned on the first pseudo gate material layer; patterning the second dummy gate material layer to form a second dummy gate layer; and etching the first pseudo gate material layer exposed by the second pseudo gate layer to form a first pseudo gate layer.
Optionally, the step of forming the first dummy gate material layer includes: forming a first gate film covering the fin portion; flattening the first gate film; and etching back the first gate film with partial thickness so that the top of the remaining first gate film is flush with or lower than the top wall of the fin part, and forming a first pseudo gate material layer.
Optionally, the step of forming the first gate film includes: and depositing for multiple times by adopting a chemical vapor deposition process to form the first grid film.
Optionally, in the step of the chemical vapor deposition process, a deposition thickness of 1 nm to 2 nm is formed each time.
Optionally, the material of the first gate film is silicon germanium, and in the step of the chemical vapor deposition process, the germanium ion duty ratio in the last deposition is lower than the germanium ion duty ratio in the previous deposition.
Optionally, the material of the first dummy gate layer is silicon germanium, and the ratio of germanium ions in the first dummy gate layer is sequentially reduced from bottom to top.
Optionally, the mole volume percentage of germanium ions in the first dummy gate layer is 20% to 80%.
Optionally, an included angle between the side wall of the first pseudo gate layer and the top surface of the substrate is alpha, and alpha is more than or equal to 80 degrees and less than 90 degrees.
Optionally, the bottom surface of the second dummy gate layer is lower than the top wall of the fin portion or is flush with the top wall of the fin portion.
Optionally, the width of the second dummy gate layer is the same as the width of the top surface of the first dummy gate layer along a direction perpendicular to the side wall of the second dummy gate layer.
Optionally, the material of the second dummy gate layer is silicon, silicon oxide or silicon oxynitride.
Optionally, the method for forming the semiconductor structure includes: after the dummy gate structure is formed, forming a first side wall layer on the side wall of the first dummy gate layer before forming a source-drain doped layer; and after the first side wall layer is formed, forming a second side wall on the side wall of the first side wall layer and the side wall of the second pseudo gate layer.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a fin portion separated from the substrate; a metal gate structure crossing the fin portion, wherein the metal gate structure covers part of the top wall and part of the side wall of the fin portion; the source-drain doping layers are positioned in the fin parts at two sides of the metal gate structure; the metal gate structure comprises a first gate layer and a second gate layer positioned on the first gate layer, the side wall of the second gate layer is perpendicular to the top surface of the substrate, and the width of the first gate layer is gradually wider from bottom to top.
Optionally, an included angle between the side wall of the first gate layer and the top surface of the substrate is alpha, and alpha is more than or equal to 80 degrees and less than 90 degrees.
Optionally, the materials of the second gate layer and the first gate layer are magnesium-tungsten alloy.
Optionally, the bottom surface of the second gate layer is lower than the top wall of the fin portion or is flush with the top wall of the fin portion.
Optionally, the semiconductor structure further includes a first sidewall layer, located on a sidewall of the first gate layer; and the second side wall layer is positioned on the side walls of the first side wall layer and the second grid layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the width of the first pseudo gate layer positioned at the lower layer is gradually increased from bottom to top, so that the included angle between the side wall of the first pseudo gate layer and the top wall of the fin part is smaller than 90 degrees, the process space for removing the first pseudo gate layer in the subsequent removing process of the pseudo gate structure is large, the first pseudo gate layer is removed, and particularly the first pseudo gate layer positioned at the corner of the bottom can be effectively removed, and the problem of etching residues of the pseudo gate structure is avoided; in addition, the side wall of the second pseudo gate layer positioned on the upper layer is vertical to the top of the substrate, so that the transverse space of the top of the pseudo gate structure is saved, and the size of the semiconductor structure is reduced. Therefore, the invention solves the problem of etching residues of the pseudo gate structure and simultaneously can ensure that the semiconductor structure meets the development trend of miniaturization and microminiaturization of devices.
In an alternative scheme, three sides of the metal gate structure surround the channel, wherein the control capability of the part, which is contacted with the top wall of the fin part, of the metal gate structure on the channel is larger than the control capability of the part, which is contacted with the side wall of the fin part, of the metal gate structure on the channel. Therefore, when the lateral width of the dummy gate structure is unchanged, the bottom surface of the second dummy gate layer is flush with or lower than the top wall of the fin portion, so that the contact area between the second dummy gate layer and the top wall of the fin portion is the largest, that is, the contact area between the metal gate structure formed in the later stage and the top wall of the fin portion is the largest, and the corresponding control capability of the metal gate structure on the channel is good.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure formed by a method;
fig. 2 to 16 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 17 to 20 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1, a schematic structure diagram corresponding to a method of forming a semiconductor structure is shown.
Referring to fig. 1, a base is provided, the base comprising a substrate 1, a discrete fin 2 protruding above the substrate 1, and a dummy gate structure 3 crossing the fin 2, the dummy gate structure 3 covering part of the top wall and part of the side walls of the fin 2.
The dummy gate structure 3 includes a dummy gate oxide layer 31 conformally covering portions of the top and side walls of the fin, and a dummy gate layer 32 on the dummy gate oxide layer 31. In the dummy gate layer 32, the length perpendicular to the side wall direction of the dummy gate structure 3 is taken as the width, the position of the fin portion 2 is the upper position relative to the substrate 1, the width of the dummy gate layer 32 is gradually widened from bottom to top, and the included angle between the side wall of the dummy gate layer 32 and the top wall of the fin portion 2 is alpha, and is 80 degrees less than or equal to alpha and less than 90 degrees, so that the dummy gate layer 32 is not easy to remain when removed.
Specifically, the material of the dummy gate structure 3 is silicon germanium.
With continued reference to fig. 1, the included angle between the dummy gate layer 32 and the top wall of the fin portion 2 is α, and α is 80 ° or less and is less than 90 ° degrees, so that the dummy gate layer 32 is not easy to remain when removed. Taking the direction perpendicular to the side wall of the dummy gate structure 3 as the transverse direction, the included angle between the dummy gate layer 32 and the dummy gate oxide layer 31 makes the transverse width of the top end of the dummy gate layer 32 larger than the transverse width of the bottom end of the dummy gate layer 32, so that the transverse space at the top end of the fin portion 2 is wasted.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and discrete fin parts protruding on the substrate; forming a dummy gate structure crossing the fin part, wherein the dummy gate structure covers part of the top wall and part of the side wall of the fin part, the dummy gate structure comprises a first dummy gate layer and a second dummy gate layer positioned on the first dummy gate layer, the width of the first dummy gate layer gradually increases from bottom to top, and the side wall of the second dummy gate layer is perpendicular to the top surface of the substrate; forming source-drain doped layers in the fin parts at two sides of the pseudo gate structure; forming a dielectric layer on the source-drain doped layer, wherein the dielectric layer exposes the top of the pseudo gate structure; removing the pseudo gate structure and forming an opening in the dielectric layer; and forming a metal gate structure filling the opening.
According to the embodiment of the invention, the dummy gate structure is divided into two layers, the width of the first dummy gate layer gradually increases from bottom to top, so that the included angle between the side wall of the first dummy gate layer and the top wall of the fin part is smaller than 90 degrees, and therefore, the process space is large when the first dummy gate layer is removed later, and the first dummy gate layer is not easy to remain; the side wall of the second pseudo gate layer is perpendicular to the top surface of the substrate, so that the transverse space of the top surface of the fin part is saved, the size of the device is further reduced, the power consumption is reduced, and the performance of the semiconductor structure is optimized.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 2 to 16 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a base is provided, the base comprising a substrate 100, a discrete fin 101 protruding above the substrate 100.
The fin portion 101 is separated on the substrate 100, and the material of the fin portion 101 is the same as that of the substrate 100 and is silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Semiconductor devices, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, or inductors, etc., can also be formed within the substrate 100. The surface of the substrate 100 may further be formed with an interface layer, and the material of the interface layer may be silicon oxide, silicon nitride, silicon oxynitride, or the like.
Note that the semiconductor structure further includes a hard mask layer 103 formed on the top wall of the fin 101.
In this embodiment, the material of the hard mask layer 103 is silicon nitride. In other embodiments, the material of the hard mask layer may also be silicon oxynitride.
Note that, the thermal expansion coefficient of the material of the hard mask layer 103 and the material of the fin portion 101 is greatly different, if the hard mask layer 103 is directly formed on the fin portion 101, the hard mask layer 103 is easy to crack or even fall off, so that the hard mask layer cannot function as a mask layer, and therefore, a dummy gate oxide layer 1041 is formed between the hard mask layer 103 and the fin portion 101, and the dummy gate oxide layer 1041 plays a role of buffering.
In this embodiment, the material of the dummy gate oxide layer 1041 is silicon oxide.
In this embodiment, an isolation layer 102 is formed on the substrate 100 where the fin portion 101 is exposed. The isolation layer 102 is used to isolate adjacent devices.
In this embodiment, the material of the isolation layer 102 is silicon oxide. In other embodiments, the material of the isolation layer is silicon oxide, silicon nitride or silicon oxynitride.
Referring to fig. 3 to 12, a dummy gate structure 104 is formed across the fin 101, the dummy gate structure 104 covers a portion of the top wall and a portion of the side wall of the fin 101, the dummy gate structure 104 includes a first dummy gate layer 1046 and a second dummy gate layer 1045 on the first dummy gate layer 1046, the width of the first dummy gate layer 1046 gradually increases from bottom to top, and the side wall of the second dummy gate layer 1045 is perpendicular to the top surface of the substrate 100.
The dummy gate structure 104 occupies a space for a metal gate structure formed in a subsequent process.
Note that the dummy gate structure 104 further includes a dummy gate oxide layer 1041.
As shown in fig. 3 to 4, the step of forming the dummy gate structure 104 across the fin 101 includes: a first dummy gate material layer 1042 covering the fin 101 and a second dummy gate material layer 1043 on the first dummy gate material layer 1042 are formed.
The first dummy gate material layer 1042 and the second dummy gate material layer 1043 provide for forming the first dummy gate layer and the second dummy gate layer in the subsequent process.
In this embodiment, the step of forming the first dummy gate material layer 1042 includes: forming a first gate film 106 covering the fin portion 101, and performing planarization treatment on the first gate film 106; and etching back a part of the first gate film 106, so that the top of the remaining first gate film is flush with the top wall of the fin portion 101 or lower than the top wall of the fin portion 101, thereby forming a first dummy gate material layer 1042.
In this embodiment, the position of the fin 101 is upper relative to the position of the substrate 100, the material of the first gate film 106 is silicon germanium, and the ratio of germanium ions in the first gate film 106 decreases from bottom to top. The proportion of germanium ions in the first gate film 106 is reduced from bottom to top in order to prepare for etching the transitional first dummy gate layer in the subsequent process to form a first dummy gate layer that is gradually wider from bottom to top.
The first gate film 106 provides for the formation of the first dummy gate layer in a subsequent process.
Specifically, the mole volume percentage of germanium ions in the first gate film 106 is 20% to 80%.
It should be noted that the molar volume percentage of germanium ions in the first gate film 106 should not be too large or too small. Because the lattice sizes of the germanium ions and the silicon ions are different, if the ratio of the germanium ions in the first gate film 106 is too high, stress is introduced into the subsequently formed first dummy gate layer, so that the interface performance of the first dummy gate layer is poor, and the formed silicon germanium lattice is defective. If the germanium ion ratio is too small, the etched rate of the silicon germanium may be reduced. Accordingly, the mole volume percentage of germanium ions in the first gate film 106 is 20% to 80%.
In this embodiment, the step of forming the first gate film 106 covering the fin 101 includes: the first gate film 106 is formed by multiple depositions using a chemical vapor deposition process.
In the step of the chemical vapor deposition process, the deposition thickness is 1 nm to 2 nm each time.
From bottom to top, the germanium ions in the material of the first gate film 106 are different from each other in the material of the first gate film, and the germanium ions in the next deposition have a lower ratio than the germanium ions in the previous deposition.
In this embodiment, the top of the first dummy gate material layer 1042 is flush with the top wall of the fin portion 101 or lower than the top wall of the fin portion 101, that is, the bottom of the second dummy gate material layer 1043 is lower than the top wall of the fin portion 101 or flush with the top wall of the fin portion 101. Therefore, the bottom surface of the second dummy gate layer 1045 formed later is lower than the top wall of the fin portion 101 or is flush with the top wall of the fin portion 101.
In the process of performing the planarization treatment on the first gate film 106, the hard mask layer 103 plays a role in defining an etching stop; and etching back a part of the thickness of the first gate film 106, and removing the hard mask layer 103 in the process of forming the first dummy gate material layer 1042.
In this embodiment, the step of forming the second dummy gate material layer 1043 includes: a second gate film (not shown) is formed to cover the first dummy gate material layer 1042, the second gate film is planarized and the second gate film is etched back to a partial thickness to form a second dummy gate material layer 1043.
As shown in fig. 5 to 8, fig. 5 is a three-dimensional model in which a first dummy gate material layer 1044 and a second dummy gate layer 1045 are formed across the fin 101, and referring to the three-dimensional model of fig. 5, fig. 6 is a cross-sectional view in the A-A direction in fig. 5, fig. 7 is a cross-sectional view in the B-B direction in fig. 5, and fig. 8 is a cross-sectional view in the C-C direction in fig. 5.
The step of forming the dummy gate structure 104 across the fin 101 further includes: the first dummy gate material layer 1042 and the second dummy gate material layer 1043 are patterned to form a transition first dummy gate layer 1044 and a second dummy gate layer 1045 on the transition first dummy gate layer 1044, and the sidewall of the transition first dummy gate layer 1044 is perpendicular to the top surface of the fin 101.
The step of forming the transition first dummy gate layer 1044 and the second dummy gate layer 1045 on the transition first dummy gate layer 1044 includes: a shielding layer 105 is formed on the second dummy gate material layer 1043, and the second dummy gate material layer 1043 and the first dummy gate material layer 1042 are etched by using the shielding layer 105 as a mask, so as to form a transition first dummy gate layer 1044 and a second dummy gate layer 1045 on the transition first dummy gate layer 1044.
Referring to fig. 9 to 12, fig. 9 is a three-dimensional model in which a dummy gate structure 104 crossing the fin 101 is formed, and referring to the three-dimensional model of fig. 9, fig. 10 is a cross-sectional view based on the D-D direction in fig. 9, fig. 11 is a cross-sectional view in the E-E direction in fig. 9, and fig. 12 is a cross-sectional view in the F-F direction in fig. 9.
The width of the first dummy gate layer 1046 is gradually increased from bottom to top, and the width is perpendicular to the sidewall direction of the second dummy gate layer 1045.
In this embodiment, the width of the second dummy gate layer 1045 is the same as the width of the top surface of the first dummy gate layer 1046.
In this embodiment, in the step of etching the transition first dummy gate layer 1044 to form the first dummy gate layer 1046, the etching process etches the transition first dummy gate layer 1044 at a rate greater than that of the second dummy gate layer 1045.
In this embodiment, the material of the transition first dummy gate layer 1044 is silicon germanium, and the material of the second dummy gate layer 1045 is silicon; in the step of forming the first dummy gate layer 1046 by etching the transition first dummy gate layer 1044, the etched rate of the silicon germanium is greater than the etched rate of the silicon.
In other embodiments, the material of the second dummy gate layer 1045 may be polysilicon, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.
In this embodiment, the material of the transition first dummy gate layer 1044 is silicon germanium, and the material of the second dummy gate layer 1045 is silicon; the etching solution adopted in the wet etching process is tetramethyl ammonium hydroxide solution.
Since the proportion of germanium ions in the transition first dummy gate layer 1044 decreases in order from bottom to top, the etching rate of the silicon germanium in the lower portion of the transition first dummy gate layer 1044 is higher than that in the upper portion, and the width of the first dummy gate layer 1046 is gradually increased from bottom to top.
It should be noted that, the included angle α between the sidewall of the first dummy gate layer 1046 and the top surface of the substrate 100 should not be too large or too small. If the included angle alpha is too small, the formed process time is too long, and the etching effect is difficult to control; if the included angle α is too large, the process space for removing the dummy gate structure 104 in the subsequent process is too small, and residues are generated when removing the first dummy gate layer 1046. For this purpose, in this embodiment, the included angle between the sidewall of the first dummy gate layer 1046 and the top surface of the substrate 100 is α, and α is 80 ° or more and less than 90 °.
In the embodiment of the present invention, the dummy gate structure 104 is divided into two layers, and the width of the first dummy gate layer 1046 is gradually widened from bottom to top, so that the included angle between the sidewall of the first dummy gate layer 1046 and the top surface of the substrate 100 is smaller than 90 °, so that the process space is large when the first dummy gate layer 1046 is subsequently removed, and the first dummy gate layer 1046 is not easy to remain; the side wall of the second dummy gate layer 1045 is perpendicular to the top surface of the substrate 100, which saves the lateral space of the top surface of the fin portion 101, and is beneficial to further reducing the device size and power consumption.
In the embodiment of the present invention, the dummy gate structure 104 is removed in a subsequent process to form a metal gate structure, and three sides of the metal gate structure surround the channel, wherein the control capability of the portion of the metal gate structure, which contacts the top wall of the fin portion 101, on the channel is greater than the control capability of the portion of the metal gate structure, which contacts the side wall of the fin portion 101, on the channel. Therefore, when the lateral width of the dummy gate structure 104 is unchanged, the bottom surface of the second dummy gate layer 1045 is flush with the top wall of the fin portion 101 or lower than the top wall of the fin portion 101, so that the contact area between the second dummy gate layer 1045 and the top wall of the fin portion 101 is the largest, that is, the contact area between the metal gate structure formed at a later stage and the top wall of the fin portion 101 is the largest, and the corresponding control capability of the metal gate structure on the channel is good.
Referring to fig. 13 to 14, the method for forming a semiconductor structure further includes: after the dummy gate structure 104 is formed, before the source-drain doped layer is formed, a first side wall layer 107 is formed on the side wall of the first dummy gate layer 1046; after the first sidewall layer 107 is formed, a second sidewall 108 is formed on the sidewall of the first sidewall layer 107 and the sidewall of the second dummy gate layer 1045.
The step of forming the first sidewall layer 107 includes: a first sidewall material layer is formed to cover the first dummy gate layer 1046, and the first sidewall material layer (not shown) is etched using the mask layer 105 as a mask, so as to form a first sidewall layer 107.
In this embodiment, the materials of the first sidewall layer 107 and the second sidewall layer 108 are silicon nitride, and in other embodiments, the materials of the first sidewall layer 107 and the second sidewall layer 108 may also be silicon oxynitride or silicon carbide nitride.
Referring to fig. 15 to 16, fig. 15 is a cross-sectional view of a source and drain region, fig. 16 is a cross-sectional view between fin portions 101, and source and drain doped layers 109 are formed in the fin portions 101 on both sides of the dummy gate structure; forming a dielectric layer (not shown) on the source-drain doped layer 109, wherein the dielectric layer exposes the top of the dummy gate structure 104 (shown in fig. 10); removing the dummy gate structure 104 to form an opening in the dielectric layer; a metal gate structure 110 is formed filling the opening.
In this embodiment, the step of forming the source-drain doped layer 109 in the fin 101 at two sides of the dummy gate structure 104 includes: the fin portions 101 at two sides of the dummy gate structure 104 are etched to form grooves (not shown), and the source-drain doped layers 109 are formed in the grooves in an epitaxial growth mode.
In this embodiment, a dielectric layer is formed on the source-drain doped layer 109, and the step of exposing the top of the dummy gate structure 104 includes: a dielectric material layer (not shown) is formed on the source-drain doped layer 109, the dielectric material layer is planarized, the mask layer 105 is used as an etching stop layer, and the dielectric material layer with a partial thickness is etched back to form the dielectric layer.
In the process of etching back the dielectric material layer to form a dielectric layer, the mask layer 105 is removed.
In this embodiment, the step of forming the metal gate structure 110 filling the opening includes: a first gate layer 1101 and a second gate layer 1102 on the first gate layer 1101 are formed.
In this embodiment, the materials of the first gate layer 1101 and the second gate layer 1102 are the same and are made of magnesium-tungsten alloy, and in other embodiments, the materials of the first gate layer and the second gate layer may be Al, cu, ag, au, pt, ni, ti, or the like.
It should be noted that the step of forming the metal gate structure 110 filling the opening further includes: a gate dielectric layer (not shown) is formed in the openings prior to forming the first gate layer 1101.
In this embodiment, the gate dielectric layer is made of HfO2. In other embodiments, the material of the gate dielectric layer may be one or more of ZrO2, hfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al2O 3.
In the embodiment of the present invention, the width of the first dummy gate layer 1046 (as shown in fig. 10) is gradually widened from bottom to top, so that the included angle between the sidewall of the first dummy gate layer 1046 and the top wall of the fin portion 101 is smaller than 90 °, so that the process space is large when the first dummy gate layer 1046 is removed later, the first dummy gate layer 1046 is not easy to remain, the probability of remaining on the bottom surface of the formed metal gate structure 110 is reduced, so that the metal gate structure 110 has good control over the channel, and on this basis, the sidewall of the second dummy gate layer 1045 (as shown in fig. 10) is perpendicular to the top surface of the substrate 100, which saves the space in the lateral direction of the top surface of the fin portion 101, is favorable for further reducing the device size, reducing the power consumption, and optimizing the performance of the semiconductor structure.
In an alternative, when the lateral width of the dummy gate structure 104 is unchanged, the bottom surface of the second dummy gate layer 1045 is flush with the top wall of the fin portion 101 or lower than the top wall of the fin portion 101, so that the contact area between the second dummy gate layer 1045 and the top wall of the fin portion 101 is the largest, that is, the contact area between the formed metal gate structure 110 and the top wall of the fin portion 101 is the largest, and accordingly, the control capability of the metal gate structure 110 on the channel is good.
Fig. 17 to 20 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the embodiment of the present invention.
The embodiment of the present invention is the same as the previous embodiment, and is not described in detail, and is different from the previous embodiment in that: and forming a dummy gate structure.
Referring to fig. 17 to 20, the forming step of the dummy gate structure 204 includes: forming a first dummy gate material layer 2042 covering the fin 201 and a second dummy gate material layer 2043 located on the first dummy gate material layer 2042; patterning the second dummy gate material layer 2043 to form a second dummy gate layer 2045; the first dummy gate material layer 2042 exposed from the second dummy gate layer 2045 is etched to form a first dummy gate layer 2046.
As shown in fig. 17, the step of forming the first dummy gate material layer 2042 includes: forming a first gate film (not shown) covering the fin 201, and performing planarization treatment on the first gate film; and etching back part of the first gate film to enable the top of the remaining first gate film to be flush with the top wall of the fin 201 or lower than the top wall of the fin 201, so as to form a first pseudo gate material layer 2042.
In this embodiment, the position of the fin 201 is upper relative to the position of the substrate 100, the material of the first gate film is silicon germanium, and the ratio of germanium ions in the first gate film decreases from bottom to top.
In the first gate film, the ratio of germanium ions is reduced from bottom to top in order to prepare for etching the first dummy gate material layer 2042 by a wet etching process to form a first dummy gate layer in a subsequent process, and the higher the ratio of germanium ions is, the faster the etched rate is.
In this embodiment, the step of forming the first gate film covering the fin 201 includes: and depositing for multiple times by adopting a chemical vapor deposition process to form the first grid film.
In the step of the chemical vapor deposition process, the deposition thickness is 1 nm to 2 nm each time.
From bottom to top, the germanium ions in the material of the first gate film 106 are different from each other in the material of the first gate film, and the germanium ions in the next deposition have a lower ratio than the germanium ions in the previous deposition.
In this embodiment, the top of the first dummy gate material layer 2042 is flush with the top wall of the fin 201 or lower than the top wall of the fin 201, that is, the bottom surface of the second dummy gate material layer 2043 is lower than the top wall of the fin 201 or flush with the top wall of the fin 201. Therefore, the bottom surface of the second dummy gate layer 1045 formed later is lower than the top wall of the fin 201 or is flush with the top wall of the fin 201.
In this embodiment, the step of forming the second dummy gate material layer 2043 includes: a second gate film (not shown) is formed overlying the first dummy gate material layer 2042, the second gate film is planarized and etched back to a partial thickness to form a second dummy gate material layer 2043.
As shown in fig. 18, the step of patterning the second dummy gate material layer 2043 to form a second dummy gate layer 2045 includes: a shielding layer 205 is formed on the second dummy gate material layer 2043, and the second dummy gate material layer 2043 is etched with the shielding layer 205 as a mask, so as to form a second dummy gate layer 2045.
As shown in fig. 19 to 20, the step of etching the first dummy gate material layer 2042 exposed by the second dummy gate layer 2045 to form a first dummy gate layer 2046 includes: the second dummy gate material layer 2042 is etched using a wet etching process.
In the first dummy gate material layer 2042, the higher the ratio of germanium ions is, the faster the etching rate is, and the ratio of germanium ions in the first dummy gate material layer 2042 gradually decreases from bottom to top, so that the first dummy gate layer gradually becomes wider from bottom to top is advantageously formed.
Specifically, the etching solution adopted in the wet etching process is hydrochloric acid solution.
Note that, the dummy gate structure 204 includes a dummy gate oxide layer (not shown) in addition to the first dummy gate layer 2046 and the second dummy gate layer 2045
In the embodiment of the present invention, the advantages of the formed dummy gate structure are the same as those in the previous embodiment, and the advantages of the formed metal gate structure are the same as those in the previous embodiment, and are not described here again.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 15-16, schematic structural diagrams of an embodiment of a semiconductor structure according to an embodiment of the present invention are shown.
The semiconductor structure includes: a substrate 100; a fin 101, which is separated from the substrate 100; a metal gate structure 110 spanning the fin 101, the metal gate structure 110 covering a portion of a top wall and a portion of a side wall of the fin 101; the source-drain doped layer 109 is located in the fin 101 at two sides of the metal gate structure 110; the metal gate structure 110 includes a first gate layer 1101 and a second gate layer 1102 on the first gate layer 1101, wherein a sidewall of the second gate layer 1102 is perpendicular to the top surface of the substrate 100, and a width of the first gate layer 1101 is gradually wider from bottom to top.
The fin portion 101 is separated on the substrate 100, and the material of the fin portion 101 is the same as that of the substrate 100 and is silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Semiconductor devices, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, or inductors, etc., can also be formed within the substrate 100. The surface of the substrate 100 may further be formed with an interface layer, and the material of the interface layer may be silicon oxide, silicon nitride, silicon oxynitride, or the like.
In this embodiment, the width of the first gate layer 1101 is gradually increased from bottom to top, where the width is perpendicular to the sidewall direction of the second gate layer 1102.
In this embodiment, the position of the fin 101 is above the position of the substrate 100.
In this embodiment, the bottom surface of the second gate layer 1102 is flush with the top wall of the fin portion 101 or lower than the top wall of the fin portion 101. When the lateral width of the metal gate structure 110 is unchanged, the contact area between the second gate layer 1102 and the top wall of the fin portion 101 is maximized, that is, the contact area between the formed metal gate structure 110 and the top wall of the fin portion 101 is maximized, and the control capability of the corresponding metal gate structure 110 on the channel is good.
It should be noted that, the angle α between the sidewall of the first gate layer 1101 and the top surface of the substrate 100 should not be too large or too small. If the included angle alpha is too small, the formed process time is too long, and the etching effect is difficult to control; if the included angle alpha is too large, the process space for removing the dummy gate structure in the previous process is too small, and residues are generated when the dummy gate structure is removed. For this purpose, in this embodiment, the sidewall of the first gate layer 1101 forms an angle α with the top surface of the substrate 100, and α is 80 ° or less and less than 90 °.
In the embodiment of the present invention, the metal gate structure 110 is divided into two layers, the width of the first gate layer 1101 is gradually widened from bottom to top, so that the included angle between the sidewall of the first gate layer 1101 and the top wall of the fin portion 101 is smaller than 90 °, therefore, the process space is large when the dummy gate structure is removed in advance, the dummy gate structure is not easy to remain, the probability of remaining residues on the bottom surface of the formed metal gate structure 110 is reduced, so that the metal gate structure 110 has good control over the channel, on this basis, the sidewall of the second gate layer 1102 is perpendicular to the top surface of the substrate 100, thereby saving the space on the top surface of the fin portion 101, being beneficial to further reducing the device size, reducing the power consumption, and optimizing the performance of the semiconductor structure.
In an alternative, when the lateral width of the metal gate structure 110 is unchanged, the bottom surface of the second gate layer 1102 is flush with the top wall of the fin portion 101 or lower than the top wall of the fin portion 101, so that the contact area between the second gate layer 1102 and the top wall of the fin portion 101 is the largest, that is, the contact area between the formed metal gate structure 110 and the top wall of the fin portion 101 is the largest, and accordingly the control capability of the metal gate structure 110 on the channel is good.
In this embodiment, the materials of the second gate layer 1102 and the first gate layer 1101 are magnesium-tungsten alloy, and in other embodiments, the materials of the first gate layer and the second gate layer may be Al, cu, ag, au, pt, ni, ti, or the like.
In this embodiment, the semiconductor structure further includes a first sidewall layer 107 located on a sidewall of the first gate layer 1101;
in this embodiment, the second sidewall layer 108 is located on the sidewalls of the first sidewall layer 107 and the second gate layer 1102.
In this embodiment, the materials of the first side wall layer 107 and the second side wall layer 108 are silicon nitride, and in other embodiments, the materials of the first side wall layer and the second side wall layer may be silicon oxynitride or silicon carbide nitride.
In this embodiment, an isolation layer 102 is formed on the substrate 100 where the fin portion 101 is exposed. The isolation layer 102 is used to isolate adjacent devices.
In this embodiment, the material of the isolation layer 102 is silicon oxide. In other embodiments, the material of the isolation layer is silicon oxide, silicon nitride or silicon oxynitride.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and discrete fin parts protruding on the substrate;
forming a dummy gate structure crossing the fin part, wherein the dummy gate structure covers part of the top wall and part of the side wall of the fin part, the dummy gate structure comprises a first dummy gate layer and a second dummy gate layer positioned on the first dummy gate layer, the width of the first dummy gate layer gradually increases from bottom to top, the side wall of the second dummy gate layer is perpendicular to the top surface of the substrate, and the bottom surface of the second dummy gate layer is lower than the top wall of the fin part or is flush with the top wall of the fin part;
forming source-drain doped layers in the fin parts at two sides of the pseudo gate structure;
forming a dielectric layer on the source-drain doped layer, wherein the dielectric layer exposes the top of the pseudo gate structure;
removing the pseudo gate structure and forming an opening in the dielectric layer;
and forming a metal gate structure filling the opening.
2. The method of forming a semiconductor structure of claim 1, wherein the step of forming a dummy gate structure comprises:
forming a first pseudo gate material layer covering the fin part and a second pseudo gate material layer positioned on the first pseudo gate material layer;
patterning the first pseudo gate material layer and the second pseudo gate material layer to form a transition first pseudo gate layer and a second pseudo gate layer positioned on the transition first pseudo gate layer, wherein the side wall of the transition first pseudo gate layer is perpendicular to the top surface of the fin part;
and etching the side wall of the transition first pseudo gate layer by adopting a wet etching process to form the first pseudo gate layer.
3. The method of forming a semiconductor structure of claim 2, wherein the material of the first dummy gate layer is silicon germanium and the material of the second dummy gate layer is silicon; the etching solution adopted in the wet etching process is tetramethyl ammonium hydroxide solution.
4. The method of forming a semiconductor structure of claim 1, wherein the step of forming a dummy gate structure comprises:
forming a first pseudo gate material layer covering the fin part and a second pseudo gate material layer positioned on the first pseudo gate material layer;
patterning the second dummy gate material layer to form a second dummy gate layer;
and etching the first pseudo gate material layer exposed by the second pseudo gate layer to form a first pseudo gate layer.
5. The method of forming a semiconductor structure of claim 2 or 4, wherein the step of forming the first dummy gate material layer comprises: forming a first gate film covering the fin portion; flattening the first gate film; and etching back the first gate film with partial thickness so that the top of the remaining first gate film is flush with or lower than the top wall of the fin part, and forming a first pseudo gate material layer.
6. The method of forming a semiconductor structure of claim 5, wherein the step of forming the first gate film comprises: and depositing for multiple times by adopting a chemical vapor deposition process to form the first grid film.
7. The method of claim 6, wherein each deposition thickness in the step of the chemical vapor deposition process is 1 nm to 2 nm.
8. The method of claim 6, wherein the material of the first gate film is silicon germanium, and the germanium ion ratio in the next deposition is lower than the germanium ion ratio in the previous deposition in the step of the chemical vapor deposition process.
9. The method of claim 1, wherein the material of the first dummy gate layer is silicon germanium, and the ratio of germanium ions in the first dummy gate layer decreases from bottom to top.
10. The method of forming a semiconductor structure of claim 9, wherein a molar volume percentage of germanium ions in the first dummy gate layer is 20% to 80%.
11. The method of forming a semiconductor structure of claim 1, wherein sidewalls of said first dummy gate layer are at an angle α,80 ° - α < 90 ° to a top surface of said substrate.
12. The method of forming a semiconductor structure of claim 1, wherein a width of the second dummy gate layer is the same as a width of a top surface of the first dummy gate layer in a direction perpendicular to sidewalls of the second dummy gate layer.
13. The method of claim 1, wherein the material of the second dummy gate layer is silicon, silicon oxide, or silicon oxynitride.
14. The method of forming a semiconductor structure of claim 1, wherein,
the method for forming the semiconductor structure comprises the following steps: after the dummy gate structure is formed, forming a first side wall layer on the side wall of the first dummy gate layer before forming a source-drain doped layer; and after the first side wall layer is formed, forming a second side wall on the side wall of the first side wall layer and the side wall of the second pseudo gate layer.
15. A semiconductor structure, comprising:
a substrate;
a fin portion separated from the substrate;
a metal gate structure crossing the fin portion, wherein the metal gate structure covers part of the top wall and part of the side wall of the fin portion;
the source-drain doping layers are positioned in the fin parts at two sides of the metal gate structure;
the metal gate structure comprises a first gate layer and a second gate layer positioned on the first gate layer, the side wall of the second gate layer is perpendicular to the top surface of the substrate, the width of the first gate layer is gradually widened from bottom to top, and the bottom surface of the second gate layer is lower than the top wall of the fin portion or is flush with the top wall of the fin portion.
16. The semiconductor structure of claim 15, wherein sidewalls of said first gate layer form an angle α,80 ° - α < 90 ° with a top surface of said substrate.
17. The semiconductor structure of claim 16, wherein the material of the second gate layer and the first gate layer are both magnesium-tungsten alloy.
18. The semiconductor structure of claim 16, wherein the semiconductor structure further comprises
The first side wall layer is positioned on the side wall of the first grid electrode layer;
and the second side wall layer is positioned on the side walls of the first side wall layer and the second grid layer.
CN201811191867.4A 2018-10-12 2018-10-12 Semiconductor structure and forming method thereof Active CN111048417B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811191867.4A CN111048417B (en) 2018-10-12 2018-10-12 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811191867.4A CN111048417B (en) 2018-10-12 2018-10-12 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN111048417A CN111048417A (en) 2020-04-21
CN111048417B true CN111048417B (en) 2023-09-12

Family

ID=70229841

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811191867.4A Active CN111048417B (en) 2018-10-12 2018-10-12 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN111048417B (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002198521A (en) * 2000-12-25 2002-07-12 Nec Corp Method of manufacturing semiconductor device
CN101656212A (en) * 2008-08-21 2010-02-24 上海华虹Nec电子有限公司 Process for manufacturing MOS transistor of T metal grid
CN102486998A (en) * 2010-12-01 2012-06-06 中芯国际集成电路制造(上海)有限公司 Method for forming grid
CN102569367A (en) * 2010-12-22 2012-07-11 株式会社电装 Silicon carbide semiconductor device and manufacturing method of the same
CN103531475A (en) * 2012-07-03 2014-01-22 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
CN104752202A (en) * 2013-12-26 2015-07-01 中国科学院微电子研究所 Method for manufacturing semiconductor device
CN105206605A (en) * 2014-06-03 2015-12-30 三星电子株式会社 Electrostatic discharge protection devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8435846B2 (en) * 2011-10-03 2013-05-07 International Business Machines Corporation Semiconductor devices with raised extensions

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002198521A (en) * 2000-12-25 2002-07-12 Nec Corp Method of manufacturing semiconductor device
CN101656212A (en) * 2008-08-21 2010-02-24 上海华虹Nec电子有限公司 Process for manufacturing MOS transistor of T metal grid
CN102486998A (en) * 2010-12-01 2012-06-06 中芯国际集成电路制造(上海)有限公司 Method for forming grid
CN102569367A (en) * 2010-12-22 2012-07-11 株式会社电装 Silicon carbide semiconductor device and manufacturing method of the same
CN103531475A (en) * 2012-07-03 2014-01-22 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
CN104752202A (en) * 2013-12-26 2015-07-01 中国科学院微电子研究所 Method for manufacturing semiconductor device
CN105206605A (en) * 2014-06-03 2015-12-30 三星电子株式会社 Electrostatic discharge protection devices

Also Published As

Publication number Publication date
CN111048417A (en) 2020-04-21

Similar Documents

Publication Publication Date Title
CN112309978B (en) Method for forming semiconductor structure and transistor
CN111370488A (en) Semiconductor structure and forming method thereof
CN111106009B (en) Semiconductor structure and forming method thereof
CN110718465B (en) Semiconductor structure and forming method thereof
CN111554578A (en) Semiconductor structure and forming method thereof
CN107346730B (en) Improve the method for performance of semiconductor device
CN111048417B (en) Semiconductor structure and forming method thereof
CN111755498B (en) Semiconductor structure and forming method thereof
CN113053739B (en) Semiconductor structure and forming method thereof
CN112670179B (en) Semiconductor structure and forming method thereof
CN113314605B (en) Semiconductor structure and forming method thereof
CN111261517B (en) Semiconductor structure and forming method thereof
CN111463275B (en) Semiconductor structure and forming method thereof
CN110571142B (en) Fin type field effect transistor and preparation method thereof
CN111106064A (en) Semiconductor structure and forming method thereof
CN112103182B (en) Semiconductor structure and forming method thereof
CN113539827B (en) Method for forming semiconductor structure
CN112289746B (en) Semiconductor structure and forming method thereof
CN113394098B (en) Semiconductor structure and forming method thereof
CN111162043B (en) Semiconductor structure and forming method thereof
CN113823564B (en) Semiconductor structure and forming method thereof
CN113053751B (en) Semiconductor structure and forming method thereof
CN112151595B (en) Semiconductor structure and forming method thereof
CN111696866B (en) Semiconductor structure and forming method thereof
CN111383917B (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant