CN111696866B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN111696866B CN111696866B CN201910189891.2A CN201910189891A CN111696866B CN 111696866 B CN111696866 B CN 111696866B CN 201910189891 A CN201910189891 A CN 201910189891A CN 111696866 B CN111696866 B CN 111696866B
- Authority
- CN
- China
- Prior art keywords
- forming
- layer
- fin
- fin part
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 80
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000000137 annealing Methods 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 2
- 239000000908 ammonium hydroxide Substances 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000002955 isolation Methods 0.000 description 9
- 239000011295 pitch Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052582 BN Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000003670 easy-to-clean Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein a plurality of fin parts are arranged on the substrate, an insulating layer is arranged on the substrate between the fin parts, and the top of the insulating layer is lower than the top of the fin parts; forming a dielectric layer on the insulating layer, wherein the dielectric layer covers the fin part; forming an opening in the dielectric layer, wherein the opening spans across the fin part, and the opening exposes the top of the insulating layer, the top of the fin part and the side wall surface; forming an interface layer on the top and side wall surfaces of the exposed fin part; forming an amorphous silicon layer on the interface layer, the dielectric layer and the insulating layer; annealing the interface layer and the amorphous silicon layer; and removing the amorphous silicon layer after the annealing treatment. The invention is helpful for removing the amorphous silicon layer cleanly.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor fabrication, as integrated circuit feature sizes continue to decrease, the channel length of MOSFETs also continues to decrease. However, as the channel length of the device is reduced, the distance between the source and drain of the device is also reduced, resulting in a reduced control capability of the gate to the channel, and a short-channel effect (SCE) is more likely to occur.
The fin field effect transistor (FinFET) has outstanding performance in the aspect of inhibiting short channel effect, and the grid electrode of the FinFET can control the fin part from at least two sides, so that compared with a planar MOSFET, the grid electrode of the FinFET has stronger control capability on a channel, and can well inhibit the short channel effect.
However, the electrical performance of the prior art semiconductor device is still poor.
Disclosure of Invention
The invention solves the problem of reducing the residual quantity of the amorphous silicon layer in the process of removing the amorphous silicon layer.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a plurality of fin parts are arranged on the substrate, an insulating layer is arranged on the substrate between the fin parts, and the top of the insulating layer is lower than the top of the fin parts; forming a dielectric layer on the insulating layer, wherein the dielectric layer covers the fin part; forming an opening in the dielectric layer, wherein the opening spans across the fin part, and the opening exposes the top of the insulating layer, the top of the fin part and the side wall surface; forming an interface layer on the top and side wall surfaces of the exposed fin part; forming an amorphous silicon layer on the interface layer, the dielectric layer and the insulating layer; annealing the interface layer and the amorphous silicon layer; and removing the amorphous silicon layer after the annealing treatment.
Optionally, before forming the dielectric layer, the method further includes: and forming a dummy gate crossing the fin portion on the substrate.
Optionally, the process of forming the opening includes: flattening the dielectric layer until the top surface of the dummy gate is exposed; and etching to remove the dummy gate to form the opening.
Optionally, a dry etching process is used to remove the dummy gate.
Optionally, the process parameters of the dry etching process include: the etching gas comprises fluorocarbon gas, HBr or Cl2, the pressure of the chamber is 3 millitorr-8 millitorr, and the bias power is 150 watt-800 watt.
Optionally, in the process of forming the dielectric layer, the dielectric layer covers the entire top of the insulating layer; the process for forming the opening comprises the following steps: and etching and removing part of the dielectric layer until the top of the insulating layer, the top of the fin part and the surface of the side wall are exposed, so as to form the opening.
Optionally, the thickness of the amorphous silicon layer is
Optionally, the annealing treatment process is spike annealing, laser annealing or flash annealing.
Optionally, the process temperature of the annealing treatment is 800-1000 ℃.
Optionally, a wet etching process is used to remove the amorphous silicon layer.
Optionally, the etching liquid of the wet etching process is an ammonium hydroxide solution or a tetramethylammonium hydroxide solution, wherein the temperature of the etching liquid is 25-75 ℃.
Optionally, an atomic layer deposition process is used to form the amorphous silicon layer.
Optionally, after forming the interface layer and before forming the amorphous silicon layer, the method further includes: and forming a high-k gate dielectric layer on the interface layer, the insulating layer and the dielectric layer.
Optionally, the fin portions are a first fin portion group and a second fin portion group that are adjacent.
Optionally, after removing the amorphous silicon layer, the method further includes: and forming a grid electrode filling the opening on the interface layer.
Optionally, after the gate is formed, a groove penetrating through the thickness of the gate is formed, and the groove is located between the first fin portion group and the second fin portion group.
Correspondingly, the invention also provides a semiconductor structure, which comprises: the semiconductor device comprises a substrate, wherein a plurality of fin parts are arranged on the substrate, an insulating layer is arranged on the substrate between the fin parts, and the top of the insulating layer is lower than the top of the fin parts; the dielectric layer is positioned on the insulating layer and covers the fin part; the opening is positioned in the dielectric layer, spans across the fin part, and exposes the top of the insulating layer, the top of the fin part and the surface of the side wall; and the interface layer is positioned on the top of the exposed fin part and the surface of the side wall.
Compared with the prior art, the technical scheme of the invention has the following advantages:
and forming a dielectric layer on the substrate, and forming an opening in the dielectric layer. Because the opening spans across the fin portion, the adjacent fin portions are more open. And forming an amorphous silicon layer on the interface layer, the dielectric layer and the insulating layer, wherein a process window for forming the amorphous silicon layer is large. Correspondingly, in the process for removing the amorphous silicon layer, the operation space is large, the amorphous silicon layer is easy to remove, and the residual quantity of the amorphous silicon layer can be reduced.
Drawings
Fig. 1 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, the electrical performance of the existing semiconductor structure needs to be improved.
Analysis is now performed in conjunction with a method of forming a semiconductor structure, which is formed by the process steps of: providing a substrate, wherein the substrate is provided with a plurality of fin parts, each fin part comprises a first fin part group and a second fin part group which are adjacent, an insulating layer is arranged on the substrate between the fin parts, and the top of the insulating layer is lower than the top of each fin part; forming a dielectric layer on the insulating layer, wherein the dielectric layer covers the fin part; forming an opening in the dielectric layer, wherein the opening comprises a first opening and a second opening which are intermittent, the first opening exposes the top and the side wall surfaces of the first fin part group, and the second opening exposes the top and the side wall surfaces of the second fin part group; forming an interface layer on the top and side wall surfaces of the fin portion exposed by the opening; forming an amorphous silicon layer on the interface layer, the dielectric layer and the insulating layer; annealing the interface layer and the amorphous silicon layer; and removing the amorphous silicon layer after the annealing treatment.
The first opening and the second opening are suitable for forming a gate electrode of a segmented structure subsequently so as to form a transmission gate electrode area, a pull-up area or a pull-down area.
The semiconductor structure formed by the method has poor electrical performance, and the analysis is that:
because the first opening is discontinuous with the second opening, a portion of the dielectric layer is located between the first fin group and the second fin group, resulting in occupation of a space between the first fin group and the second fin group. And gaps are formed between the side walls of the fin parts and the side walls of the dielectric layer on two sides of the dielectric layer between the first fin part group and the second fin part group. In the process of removing the amorphous silicon layer, the amorphous silicon layer in the gap is not easy to clean, and the residual quantity is excessive, so that the electrical performance of the formed semiconductor structure is affected.
In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same. The forming method comprises the following steps: and an opening is formed in the dielectric layer and spans across the fin part, and the opening exposes the top of the insulating layer, the top of the fin part and the surface of the side wall, so that the operation space for removing the amorphous silicon layer later is improved, and the amorphous silicon layer is removed thoroughly.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 has fins thereon, the substrate 100 between the fins has an insulating layer 120 thereon, and the top of the insulating layer 120 is lower than the top of the fins.
Fig. 1 shows a schematic cross-sectional view of the substrate 100 and the fin in a cross-section perpendicular to the fin extension direction.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate 100 may also be germanium, and the substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the substrate 100 includes an edge area i and a central area ii surrounded by the edge area i.
The fin portion is made of silicon or germanium. In this embodiment, the fin portion is made of silicon.
In this embodiment, the entire number of fins are located on the substrate 100 in the central region ii.
In this embodiment, the number of the fin portions is three, and along the direction perpendicular to the extending direction of the fin portions, the three fin portions are a first fin portion 111, a second fin portion 112, and a third fin portion 113 in sequence.
In other embodiments, the number of fins may be two, or greater than three.
The fin parts are a first fin part group and a second fin part group which are adjacent, the first fin part group is composed of one or more fin parts, and the second fin part group is composed of one or more fin parts.
In this embodiment, the first fin 111 and the second fin 112 are used as the first fin group, and the third fin 113 is used as the second fin group.
And subsequently forming a grid electrode which spans the fin parts, wherein the grid electrode is of a sectional structure and is separated between the first fin part group and the second fin part group.
The distance between adjacent fin parts is 25 nm-40 nm. If the distance between the adjacent fin parts is smaller than 25nm, an amorphous silicon layer is formed subsequently, and the process window is too small, so that the amorphous silicon layer is difficult to remove subsequently. If the pitch between adjacent fin portions is greater than 40nm, it is difficult to satisfy the requirement for miniaturization of the semiconductor structure to be formed.
In this embodiment, the pitches of adjacent fin portions are not equal. In other embodiments, the pitch of adjacent fins is equal.
Specifically, in this embodiment, the pitch between the first fin 111 and the second fin 112 is a first pitch L1, the pitch between the second fin 112 and the third fin 113 is a second pitch L2, and the first pitch L1 is smaller than the second pitch L2.
In this embodiment, the material of the insulating layer 120 is silicon nitride. In other embodiments, the material of the insulating layer 120 may be silicon carbide, silicon carbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
Referring to fig. 2, a pad oxide layer 130 is formed on top of the fin and on top of the insulating layer 120.
In this embodiment, the material of the pad oxide layer 130 is germanium oxide. In other embodiments, the material of the pad oxide layer 130 may also be silicon oxide.
The liner oxide 130 may protect the top and sidewall surfaces of the fin.
A dielectric layer is then formed over the substrate 100 and an opening is formed in the dielectric layer, the opening straddling the fin and exposing the top of the insulating layer 120, the top of the fin and the sidewall surfaces. The process of forming the dielectric layer and the opening is described in detail below with reference to fig. 3 and 8.
Referring to fig. 3, a dummy gate film 200 is formed on the substrate 100 across the fin; an initial hard mask layer 210 is formed overlying the top of the dummy gate film 200.
In this embodiment, the dummy gate film 200 covers the surface of the pad oxide layer 130.
The material of the initial hard mask layer 210 is silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, boron nitride or boron carbonitride. In this embodiment, the material of the initial hard mask layer 210 is silicon nitride.
Referring to fig. 4, a portion of the initial hard mask layer 210 (refer to fig. 3) and a portion of the dummy gate film 200 (refer to fig. 3) are etched away until the surface of the pad oxide layer 130 is exposed, the initial hard mask layer 210 is used as a hard mask layer 211, and the dummy gate film 200 is used as a dummy gate 201.
In this embodiment, the hard mask layer 211 and the dummy gate film 200 in the edge region i are etched and removed, and the hard mask layer 211 and the dummy gate film 200 in the central region ii are retained.
The dummy gate 201 is located on a portion of the substrate 100 and spans the entire number of the fins.
Fig. 5 shows a schematic cross-sectional view of the dummy gate 201 in a cross section perpendicular to the extending direction of the dummy gate 201.
In this embodiment, referring to fig. 5, after forming the dummy gate 201, the method further includes: a sidewall 300 is formed on the sidewall of the dummy gate 201. Furthermore, the method further comprises: and forming source-drain doped regions 301 in the fin parts at two sides of the dummy gate 201 along the extending direction of the fin parts.
Referring to fig. 6, a dielectric layer 401 is formed on the insulating layer 120, and the dielectric layer 401 covers the fin portion.
In this embodiment, the material of the dielectric layer 401 is silicon oxide. In other embodiments, the material of the dielectric layer 401 may be silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
In this embodiment, the dielectric layer 401 is located on the pad oxide layer 130 exposed by the dummy gate 201, and the dielectric layer 401 covers the sidewall of the dummy gate 201, the top of the hard mask layer 211, and the surface of the sidewall.
Referring to fig. 7, the dielectric layer 401 is planarized to expose the top surface of the dummy gate 201.
In this embodiment, the dielectric layer 401 is planarized by a chemical mechanical polishing process.
Referring to fig. 8, the hard mask layer 211 (refer to fig. 7) and the dummy gate 201 (refer to fig. 7) are removed, and an opening 410 is formed in the dielectric layer 401.
In this embodiment, a dry etching process is used to remove the dummy gate 201. The dry etching process comprises the following technological parameters: the etching gas comprises fluorocarbon gas, HBr or Cl 2 The chamber pressure is 3 millitorr-8 millitorr and the bias power is 150 watts-800 watts.
In the process of removing the hard mask layer 211 and the dummy gate 201, the method further includes: the pad oxide layer 130 (refer to fig. 7) located at the bottom of the dummy gate 201 is removed.
In this embodiment, the opening 410 spans across the fin, and the bottom of the opening 410 exposes the top of the insulating layer 120, the top of the fin, and the sidewall surface.
In this embodiment, in the process of removing the dummy gate 201, the sidewall 300 (refer to fig. 5) is remained.
In other embodiments, in the process of forming the dielectric layer, the dielectric layer covers the entire top of the insulating layer; the process for forming the opening comprises the following steps: and etching and removing part of the dielectric layer until the top of the insulating layer, the top of the fin part and the surface of the side wall are exposed, and forming the opening in the dielectric layer.
Referring to fig. 9, an interfacial layer 500 is formed on the top and sidewall surfaces of the fin exposed by the opening 410 (referring to fig. 8). A high-k gate dielectric layer 501 is formed on the interfacial layer 500, on the insulating layer 120, and on the dielectric layer 401.
The material of the high-k gate dielectric layer 501 is a high-k dielectric material (dielectric constant greater than 3.9). In this embodiment, the material of the high-k gate dielectric layer 501 is HfO 2 The method comprises the steps of carrying out a first treatment on the surface of the In other embodiments, the material of the high-k gate dielectric layer 501 may be HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or ZrO 2 。
The interfacial layer 500 is advantageous for improving the formation quality of the high-k gate dielectric layer 501.
Referring to fig. 10, an amorphous silicon layer 600 is formed on the interface layer 500, the dielectric layer 401, and the insulating layer 120; and annealing the interfacial layer 500 and the amorphous silicon layer 600.
During the annealing process, the amorphous silicon layer 600 can block oxygen atoms in the interfacial layer 500 and the external environment, thereby preventing the interfacial layer 500 from regrowing and preventing the thickness of the interfacial layer 500 from increasing, so as to improve the performance of the formed semiconductor structure.
In this embodiment, the amorphous silicon layer 600 is formed after the high-k gate dielectric layer 501 is formed, so that the amorphous silicon layer 600 covers the surface of the high-k gate dielectric layer 501, and the adhesion strength between the amorphous silicon layer 600 and the high-k gate dielectric layer 501 is small. Compared with the amorphous silicon layer 600 directly covering the surface of the interface layer 500, the amorphous silicon layer 600 covers the surface of the high-k gate dielectric layer 501, and the amorphous silicon layer 600 is easier to be removed by the subsequent process of removing the amorphous silicon layer 600.
In this embodiment, the thickness of the amorphous silicon layer 600 isIf the thickness of the amorphous silicon layer 600 is less than +>Influence the blocking effect of the amorphous silicon layer 600 on the interface layer 500In the annealing process, the interfacial layer 500 is susceptible to oxidation reaction with oxygen atoms in the external environment due to high temperature. If the thickness of the amorphous silicon layer 600 is greater than +.>The amorphous silicon layer 600 is annealed, so that the amorphous silicon layer 600 is easy to permeate into the interface layer 500, and the difficulty of removing the amorphous silicon layer 600 later is increased.
In this embodiment, the annealing process is spike annealing. In other embodiments, the annealing process may also be laser annealing or flash annealing.
In this embodiment, the annealing process temperature is 800-1000 ℃. If the process temperature of the annealing treatment is lower than 800 ℃, the annealing process has poor effect of improving the density of the interface layer 500. If the process temperature of the annealing treatment is higher than 1000 ℃, the amorphous silicon layer 600 has poor barrier properties to the interface layer 500, and the interface layer 500 is easily oxidized to increase the thickness.
Referring to fig. 11, the amorphous silicon layer 600 (refer to fig. 10) after the annealing treatment is removed.
In the process of removing the amorphous silicon layer 600, since the second space L2 between the second fin portion 112 and the third fin portion 113 is an operation space, the operation space is large, the amorphous silicon layer 600 is easy to be removed, and the residual amount of the amorphous silicon layer 600 can be reduced.
Referring to fig. 12 and 13, a gate 700 is formed to fill the opening 410, the top of the gate 700 being flush with the top of the opening 410. Fig. 13 shows a schematic cross-sectional view of the gate 700 in a section perpendicular to the extending direction of the gate 700.
In this embodiment, the material of the gate 700 is a metal material, for example, W, ag, al, or Cu. In other embodiments, the material of the gate 700 may also be polysilicon or poly-germanium.
Referring to fig. 14 and 15, a portion of the thickness of the gate 700 is removed (see fig. 13), and the top of the gate 700 is lower than the top of the dielectric layer 401.
In this embodiment, a wet etching process is used to remove a portion of the thickness of the gate 700. In other embodiments, a dry etching process may also be used to remove a portion of the thickness of the gate 700.
Referring to fig. 16, a recess 710 is formed through the thickness of the gate 700, and the bottom of the recess 710 exposes the surface of the insulating layer 120.
The recess 710 is formed to make the gate 700 a segmented structure for forming a transfer gate region, a pull-up region, or a pull-down region.
In this embodiment, the recess 710 is located between the second fin 112 and the third fin 113, such that the gate 700 is spaced apart between the first fin group and the second fin group.
Referring to fig. 17, an isolation film 800 filling the recess 710 is formed, and the isolation film 800 covers the top of the dielectric layer 401 and the top of the gate 700.
In this embodiment, the material of the isolation film 800 is silicon nitride. In other embodiments, the material of the isolation film 800 may be silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride oxide, boron nitride, or boron carbonitride.
Referring to fig. 18 and 19, a through hole penetrating through the thickness of the dielectric layer 401 is formed, and the bottom of the through hole exposes the surface of the source-drain doped region 301; a conductive film filling the through hole is formed, the conductive film covers the top of the isolation film 800, the isolation film 800 (refer to fig. 17) and the conductive film higher than the top of the dielectric layer 401 are removed, the conductive film is left to form the conductive layer 820, and the isolation film 800 is left to form the isolation layer 801.
Wherein, the isolation film 800 and the conductive film which are higher than the top of the dielectric layer 401 are removed by chemical mechanical polishing process.
Referring to fig. 11, the present invention further provides a semiconductor structure obtained by the above-described forming method, the semiconductor structure comprising: a substrate 100, wherein a plurality of fin parts are arranged on the substrate 100, an insulating layer 120 is arranged on the substrate 100 between the fin parts, and the top of the insulating layer 120 is lower than the top of the fin parts; a dielectric layer 401, located on the insulating layer 120, where the dielectric layer 401 covers the fin portion; an opening 410 located in the dielectric layer 401, wherein the opening 410 spans across the fin portion, and the opening 410 exposes the top of the insulating layer 120, the top of the fin portion, and the sidewall surface; and the interface layer 500 is positioned on the top and the side wall surface of the exposed fin part.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (16)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a plurality of fin parts, the fin parts are divided into a first fin part group and a second fin part group which are adjacent, the first fin part group comprises a first fin part and a second fin part, the second fin part group comprises a third fin part, the distance between the first fin part and the second fin part is smaller than the distance between the second fin part and the third fin part, an insulating layer is arranged on the substrate between the fin parts, and the top of the insulating layer is lower than the top of the fin parts;
forming a dielectric layer on the insulating layer, wherein the dielectric layer covers the fin part;
forming an opening in the dielectric layer, wherein the opening spans across the fin part, and the opening exposes the top of the insulating layer, the top of the fin part and the side wall surface;
forming an interface layer on the top and side wall surfaces of the exposed fin part;
forming an amorphous silicon layer on the interface layer, the dielectric layer and the insulating layer;
annealing the interface layer and the amorphous silicon layer;
and removing the amorphous silicon layer after the annealing treatment.
2. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the dielectric layer: and forming a dummy gate crossing the fin portion on the substrate.
3. The method of forming a semiconductor structure of claim 2, wherein the process of forming the opening comprises: flattening the dielectric layer until the top surface of the dummy gate is exposed;
and etching to remove the dummy gate to form the opening.
4. The method of forming a semiconductor structure of claim 3, wherein the dummy gate is removed using a dry etching process.
5. The method of forming a semiconductor structure of claim 4, wherein the process parameters of the dry etching process comprise: the etching gas comprises fluorocarbon gas, HBr or Cl 2 The chamber pressure is 3 millitorr-8 millitorr and the bias power is 150 watts-800 watts.
6. The method of claim 1, wherein the dielectric layer covers the entire top of the insulating layer during the forming of the dielectric layer; the process for forming the opening comprises the following steps: and etching and removing part of the dielectric layer until the top of the insulating layer, the top of the fin part and the surface of the side wall are exposed, so as to form the opening.
7. The method of forming a semiconductor structure according to claim 1, wherein the amorphous silicon layer has a thickness of
8. The method of forming a semiconductor structure of claim 1, wherein the annealing process is spike annealing, laser annealing, or flash annealing.
9. The method of forming a semiconductor structure of claim 8, wherein the process temperature of the annealing treatment is 800 ℃ to 1000 ℃.
10. The method of claim 1, wherein the amorphous silicon layer is removed using a wet etch process.
11. The method of claim 10, wherein the etching liquid of the wet etching process is an ammonium hydroxide solution or a tetramethylammonium hydroxide solution, and wherein the etching liquid temperature is 25 ℃ to 75 ℃.
12. The method of claim 1, wherein the amorphous silicon layer is formed using an atomic layer deposition process.
13. The method of forming a semiconductor structure of claim 1, wherein after forming the interfacial layer and before forming the amorphous silicon layer, further comprising: and forming a high-k gate dielectric layer on the interface layer, the insulating layer and the dielectric layer.
14. The method of forming a semiconductor structure of claim 1, further comprising, after removing the amorphous silicon layer: and forming a grid electrode filling the opening on the interface layer.
15. The method of claim 14, wherein after forming the gate, forming a recess through a thickness of the gate, the recess being between the first fin group and the second fin group.
16. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, wherein the substrate is provided with a plurality of fin parts, the fin parts are divided into a first fin part group and a second fin part group which are adjacent, the first fin part group comprises a first fin part and a second fin part, the second fin part group comprises a third fin part, the distance between the first fin part and the second fin part is smaller than the distance between the second fin part and the third fin part, an insulating layer is arranged on the substrate between the fin parts, and the top of the insulating layer is lower than the top of the fin parts;
the dielectric layer is positioned on the insulating layer and covers the fin part;
the opening is positioned in the dielectric layer, spans across the fin part, and exposes the top of the insulating layer, the top of the fin part and the surface of the side wall;
and the interface layer is positioned on the top of the exposed fin part and the surface of the side wall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910189891.2A CN111696866B (en) | 2019-03-13 | 2019-03-13 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910189891.2A CN111696866B (en) | 2019-03-13 | 2019-03-13 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111696866A CN111696866A (en) | 2020-09-22 |
| CN111696866B true CN111696866B (en) | 2023-09-22 |
Family
ID=72475675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910189891.2A Active CN111696866B (en) | 2019-03-13 | 2019-03-13 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111696866B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107039272A (en) * | 2016-02-03 | 2017-08-11 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin transistor |
| US9755057B1 (en) * | 2016-07-28 | 2017-09-05 | United Microelectronics Corp. | Method of fabricating a semiconductor device |
| CN107516631A (en) * | 2016-06-15 | 2017-12-26 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN107887334A (en) * | 2016-09-30 | 2018-04-06 | 台湾积体电路制造股份有限公司 | The manufacture method of semiconductor integrated circuit |
| CN108281477A (en) * | 2017-01-06 | 2018-07-13 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect pipe and forming method thereof |
| CN109427664A (en) * | 2017-08-24 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
-
2019
- 2019-03-13 CN CN201910189891.2A patent/CN111696866B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107039272A (en) * | 2016-02-03 | 2017-08-11 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin transistor |
| CN107516631A (en) * | 2016-06-15 | 2017-12-26 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| US9755057B1 (en) * | 2016-07-28 | 2017-09-05 | United Microelectronics Corp. | Method of fabricating a semiconductor device |
| CN107887334A (en) * | 2016-09-30 | 2018-04-06 | 台湾积体电路制造股份有限公司 | The manufacture method of semiconductor integrated circuit |
| CN108281477A (en) * | 2017-01-06 | 2018-07-13 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect pipe and forming method thereof |
| CN109427664A (en) * | 2017-08-24 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111696866A (en) | 2020-09-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110277316B (en) | Semiconductor structure and forming method thereof | |
| US10930517B2 (en) | Method of forming fin-shaped structure | |
| US11139294B2 (en) | Semiconductor structure and fabrication method thereof | |
| KR100574340B1 (en) | Semiconductor device and method of manufacturing for the same | |
| CN110718465B (en) | Semiconductor structure and forming method thereof | |
| CN108807179B (en) | Semiconductor structure and forming method thereof | |
| CN108281477B (en) | Fin type field effect transistor and forming method thereof | |
| CN111863609B (en) | Semiconductor structure and forming method thereof | |
| CN110854194B (en) | Semiconductor structure and forming method thereof | |
| CN111696866B (en) | Semiconductor structure and forming method thereof | |
| CN110047741B (en) | Semiconductor structure and forming method thereof | |
| CN113809011A (en) | Semiconductor structure and forming method thereof | |
| CN111755498A (en) | Semiconductor structure and forming method thereof | |
| CN111048417B (en) | Semiconductor structure and forming method thereof | |
| CN110875390B (en) | Semiconductor structure and forming method thereof | |
| CN113808947B (en) | Semiconductor structure and forming method thereof | |
| CN112951725B (en) | Semiconductor structure and forming method thereof | |
| US20220328642A1 (en) | Semiconductor structure and forming method thereof | |
| CN111162043B (en) | Semiconductor structure and forming method thereof | |
| CN111312812B (en) | Semiconductor structure and forming method thereof | |
| CN109950202B (en) | Semiconductor structure and forming method thereof | |
| CN115132660A (en) | Method for forming semiconductor structure | |
| CN114497215A (en) | Semiconductor structure and forming method thereof | |
| CN114334654A (en) | Semiconductor structure and forming method thereof | |
| CN117476463A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |