JP2002198521A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To bury and form a low-resistance gate electrode by a simple method when a MOS transistor is subjected to ultra fining. SOLUTION: A dummy gate electrode 4 and an interlayer insulating film 8a are formed on a silicon substrate 1, and the dummy gate electrode 4 is selectively etched and eliminated for a specific thickness for forming a first groove section 9. The interlayer insulating film 8a on the sidewall of the first groove section 9 is etched for forming the first groove section 9a where opening dimensions are expanded. Then, a dummy gate remainder section 10 is etched and removed for forming a second groove section 11. A dummy gate insulating film 2 is removed, an insulating film with a high dielectric constant is deposited as a gate insulating film, and the second groove section 11 is filled with a conductor material for forming the gate electrode of the MOS transistor. In this case, the dummy gate insulating film 2 may be set to the gate insulating film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate electrode portion of a fine MOS transistor.

[0002]

2. Description of the Related Art Fine structure and high density of semiconductor devices such as MOS transistors are still being vigorously promoted. For miniaturization, a semiconductor element formed with a size of about 0.1 μm is currently used, and a semiconductor device such as a logic device or a memory device using this size as a design standard is being studied.

As the MOS transistor becomes finer, the thickness of the gate insulating film becomes as thin as several nm in terms of a silicon oxide film. Here, when the thickness of the gate insulating film is reduced, a leak current flowing through the gate insulating film increases. In the above-mentioned logic device, the leakage current in the gate insulating film does not cause much problem because the operation speed is emphasized. However, in a memory device, the reduction of the leak current is indispensable.

Therefore, it is necessary to provide a method for forming the gate insulating film from a high dielectric film to reduce the effective oxide film thickness.
Various materials such as a tantalum oxide film are now known as the high dielectric film. However, this high dielectric film is more vulnerable to high-temperature processing than a silicon oxide film, an oxynitride film or the like. For this reason, unlike the conventional method for manufacturing a MOS transistor, another method for forming the MOS transistor without performing high-temperature processing is required.

Another method of the above MOS transistor will be described with reference to FIGS. FIG. 11 and FIG.
2 is a cross-sectional view of an N-channel MOS transistor in the order of manufacturing steps. As shown in FIG. 11A, a dummy gate insulating film 102 is formed of a silicon oxide film or the like on a silicon substrate 101 having a P-type conductivity, and a polycrystalline silicon film 103 is formed on the dummy gate insulating film 102. I do. Then, the polycrystalline silicon film 103 and the dummy gate insulating film 102 are patterned by a known photolithography technique and a dry etching technique. Thus, a dummy gate electrode 104 is formed on the silicon substrate 101 as shown in FIG. Subsequently, the low concentration diffusion layer 105 is formed by ion implantation of phosphorus or arsenic and heat treatment.

Next, as shown in FIG. 11C, a side wall insulating film 106 is formed on the side wall of the dummy gate electrode 104 by a known method. Here, the sidewall insulating film 106 is formed of a silicon oxide film. Then, the high concentration diffusion layer 10 is again
7 is formed.

Next, as shown in FIG. 11D, an interlayer insulating film 108 is deposited so as to cover the silicon substrate 101 and the dummy gate electrode 104. This interlayer insulating film 108 is formed of a known bias ECR (Electron).
It is a silicon oxide film deposited by a Cyclotron Resonance method.

Next, as shown in FIG. 12A, the interlayer insulating film 108 is flattened by a chemical mechanical polishing (CMP) method. Here, the dummy gate electrode 104 functions as a polishing stopper. Then, the exposed dummy gate electrode 104 is removed by etching. In this way,
As shown in FIG. 12B, a groove 109 is formed in the interlayer insulating film 108a. Further, the dummy gate insulating film 102 in the groove 109 is also removed.

Next, as shown in FIG. 12C, a gate insulating film 110 and a gate electrode 111 are formed in a groove 109 formed in a predetermined region of the interlayer insulating film 108a. Here, the gate electrode 111 is formed so as to be embedded in the trench 109. Hereinafter, the gate electrode having the above structure is referred to as a buried gate electrode. In this manner, on the silicon substrate 101, the LDD (Lightly Do) using the low concentration diffusion layer 105 and the high concentration diffusion layer 107 as the source / drain regions.
(Ped Drain) MOS transistor. Here, the gate insulating film 110 is made of a high-dielectric-constant insulating film such as a tantalum oxide film or a hafnium oxide film, and the gate electrode 111 is made of a low-resistance metal material such as copper (Cu).

[0010]

The inventor has studied in detail the MOS transistor having the buried gate electrode described above.

As a result, the present inventor has found that when the width of the gate electrode is reduced, it becomes difficult to embed the material of the gate electrode. When a MOS transistor constituting a semiconductor device becomes finer and is designed to be about 0.1 μm, the width of a gate electrode becomes 0.1 μm.
m. With such a gate electrode width, the above-described gate electrode material cannot be embedded.

It is a main object of the present invention to enable a gate electrode to be buried by a simple method when a MOS transistor is miniaturized.

[0013]

According to the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first insulating film on a surface of a semiconductor substrate and forming a dummy on the first insulating film in manufacturing a MOS transistor; A step of forming a gate pattern; a step of forming a diffusion layer serving as a source / drain region of a MOS transistor by ion implantation of impurities using the dummy gate pattern as a mask and a subsequent heat treatment; After forming a second insulating film and depositing a third insulating film covering the dummy gate pattern and the second insulating film, the surface of the third insulating film is removed, and the upper surface of the dummy gate pattern and Exposing an upper portion of the second insulating film; and selectively removing the dummy gate pattern by a predetermined thickness to remove the dummy gate pattern. Forming a first groove with the surface of the remaining portion of the blade as a bottom surface and the second insulating film as a side surface; and etching the second insulating film on the side wall of the first groove to form the first groove. Enlarging the opening dimension of the groove, etching and removing the remaining portion of the dummy gate pattern, and forming a second groove formed by the etching region of the remaining portion and the first groove; Filling the second trench with a conductive material to form a gate electrode of the MOS transistor.

Alternatively, a method of manufacturing a semiconductor device according to the present invention includes, in the manufacture of a MOS transistor, a step of forming a first insulating film on a surface of a semiconductor substrate and forming a dummy gate pattern on the first insulating film. Forming a diffusion layer serving as a source / drain region of a MOS transistor by ion implantation of impurities using the dummy gate pattern as a mask and a subsequent heat treatment, and depositing a third insulating film covering the dummy gate pattern Removing the surface of the third insulating film to expose the upper surface of the dummy gate pattern, and selectively removing the dummy gate pattern by a predetermined thickness to remove the dummy gate pattern by etching. Forming a first groove in the region; and etching the third insulating film on the side wall of the first groove to form the first groove. A step of enlarging the opening dimension of the groove part, a step of etching and removing the remaining part of the dummy gate pattern, and forming a second groove part composed of an etching region of the remaining part and the first groove part; Filling the second trench with a conductive material to form a gate electrode of the MOS transistor.

Here, the dummy gate pattern is composed of laminated upper and lower semiconductor films or conductive films,
The region where the dummy gate pattern is removed by etching is the upper semiconductor film or conductive film, and the remaining portion of the dummy gate pattern is the lower semiconductor film or conductive film. Alternatively, the dummy gate pattern is composed of a lower semiconductor film or conductive film laminated thereon and an upper fourth insulating film, and the region of the dummy gate pattern to be removed by etching is the upper fourth insulating film, The remaining portion of the dummy gate pattern is the lower semiconductor film or conductive film.

The first insulating film is used as a gate insulating film of a MOS transistor. Alternatively, after forming the second groove, the first insulating film is removed, a high dielectric constant insulating film having a higher dielectric constant than the first insulating film is applied, and the high dielectric constant insulating film is formed of a MOS. A gate insulating film of a transistor.

Further, the second insulating film or the third insulating film is a silicon oxide film, and the semiconductor film is a silicon film. Alternatively, the third insulating film is a silicon oxide film, the second insulating film or the fourth insulating film is a silicon nitride film, and the semiconductor film is a silicon film.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, in manufacturing a MOS transistor, a gate insulating film is formed on a surface of a semiconductor substrate, and a gate electrode film, an insulating film, a lower layer film to be laminated, and A step of depositing an upper layer film in this order; a step of processing the gate electrode film, the insulating film, and the laminated upper / lower layer film into a gate pattern of a MOS transistor; and ion implantation of impurities using the gate pattern as a mask; Forming a diffusion layer to be a source / drain region of the MOS transistor by heat treatment; and forming a second insulating film on a side wall of the gate pattern and covering the gate pattern and the second insulating film. After depositing the insulating film, the surface of the third insulating film is removed to expose the upper layer of the gate pattern and the upper portion of the second insulating film. Forming a first groove having the surface of the lower film as a bottom surface and the second insulating film as a side surface by etching and removing the upper layer film of the gate pattern; Etching the second insulating film on the side wall to enlarge the opening dimension of the first groove; etching and removing the lower film and the insulating film in the gate pattern to form an etched region of the lower film and the insulating film; Forming a second groove composed of the first groove and filling the second groove with a conductive material connected to the gate electrode film to form a gate electrode of the MOS transistor; Including.

Alternatively, in a method of manufacturing a semiconductor device according to the present invention, in manufacturing a MOS transistor, a gate insulating film is formed on a surface of a semiconductor substrate, and a gate electrode film, an insulating film, a lower film to be laminated, A step of depositing an upper layer film in this order; a step of processing the gate electrode film, the insulating film, and the laminated upper / lower layer film into a gate pattern of a MOS transistor; and ion implantation of impurities using the gate pattern as a mask; Forming a diffusion layer to be a source / drain region of a MOS transistor by heat treatment, and removing a surface of the third insulating film after depositing a third insulating film covering the gate pattern; Exposing the upper layer film, and etching the upper layer film by etching away the upper layer film in the gate pattern. Forming a first groove in the removed region, etching the third insulating film on the side wall of the first groove to enlarge the opening dimension of the first groove, and forming the lower layer of the gate pattern. Removing a film and an insulating film by etching to form a second groove portion including the etching region of the lower film and the insulating film and the first groove portion; and forming a conductive material connected to the gate electrode film. The second
And filling the trenches as the gate electrodes of the MOS transistors.

According to the present invention, after the first groove is first formed as described above, the opening size of the first groove is increased.
A second groove having a two-stage cross section is formed. Then, the conductive material is buried in the second groove.

For this reason, it becomes very easy to bury the low-resistance gate electrode material of the MOS transistor in the above-mentioned trench. Then, the manufacture of a fine MOS transistor having a buried gate electrode using the insulating film having a high dielectric constant as a gate insulating film is simplified.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. 1 to 3
FIG. 4 is a cross-sectional view of an N-channel MOS transistor in the order of the manufacturing process according to the present invention.

As described in the prior art, FIG.
1A, a dummy gate insulating film 2 made of a silicon oxide film or the like having a thickness of about 3 nm is formed on a P-type silicon substrate 1 having a conductivity type, and a polycrystalline silicon film 3 is formed on the dummy gate insulating film 2. Form a film. This dummy gate insulating film becomes a first insulating film. Then, the polycrystalline silicon film 3 and the dummy gate insulating film 2 are patterned by a known photolithography technique and a dry etching technique. Here, the thickness of the polycrystalline silicon film 3 is about 200 nm, and in the above dry etching, an ICP (Inductive C
multi-step method using an combined plasma (etched) apparatus. Therefore, as the reaction gas, Cl _2, HBr, a mixture gas of O ₂ used in the first step, using HBr, mixed gas of O ₂ in the second step. Thus, the dry etching of the dummy gate insulating film 2 is prevented, and the surface of the silicon substrate 1 thereunder is protected from the dry etching. Thus, FIG.
As shown in (b), a dummy gate electrode 4 having a width of 0.1 μm is formed. This dummy gate electrode becomes a dummy gate pattern. Then, heat treatment is performed by ion-implanting an N-type impurity such as phosphorus using the dummy gate electrode 4 as a part of the mask. Thus, the low concentration diffusion layer 5 is formed.

Next, as shown in FIG. 1C, a side wall insulating film 6 is formed as a second insulating film on the side wall of the dummy gate electrode 4 by forming a silicon oxide film and etching back. Then, a high concentration diffusion layer 7 is formed by ion implantation of N-type impurities such as arsenic again and heat treatment.

Next, as shown in FIG. 1D, an interlayer insulating film 8 is deposited as a third insulating film so as to cover the silicon substrate 1 and the dummy gate electrode 4. here,
The interlayer insulating film 8 is a silicon oxide film having a thickness of about 500 nm deposited by a known CVD (chemical vapor deposition) method.

Next, as shown in FIG. 2A, the interlayer insulating film 8 is flattened by a CMP method to form an interlayer insulating film 8a. Here, the dummy gate electrode 4 functions as a polishing stopper. Then, a part of the exposed dummy gate electrode 4 is etched. In this way, as shown in FIG. 2B, the first groove 9 is formed in the interlayer insulating film 8a. The size of the first groove is 0.1 μm. Here, the thickness of the remaining dummy gate 10 is １ ／ of that of the dummy gate electrode 4.
１ ／.

Next, the entire surface of the interlayer insulating film 8a is isotropically etched by wet etching using dilute hydrofluoric acid as an etchant to form a first groove 9a as shown in FIG. 2C. Here, the etching amount is about 50 nm. Thus, the first groove 9 having a size of 0.1 μm is formed.
Is a first groove 9a having a size of 0.2 μm. here,
The above-mentioned dummy gate remaining portion 10 protects the lower portion of the dummy gate insulating film 2 and the interlayer insulating film 8a on the side wall of the dummy gate remaining portion 10 from the wet etching. Here, isotropic plasma etching may be used instead of wet etching using a chemical solution.

Next, the remaining dummy gate 10 is selectively removed by isotropic dry etching. Here, a multi-step method is used using an isotropic plasma etching apparatus. As a reaction gas, Cl ₂ and H are used in the first step.
Using a mixed gas of Br and O ₂ , HBr,
By using a mixed gas of O ₂ , dry etching of the dummy gate insulating film 2 is prevented, and the surface of the silicon substrate 1 thereunder is protected from dry etching. Thus, FIG.
As shown in (d), the second groove 11 is formed in the interlayer insulating film 8a.
To form The cross-sectional shape of the second groove portion 11 becomes a groove having a two-stage structure, and the embedding property of the above-described metal material is greatly improved. Further, the dummy gate insulating film 2 in the second groove 11 is also removed.

Next, as shown in FIG.
A 0 nm high dielectric constant insulating film 12 is formed on the entire surface. The high dielectric constant insulating film 12 is a tantalum oxide film or the like deposited by a CVD method. Then, a low-resistance conductive film 13 is formed on the high-dielectric-constant insulating film 12 so as to fill the second groove 11. Here, the low resistance conductive film 13 is a laminated film of TiN (titanium nitride) and Cu.

Next, the above-mentioned low resistance conductive film 13 is subjected to CMP.
3B, the interlayer insulating film 8a is polished as shown in FIG.
The gate insulating film 14 and the gate electrode 15 are formed in the second groove 11 formed in the predetermined region. In this way,
A MOS transistor having an LDD structure using the low-concentration diffusion layer 5 and the high-concentration diffusion layer 7 as source / drain regions can be obtained.
Here, the gate insulating film 14 is formed of a high dielectric constant insulating film such as a tantalum oxide film or a hafnium oxide film, and the gate electrode 15 is formed of a low-resistance metal such as copper.

In the present invention, the second groove having a two-stage structure in cross section is formed. For this reason, it becomes very easy to embed the gate electrode material in the above-mentioned groove. In this way, the problems of the prior art are completely solved, and the manufacture of a fine MOS transistor having a buried gate electrode is simplified.

Next, the second embodiment of the present invention will be described with reference to FIGS.
An embodiment will be described. Here, FIGS. 4 and 5 are cross-sectional views in the order of the manufacturing process of the MOS transistor of the present invention.
Here, the same components as those described in the first embodiment are denoted by the same reference numerals. The second embodiment is a modification of the first embodiment, and shows a method of improving the controllability of forming a groove having a two-stage cross section.

As shown in FIG. 4A, the silicon substrate 1
A first silicon oxide film 16 having a thickness of about 2 nm, a first polycrystalline silicon film 17 having a thickness of 150 nm, a thickness of 3 n
m second silicon oxide film 18 and a 200 nm thick second silicon oxide film 18.
Is formed by laminating the polycrystalline silicon films 19.

Then, a resist mask of a gate electrode pattern is formed by using a known photolithography technique.
Then, the second polycrystalline silicon film 19, the second silicon oxide film 18, and the first polycrystalline silicon film 17 are sequentially etched by a dry etching technique. In the above dry etching, the IC as described in the first embodiment is used.
A P etching device is used. Thus, FIG.
As shown in FIG. 2B, a lower dummy gate electrode 20 and an upper dummy gate electrode 21 are formed to form a dummy gate electrode 4 having a width of 0.1 μm. Further, using the dummy gate electrode 4 as a part of the mask, an N-type impurity such as phosphorus is ion-implanted and heat-treated to form the low concentration diffusion layer 5.

Next, as shown in FIG. 4C, a sidewall insulating film 6 is formed on the side wall of the dummy gate electrode 4,
The high-concentration diffusion layer 7 is formed again by ion implantation of N-type impurities such as arsenic and heat treatment.

Next, as shown in FIG. 4D, a silicon oxide film is deposited so as to cover the silicon substrate 1 and the dummy gate electrode 4, and is planarized by a CMP method to form an interlayer insulating film 8a. Here, the upper dummy gate electrode 21
Functions as a polishing stopper.

Next, the exposed upper dummy gate electrode 21
Only those are selectively removed by dry etching. In this dry etching, a multi-step method is used using the above-described ICP etching apparatus. In this dry etching, the second silicon oxide film 18 functions as an etching stopper, and the first polycrystalline silicon film 20 is completely protected from etching. Thus, FIG.
As shown in (a), the depth of the first groove 9 in the interlayer insulating film 8a is controlled with high precision. The depth of this first groove is 0.
At 20 μm (200 nm), the width dimension is 0.1 μm.

Next, the entire surface of the interlayer insulating film 8a is isotropically etched by wet etching using diluted hydrofluoric acid as an etchant to form a first groove 9a as shown in FIG.
To form Also in this case, the etching amount is about 50 nm. In this way, the first groove 9 having the size of 0.1 μm becomes the first groove 9a having the size of 0.2 μm. Here, the lower dummy gate electrode 20 described above is formed by the first silicon oxide film 16 and the lower dummy gate electrode
The interlayer insulating film 8a on the zero side wall is protected from the wet etching.

Next, the lower dummy gate electrode 20 is selectively removed by dry etching. Here, a multi-step method is used using an ICP etching apparatus. In this way, as shown in FIG.
A second groove portion 11 is formed in a. The cross-sectional shape of the second groove 11 becomes a groove having a two-stage structure, and the embedding property of the above-described metal material is greatly improved. Further, the second groove 11
The dummy gate insulating film 2 is also removed.

Thereafter, as described in the first embodiment, a gate insulating film of a high dielectric constant insulating film and a gate electrode are formed in the above-mentioned second groove portion 11.

In the second embodiment, the same effects as described in the first embodiment are produced. In this case, the controllability of the cross-sectional shape of the two-stage groove is greatly improved.

Next, a third embodiment of the present invention will be described with reference to FIGS. Here, FIGS. 6 and 7 are cross-sectional views in the order of the manufacturing process of the MOS transistor of the present invention.
Here, the same components as those described in the first (2) embodiment are denoted by the same reference numerals.

As shown in FIG. 6A, the silicon substrate 1
An oxynitride film 22 having a thickness of about 5 nm, a first polycrystalline silicon film 17, and a silicon nitride film 2 serving as a fourth insulating film are formed thereon.
3 are formed by lamination. Here, the thickness of the first polycrystalline silicon film 17 is 150 nm, and
Has a thickness of 150 nm.

Then, the silicon nitride film 23 and the first polycrystalline silicon film 17 are patterned by a known photolithography technique and a dry etching technique. In this patterning, reactive ion etching (R
The dummy gate nitride film 24 is formed by processing the silicon nitride film 23 by IE), and then the first polycrystalline silicon film 17 is formed by dry etching using the above-described ICP etching apparatus using the dummy gate nitride film 24 as a mask. Here, as the reaction gas, Cl ₂ and HB were used in the first step.
Using a mixed gas of r and O ₂ , HBr and O 2 are used in the second step.
The mixed gas of ₂ is used. Thus, as shown in FIG. 6B, the dummy gate electrode 4 having a width of 0.2 μm is formed.
To form Then, the low concentration diffusion layer 5 is formed.

Next, as shown in FIG. 6C, a side wall insulating film 25 is formed on the side wall of the dummy gate electrode 4 by forming a silicon nitride film and etching back. And
The high concentration diffusion layer 7 is formed. Here, the thickness of the sidewall insulating film 25 is 100 nm.

Next, as shown in FIG. 6D, a silicon oxide film having a thickness of about 700 nm is deposited on the silicon substrate 1 and the dummy gate electrode 4 so as to cover the dummy gate electrode 4, and then flattened by the CMP method. An interlayer insulating film 8a is formed. Here, the dummy gate nitride film 24 and the side wall insulating film 25 function as a polishing stopper.

Next, the exposed dummy gate nitride film 24 is removed by wet etching with a chemical solution of hot phosphoric acid.
By this wet etching, the sidewall insulating film 25 is formed.
Is also etched, and the sidewall insulating film remains 26
Is formed. The remaining portion of the sidewall insulating film 26 has a height up to about the height of the lower dummy gate electrode 20. Thus, as shown in FIG. 7A, the first groove 9a is formed in the interlayer insulating film 8a.

In the wet etching with the chemical solution of hot phosphoric acid, the interlayer insulating film 8 composed of a silicon oxide film is formed.
a is not etched. For this, the first formed
The width of the groove 9a is precisely controlled to 0.4 μm,
The depth is also controlled with a high precision of 150 nm.

Next, the lower dummy gate electrode 20 is selectively removed by wet etching. In this way, as shown in FIG. 7B, the second groove 11 is formed. Even in this wet etching, the interlayer insulating film 8a composed of the silicon oxide film is hardly etched. Therefore, the width and depth of the second groove 11 can be formed with high precision. The oxynitride film 22 and the remaining sidewall insulating film 26 are not etched by this wet etching.

Next, as shown in FIG. 7C, a barrier film 27 such as TiN
The gate electrode 15 is formed by laminating the films 28. In this case, the oxynitride film 22 becomes the gate insulating film of the MOS transistor as it is.

In the second embodiment, the same effects as described in the first embodiment are produced. Further, in this case, the control of the width dimension and the depth dimension of the second groove 11 is greatly improved.

Next, a fourth embodiment of the present invention will be described with reference to FIGS. Here, FIGS. 8 to 10
3A to 3C are cross-sectional views in the order of the manufacturing steps of the MOS transistor of the present invention. Here, the same components as those described in the above embodiment are denoted by the same reference numerals. The fourth embodiment is basically a modification of the second embodiment.

As shown in FIG. 8A, the silicon substrate 1
An oxynitride film 22 having a thickness of about 2 nm and a gate electrode film 2
9, a first silicon oxide film 16 having a thickness of 3 nm, a first polycrystalline silicon film 17 having a thickness of 150 nm as a lower layer film, a second silicon oxide film 18 having a thickness of 3 nm, and a thickness of 200 nm being an upper layer film Is formed by laminating the second polycrystalline silicon film 19. Here, the gate electrode film 29 is a polycrystalline silicon film containing a phosphorus impurity and having a thickness of about 100 nm.

Then, as described in the second embodiment, the second polycrystalline silicon film 19, the second silicon oxide film 18, the first polycrystalline The silicon film 17, the first silicon oxide film 16, and the gate electrode film 29 are sequentially etched. In this way, as shown in FIG.
A lower gate electrode 30, a lower dummy gate electrode 20, and an upper dummy gate electrode 21 are formed to form a dummy gate electrode 4 having a width of 0.1 μm. Then, the low concentration diffusion layer 5 is formed.

Next, as shown in FIG. 8C, a side wall insulating film 6 of a silicon oxide film is formed on the side walls of the lower gate electrode 30 and the dummy gate electrode 4, and a high concentration diffusion layer 7 is formed. Then, as shown in FIG. 8D, a silicon oxide film is deposited so as to cover the silicon substrate 1 and the dummy gate electrode 4 and the lower gate electrode 30, and is flattened by the CMP method to form an interlayer insulating film 8a. . Here, the upper dummy gate electrode 21 functions as a polishing stopper.

Next, the exposed upper dummy gate electrode 21
Only those portions are selectively removed by dry etching as described in the second embodiment. In this dry etching,
The second silicon oxide film 18 functions as an etching stopper, and the first polycrystalline silicon film 20 is completely protected from etching. Thus, as shown in FIG. 9A, the first groove 9 is formed in the interlayer insulating film 8a.
Here, the first groove has a depth of 0.20 μm and a width of 0.1 μm.

Next, the interlayer insulating film 8a is isotropically etched by wet etching using dilute hydrofluoric acid as an etchant to form a first groove 9a as shown in FIG.
To form Here, the etching amount is about 50 nm. Thus, the first groove 9 having a size of 0.1 μm is formed.
Is a first groove 9a having a size of 0.2 μm. here,
The lower dummy gate electrode 20 described above has a lower first gate electrode 20.
The silicon oxide film 16 and the interlayer insulating film 8a on the side walls of the lower gate electrode 30 are protected from the wet etching.

Next, the lower dummy gate electrode 20 is selectively removed by dry etching. Here, a multi-step method is used using an ICP etching apparatus. Thus, as shown in FIG. 9C, the interlayer insulating film 8a
Then, a second groove 11 is formed. The cross-sectional shape of the second groove 11 becomes a groove having a two-stage structure, and the embedding property of the above-described metal material is greatly improved.

Next, the very thin first silicon oxide film 16 is removed by wet etching. Thus, FIG.
As shown in (d), the surface of the lower gate electrode 30 is exposed.

Next, as shown in FIG. 10A, a conductive film 31 is formed so as to be connected to the lower gate electrode and to fill the second groove 11. Here, the conductive film 31 is a metal film in which WN (tungsten nitride) and W (tungsten) are stacked in this order.

Next, the above-described conductive film 31 is polished by a CMP method, and as shown in FIG. 10B, a gate insulating film and a gate insulating film are formed in a second groove 11 formed in a predetermined region of the interlayer insulating film 8a. An oxynitride film 22, a lower gate electrode 30, and an upper gate electrode 32 are formed. Thus, a MOS transistor having an LDD structure in which the low-concentration diffusion layer 5 and the high-concentration diffusion layer 7 are formed on the surface of the silicon substrate 1 as the source / drain regions can be obtained.

In this embodiment, the effects described in the first and second embodiments are obtained. Further, since the gate insulating film and the lower gate electrode are formed in advance, the manufacturing process of the MOS transistor can be simplified.

In the first and second embodiments,
The case where a high dielectric constant insulating film is used as the gate insulating film has been described. In this case, the dummy gate insulating film 2 or the first silicon oxide film 16 may be used as it is as the gate insulating film. Conversely, in the third embodiment, the oxynitride film 22 may be removed and an insulating film having a high dielectric constant may be used as the gate insulating film.

In the above embodiment, the dummy gate electrode is formed of a polycrystalline silicon film, but the present invention is not limited to this. The dummy gate electrode may be made of a material different from the material forming the interlayer insulating film and having a different etching rate. For example, a conductive film such as a refractory metal silicide is used.

In the above-described embodiment of the present invention, the case where the gate electrode is formed of Cu metal or a laminated W / WN metal is described, but the present invention is not limited to this. In addition, aluminum (Al), or
Molybdenum (Mo), tantalum (Ta), titanium (T
The present invention can be similarly applied to the case of forming with a high melting point metal such as i) or a noble metal such as platinum (Pt) or ruthenium (Ru).

In the above embodiment, the case where the interlayer insulating film is a silicon oxide film has been described.
In addition, a low dielectric constant film based on Si—O may be used as the interlayer insulating film. Examples of such an insulating film include hydrogen silsesquioxane which is a silsesquioxane, methyl silsesquioxane, methylated hydrogen silsesquioxane, and methylated hydrogen silsesquioxane.
There is a low dielectric constant film such as Silsesquioxane) or Fluorinated Silsesquioxane.

It should be noted that the present invention is not limited to the above-described embodiment, and it is clear that the embodiment can be appropriately changed within the scope of the technical idea of the present invention.

[0068]

According to a principal part of the present invention, in the manufacture of a MOS transistor, a dummy gate pattern is formed on the surface of a semiconductor substrate, and the source / drain regions of the MOS transistor are formed by ion implantation of impurities using the dummy gate pattern as a mask. Is formed. After the insulating film covering the dummy gate pattern is deposited, the upper surface of the dummy gate pattern is exposed. The dummy gate pattern is selectively etched away by a predetermined thickness to form a first groove. Next, the opening of the first groove is enlarged by etching the side wall of the first groove. Then, the remaining portion of the dummy gate pattern is removed by etching to form a second groove having a two-stage cross-sectional shape. This second
Is filled with a conductive material to form a gate electrode of a MOS transistor. Alternatively, a gate insulating film having a high dielectric constant and a gate electrode are formed in the second groove.

According to the method of the present invention, it becomes very easy to bury a low-resistance gate electrode material of a MOS transistor in the above-mentioned trench. Furthermore, it becomes very simple to manufacture an ultra-fine MOS transistor having a low-resistance buried gate electrode using a high-dielectric-constant insulating film as a gate insulating film.

The present invention promotes miniaturization of MOS transistors and higher density or higher integration of semiconductor devices.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an M mode for explaining a first embodiment of the present invention.
FIG. 7 is a cross-sectional view illustrating the order of manufacturing steps of an OS transistor.

FIG. 2 is a cross-sectional view showing a continuation of the manufacturing process of the MOS transistor.

FIG. 3 is a cross-sectional view showing a continuation of the manufacturing process of the MOS transistor.

FIG. 4 is a diagram illustrating M for explaining a second embodiment of the present invention;
FIG. 7 is a cross-sectional view illustrating the order of manufacturing steps of an OS transistor.

FIG. 5 is a cross-sectional view showing a continuation of the manufacturing process of the MOS transistor.

FIG. 6 is a diagram for explaining M according to a third embodiment of the present invention;
FIG. 7 is a cross-sectional view illustrating the order of manufacturing steps of an OS transistor.

FIG. 7 is a cross-sectional view showing a continuation of the manufacturing process of the MOS transistor.

FIG. 8 is a diagram for explaining a fourth embodiment of the present invention;
FIG. 7 is a cross-sectional view illustrating the order of manufacturing steps of an OS transistor.

FIG. 9 is a cross-sectional view showing a continuation of the manufacturing process of the MOS transistor.

FIG. 10 is a cross-sectional view showing a continuation of the manufacturing process of the MOS transistor.

FIG. 11 is a cross-sectional view of a MOS transistor in a manufacturing process order for describing a conventional technique.

FIG. 12 is a cross-sectional view showing a continuation of the manufacturing process of the MOS transistor.

[Description of Signs] 1,101 Silicon substrate 2,102 Dummy gate insulating film 3,103 Polycrystalline silicon film 4,104 Dummy gate electrode 5,105 Low concentration diffusion layer 6,25,106 Side wall insulating film 7,107 High Concentration diffusion layer 8, 8a, 108, 108a Interlayer insulating film 9, 9a First trench 10 Remaining dummy gate 11 Second trench 12 High dielectric constant insulating film 13 Low resistance conductive film 14, 110 Gate insulating film 15, 111 Gate Electrode 16 First silicon oxide film 17 First polycrystalline silicon film 18 Second silicon oxide film 19 Second polycrystalline silicon film 20 Lower dummy gate electrode 21 Upper dummy gate electrode 22 Oxynitride film 23 Silicon nitride film 24 Dummy gate nitride film 26 Remaining sidewall insulating film 27 Barrier film 28 Cu film 29 Gate electrode 30 lower gate electrode 31 conductive film 32 upper gate electrode

Claims (10)

[Claims] A step of forming a first insulating film on a surface of a semiconductor substrate and forming a dummy gate pattern on the first insulating film in manufacturing an insulated gate field effect transistor (hereinafter referred to as a MOS transistor); Forming a diffusion layer serving as a source / drain region of a MOS transistor by ion implantation of impurities using the dummy gate pattern as a mask and a subsequent heat treatment; forming a second insulating film on a side wall of the dummy gate pattern Then, after depositing a third insulating film covering the dummy gate pattern and the second insulating film, the surface of the third insulating film is removed, and the upper surface of the dummy gate pattern and the upper portion of the second insulating film are removed. Exposing the dummy gate pattern selectively by a predetermined thickness to remove the remaining dummy gate pattern. Forming a first groove having the surface of the remaining portion as a bottom surface and the second insulating film as a side surface; and etching the second insulating film on a side wall of the first groove to open the first groove. A step of enlarging a dimension, a step of etching and removing a remaining portion of the dummy gate pattern, and a step of forming a second groove formed by an etching region of the remaining portion and the first groove; Filling the trench with a conductive material to form a gate electrode of the MOS transistor. 2. A method of manufacturing a MOS transistor, comprising: forming a first insulating film on a surface of a semiconductor substrate and forming a dummy gate pattern on the first insulating film; and forming an impurity using the dummy gate pattern as a mask. Forming a diffusion layer to be a source / drain region of a MOS transistor by ion implantation of a metal oxide film and a heat treatment thereafter; and depositing a third insulating film covering the dummy gate pattern. Removing a surface to expose an upper surface of the dummy gate pattern; and selectively removing the dummy gate pattern by a predetermined thickness to form a first groove in an etching-removed region of the dummy gate pattern. Etching the third insulating film on the side wall of the first groove to enlarge the opening dimension of the first groove; Removing the remaining portion of the dummy gate pattern by etching to form a second groove portion including the etching region of the remaining portion and the first groove portion; and filling the second groove portion with a conductive material. Forming a gate electrode of the MOS transistor. 3. The semiconductor device according to claim 1, wherein the dummy gate pattern is formed of an upper semiconductor layer and a lower semiconductor film or a conductive film, and a region of the dummy gate pattern to be removed by etching is the upper semiconductor film or the conductive film. 3. The method according to claim 1, wherein the remaining portion is the lower semiconductor film or the conductive film. 4. The lower insulating film or conductive film on which the dummy gate pattern is laminated and an upper fourth insulating film, and a region of the dummy gate pattern to be removed by etching is the upper insulating film. 3. The method according to claim 1, wherein the remaining portion of the dummy gate pattern is the lower semiconductor film or the conductive film. 5. The method for manufacturing a semiconductor device according to claim 1, wherein said first insulating film is a gate insulating film of a MOS transistor. 6. The method according to claim 6, wherein the first insulating film is removed after forming the second groove, and a high dielectric constant insulating film having a higher dielectric constant than the first insulating film is applied. MOS film
5. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a gate insulating film of a transistor. 7. The semiconductor device according to claim 1, wherein the second insulating film or the third insulating film is a silicon oxide film, and the semiconductor film is a silicon film. 13. The method for manufacturing a semiconductor device according to the above item. 8. The semiconductor device according to claim 1, wherein the third insulating film is a silicon oxide film, the second insulating film or the fourth insulating film is a silicon nitride film, and the semiconductor film is a silicon film. The method of manufacturing a semiconductor device according to claim 1. 9. A process for manufacturing a MOS transistor, comprising: forming a gate insulating film on a surface of a semiconductor substrate; and depositing a gate electrode film, an insulating film, a laminated lower film and an upper film on the gate insulating film in this order. The gate electrode film, the insulating film, and the laminated upper / lower film are denoted by M
Processing a gate pattern of an OS transistor; forming a diffusion layer to be a source / drain region of a MOS transistor by ion implantation of impurities using the gate pattern as a mask and a subsequent heat treatment; Forming a second insulating film on the substrate; depositing a third insulating film covering the gate pattern and the second insulating film; removing a surface of the third insulating film; Exposing an upper portion of a second insulating film; and etching away the upper layer film of the gate pattern to form a first groove having a surface of the lower film as a bottom surface and a side surface of the second insulating film as a side surface. A step of etching a second insulating film on a side wall of the first groove to enlarge an opening dimension of the first groove; Removing the lower layer film and the insulating film by etching to form a second groove portion including the etching region of the lower layer film and the insulating film and the first groove portion; and a conductor connected to the gate electrode film. Filling the second trench with a material to form a gate electrode of the MOS transistor. 10. A method for manufacturing a MOS transistor, comprising:
Forming a gate insulating film on the surface of the semiconductor substrate and depositing a gate electrode film, an insulating film, a laminated lower layer film and an upper layer film in this order on the gate insulating film; and the gate electrode film, the insulating film, and the laminated upper layer. / Lower layer film is M
Processing a gate pattern of the OS transistor; forming a diffusion layer serving as a source / drain region of the MOS transistor by ion implantation of impurities using the gate pattern as a mask and a subsequent heat treatment; covering the gate pattern Removing a surface of the third insulating film to expose an upper layer film of the gate pattern after depositing a third insulating film to be formed; and removing the upper layer film of the gate pattern by etching. Forming a first groove in an etching-removed region; etching the third insulating film on a side wall of the first groove to enlarge an opening dimension of the first groove; A second groove formed by etching and removing the lower layer film and the insulating film, and an etching region of the lower layer film and the insulating film and the first groove portion; Forming a step of the gate electrode of filling the conductive material to be connected to the gate electrode film in the second groove said MOS transistor, a method of manufacturing a semiconductor device which comprises a city.