JP2016025351A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a SGT of gate-last process, by forming a fin-like semiconductor layer, a columnar semiconductor layer, a gate electrode and gate wiring by two masks, thereby reducing the parasitic resistance, and to provide a structure of the SGT.SOLUTION: A method of manufacturing a semiconductor device has a first step for forming a fin-like semiconductor layer on a semiconductor substrate, and forming a first insulating film on the periphery thereof, a second step for forming a second insulating film on the periphery of the fin-like semiconductor layer, and forming a columnar semiconductor layer and a first dummy gate and a first hard mask, a third step for forming a second hard mask on the sidewall of the first hard mask, leaving second polysilicon on the sidewall of the first dummy gate and columnar semiconductor layer by etching, and fourth step for forming a fifth insulating film around the second dummy gate, leaving it like a sidewall by etching, forming a sidewall composed of the fifth insulating film, and then forming a first epitaxial growth layer on the fin-like semiconductor layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

  Semiconductor integrated circuits, in particular integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region. When the miniaturization of such a MOS transistor progresses, it is difficult to suppress the leakage current, and there is a problem that the occupied area of the circuit cannot be easily reduced due to a request for securing a necessary amount of current. In order to solve such a problem, a Surrounding Gate Transistor (hereinafter referred to as “SGT”) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and a gate electrode surrounds a columnar semiconductor layer is proposed. (For example, see Patent Document 1, Patent Document 2, and Patent Document 3).

  In a conventional SGT manufacturing method, a silicon pillar in which a nitride film hard mask is formed in a columnar shape is formed using a mask for drawing a silicon pillar, and a silicon pillar is drawn using a mask for drawing a planar silicon layer. A planar silicon layer is formed at the bottom, and a gate wiring is formed using a mask for drawing the gate wiring (see, for example, Patent Document 4). That is, a silicon pillar, a planar silicon layer, and a gate wiring are formed using three masks.

  Further, in a conventional MOS transistor, in order to achieve both a metal gate process and a high temperature process, a metal gate last process for creating a metal gate after a high temperature process is used in an actual product (Non-Patent Document 1). After forming a gate with polysilicon, an interlayer insulating film is deposited, then the polysilicon gate is exposed by chemical mechanical polishing, and after etching the polysilicon gate, a metal is deposited. Therefore, also in SGT, in order to make a metal gate process and a high temperature process compatible, it is necessary to use the metal gate last process which produces a metal gate after a high temperature process.

  Further, when the metal is embedded, if the upper part of the hole is narrower than the lower part of the hole, the upper part of the hole is filled first, and a hole is generated.

  In order to reduce the parasitic capacitance between the gate wiring and the substrate, the conventional MOS transistor uses the first insulating film. For example, in FINFET (Non-patent Document 2), a first insulating film is formed around one fin-like semiconductor layer, the first insulating film is etched back, the fin-like semiconductor layer is exposed, and the gate wiring and the substrate The parasitic capacitance between them is reduced. Therefore, also in SGT, it is necessary to use the first insulating film in order to reduce the parasitic capacitance between the gate wiring and the substrate. In SGT, since there is a columnar semiconductor layer in addition to the fin-shaped semiconductor layer, a device for forming the columnar semiconductor layer is required.

  Further, when the parasitic resistance of the fin-like semiconductor layer is large, the current driving capability of the transistor is reduced.

JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2009-182317 A

IEDM2007 K. Mistry et.al, pp 247-250 IEDM2010 CC.Wu, et.al, 27.1.1-27.1.4.

  Therefore, a method of manufacturing SGT, which is a gate last process, is obtained by forming a fin-like semiconductor layer, a columnar semiconductor layer, a gate electrode and a gate wiring with two masks, and having a structure for reducing parasitic resistance. An object is to provide a structure of SGT.

  The method for manufacturing a semiconductor device of the present invention includes a first step of forming a fin-like semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-like semiconductor layer, and after the first step, A second insulating film is formed around the fin-like semiconductor layer, a first polysilicon is deposited and planarized on the second insulating film, and a third insulating film is formed on the first polysilicon. A second resist for forming a gate wiring and a columnar semiconductor layer is formed in a direction perpendicular to the direction of the fin-shaped semiconductor layer, and the third insulating film and the first poly Etching silicon, the second insulating film, and the fin-like semiconductor layer to form a columnar semiconductor layer, a first dummy gate made of the first polysilicon, and a first hard mask made of the third insulating film Forming a second step and the second step Thereafter, a fourth insulating film is formed around the columnar semiconductor layer and the first dummy gate, a second polysilicon is deposited around the fourth insulating film, planarized, etched back, and A first hard mask is exposed, a sixth insulating film is deposited, and etching is performed to form a second hard mask on a sidewall of the first hard mask, and the second polysilicon is formed. A third step of forming a second dummy gate by etching and remaining on the side walls of the first dummy gate and the columnar semiconductor layer, and a fifth insulating film around the second dummy gate A fourth step of forming a first epitaxial growth layer on the fin-like semiconductor layer by forming, etching, remaining in a sidewall shape, forming a sidewall made of the fifth insulating film, and And features.

  The area of the upper surface of the second dummy gate is larger than the area of the lower surface of the second dummy gate.

  Further, after forming a fourth insulating film around the columnar semiconductor layer and the first dummy gate, a third resist is formed, etch back is performed, and the upper portion of the columnar semiconductor layer is exposed to expose the columnar semiconductor. A first diffusion layer is formed on the upper layer.

  In addition, a second diffusion layer is formed in the upper part of the fin-like semiconductor layer and the lower part of the columnar semiconductor layer after forming the sidewall made of the fifth insulating film.

  Further, a compound of a metal and a semiconductor is formed in the first epitaxial growth layer.

  In addition, after the fourth step, a contact stopper film is deposited, an interlayer insulating film is deposited, and chemical mechanical polishing is performed to expose the second dummy gate and the upper portion of the first dummy gate, The dummy gate and the first dummy gate are removed, the second insulating film and the fourth insulating film are removed, and the gate insulating film is disposed around the columnar semiconductor layer and inside the fifth insulating film. And a fifth step of forming a gate electrode and a gate wiring by depositing metal, performing etch back, and forming a gate electrode.

  The semiconductor device of the present invention is formed on the fin-like semiconductor layer, the fin-like semiconductor layer formed on the semiconductor substrate, the first insulating film formed around the fin-like semiconductor layer, and the fin-like semiconductor layer. A columnar semiconductor layer; a gate insulating film formed around the columnar semiconductor layer; a gate electrode made of metal formed around the gate insulating film; and the fin-shaped semiconductor layer connected to the gate electrode. A gate wiring made of a metal extending in an orthogonal direction; and a first epitaxial growth layer formed on the fin-like semiconductor layer, wherein the area of the gate electrode and the upper surface of the gate wiring is the gate The width of the first epitaxial growth layer in a direction perpendicular to the fin-like semiconductor layer is larger than the area of the lower surface of the electrode and the gate wiring, and the width of the fin-like semiconductor layer is the fin. And wherein the wider than the width in the direction perpendicular to the semiconductor layer.

  And a first diffusion layer formed on the columnar semiconductor layer, and a second diffusion layer formed on the fin semiconductor layer and on the columnar semiconductor layer. To do.

  The gate insulating film further includes the gate electrode and the gate insulating film formed around and at the bottom of the gate wiring.

  According to the present invention, a method for manufacturing an SGT, which is a gate last process, has a structure in which a fin-like semiconductor layer, a columnar semiconductor layer, a gate electrode and a gate wiring are formed with two masks to reduce parasitic resistance. The resulting SGT structure can be provided.

  A first step of forming a fin-like semiconductor layer on the semiconductor substrate and forming a first insulating film around the fin-like semiconductor layer; and a second step around the fin-like semiconductor layer after the first step. A first polysilicon is deposited and planarized on the second insulating film, a third insulating film is formed on the first polysilicon, and a gate wiring and a columnar semiconductor layer are formed. A second resist is formed in a direction perpendicular to the direction of the fin-like semiconductor layer, and the third insulating film, the first polysilicon, the second insulating film, and the Etching the fin-like semiconductor layer to form a columnar semiconductor layer, a first dummy gate made of the first polysilicon, and a first hard mask made of the third insulating film; After the two steps, the columnar semiconductor layer and the first A fourth insulating film is formed around the dummy gate, and second polysilicon is deposited and planarized around the fourth insulating film, etched back, and the first hard mask is exposed, A second hard mask is formed on the side wall of the first hard mask by depositing and etching the insulating film, and the second polysilicon is etched to thereby form the first dummy gate. And a third step of forming a second dummy gate, which is left on the side wall of the columnar semiconductor layer, thereby providing a fin-shaped semiconductor layer, a columnar semiconductor layer, and a gate electrode later with two masks. As a result, the first dummy gate and the second dummy gate to be the gate wiring can be formed, and the number of steps can be reduced.

  In addition, a fifth insulating film is formed around the second dummy gate, etched and left in a sidewall shape, and the first dummy gate and the second dummy gate are formed by the sidewall made of the fifth insulating film. 2 dummy gates are covered with sidewalls made of the first and second hard masks and the fifth insulating film, so that only the upper part of the fin-like semiconductor layer can be exposed, so that only on the fin-like semiconductor layer. A first epitaxial growth layer can be formed, and parasitic resistance can be reduced. In addition, the sidewalls made of the first and second hard masks and the fifth insulating film prevent the formation of the metal and semiconductor compound on the first and second dummy gates, and are formed on the fin-like semiconductor layer. A metal and semiconductor compound can be formed only in the first epitaxial growth layer.

  In addition, when etching the second polysilicon, by using reverse taper etching, the area of the upper surface of the second dummy gate can be made larger than the area of the lower surface of the second dummy gate. When the metal for embedding is embedded, voids can be prevented from being formed.

  Misalignment between the columnar semiconductor layer and the gate wiring can be eliminated.

  In addition, the first dummy gate and the second dummy gate are made of polysilicon, and after that, an interlayer insulating film is deposited, and then the first dummy gate and the second dummy gate are exposed by chemical mechanical polishing. Since the conventional metal gate last manufacturing method of depositing metal after etching the gate can be used, the metal gate SGT can be easily formed.

  Further, the gate electrode and the gate wiring can be insulated from the columnar semiconductor layer and the fin-shaped semiconductor layer by the gate insulating film formed around and at the bottom of the gate electrode and the gate wiring.

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  Below, the manufacturing process for forming the structure of SGT which concerns on embodiment of this invention is demonstrated with reference to FIGS.

  First, a first step of forming a fin-like semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-like semiconductor layer is shown. In this embodiment, the silicon substrate is used. However, a semiconductor other than silicon can be used as the substrate.

  As shown in FIG. 2, a first resist 102 for forming a fin-like silicon layer is formed on the silicon substrate 101.

  As shown in FIG. 3, the silicon substrate 101 is etched to form a fin-like silicon layer 103. Although the fin-like silicon layer is formed using a resist as a mask this time, a hard mask such as an oxide film or a nitride film may be used.

  As shown in FIG. 4, the first resist 102 is removed.

  As shown in FIG. 5, a first insulating film 104 is deposited around the fin-like silicon layer 103. An oxide film formed by high-density plasma or an oxide film formed by low-pressure CVD (Chemical Vapor Deposition) may be used as the first insulating film.

  As shown in FIG. 6, the 1st insulating film 104 is etched back and the upper part of the fin-like silicon layer 103 is exposed. The process up to here is the same as the manufacturing method of the fin-like silicon layer of Non-Patent Document 2.

  Thus, the first step of forming the fin-like silicon layer 103 on the silicon substrate 101 and forming the first insulating film 104 around the fin-like silicon layer 103 is shown.

  Next, a second insulating film is formed around the fin-like semiconductor layer, a first polysilicon is deposited and planarized on the second insulating film, and a third is formed on the first polysilicon. A second resist for forming a gate wiring and a columnar semiconductor layer is formed in a direction perpendicular to the direction of the fin-shaped semiconductor layer, and the third insulating film and the first insulating film are formed. 1 polysilicon, the second insulating film, and the fin-like semiconductor layer are etched, whereby a columnar semiconductor layer, a first dummy gate made of the first polysilicon, and a first insulating film made of the third insulating film. The 2nd process of forming a hard mask is shown.

  As shown in FIG. 7, a second insulating film 105 is formed around the fin-like silicon layer 103. The second insulating film 105 is preferably an oxide film. Further, a nitride film may be used for the second insulating film 105.

  As shown in FIG. 8, a first polysilicon 106 is deposited on the second insulating film 105 and planarized.

  As shown in FIG. 9, a third insulating film 107 is formed on the first polysilicon 106. The third insulating film 107 is preferably a nitride film.

  As shown in FIG. 10, a second resist 108 for forming the gate wiring and the columnar silicon layer is formed in a direction perpendicular to the direction of the fin-shaped silicon layer 103. Further, a hard mask may be used instead of the second resist 108.

  As shown in FIG. 11, by etching the third insulating film 107, the first polysilicon 106, the second insulating film 105, and the fin-like silicon layer 103, the columnar silicon layer 109 and the first silicon layer 109 are etched. A first dummy gate 106a made of one polysilicon and a first hard mask 107a made of a third insulating film are formed.

  As shown in FIG. 12, the second resist 108 is removed.

  As described above, the second insulating film is formed around the fin-like semiconductor layer, the first polysilicon is deposited and planarized on the second insulating film, and the third polysilicon is formed on the first polysilicon. A second resist for forming a gate wiring and a columnar semiconductor layer is formed in a direction perpendicular to the direction of the fin-shaped semiconductor layer, and the third insulating film and the first insulating film are formed. 1 polysilicon, the second insulating film, and the fin-like semiconductor layer are etched, whereby a columnar semiconductor layer, a first dummy gate made of the first polysilicon, and a first insulating film made of the third insulating film. A second step of forming a hard mask is shown.

  Next, after the second step, a fourth insulating film is formed around the columnar semiconductor layer and the first dummy gate, and second polysilicon is deposited around the fourth insulating film. By planarizing, etching back, exposing the first hard mask, depositing a sixth insulating film, and etching, a second hard mask is formed on the side wall of the first hard mask. 3 shows a third step of forming the second dummy gate by etching the second polysilicon so as to remain on the side walls of the first dummy gate and the columnar semiconductor layer.

  As shown in FIG. 13, a fourth insulating film 110 is formed around the columnar silicon layer 109 and the first dummy gate 106a. The fourth insulating film 110 is preferably an oxide film. Further, a nitride film may be used for the fourth insulating film 110.

  As shown in FIG. 14, a third resist 111 is formed and etched back to expose the upper portion of the columnar silicon layer 109. Further, an organic material or an inorganic material may be used as the third resist 111.

  As shown in FIG. 15, impurities are introduced to form a first diffusion layer 112 on the columnar silicon layer 109. In the case of an n-type diffusion layer, it is preferable to introduce arsenic or phosphorus. In the case of a p-type diffusion layer, it is preferable to introduce boron.

  As shown in FIG. 16, the third resist 111 is removed.

  As shown in FIG. 17, the second polysilicon 113 is deposited around the fourth insulating film 110 and planarized.

  As shown in FIG. 18, the second polysilicon 113 is etched back to expose the first hard mask 107a.

  As shown in FIG. 19, the 6th insulating film 114 is deposited. The sixth insulating film 114 is preferably a nitride film.

  As shown in FIG. 20, the 6th insulating film 114 is etched, The 2nd hard mask 114a is formed in the side wall of the said 1st hard mask 107a.

  As shown in FIG. 21, the second polysilicon 113 is etched to remain on the sidewalls of the first dummy gate 106a and the columnar semiconductor layer 109, thereby forming a second dummy gate 113a. When etching the second polysilicon 113, the area of the upper surface of the second dummy gate 113a can be made larger than the area of the lower surface of the second dummy gate 113a by using reverse taper etching. When embedding the metal for the gate, it is possible to prevent voids from being formed.

  As described above, after the second step, the fourth insulating film is formed around the columnar semiconductor layer and the first dummy gate, and the second polysilicon is deposited around the fourth insulating film. By planarizing, etching back, exposing the first hard mask, depositing a sixth insulating film, and etching, a second hard mask is formed on the side wall of the first hard mask. The third step of forming the second dummy gate by etching the second polysilicon so as to remain on the side walls of the first dummy gate and the columnar semiconductor layer is shown.

  Next, a fifth insulating film is formed around the second dummy gate, etched, and left in a sidewall shape to form a sidewall made of the fifth insulating film, and the fin-like semiconductor A fourth step of forming a first epitaxial growth layer on the layer is shown.

  As shown in FIG. 22, a fifth insulating film 115 is formed around the second dummy gate 113a. The fifth insulating film 115 is preferably a nitride film. The fifth insulating film 115 may have a stacked structure of an oxide film and a nitride film.

  As shown in FIG. 23, the fifth insulating film 115 is etched and left in the shape of a sidewall to form a sidewall 115a made of the fifth insulating film.

  As shown in FIG. 24, impurities are introduced to form a second diffusion layer 116 above the fin-like silicon layer 103 and below the columnar silicon layer 109. In the case of an n-type diffusion layer, it is preferable to introduce arsenic or phosphorus. In the case of a p-type diffusion layer, it is preferable to introduce boron.

  As shown in FIG. 25, selective epitaxial growth is performed to form a first epitaxial growth layer 117 on the fin-like semiconductor layer 103. The first epitaxial growth layer 117 is preferably silicon. Alternatively, a compound layer of silicon and germanium may be grown. The width of the first epitaxial growth layer 117 in the direction perpendicular to the fin-like semiconductor layer 103 is wider than the width of the fin-like semiconductor layer 103 in the direction perpendicular to the fin-like semiconductor layer 103. Since the first dummy gate and the second dummy gate are covered with the sidewalls made of the first and second hard masks and the fifth insulating film, only the upper part of the fin-like semiconductor layer can be exposed. The first epitaxial growth layer can be formed only on the fin-like semiconductor layer, and parasitic resistance can be reduced.

  As shown in FIG. 26, a metal-semiconductor compound 118 is formed in the first epitaxial growth layer 117. The metal / semiconductor compound 118 may be formed on the entire first epitaxial growth layer 117. In addition, the sidewalls made of the first and second hard masks and the fifth insulating film prevent the formation of the metal and semiconductor compound on the first and second dummy gates, and are formed on the fin-like semiconductor layer. A metal and semiconductor compound can be formed only in the first epitaxial growth layer.

  As described above, a fifth insulating film is formed around the second dummy gate, etched, left in a sidewall shape, and a sidewall made of the fifth insulating film is formed. A fourth step of forming a first epitaxial growth layer on the layer has been shown.

  Next, after the fourth step, a contact stopper film is deposited, an interlayer insulating film is deposited, and chemical mechanical polishing is performed to expose the upper portions of the second dummy gate and the first dummy gate, and 2 dummy gates and the first dummy gate are removed, the second insulating film and the fourth insulating film are removed, and the gate insulating film is formed around the columnar semiconductor layer and the fifth insulating film. A fifth step of forming a gate electrode and a gate wiring by forming metal, depositing an etch back, and forming a gate electrode and a gate wiring is shown.

  As shown in FIG. 27, a contact stopper film 119 is deposited, and an interlayer insulating film 120 is deposited. The contact stopper film 119 is preferably a nitride film.

  As shown in FIG. 28, chemical mechanical polishing is performed to expose the upper portions of the second dummy gate 113a and the first dummy gate 106a.

  As shown in FIG. 29, the second dummy gate 113a and the first dummy gate 106a are removed.

  As shown in FIG. 30, the second insulating film 105 and the fourth insulating film 110 are removed.

  As shown in FIG. 31, a gate insulating film 121 is formed around the columnar silicon layer 109 and inside the fifth insulating film 115a. The gate insulating film 121 is preferably a high dielectric film. As the gate insulating film 121, an oxide film, an oxynitride film, or a nitride film may be used.

  As shown in FIG. 32, a metal 122 is deposited.

  As shown in FIG. 33, the metal 122 is etched back to expose the upper portion of the columnar silicon layer 109. A gate electrode 122 a is formed around the columnar silicon layer 109. Further, the gate wiring 122b is formed. The gate electrode 122a and the gate wiring 122b are insulated from the columnar silicon layer 109 and the fin-shaped silicon layer 103 by the gate insulating film 121 formed around and at the bottom of the gate electrode 122a and the gate wiring 122b. Can do.

  As described above, after the fourth step, a contact stopper film is deposited, an interlayer insulating film is deposited and chemical mechanical polishing is performed, and the upper portions of the second dummy gate and the first dummy gate are exposed. 2 dummy gates and the first dummy gate are removed, the second insulating film and the fourth insulating film are removed, and the gate insulating film is formed around the columnar semiconductor layer and the fifth insulating film. A fifth step is shown in which a gate electrode and a gate wiring are formed by depositing a metal, etching back, and forming a gate electrode and a gate wiring.

  As shown in FIG. 34, the 7th insulating film 123 is deposited. The seventh insulating film 123 is preferably a nitride film.

  As shown in FIG. 35, the seventh insulating film 123 is etched back to expose the gate insulating film 121.

  As shown in FIG. 36, the exposed gate insulating film 121 is removed.

  As shown in FIG. 37, the 4th resist 124 for forming a contact hole is formed.

  As shown in FIG. 38, the contact hole 125 is formed by etching the interlayer insulating film 120.

  As shown in FIG. 39, the 4th resist 124 is removed.

  As shown in FIG. 40, the 5th resist 126 for forming a contact hole is formed.

  As shown in FIG. 41, the 7th insulating film 123 is etched and the contact hole 127 is formed.

  As shown in FIG. 42, the fifth resist 126 is removed.

  As shown in FIG. 43, the contact stopper film 119 under the contact hole 125 is removed.

  As shown in FIG. 44, metal 128 is deposited to form contacts 129 and 130.

  As shown in FIG. 45, sixth resists 131, 132, and 133 are formed to form metal wiring.

  As shown in FIG. 46, the metal 128 is etched to form metal wirings 128a, 128b, and 128c.

  As shown in FIG. 47, the sixth resists 131, 132, 133 are removed.

  As described above, a method of manufacturing SGT, which is a gate last process, has a structure in which a fin-like semiconductor layer, a columnar semiconductor layer, a gate electrode and a gate wiring are formed with two masks to reduce parasitic resistance. .

  A structure of a semiconductor device obtained by the manufacturing method is shown in FIG.

  1 includes a fin-like silicon layer 103 formed on a silicon substrate 101, a first insulating film 104 formed around the fin-like silicon layer 103, and the fin-like silicon layer. A columnar silicon layer 109 formed on the gate insulating layer 103; a gate insulating film 121 formed around the columnar silicon layer 109; a gate electrode 122a made of metal formed around the gate insulating film 121; A gate wiring 122b made of a metal extending in a direction orthogonal to the fin-like silicon layer 103 connected to the electrode 122a, and the area of the upper surface of the gate electrode 122a and the gate wiring 122b is the same as that of the gate electrode 122a. It is larger than the area of the lower surface of the gate wiring 122b and is formed on the fin-like silicon layer 103. And a width of the first epitaxial growth layer 117 in a direction perpendicular to the fin-like silicon layer 103 is perpendicular to the fin-like silicon layer 103 of the fin-like silicon layer 103. Wider than the width of the direction.

  Also, a first diffusion layer 112 formed on the columnar silicon layer 109, and a second diffusion layer 116 formed on the fin-like silicon layer 103 and below the columnar silicon layer 109, Have.

  The gate insulating film 121 is further formed on the periphery and bottom of the gate electrode 122a and the gate wiring 122b.

  By forming the first epitaxial growth layer 117 having a width wider than that of the fin-shaped silicon layer 103 on the fin-shaped silicon layer 103, parasitic resistance can be reduced. Moreover, since the width of the compound layer of the metal and semiconductor is increased, the parasitic resistance can be further reduced. Further, since the contact area with the contact is increased, the contact resistance with the contact can be reduced.

  Since it is formed by self-alignment, misalignment between the columnar silicon layer 109 and the gate wiring 122b can be eliminated.

  Further, the gate electrode 122a and the gate wiring 122b are insulated from the columnar silicon layer 109 and the fin-shaped silicon layer 103 by the gate insulating film 121 formed around and at the bottom of the gate electrode 122a and the gate wiring 122b. can do.

  It should be noted that the present invention can be variously modified and modified without departing from the broad spirit and scope of the present invention. Further, the above-described embodiment is for explaining an example of the present invention, and does not limit the scope of the present invention.

For example, in the above embodiment, a method of manufacturing a semiconductor device in which p-type (including p ⁺ -type) and n-type (including n ⁺ -type) are opposite in conductivity type, and a semiconductor obtained thereby An apparatus is naturally included in the technical scope of the present invention.

101. Silicon substrate 102. First resist 103. Fin-like silicon layer 104. First insulating film 105. Second insulating film 106. First polysilicon 106a. First dummy gate 107. Third insulating film 107a. First hard mask 108. Second resist 109. Columnar silicon layer 110. Fourth insulating film 111. Third resist 112. First diffusion layer 113. Second polysilicon 113a. Second dummy gate 114. Sixth insulating film 114a. Second hard mask 115. Fifth insulating film 115a. Sidewall 116. Second diffusion layer 117. First epitaxial growth layer 118. Compound of metal and semiconductor 119. Contact stopper film 120. Interlayer insulating film 121. Gate insulating film 122. Metal 122a. Gate electrode 122b. Gate wiring 123. Seventh insulating film 124. Fourth resist 125. Contact hole 126. Fifth resist 127. Contact hole 128. Metal 128a. Metal wiring 128b. Metal wiring 128c. Metal wiring 129. Contact 130. Contact 131. Sixth resist 132. Sixth resist 133. 6th resist

Claims (1)

A fin-like semiconductor layer formed on a semiconductor substrate;
A columnar semiconductor layer formed on the fin-shaped semiconductor layer;
A gate insulating film formed around the columnar semiconductor layer;
A gate electrode made of metal formed around the gate insulating film;
A gate wiring made of metal connected to the gate electrode;
A first epitaxial growth layer formed on the fin-like semiconductor layer,
The area of the upper surface of the gate electrode and the gate wiring is larger than the area of the lower surface of the gate electrode and the gate wiring, and the width of the first epitaxial growth layer in the direction perpendicular to the fin-like semiconductor layer is A semiconductor device, wherein the fin-shaped semiconductor layer is wider than a width in a direction perpendicular to the fin-shaped semiconductor layer.

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