JP5861197B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

  Semiconductor integrated circuits, in particular integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region. When the miniaturization of such a MOS transistor progresses, it is difficult to suppress the leakage current, and there is a problem that the occupied area of the circuit cannot be easily reduced due to a request for securing a necessary amount of current. In order to solve such a problem, a Surrounding Gate Transistor (hereinafter referred to as “SGT”) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and a gate electrode surrounds a columnar semiconductor layer is proposed. (For example, see Patent Document 1, Patent Document 2, and Patent Document 3).

In the conventional SGT manufacturing method, a silicon pillar in which a nitride film hard mask is formed in a columnar shape is formed using a mask for drawing a silicon pillar, and a silicon pillar is drawn using a mask for drawing a planar silicon layer. A planar silicon layer is formed at the bottom, and a gate wiring is formed using a mask for drawing the gate wiring (see, for example, Patent Document 4).
That is, a silicon pillar, a planar silicon layer, and a gate wiring are formed using three masks.

  Further, in a conventional MOS transistor, in order to achieve both a metal gate process and a high temperature process, a metal gate last process for creating a metal gate after a high temperature process is used in an actual product (Non-Patent Document 1). After forming a gate with polysilicon, an interlayer insulating film is deposited, then the polysilicon gate is exposed by chemical mechanical polishing, and after etching the polysilicon gate, a metal is deposited. Therefore, also in SGT, in order to make a metal gate process and a high temperature process compatible, it is necessary to use the metal gate last process which produces a metal gate after a high temperature process.

  In order to reduce the parasitic capacitance between the gate wiring and the substrate, the conventional MOS transistor uses the first insulating film. For example, in FINFET (Non-patent Document 2), a first insulating film is formed around one fin-like semiconductor layer, the first insulating film is etched back, the fin-like semiconductor layer is exposed, and the gate wiring and the substrate The parasitic capacitance between them is reduced. Therefore, also in SGT, it is necessary to use the first insulating film in order to reduce the parasitic capacitance between the gate wiring and the substrate. In SGT, since there is a columnar semiconductor layer in addition to the fin-shaped semiconductor layer, a device for forming the columnar semiconductor layer is required.

JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2009-182317 A

IEDM2007 K. Mistry et.al, pp 247-250 IEDM2010 CC.Wu, et.al, 27.1.1-27.1.4.

  Accordingly, an object of the present invention is to provide a method of manufacturing SGT which is a gate last process and a structure of SGT obtained as a result of forming a fin-like semiconductor layer, a columnar semiconductor layer, a gate electrode and a gate wiring with two masks. To do.

  The method for manufacturing a semiconductor device of the present invention includes a first step of forming a fin-like semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-like semiconductor layer, and after the first step, A second insulating film is formed around the fin-shaped semiconductor layer, a first polysilicon is deposited on the second insulating film and planarized, and a second wiring for forming a gate wiring and a columnar semiconductor layer is formed. The columnar semiconductor layer is formed by etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer in a direction perpendicular to the direction of the fin-shaped semiconductor layer. And a second step of forming a first dummy gate made of the first polysilicon.

  The method may further include forming a third insulating film on the first polysilicon after depositing and planarizing the first polysilicon on the second insulating film.

  Further, after the second step, a fourth insulating film is formed around the columnar semiconductor layer and the first dummy gate, and second polysilicon is deposited around the fourth insulating film, It has a third step of forming a second dummy gate by etching and remaining on the side walls of the first dummy gate and the columnar semiconductor layer.

  Further, after forming a fourth insulating film around the columnar semiconductor layer and the first dummy gate, a third resist is formed, etch back is performed, and the upper portion of the columnar semiconductor layer is exposed to expose the columnar semiconductor. A first diffusion layer is formed on the upper layer.

  Further, a fifth insulating film is formed around the second dummy gate, etched, and left in a sidewall shape to form a sidewall made of the fifth insulating film, and the fin-like semiconductor The method includes a fourth step of forming a second diffusion layer above the layer and below the columnar semiconductor layer, and forming a metal-semiconductor compound on the second diffusion layer.

  In addition, after the fourth step, a contact stopper film is deposited, an interlayer insulating film is deposited, and chemical mechanical polishing is performed to expose the second dummy gate and the upper portion of the first dummy gate, The dummy gate and the first dummy gate are removed, the second insulating film and the fourth insulating film are removed, and the gate insulating film is disposed around the columnar semiconductor layer and inside the fifth insulating film. A fifth step of forming a gate electrode and a gate wiring by depositing a metal film, performing an etch back, and forming a gate electrode.

  The semiconductor device of the present invention is formed on the fin-like semiconductor layer, the fin-like semiconductor layer formed on the semiconductor substrate, the first insulating film formed around the fin-like semiconductor layer, and the fin-like semiconductor layer. The width of the columnar semiconductor layer and the width of the columnar semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer is the same as the width of the fin-shaped semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer, and is formed around the columnar semiconductor layer. A gate insulating film, a gate electrode made of metal formed around the gate insulating film, a gate wiring made of metal extending in a direction perpendicular to the fin-like semiconductor layer connected to the gate electrode, The gate insulating film formed on the periphery and bottom of the gate electrode and the gate wiring, and the width outside the gate electrode and the width of the gate wiring are the same, and formed on the top of the columnar semiconductor layer A first diffusion layer, and having a second diffusion layer formed in the lower portion of the upper and the pillar-shaped semiconductor layer of the fin-shaped semiconductor layer.

  According to the present invention, a fin-like silicon layer, a columnar silicon layer, a gate electrode and a gate wiring are formed with two masks, and a method for producing SGT, which is a gate last process, and the resulting SGT structure are provided. be able to.

  A first step of forming a fin-like semiconductor layer on the semiconductor substrate and forming a first insulating film around the fin-like semiconductor layer; and a second step around the fin-like semiconductor layer after the first step. A first polysilicon is deposited and planarized on the second insulating film, and a second resist for forming a gate wiring and a columnar semiconductor layer is formed on the fin-shaped semiconductor layer. Forming the first polysilicon, the second insulating film, and the fin-like semiconductor layer by etching the first polysilicon, the second insulating film, and the fin-like semiconductor layer; A second step of forming a dummy gate; a fourth insulating film is formed around the columnar semiconductor layer and the first dummy gate; and a second polysilicon is deposited around the fourth insulating film. By etching, the above The fin-like semiconductor layer and the columnar semiconductor layer are formed with two masks by having a third step of forming a second dummy gate by remaining on the side walls of the one dummy gate and the columnar semiconductor layer. Then, a first dummy gate and a second dummy gate that will later become a gate electrode and a gate wiring can be formed, and the number of steps can be reduced.

  Misalignment between the columnar semiconductor layer and the gate wiring can be eliminated.

  In addition, the first dummy gate and the second dummy gate are made of polysilicon, and after that, an interlayer insulating film is deposited, and then the first dummy gate and the second dummy gate are exposed by chemical mechanical polishing. Since the conventional metal gate last manufacturing method of depositing metal after etching the gate can be used, the metal gate SGT can be easily formed.

  Further, the gate electrode and the gate wiring can be insulated from the columnar semiconductor layer and the fin-shaped semiconductor layer by the gate insulating film formed around and at the bottom of the gate electrode and the gate wiring.

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  Below, the manufacturing process for forming the structure of SGT which concerns on embodiment of this invention is demonstrated with reference to FIGS.

  First, a first step of forming a fin-like semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-like semiconductor layer is shown. In this embodiment, the silicon substrate is used, but a substrate made of another semiconductor may be used.

  As shown in FIG. 2, a first resist 102 for forming a fin-like silicon layer is formed on the silicon substrate 101.

  As shown in FIG. 3, the silicon substrate 101 is etched to form a fin-like silicon layer 103. Although the fin-like silicon layer is formed using a resist as a mask this time, a hard mask such as an oxide film or a nitride film may be used.

  As shown in FIG. 4, the first resist 102 is removed.

  As shown in FIG. 5, a first insulating film 104 is deposited around the fin-like silicon layer 103. As the first insulating film 104, an oxide film formed by high-density plasma or an oxide film formed by low-pressure CVD (Chemical Vapor Deposition) may be used.

  As shown in FIG. 6, the 1st insulating film 104 is etched back and the upper part of the fin-like silicon layer 103 is exposed. The process up to here is the same as the manufacturing method of the fin-like silicon layer of Non-Patent Document 2.

  Thus, the first step of forming the fin-like silicon layer 103 on the silicon substrate 101 and forming the first insulating film 104 around the fin-like silicon layer 103 is shown.

  Next, a second insulating film is formed around the fin-shaped semiconductor layer, and first polysilicon is deposited and planarized on the second insulating film to form a gate wiring and a columnar semiconductor layer. The second resist is formed in a direction perpendicular to the direction of the fin-shaped semiconductor layer, and the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer are etched to form a columnar shape. A second step of forming a semiconductor layer and a first dummy gate made of the first polysilicon is shown.

  As shown in FIG. 7, a second insulating film 105 is formed around the fin-like silicon layer 103. The second insulating film 105 is preferably an oxide film.

  As shown in FIG. 8, a first polysilicon 106 is deposited on the second insulating film 105 and planarized.

  As shown in FIG. 9, a third insulating film 107 is formed on the first polysilicon 106. The third insulating film 107 is preferably a nitride film.

  As shown in FIG. 10, a second resist 108 for forming the gate wiring and the columnar silicon layer is formed in a direction perpendicular to the direction of the fin-shaped silicon layer 103.

  As shown in FIG. 11, by etching the third insulating film 107, the first polysilicon 106, the second insulating film 105, and the fin-like silicon layer 103, the columnar silicon layer 109 and the first silicon layer 109 are etched. A first dummy gate 106 made of one polysilicon is formed. At this time, when the second resist is removed during etching, the third insulating film 107 functions as a hard mask. When the second resist is not removed during etching, the third insulating film may not be used.

  As shown in FIG. 12, the second resist 108 is removed.

  As described above, the second insulating film is formed around the fin-like semiconductor layer, the first polysilicon is deposited and planarized on the second insulating film, and the gate wiring and the columnar semiconductor layer are formed. The second resist is formed in a direction perpendicular to the direction of the fin-shaped semiconductor layer, and the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer are etched to form a columnar shape. A second step of forming a semiconductor layer and a first dummy gate made of the first polysilicon is shown.

  Next, after the second step, a fourth insulating film is formed around the columnar semiconductor layer and the first dummy gate, and second polysilicon is deposited around the fourth insulating film. , Shows a third step of forming a second dummy gate by etching and remaining on the side walls of the first dummy gate and the columnar semiconductor layer.

  As shown in FIG. 13, a fourth insulating film 110 is formed around the columnar silicon layer 109 and the first dummy gate 106. The fourth insulating film 110 is preferably an oxide film.

  As shown in FIG. 14, a third resist 111 is formed and etched back to expose the upper portion of the columnar silicon layer 109.

  As shown in FIG. 15, impurities are introduced to form a first diffusion layer 112 on the columnar silicon layer 109. In the case of an n-type diffusion layer, it is preferable to introduce arsenic or phosphorus. In the case of a p-type diffusion layer, it is preferable to introduce boron.

  As shown in FIG. 16, the third resist 111 is removed.

  As shown in FIG. 17, second polysilicon 113 is deposited around the fourth insulating film 110.

  As shown in FIG. 18, the second polysilicon 113 is etched, and the remaining portion of the second polysilicon 113 is left on the side walls of the first dummy gate 106 and the columnar silicon layer 109 to form the second polysilicon 113. The dummy gate 113 is formed.

  As described above, after the second step, the fourth insulating film is formed around the columnar semiconductor layer and the first dummy gate, and the second polysilicon is deposited around the fourth insulating film. The third step of forming the second dummy gate by etching is left on the side walls of the first dummy gate and the columnar semiconductor layer.

  Next, a fifth insulating film is formed around the second dummy gate, etched, and left in a sidewall shape to form a sidewall made of the fifth insulating film, and the fin shape A fourth step is shown in which a second diffusion layer is formed on the upper part of the semiconductor layer and the lower part of the columnar semiconductor layer, and a compound of metal and semiconductor is formed on the second diffusion layer.

  As shown in FIG. 19, a fifth insulating film 114 is formed around the second dummy gate 113. The fifth insulating film 114 is preferably a nitride film.

  As shown in FIG. 20, the fifth insulating film 114 is etched and left in a sidewall shape, thereby forming the sidewall 114 made of the fifth insulating film.

  As shown in FIG. 21, impurities are introduced to form a second diffusion layer 115 above the fin-like silicon layer 103 and below the columnar silicon layer 109. In the case of an n-type diffusion layer, it is preferable to introduce arsenic or phosphorus. In the case of a p-type diffusion layer, it is preferable to introduce boron.

  As shown in FIG. 22, a metal / semiconductor compound 116 is formed on the second diffusion layer 115. At this time, a metal-semiconductor compound 117 is also formed on the second dummy gate 113.

  As described above, a fifth insulating film is formed around the second dummy gate, etched, and left in a sidewall shape to form a sidewall made of the fifth insulating film. A fourth step is shown in which a second diffusion layer is formed in the upper part of the semiconductor layer and the lower part of the columnar semiconductor layer, and a compound of metal and semiconductor is formed on the second diffusion layer.

  Next, after the fourth step, a contact stopper film is deposited, an interlayer insulating film is deposited, and chemical mechanical polishing is performed to expose the upper portions of the second dummy gate and the first dummy gate, and 2 dummy gates and the first dummy gate are removed, the second insulating film and the fourth insulating film are removed, and the gate insulating film is formed around the columnar semiconductor layer and the fifth insulating film. A fifth step of forming a gate electrode and a gate wiring by forming metal, depositing an etch back, and forming a gate electrode and a gate wiring is shown.

  As shown in FIG. 23, a contact stopper film 118 is deposited, and an interlayer insulating film 119 is deposited. The contact stopper film 118 is preferably a nitride film.

  As shown in FIG. 24, chemical mechanical polishing is performed to expose the upper portions of the second dummy gate and the first dummy gate. At this time, the metal-semiconductor compound 117 formed on the second dummy gate 113 is removed.

  As shown in FIG. 25, the second dummy gate 113 and the first dummy gate 106 are removed.

  As shown in FIG. 26, the second insulating film 105 and the fourth insulating film 110 are removed.

  As shown in FIG. 27, a gate insulating film 120 is formed around the columnar silicon layer 109 and inside the fifth insulating film 114, and a metal 121 is deposited. A gate electrode 121 a is formed around the columnar silicon layer 109. In addition, the gate wiring 121b is formed. The gate electrode 121a and the gate wiring 121b are insulated from the columnar silicon layer 109 and the fin-shaped silicon layer 103 by the gate insulating film 120 formed around and at the bottom of the gate electrode 121a and the gate wiring 121b. Can do.

  As shown in FIG. 28, the metal 121 is etched back to expose the upper portion of the columnar silicon layer 109.

  As described above, after the fourth step, a contact stopper film is deposited, an interlayer insulating film is deposited and chemical mechanical polishing is performed, and the upper portions of the second dummy gate and the first dummy gate are exposed. 2 dummy gates and the first dummy gate are removed, the second insulating film and the fourth insulating film are removed, and the gate insulating film is formed around the columnar semiconductor layer and the fifth insulating film. A fifth step is shown in which a gate electrode and a gate wiring are formed by depositing a metal, etching back, and forming a gate electrode and a gate wiring.

  As shown in FIG. 29, an oxide film 122 is deposited.

  As shown in FIG. 30, a fourth resist 123 for forming contact holes is formed.

  As shown in FIG. 31, the contact holes 124 and 125 are formed by etching the oxide film 122, the gate insulating film 120, and the interlayer insulating film 119.

  As shown in FIG. 32, the 4th resist 123 is removed.

  As shown in FIG. 33, the 5th resist 126 for forming a contact hole is formed.

  As shown in FIG. 34, the oxide film 122 and the gate insulating film 120 are etched to form contact holes 127.

  As shown in FIG. 35, the fifth resist 126 is removed.

  As shown in FIG. 36, the contact stopper film 118 under the contact hole 124 is removed.

  As shown in FIG. 37, metal 128 is deposited to form contacts 129, 130, and 131.

  As shown in FIG. 38, sixth resists 132, 133, and 134 are formed to form metal wiring.

  As shown in FIG. 39, the metal 128 is etched to form metal wirings 135, 136, and 137.

  As shown in FIG. 40, the sixth resists 132, 133, and 134 are removed.

  As described above, the fin-like semiconductor layer, the columnar semiconductor layer, the gate electrode, and the gate wiring are formed using two masks, and the method for manufacturing SGT, which is a gate last process, is shown.

A structure of a semiconductor device obtained by the manufacturing method is shown in FIG.
A fin-like silicon layer 103 formed on the silicon substrate 101, a first insulating film 104 formed around the fin-like silicon layer 103, and a columnar silicon layer 109 formed on the fin-like silicon layer 103. And the width of the columnar silicon layer 109 in the direction orthogonal to the fin-shaped semiconductor layer is the same as the width of the fin-shaped silicon layer 103 in the direction orthogonal to itself, and the gate formed around the columnar silicon layer 109. An insulating film 120; a gate electrode 121a made of metal formed around the gate insulating film 120; and a gate made of metal extending in a direction perpendicular to the fin-like silicon layer 109 connected to the gate electrode 121a. The gate insulating film formed on the periphery and bottom of the wiring 121b, the gate electrode 121a, and the gate wiring 121b 20, the outer width W1 of the gate electrode 121a and the width W2 of the gate wiring 121b are the same, the first diffusion layer 112 formed on the columnar silicon layer 109, and the fin-like silicon layer 103. And a second diffusion layer 115 formed below the columnar silicon layer 109.

  Since it is formed by self-alignment, misalignment between the columnar silicon layer 109 and the gate wiring 121b can be eliminated.

  Further, the gate electrode 121a and the gate wiring 121b are insulated from the columnar silicon layer 109 and the fin-shaped silicon layer 103 by the gate insulating film 120 formed around and at the bottom of the gate electrode 121a and the gate wiring 121b. can do.

  It should be noted that the present invention can be variously modified and modified without departing from the broad spirit and scope of the present invention. Further, the above-described embodiment is for explaining an example of the present invention, and does not limit the scope of the present invention.

For example, in the above embodiment, a method of manufacturing a semiconductor device in which p-type (including p ⁺ -type) and n-type (including n ⁺ -type) are opposite in conductivity type, and a semiconductor obtained thereby An apparatus is naturally included in the technical scope of the present invention.

101. Silicon substrate 102. First resist 103. Fin-like silicon layer 104. First insulating film 105. Second insulating film 106. First polysilicon, first dummy gate 107. Third insulating film 108. Second resist 109. Columnar silicon layer 110. Fourth insulating film 111. Third resist 112. First diffusion layer 113. Second polysilicon, second dummy gate 114. Side wall 115. Made of fifth insulating film, fifth insulating film. Second diffusion layer 116. Compound of metal and semiconductor 117. Compound of metal and semiconductor 118. Contact stopper film 119. Interlayer insulating film 120. Gate insulating film 121. Metal 121a. Gate electrode 121b. Gate wiring 122. Oxide film 123. Fourth resist 124. Contact hole 125. Contact hole 126. Fifth resist 127. Contact hole 128. Metal 129. Contact 130. Contact 131. Contact 132. Sixth resist 133. Sixth resist 134. Sixth resist 135. Metal wiring 136. Metal wiring 137. Metal wiring

Claims (1)

Forming a fin-like semiconductor layer on a semiconductor substrate;
Forming a columnar semiconductor layer on the fin-shaped semiconductor layer;
Forming a first dummy gate so as to straddle the columnar semiconductor layer;
A method of manufacturing a semiconductor device, comprising: forming a second dummy gate on a side wall of the columnar semiconductor layer and a side wall of the first dummy gate after forming the columnar semiconductor layer and the first dummy gate.

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