CN101604705B - Fin grids transistor surrounded with grid electrodes and manufacturing method thereof - Google Patents
Fin grids transistor surrounded with grid electrodes and manufacturing method thereof Download PDFInfo
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- CN101604705B CN101604705B CN200910053502XA CN200910053502A CN101604705B CN 101604705 B CN101604705 B CN 101604705B CN 200910053502X A CN200910053502X A CN 200910053502XA CN 200910053502 A CN200910053502 A CN 200910053502A CN 101604705 B CN101604705 B CN 101604705B
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Abstract
A fin grids transistor surrounded with grid electrodes comprises a substrate, an insulating layer, a semiconductor layer, a grid medium layer, a control grid, a source electrode region and a drain electrode region; wherein the insulating layer and the semiconductor layer are arranged on the surface of the substrate in turn, the surface of the insulating layer close to the semiconductor layer is provided with a pit, and the semiconductor layer comprises a suspended part over the pit; the grid medium layer surrounds the suspended part of the semiconductor layer over the pit; and the control grid is arranged on the surface of the insulating layer and comprises a part surrounding the grid medium layer. The transistor and the manufacturing method have the advantages of improving the control capability of the grid electrode to conductive channels and the electric performance of the transistor, and have the advantages of high integration degree, low cost, and the like.
Description
[technical field]
The present invention relates to field of semiconductor devices, relate in particular to a kind of fin grids transistor surrounded with grid electrodes device and preparation method thereof.
[background technology]
In the past few decades, each lifting of silicon base CMOS device performance mainly be rely on device size reduce bring, mainly comprise reducing channel length gate oxide thickness and threshold voltage.But, the characteristic size of integrated circuit began to narrow down to inferior 100 nanometers in 1999, enter the era of nanotechnology, along with the further raising of chip integration, promptly further dwindling of device feature size will face a large amount of problems from aspects such as traditional working mode, traditional material and even traditional devices physical basis.Particularly from the 90nm node,, make the scaled limit that has reached it of traditional gate oxide thickness because of grid oxygen leakage current when grid oxygen critical thickness is following sharply increases.Therefore must be at basic research field seeking breakthroughs such as device physics, material, device architecture, critical process, integrated technologies.
At present, use the simple stress device to leak the carrier channels mobility and the current driving ability of cmos device effectively such as the silicon Germanium source of straining isolated layer or embedding.Therefore by using different stressors to obtain different stress levels, need not further dwindle under the situation of grid oxygen, can keep the trend (being Moore's Law) of CMOS performance improvement from 90nm, 65nm up to 45nm technology node semi-conductor industry.But, arrived 32nm and the lifting of the device performance that brought with lower node channel stress and stressor reduces rapidly, particularly the pMOS device since stress reduce can make its loss surpass 20% drive current.
Therefore, just near their physics limit, running into stern challenge aspect the characteristic size that further reduces integrated circuit, new important breakthrough must arranged on material and technology in existing body silicon materials and technology.In order to break through this restriction, the researcher constantly proposes and studies new device architecture and material, for example fin gate transistor (FinFETs), vertical MOSFETs, high k insulating material or metal gate.In addition, also stepping up research by the new channel material high mobility that for example Ge brought.On the other hand, also can promote the mobility of charge carrier rate by the optimization based on substrate and raceway groove crystal orientation, this method is crystallographic orientation technology (hybrid orientation technology).
In present semiconductor technology, cmos circuit mainly is to be produced on the silicon substrate with (100) crystal face, and this is because have little oxide-interface charge density and the highest electron mobility on (100) crystal face.But, the mobility in hole is lower on (100) wafer, this just makes the drive current of the pMOSFETs for preparing on (100) wafer be about half of nMOSFETs, though use bigger pMOSFETs can come balance nMOSFETs traditionally, in fact this has increased grid and parasitic capacitance.Have report (100) substrate by with channel direction from＜110 be transferred to＜100〉crystal orientation can improve the performance of pFET, work but more mainly is to concentrate in the effort that changes surface orientation, such as the lifting of adopting (110) or (111) substrate can bring more hole mobility.It is found that hole mobility (110) wafer＜have maximum on 110〉crystal orientation, this value is that the hole is more than the twice of the mobility on (100) wafer.But even under the situation of not considering channel direction, this crystal plane direction is not suitable for fully makes nFET.Thereby the crystallographic orientation technology promotes the purpose that the mobility of charge carrier rate reaches the boost device performance based on the optimization in substrate and raceway groove crystal orientation, promptly can be by preparing nMOS to realize the lifting of device performance at (110) zone preparation pMOS in (100) zone.But the employed substrate surface of crystallographic orientation technology is owing to have two kinds of different crystalline substance pictures simultaneously, and therefore preparation is difficult, and cost is higher, and is easy to generate dislocation and stretching material inside at the boundary of two kinds of brilliant pictures, has reduced transistorized electric property.
In addition, the researcher has also proposed some new construction devices, such as the FinFET that preamble is carried, in this structure, grid can be controlled ultra-thin body from both sides at least, thereby has improved grid to the control ability of raceway groove with reduced short-channel effect.In addition, this structure also allows raceway groove to mix, and has avoided in very little volume range doping content to occur the problem that fluctuates easily.Under the acting in conjunction of ultra-thin body, multiple-grid and non-impurity-doped raceway groove, can also improve the mobility of charge carrier in the raceway groove.All these advantages have improved the performance of FinFET greatly.But conventional FinFET preparation is limited to the pFET performance boost on (100) substrate, and conventional FinFET only controls raceway groove from both sides, and control ability promotes limited.In addition, the device of traditional F inFET distributes in two-dimensional directional, and promptly nFET and pFET prepare separately, has so just limited the further raising of the integrated level of device.
[summary of the invention]
Technical problem to be solved by this invention is that providing a kind of can carry out the circulating type fin gate transistor device of control comprehensively to raceway groove, improves transistorized electric property, and the manufacture method of described device is provided.
The technical problem that the present invention further solves is, a kind of high integration, low cost, the fin gate transistor device based on the mix-crystal picture that control ability is strong are provided, and the manufacture method of described device is provided.
In order to address the above problem, to the invention provides a kind of fin grids transistor surrounded with grid electrodes device and comprise: substrate; In insulating barrier and the semiconductor layer that substrate surface sets gradually, described insulating barrier has a depression near the surface of semiconductor layer, and described semiconductor layer comprises the overhanging portion that is positioned at the recess top; Gate dielectric layer, described gate dielectric layer are positioned at the overhanging portion of groove top around semiconductor layer; Described by gate dielectric layer around the semiconductor layer overhanging portion have first conduction type, the semiconductor layer of overhanging portion both sides has second conduction type; Control gate, described control gate is arranged at surface of insulating layer, and described control gate comprises the part around described gate dielectric layer; And source electrode and drain region, be arranged in the semiconductor layer of overhanging portion both sides, and, have second conduction type near the both sides of semiconductor layer overhanging portion.
As optional technical scheme, the described first conduction type N type, second conduction type is the P type, the crystal face of semiconductor layer surface is (110) face.
As optional technical scheme, the described first conduction type P type, second conduction type is the N type, the crystal face of semiconductor layer surface is (100) face.
As optional technical scheme, comprise two lightly doped regions, described two lightly doped regions lay respectively in source electrode and the drain region, have second conduction type, and the doping content of described lightly doped region is lower than other parts of source electrode and drain region.
The present invention further provides a kind of method of making above-mentioned device, comprised the steps: to provide substrate, described substrate surface is disposed with insulating barrier and semiconductor layer, and described semiconductor layer has first conduction type; Form two corrosion windows in semiconductor layer, described two windows are arranged in the pre-top that forms recess of insulating barrier; Adopt the method for isotropic etch to remove the insulating barrier of the semiconductor layer below between two corrosion windows, thereby in insulating barrier, form a depression, and make two semiconductor layers between the corrosion window unsettled; Adopt depositing operation, at the gate dielectric layer of semiconductor layer surface making around the semiconductor layer overhanging portion; Adopt depositing operation, make control gate at surface of insulating layer around gate dielectric layer by corrosion window; The semiconductor layer of doping circle segment both sides makes it have second conduction type.
As optional technical scheme, in the step of the semiconductor layer of described doping circle segment both sides, further comprise the steps: the semiconductor layer of circle segment both sides is carried out the doping first time, make doped portion be transformed into second conduction type, form side wall in the control gate both sides by first conduction type; Mix to not carried out the second time in the semiconductor layer with second conduction type, increase its doping content, thereby define owing to side wall blocks the lightly doped region that forms by the side wall shield portions.
The present invention further provides a kind of method of making above-mentioned device, comprise the steps: to provide substrate, described substrate surface is disposed with insulating barrier and semiconductor layer, in the described semiconductor layer, the pre-part that forms source and drain areas has second conduction type, and remainder has first conduction type; Form two corrosion windows in semiconductor layer, described two windows are arranged in the pre-top that forms recess of insulating barrier; Adopt the method for isotropic etch to remove the insulating barrier of the semiconductor layer below between two corrosion windows, thereby in insulating barrier, form a depression, and make two semiconductor layers between the corrosion window unsettled; Adopt depositing operation, at the gate dielectric layer of semiconductor layer surface making around the semiconductor layer overhanging portion; Adopt depositing operation, make control gate at surface of insulating layer around gate dielectric layer by corrosion window.
As optional technical scheme, adopt ion implantation technology to form second conduction type in by the semiconductor layer of gate dielectric layer circle segment in described pre-formation.
It is a kind of based on the fin grids transistor surrounded with grid electrodes device that the present invention also provides, and comprising: substrate; First insulating barrier, first semiconductor layer, second insulating barrier, second semiconductor layer that set gradually in substrate surface; Described first insulating barrier has a depression near the surface of first semiconductor layer, and described second insulating barrier has the through hole that connects first semiconductor layer and second semiconductor layer in the position corresponding with depression; Described first semiconductor layer comprises the overhanging portion between groove and through hole, and described second semiconductor layer comprises the overhanging portion that is positioned at the through hole top; Described first semiconductor layer surface has first crystal face, and described second semiconductor layer surface has second crystal face; First grid dielectric layer, described first grid dielectric layer is around the overhanging portion of first semiconductor layer between groove and through hole; Second gate dielectric layer, described second gate dielectric layer are positioned at the overhanging portion of through hole top around second semiconductor layer; Described first semiconductor layer by first grid dielectric layer around part have first conduction type, had second conduction type by first semiconductor layer of circle segment both sides; Described second semiconductor layer by second gate dielectric layer around part have second conduction type, had first conduction type by second semiconductor layer of circle segment both sides; Control gate, described control gate is arranged at first surface of insulating layer, and described control gate comprises around the part of described first grid dielectric layer and around the part of described second gate dielectric layer.
As optional technical scheme, the thickness of described first insulating barrier is greater than the thickness of second insulating barrier.
As optional technical scheme, described first conduction type is the N type, and second conduction type is the P type; Described first crystal face is (110), and described second crystal face is (100).
As optional technical scheme, described first conduction type is the P type, and second conduction type is the N type; Described first crystal face is (100), and described second crystal face is (110).
The present invention further provides a kind of method of making above-mentioned device, comprise the steps: to provide substrate, described substrate surface is disposed with first insulating barrier, first semiconductor layer, second insulating barrier and second semiconductor layer, described first semiconductor layer has second conduction type, second semiconductor layer has first conduction type, described first semiconductor layer surface has first crystal face, and described second semiconductor layer surface has second crystal face; Form in second semiconductor layer, second insulating barrier and first semiconductor layer and run through two above-mentioned three layers corrosion windows, described two windows are arranged in the pre-top that forms recess of first insulating barrier; Adopt the method for isotropic etch to remove first insulating barrier of first semiconductor layer below between two corrosion windows and second insulating barrier between two corrosion windows, thereby in first insulating barrier, form a depression, in second insulating barrier, form through hole, and make first semiconductor layer and second semiconductor layer between two corrosion windows unsettled; Adopt depositing operation, make the first grid dielectric layer and second gate dielectric layer respectively around first semiconductor layer and the second semiconductor layer overhanging portion in first semiconductor layer and second semiconductor layer surface; Adopt depositing operation, make control gate at first surface of insulating layer around the first grid dielectric layer and second gate dielectric layer by corrosion window; First semiconductor layer of doping circle segment both sides makes it have first conduction type, and second semiconductor layer of doping circle segment both sides makes it have second conduction type.
As optional technical scheme, in first semiconductor layer of described doping circle segment both sides and the step of second semiconductor layer, further comprise the steps: first semiconductor layer and second semiconductor layer of circle segment both sides are carried out the doping first time, make the part that is doped of first semiconductor layer be transformed into first conduction type by second conduction type, the part that is doped of second semiconductor layer is transformed into second conduction type by first conduction type; Form side wall in the control gate both sides; Do not mix to being carried out the second time in first semiconductor layer with first conduction type and second semiconductor layer, increase its doping content, thereby define owing to side wall blocks the lightly doped region that forms by the side wall shield portions with second conduction type.
The present invention further provides a kind of method of making above-mentioned device, comprise the steps: to provide substrate, described substrate surface is disposed with first insulating barrier, first semiconductor layer, second insulating barrier and second semiconductor layer, in described first semiconductor layer, the pre-part that forms source and drain areas has first conduction type, remainder has second conduction type, in described second semiconductor layer, the pre-part that forms source and drain areas has second conduction type, remainder has first conduction type, described first semiconductor layer surface has first crystal face, and described second semiconductor layer surface has second crystal face; Form in second semiconductor layer, second insulating barrier and first semiconductor layer and run through two above-mentioned three layers corrosion windows, described two windows are arranged in the pre-top that forms recess of first insulating barrier; Adopt the method for isotropic etch remove first semiconductor layer below between two corrosion windows first insulating barrier and, second insulating barrier between two corrosion windows, thereby in first insulating barrier, form a depression, in second insulating barrier, form through hole, and make first semiconductor layer and second semiconductor layer between two corrosion windows unsettled; Adopt depositing operation, make the first grid dielectric layer and second gate dielectric layer respectively around first semiconductor layer and the second semiconductor layer overhanging portion in first semiconductor layer and second semiconductor layer surface; Adopt depositing operation, make control gate at first surface of insulating layer around the first grid dielectric layer and second gate dielectric layer by corrosion window.
As optional technical scheme, adopt following steps to obtain first and second semiconductor layers: substrate is provided with described dopant states, described substrate surface has first insulating barrier and first semiconductor layer successively, in described first semiconductor layer, the pre-part that forms source and drain areas has first conduction type, and remainder has second conduction type; Provide support substrate, described support substrates surface has the corrosion barrier layer and second semiconductor layer successively, and in described second semiconductor layer, the part that forms source and drain areas in advance has second conduction type, and remainder has first conduction type; At superficial growth second insulating barrier of described first semiconductor layer away from substrate; Is bonding face away from the surface and second semiconductor layer of first semiconductor layer away from the surface of corrosion barrier layer with second insulating barrier, and substrate and support substrates are bonded together; Support substrates and corrosion barrier layer are removed in corrosion.
As optional technical scheme, adopt ion implantation technology to form second conduction type in by first semiconductor layer of first grid dielectric layer circle segment, and form first conduction type in by second semiconductor layer of the second gate dielectric layer circle segment in described pre-formation in described pre-formation.
The invention has the advantages that, form depression in the insulating barrier below semiconductor layer, to obtain unsettled semiconductor layer, and the further circulating type gate dielectric layer that forms around the semiconductor layer overhanging portion, fin gate transistor device with this kind grid structure, can improve the control ability of grid, improve transistorized electric property conducting channel.The present invention also provide a kind of with two transistors along fin gate transistor structure perpendicular to the overlapping setting of substrate direction, the structure that is provided further has extra advantages such as high integration, low cost except can improving the control ability of grid to conducting channel.
[description of drawings]
Accompanying drawing 1 is the process chart of the described manufacture method of the present invention's first embodiment;
Accompanying drawing 2 to accompanying drawing 9 is the process schematic representation of the described manufacture method of the present invention's first embodiment;
Accompanying drawing 10 is process charts of the described manufacture method of the present invention's second embodiment;
Accompanying drawing 11A is the process schematic representation of the described manufacture method of the present invention's second embodiment to accompanying drawing 12B;
Accompanying drawing 13 is process charts of the described manufacture method of the present invention's the 3rd embodiment;
Accompanying drawing 14 to accompanying drawing 21 is process schematic representations of the described manufacture method of the present invention's the 3rd embodiment;
Accompanying drawing 22 is process charts of the described manufacture method of the present invention's the 4th embodiment;
Accompanying drawing 23A is process schematic representations of the described manufacture method of the present invention's the 4th embodiment to accompanying drawing 26.
[embodiment]
Elaborate below in conjunction with the embodiment of accompanying drawing to fin grids transistor surrounded with grid electrodes device provided by the invention and preparation method thereof.
At first provide first embodiment of fin grids transistor surrounded with grid electrodes device and preparation method thereof.
Be the process chart of the described manufacture method of this embodiment shown in the accompanying drawing 1, comprise the steps: step S10, substrate is provided, described substrate surface is disposed with insulating barrier and semiconductor layer, and described semiconductor layer has first conduction type; Step S11 forms two corrosion windows in semiconductor layer, described two windows are arranged in the pre-top that forms recess of insulating barrier; Step S12 adopts the method for isotropic etch to remove the insulating barrier of the semiconductor layer below between two corrosion windows, thereby form a depression in insulating barrier, and makes two semiconductor layers between the corrosion window unsettled; Step S13 adopts depositing operation, at the gate dielectric layer of semiconductor layer surface making around the semiconductor layer overhanging portion; Step S14 adopts depositing operation, makes control gate around gate dielectric layer by corrosion window at surface of insulating layer; Step S15 carries out the first time to the semiconductor layer of circle segment both sides and mixes, and makes doped portion be transformed into second conduction type by first conduction type; Step S16 forms side wall in the control gate both sides; Step S17 mixes to not carried out the second time by the side wall shield portions in the semiconductor layer with second conduction type, increases its doping content, thereby defines owing to side wall blocks the lightly doped region that forms.
Accompanying drawing 2 is depicted as the process schematic representation of above step to accompanying drawing 9.
Shown in the accompanying drawing 2, refer step S10 provides substrate 100, and described substrate 100 surfaces are disposed with insulating barrier 110 and semiconductor layer 120, and described semiconductor layer 120 has first conduction type.
In this embodiment, substrate 100 is a monocrystalline substrate, and the material of described insulating barrier 110 is a silicon dioxide, and the material of described semiconductor layer 120 is a monocrystalline silicon, and described first conduction type is the N type.
In other execution mode, substrate 100 also can be other materials such as sapphire or compound semiconductor such as carborundum, insulating barrier 110 also can be other materials such as silicon nitride, silicon oxynitride, and semiconductor layer 120 also can be other materials such as stress silicon, carborundum or SiGe.
Shown in accompanying drawing 3A and the accompanying drawing 3B, refer step S11 forms two corrosion windows 121 and 122 in semiconductor layer 120, and described two windows are arranged in the insulating barrier 110 pre-tops that form recess.Wherein, shown in the accompanying drawing 3A vertical view of this processing step implementation result, accompanying drawing 3B is the profile of accompanying drawing 3A along the A-A direction.
More than the method that forms window 121 and 122 can adopt photoetching and corroding method, repeats no more herein.
Shown in accompanying drawing 4A, 4B and the 4C, refer step S12, adopt the method for isotropic etch to remove the insulating barrier of the semiconductor layer below between two corrosion windows 121 and 122, thereby in insulating barrier 110, form a depression 111, and make the semiconductor layer between two corrosion windows 111 and 112 unsettled.This step forms an overhanging portion 123 in semiconductor layer 120.
Wherein, accompanying drawing 4A is the vertical view of this processing step implementation result, and accompanying drawing 4B is the profile of accompanying drawing 4A along the A-A direction, and accompanying drawing 4C is the profile of accompanying drawing 4A along the B-B direction.
The isotropic etch method is a kind of caustic solution common in the semiconductor technology, for common material ripe isotropic etch liquid and etching condition is arranged all.For example can adopt hydrofluoric acid to carry out the isotropic corrosion for silica or silicon nitride.Isotropic etch when corroding perpendicular to the direction on insulating barrier 110 surfaces, the part that can also sideetching be covered, and then make the part of semiconductor layer 120 unsettled by semiconductor layer 120, thus obtain structure as accompanying drawing 4B and 4C.
Shown in accompanying drawing 5A, 5B and the 5C, refer step S13 adopts depositing operation, makes the gate dielectric layer 130 around semiconductor layer overhanging portion 123 on semiconductor layer 120 surfaces.
Wherein, accompanying drawing 5A is the vertical view of this processing step implementation result, and accompanying drawing 5B is the profile of accompanying drawing 5A along the A-A direction, and accompanying drawing 5C is the profile of accompanying drawing 5A along the B-B direction.
In this embodiment, the material of described gate dielectric layer is a silica.In other execution mode, the gate dielectric layer material also can be a high dielectric constant material common in silicon nitride or the semiconductor technology.
So-called depositing operation, for example chemical vapour deposition (CVD) is that substrate is placed specific atmosphere, the source material reacts and generates the process of target substance at substrate surface at substrate surface.Because substrate is immersed among the reaction atmosphere, so depositing operation not only can be on the surface of semiconductor layer 120, and can generate target substance in the side and the back side.
Then by photoetching and corroding method, remainder removed and only keep gate dielectric layer 130 around semiconductor layer overhanging portion 123.
Shown in accompanying drawing 6A, 6B and the 6C, refer step S14 adopts depositing operation, makes control gates 140 around gate dielectric layer 130 on insulating barrier 110 surfaces by corrosion window.
Wherein, accompanying drawing 6A is the vertical view of this processing step implementation result, and accompanying drawing 6B is the profile of accompanying drawing 6A along the A-A direction, and accompanying drawing 6C is the profile of accompanying drawing 6A along the B-B direction.
The material of described control gate 140 can be polysilicon or metal material, for example aluminium etc.
Depositing operation, for example electron beam deposition process metal or chemical vapour deposition (CVD) polysilicon etc. can wrap up the layer of metal layer equally around control gate 140, and by photoetching and the unwanted part of erosion removal, form the described structure of accompanying drawing 6A to 6C.
In the above grid structure that obtains, gate dielectric layer and control gate not only are arranged on the surface of conducting channel, also are arranged at the back side even, side, are a kind of typical fin grid structures therefore.
Shown in accompanying drawing 7A and the 7B, refer step S15 carries out the first time to the semiconductor layer 120 of circle segment both sides and mixes, and makes doped portion 124 and 125 be transformed into second conduction type by first conduction type.
Wherein, accompanying drawing 7A is the vertical view of this processing step implementation result, and accompanying drawing 7B is the profile of accompanying drawing 5A along the B-B direction.This step there is no significant change along the structure with the B-B vertical direction after implementing to finish, so omit.
Described second conduction type is the P type, and dopant can be selected boron for use, adopts the mode of ion injection or diffusion to carry out.In the process of mixing, can adopt photoresist, will not need doped regions to shelter as mask layer, wait to inject finish after, again mask layer is removed.Above technology is the common means in this area, will not give unnecessary details herein.
Shown in accompanying drawing 8A and the 8B, refer step S16 forms side wall 151 and 152 (Spacer) in the control gate both sides.
The technology that forms side wall in the grid both sides is the common means in this area, will not give unnecessary details herein.
Shown in the accompanying drawing 9, refer step S17, to not carried out the doping second time in the semiconductor layer 120 with second conduction type, increase its doping content, thereby define owing to side wall 151 and 152 blocks the lightly doped region 126 and 127 that forms by side wall 151 and 152 shield portions.Mix for the second time injection element that adopted of this step is identical with the injection element that mixes for the first time.
Above step S16 and S17 are the technology of a kind of formation lightly doped drain (LDD) structure, belong to optional step, belong to the optional step of carrying out in order to improve the transistor electricity performance.In the actual implementation process,, also can adopt other by the known more complicated technology of those skilled in that art in order to make good LDD structure.
Above step can further adopt semiconductor postchannel process means after implementing to finish, and metal damascene structure or other similar structures in chip surface formation multilayer with extraction electrode, thereby form complete fin gate transistor device.
The fin gate transistor device architecture that is obtained after above-mentioned steps is implemented to finish comprises substrate 100 as shown in Figure 9; The insulating barrier 110 and the semiconductor layer 120 that set gradually in substrate 100 surfaces, described insulating barrier 110 has a depression near the surface of semiconductor layer 120, and described semiconductor layer comprises the overhanging portion 123 that is positioned at the recess top; Gate dielectric layer 130, described gate dielectric layer 130 are positioned at the overhanging portion 123 of groove top around semiconductor layer 120; Described by gate dielectric layer 130 around semiconductor layer overhanging portion 123 have first conduction type, the semiconductor layer of overhanging portion both sides has second conduction type; Control gate 140, described control gate 140 is arranged at insulating barrier 110 surfaces, and described control gate 140 comprises the part around described gate dielectric layer 130; Source electrode and drain region 124 and 125 are arranged in the semiconductor layer of overhanging portion both sides, and near the both sides of semiconductor layer overhanging portion, have second conduction type; And two lightly doped regions 126 and 127, described two lightly doped regions 126 and 127 lay respectively in source electrode and drain region 124 and 125, have second conduction type, described lightly doped region 126 and 127 doping content are lower than other parts of source electrode and drain region 124 and 125.The material of above various piece and correlation can be with reference to the contents described in the manufacture method.
The advantage of said structure is, form depression in the insulating barrier below semiconductor layer, to obtain unsettled semiconductor layer, and the further circulating type gate dielectric layer that forms around the semiconductor layer overhanging portion, fin gate transistor device with this kind grid structure, can improve the control ability of grid, improve transistorized electric property conducting channel.
Next provide second embodiment of fin grids transistor surrounded with grid electrodes device of the present invention and preparation method thereof in conjunction with the accompanying drawings.
It shown in the accompanying drawing 10 process chart of the described manufacture method of this embodiment, comprise the steps: step S20, substrate is provided, described substrate surface is disposed with insulating barrier and semiconductor layer, in the described semiconductor layer, the pre-part that forms source and drain areas has second conduction type, and remainder has first conduction type; Step S21 forms two corrosion windows in semiconductor layer, described two windows are arranged in the pre-top that forms recess of insulating barrier; Step S22 adopts the method for isotropic etch to remove the insulating barrier of the semiconductor layer below between two corrosion windows, thereby form a depression in insulating barrier, and makes two semiconductor layers between the corrosion window unsettled; Step S23 adopts depositing operation, at the gate dielectric layer of semiconductor layer surface making around the semiconductor layer overhanging portion; Step S24 adopts depositing operation, makes control gate around gate dielectric layer by corrosion window at surface of insulating layer.
Accompanying drawing 11A is the process schematic representation of this embodiment to accompanying drawing 12B.
Shown in accompanying drawing 11A and the 11B, refer step S20 provides substrate 200, described substrate 200 surfaces are disposed with insulating barrier 210 and semiconductor layer 220, in the described semiconductor layer 220, the part 221 and 222 that forms source and drain areas in advance has second conduction type, and remainder has first conduction type.
Wherein, Figure 11 A is the vertical view of structure that this step provides, and Figure 11 B is the profile of Figure 11 A along the B-B direction.
Can adopt ion implantation technology to form second conduction type in by the semiconductor layer of gate dielectric layer circle segment, to form the doped structure of above-mentioned semiconductor layer 220 in described pre-formation.
Shown in accompanying drawing 12A and the 12B, refer step S21 forms two corrosion windows 223 and 224 in semiconductor layer 220, and described two corrosion windows 223 and 224 are arranged in the insulating barrier 210 pre-tops that form recess.
Wherein, Figure 12 A is the vertical view of this step implementation result, and Figure 12 B is the profile of Figure 12 A along the A-A direction.Figure 12 A along with the cross-section structure and the no change of A-A vertical direction, so omit.
Identical with implementation method with previous embodiment down to step S24, so will not give unnecessary details.After step S24 was finished, all right further growth side wall was to form the LDD structure.Device architecture after the formation LDD structure is identical with structure shown in the accompanying drawing 9 of previous embodiment.
After step S24 was finished, because the Semiconductor substrate that is provided in step S20 has had pre-doping, first embodiment of therefore comparing need not to carry out doping process again.
Next provide the 3rd embodiment of fin grids transistor surrounded with grid electrodes device of the present invention and preparation method thereof in conjunction with the accompanying drawings.
It shown in the accompanying drawing 13 process chart of the described manufacture method of this embodiment, comprise the steps: step S30, substrate is provided, described substrate surface is disposed with first insulating barrier, first semiconductor layer, second insulating barrier, second semiconductor layer, described first semiconductor layer has second conduction type, second semiconductor layer has first conduction type, and described first semiconductor layer surface has first crystal face, and described second semiconductor layer surface has second crystal face; Step S31 forms in second semiconductor layer, second insulating barrier and first semiconductor layer and runs through two above-mentioned three layers corrosion windows, and described two windows are arranged in the pre-top that forms recess of first insulating barrier; Step S32, adopt the method for isotropic etch to remove first insulating barrier of first semiconductor layer below between two corrosion windows and second insulating barrier between two corrosion windows, thereby in first insulating barrier, form a depression, in second insulating barrier, form through hole, and make first semiconductor layer and second semiconductor layer between two corrosion windows unsettled; Step S33 adopts depositing operation, makes the first grid dielectric layer and second gate dielectric layer around first semiconductor layer and the second semiconductor layer overhanging portion respectively in first semiconductor layer and second semiconductor layer surface; Step S34 adopts depositing operation, makes control gate around the first grid dielectric layer and second gate dielectric layer by corrosion window at first surface of insulating layer; Step S35, first semiconductor layer and second semiconductor layer to the circle segment both sides carry out the doping first time, make the part that is doped of first semiconductor layer be transformed into first conduction type by second conduction type, the part that is doped of second semiconductor layer is transformed into second conduction type by first conduction type; Step S36 forms side wall in the control gate both sides; Step S37, do not mix to being carried out the second time in first semiconductor layer with first conduction type and second semiconductor layer by the side wall shield portions with second conduction type, increase its doping content, thereby define owing to side wall blocks the lightly doped region that forms.
Accompanying drawing 14 to accompanying drawing 21 is the process schematic representation of this embodiment.
Shown in the accompanying drawing 14, refer step S30, substrate 300 is provided, described substrate 300 surfaces are disposed with first insulating barrier 310, first semiconductor layer 330, second insulating barrier 320, second semiconductor layer 340, described first semiconductor layer 330 has second conduction type, and second semiconductor layer 340 has first conduction type.
In this embodiment, the thickness of described first insulating barrier 310 is greater than the thickness of second insulating barrier 320, and this is provided with and is beneficial to the device that improves follow-up making and the electric isolation characteristic between the substrate.
In this embodiment, first conduction type is the N type, and second conduction type is the P type, and first crystal face is (110), and described second crystal face is (100).N type semiconductor layer has (100) crystal face, the advantage that p type semiconductor layer has (110) crystal face is, the follow-up P-type conduction raceway groove that in n type semiconductor layer, forms, p type semiconductor layer forms under the situation of N type conducting channel, the P-type conduction channel shape is formed in (110) crystal face zone, and N type conducting channel is formed at (100) crystal face zone, therefore helps improving the electron mobility of conducting channel, thereby improves transistorized electrology characteristic.
In other embodiment, also can be that first conduction type is the P type, second conduction type is the N type.Corresponding, first crystal face is (100), described second crystal face is (110).
In this embodiment, substrate 300 is a monocrystalline substrate, and the material of described first insulating barrier 310 and second insulating barrier 320 is a silicon dioxide, and the material of described first semiconductor layer 330 and second semiconductor layer 340 is a monocrystalline silicon.
In other execution mode, substrate 300 also can be other materials such as sapphire or compound semiconductor such as carborundum, first insulating barrier 310 and second insulating barrier 320 also can be other materials such as silicon nitride, silicon oxynitride, and first semiconductor layer 330 and second semiconductor layer 340 also can be other materials such as stress silicon, carborundum or SiGe.First insulating barrier 310 can be selected identical or different materials according to actual conditions with second insulating barrier 320, first semiconductor layer 330 and second semiconductor layer 340.
Shown in accompanying drawing 15A and the 15B, refer step S31, in second semiconductor layer 340, second insulating barrier 320 and first semiconductor layer 330, form run through above-mentioned three layers two corrosion windows 351 with 352, described two windows are arranged in the tops of first insulating barrier, 310 pre-formation recess.
Wherein, Figure 15 A is the vertical view of this step implementation result, and Figure 15 B is the profile of Figure 15 A along the A-A direction.
More than the method that forms window 351 and 352 can adopt photoetching and corroding method, and adopts different etchant gas or etchant solution at different materials, and above etching process is a common methods in this area, repeats no more herein.
Shown in accompanying drawing 16A, 16B and the 16C, refer step S32, adopt the method for isotropic etch to remove first insulating barrier 310 of first semiconductor layer, 330 belows between two corrosion windows 351 and 352 and second insulating barrier 320 between two corrosion windows 351 and 352, thereby in first insulating barrier 310, form a depression 311, in second insulating barrier 320, form through hole, and make first semiconductor layer 330 and 340 layers of second semiconductors between two corrosion windows 351 and 352 unsettled.
Wherein, accompanying drawing 16A is the vertical view of this processing step implementation result, and accompanying drawing 16B is the profile of accompanying drawing 16A along the A-A direction, and accompanying drawing 16C is the profile of accompanying drawing 16A along the B-B direction.
Isotropic etch technology is both can use the effect that this technology can obtain sideetching to a kind of common etching process of side etch again to the direction corrosion perpendicular to the surface.Narration about this technology can be with reference to first embodiment of the present invention.
Shown in accompanying drawing 17A, 17B and the 17C, refer step S33, adopt depositing operation, make the first grid dielectric layer 360 and second gate dielectric layer 370 on first semiconductor layer 330 and second semiconductor layer, 340 surfaces respectively around first semiconductor layer 330 and second semiconductor layer, 340 overhanging portions.
Wherein, accompanying drawing 17A is the vertical view of this processing step implementation result, and accompanying drawing 17B is the profile of accompanying drawing 17A along the A-A direction, and accompanying drawing 17C is the profile of accompanying drawing 17A along the B-B direction.
In this embodiment, the material of described gate dielectric layer is a silica.In other execution mode, the gate dielectric layer material also can be a high dielectric constant material common in silicon nitride or the semiconductor technology.
So-called depositing operation, for example chemical vapour deposition (CVD) is that substrate is placed specific atmosphere, the source material reacts and generates the process of target substance at substrate surface at substrate surface.Because substrate is immersed among the reaction atmosphere, so depositing operation not only can be on first semiconductor layer 330 and second semiconductor layer, 340 surfaces, and can be at side and back side generation target substance.
Then by photoetching and corroding method, remainder removed and only keep the first grid dielectric layer 360 and second gate dielectric layer 370 around first semiconductor layer 330 and second semiconductor layer, 340 surperficial overhanging portions.
Shown in accompanying drawing 18A, 18B and the 18C, step S34 adopts depositing operation, makes control gates 380 around the first grid dielectric layer 360 and second gate dielectric layer 370 on first insulating barrier, 310 surfaces by corrosion window.
Wherein, accompanying drawing 18A is the vertical view of this processing step implementation result, and accompanying drawing 18B is the profile of accompanying drawing 18A along the A-A direction, and accompanying drawing 18C is the profile of accompanying drawing 18A along the B-B direction.
The material of described control gate 380 can be polysilicon or metal material, for example aluminium etc.
Depositing operation, for example electron beam deposition process metal or chemical vapour deposition (CVD) polysilicon etc. can wrap up the layer of metal layer equally around control gate 380, and by photoetching and the unwanted part of erosion removal, form the described structure of accompanying drawing 18A to 18C.
Shown in accompanying drawing 19A and the 19B, refer step S35, first semiconductor layer 330 and second semiconductor layer 340 to the circle segment both sides carry out the doping first time, make the part 331 that is doped of first semiconductor layer 330 be transformed into first conduction type by second conduction type, the part 341 that is doped of second semiconductor layer 340 is transformed into second conduction type by first conduction type
Wherein, accompanying drawing 19A is the vertical view of this processing step implementation result, and accompanying drawing 19B is the profile of accompanying drawing 19A along the B-B direction.This step there is no significant change along the structure with the B-B vertical direction after implementing to finish, so omit.
Under the situation that forms the P-type conduction type, dopant can be selected boron for use; Under the situation that forms N type conduction type, dopant can be selected phosphorus for use.Doping can adopt ion to inject or the mode of diffusion is carried out.In the process of mixing, can adopt photoresist, will not need doped regions to shelter as mask layer, wait to inject finish after, again mask layer is removed.Above technology is the common means in this area, will not give unnecessary details herein.
Shown in accompanying drawing 20A and the 20B, refer step S36 forms side wall 391 and 392 in the control gate both sides.
The technology that forms side wall in the grid both sides is the common means in this area, will not give unnecessary details herein.
Shown in the accompanying drawing 21, refer step S37, do not mix to being carried out the second time in first semiconductor layer 330 with first conduction type and second semiconductor layer 340 by side wall 391 and 392 shield portions with second conduction type, increase its doping content, thereby define owing to side wall blocks the lightly doped region 332 and 342 that forms.
Mix for the second time injection element that adopted of this step is identical with the injection element that mixes for the first time.
Above step S36 and S37 are the technology of a kind of formation lightly doped drain (LDD) structure, belong to optional step, belong to the optional step of carrying out in order to improve the transistor electricity performance.In the actual implementation process,, also can adopt other by the known more complicated technology of those skilled in that art in order to make good LDD structure.
Above step can further adopt semiconductor postchannel process means after implementing to finish, and forms step so that make electrode being doped part surface, and forms metal damascene structure or other similar structures of multilayer at chip surface, with extraction electrode.
Structure after above-mentioned steps is implemented to finish comprises substrate 300 as shown in Figure 21; First insulating barrier 310, first semiconductor layer 330, second insulating barrier 320, second semiconductor layer 340 that set gradually in substrate surface; Described first insulating barrier 310 has a depression near the surface of first semiconductor layer 330, and described second insulating barrier 320 has the through hole that connects first semiconductor layer 330 and second semiconductor layer 340 in the position corresponding with depression; Described first semiconductor layer 330 comprises the overhanging portion between groove and through hole, and described second semiconductor layer 340 comprises the overhanging portion that is positioned at the through hole top; Described first semiconductor layer 330 surfaces have first crystal face, and described second semiconductor layer 340 surfaces have second crystal face; First grid dielectric layer 360, described first grid dielectric layer 360 is around the overhanging portion of first semiconductor layer 330 between groove and through hole; Second gate dielectric layer 370, described second gate dielectric layer 370 are positioned at the overhanging portion of through hole top around second semiconductor layer 340; Described first semiconductor layer 330 by first grid dielectric layer 360 around part have first conduction type, had second conduction type by first semiconductor layer 330 of circle segment both sides; Described second semiconductor layer 340 by second gate dielectric layer 370 around part have second conduction type, had first conduction type by second semiconductor layer 340 of circle segment both sides; Control gate 380, described control gate 380 are arranged at first insulating barrier, 310 surfaces, and described control gate 380 comprises around the part of described first grid dielectric layer 360 and around the part of described second gate dielectric layer 370.The material of above various piece and correlation can be with reference to the contents described in the manufacture method.
In the fin gate transistor device that above embodiment obtained, two fin gate transistors further have extra advantages such as high integration, low cost along perpendicular to the overlapping setting of substrate direction.
Next provide the 4th embodiment of fin grids transistor surrounded with grid electrodes device of the present invention and preparation method thereof in conjunction with the accompanying drawings.
It shown in the accompanying drawing 22 process chart of the described manufacture method of this embodiment, comprise the steps: step S40, substrate is provided, described substrate surface has first insulating barrier and first semiconductor layer successively, in described first semiconductor layer, the pre-part that forms source and drain areas has first conduction type, and remainder has second conduction type, and described first semiconductor layer surface has first crystal face; Step S41, provide support substrate, described support substrates surface has the corrosion barrier layer and second semiconductor layer successively, in described second semiconductor layer, the pre-part that forms source and drain areas has second conduction type, remainder has first conduction type,, described second semiconductor layer surface has second crystal face; Step S42 is at superficial growth second insulating barrier of described first semiconductor layer away from substrate; Step S43 is bonding face away from the surface and second semiconductor layer of first semiconductor layer away from the surface of corrosion barrier layer with second insulating barrier, and substrate and support substrates are bonded together; Step S44, support substrates and corrosion barrier layer are removed in corrosion; Step S45 forms in second semiconductor layer, second insulating barrier and first semiconductor layer and runs through two above-mentioned three layers corrosion windows, and described two windows are arranged in the pre-top that forms recess of first insulating barrier; Step S46, adopt the method for isotropic etch remove first semiconductor layer below between two corrosion windows first insulating barrier and, second insulating barrier between two corrosion windows, thereby in first insulating barrier, form a depression, in second insulating barrier, form through hole, and make first semiconductor layer and second semiconductor layer between two corrosion windows unsettled; Step S47 adopts depositing operation, makes the first grid dielectric layer and second gate dielectric layer around first semiconductor layer and the second semiconductor layer overhanging portion respectively in first semiconductor layer and second semiconductor layer surface; Step S48 adopts depositing operation, makes control gate around the first grid dielectric layer and second gate dielectric layer by corrosion window at first surface of insulating layer.
Accompanying drawing 23A is process schematic representations of this embodiment to accompanying drawing 26.
Shown in accompanying drawing 23A and the 23B, refer step S40, substrate 400 is provided, described substrate surface has first insulating barrier 410 and first semiconductor layer 430 successively, in described first semiconductor layer 430, the pre-part tool 431 that forms source and drain areas has first conduction type, and remainder has second conduction type, and described first semiconductor layer 430 surfaces have first crystal face.
Wherein, Figure 23 A is the vertical view of structure that this step provides, and Figure 23 B is the profile of Figure 23 A along the B-B direction.
Can adopt ion implantation technology to form second conduction type in by the semiconductor layer of gate dielectric layer circle segment, to form above-mentioned doped structure in described pre-formation.
Refer step S41, provide support substrate 400 ', described support substrates 400 ' surface has corrosion barrier layer 410 ' and second semiconductor layer 440 successively, in described second semiconductor layer 440, the pre-part 441 that forms source and drain areas has second conduction type, remainder has first conduction type, and described second semiconductor layer 440 surfaces have second crystal face.
The above support substrates 400 ' with and surface corrosion barrier layer 410 ' identical with the pairing part of structure that provided among the structure of second semiconductor layer 420 and the step S40, therefore 23A and 23B with reference to the accompanying drawings, rendering architecture schematic diagram no longer herein.
Shown in the accompanying drawing 24, refer step S42 is at superficial growth second insulating barrier 420 of described first semiconductor layer 430 away from substrate 400.
Shown in the accompanying drawing 25, refer step S43, with second insulating barrier 420 away from the surface of first semiconductor layer 430 and second semiconductor layer 440 away from corrosion barrier layer 410 ' the surface be bonding face, with substrate 400 and support substrates 400 ' be bonded together.
Described bonding can adopt static bonding process to carry out, and can carry out activation processing to optimize bonding effect by using plasma para-linkage face.
Shown in the accompanying drawing 26, refer step S44, corrosion remove support substrates 400 ' and corrosion barrier layer 410 '.
Can adopt dry method or wet etching method specifically to implement.
After above step is implemented to finish, acquisition has the sandwich construction of double-deck semiconductor layer shown in the accompanying drawing 26 and double hyer insulation layer, comprise substrate 400, and substrate surface first insulating barrier 410, first semiconductor layer 430, second insulating barrier 420 and second semiconductor layer 440 that set gradually.In described first semiconductor layer 430, the pre-part that forms source and drain areas has first conduction type, remainder has second conduction type, in described second semiconductor layer 440, the pre-part that forms source and drain areas has second conduction type, remainder has first conduction type, and described first semiconductor layer 430 surfaces have first crystal face, and described second semiconductor layer 440 surfaces have second crystal face.Above-mentioned steps S40～S44 is a kind of embodiment that obtains substrate shown in the accompanying drawing 26, in other embodiment, also can adopt isolation from oxygen to inject (SIMOX) and wait other common technologies to obtain accompanying drawing 26 described substrates.
Following step S45 to S48 adopts the sandwich construction shown in the accompanying drawing 26 to carry out element manufacturing, and its manufacture craft is identical with the pairing step of the 3rd embodiment, will not give unnecessary details herein.Different is, owing to carried out the doping of source and drain areas in advance, therefore compares with the 3rd embodiment, and this embodiment no longer needs to implement doping process after forming the grid structure.
After step S48 was finished, all right further growth side wall was to form the LDD structure.The device architecture that forms after the LDD structure is promptly identical with structure shown in the accompanying drawing 21 of the 3rd embodiment.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (17)
1. a fin grids transistor surrounded with grid electrodes device is characterized in that, comprising:
Substrate;
In insulating barrier and the semiconductor layer that substrate surface sets gradually, described insulating barrier has a depression near the surface of semiconductor layer, and described semiconductor layer comprises the overhanging portion that is positioned at the recess top;
Gate dielectric layer, described gate dielectric layer are positioned at the overhanging portion of groove top around semiconductor layer;
Described by gate dielectric layer around the semiconductor layer overhanging portion have first conduction type, the semiconductor layer of overhanging portion both sides has second conduction type;
Control gate, described control gate is arranged at surface of insulating layer, and described control gate comprises the part around described gate dielectric layer; And
Source electrode and drain region are arranged in the semiconductor layer of overhanging portion both sides, and near the both sides of semiconductor layer overhanging portion, have second conduction type.
2. fin grids transistor surrounded with grid electrodes device according to claim 1 is characterized in that, the described first conduction type N type, and second conduction type is the P type, the crystal face of semiconductor layer surface is (110) face.
3. fin grids transistor surrounded with grid electrodes device according to claim 1 is characterized in that, the described first conduction type P type, and second conduction type is the N type, the crystal face of semiconductor layer surface is (100) face.
4. according to any described fin grids transistor surrounded with grid electrodes device in the claim 1 to 3, it is characterized in that, comprise two lightly doped regions, described two lightly doped regions lay respectively in source electrode and the drain region, have second conduction type, the doping content of described lightly doped region is lower than other parts of source electrode and drain region.
5. a method of making device described in the claim 1 is characterized in that, comprises the steps:
Substrate is provided, and described substrate surface is disposed with insulating barrier and semiconductor layer, and described semiconductor layer has first conduction type;
Form two corrosion windows in semiconductor layer, described two windows are arranged in the pre-top that forms recess of insulating barrier;
Adopt the method for isotropic etch to remove the insulating barrier of the semiconductor layer below between two corrosion windows, thereby in insulating barrier, form a depression, and make two semiconductor layers between the corrosion window unsettled;
Adopt depositing operation, at the gate dielectric layer of semiconductor layer surface making around the semiconductor layer overhanging portion;
Adopt depositing operation, make control gate at surface of insulating layer around gate dielectric layer by corrosion window;
The semiconductor layer of doping circle segment both sides makes it have second conduction type.
6. method according to claim 5 is characterized in that, in the step of the semiconductor layer of described doping circle segment both sides, further comprises the steps:
Semiconductor layer to the circle segment both sides carries out the doping first time, makes doped portion be transformed into second conduction type by first conduction type;
Form side wall in the control gate both sides;
Mix to not carried out the second time in the semiconductor layer with second conduction type, increase its doping content, thereby define owing to side wall blocks the lightly doped region that forms by the side wall shield portions.
7. a method of making device described in the claim 1 is characterized in that, comprises the steps:
Substrate is provided, and described substrate surface is disposed with insulating barrier and semiconductor layer, and in the described semiconductor layer, the part that forms source and drain areas in advance has second conduction type, and remainder has first conduction type;
Form two corrosion windows in semiconductor layer, described two windows are arranged in the pre-top that forms recess of insulating barrier;
Adopt the method for isotropic etch to remove the insulating barrier of the semiconductor layer below between two corrosion windows, thereby in insulating barrier, form a depression, and make two semiconductor layers between the corrosion window unsettled;
Adopt depositing operation, at the gate dielectric layer of semiconductor layer surface making around the semiconductor layer overhanging portion;
Adopt depositing operation, make control gate at surface of insulating layer around gate dielectric layer by corrosion window.
8. method according to claim 7 is characterized in that, adopts ion implantation technology to form second conduction type in described pre-formation in by the semiconductor layer of gate dielectric layer circle segment.
9. one kind based on the fin grids transistor surrounded with grid electrodes device, it is characterized in that, comprising:
Substrate;
First insulating barrier, first semiconductor layer, second insulating barrier, second semiconductor layer that set gradually in substrate surface;
Described first insulating barrier has a depression near the surface of first semiconductor layer, and described second insulating barrier has the through hole that connects first semiconductor layer and second semiconductor layer in the position corresponding with depression;
Described first semiconductor layer comprises the overhanging portion between groove and through hole, and described second semiconductor layer comprises the overhanging portion that is positioned at the through hole top;
Described first semiconductor layer surface has first crystal face, and described second semiconductor layer surface has second crystal face;
First grid dielectric layer, described first grid dielectric layer is around the overhanging portion of first semiconductor layer between groove and through hole;
Second gate dielectric layer, described second gate dielectric layer are positioned at the overhanging portion of through hole top around second semiconductor layer;
Described first semiconductor layer by first grid dielectric layer around part have first conduction type, had second conduction type by first semiconductor layer of circle segment both sides;
Described second semiconductor layer by second gate dielectric layer around part have second conduction type, had first conduction type by second semiconductor layer of circle segment both sides;
Control gate, described control gate is arranged at first surface of insulating layer, and described control gate comprises around the part of described first grid dielectric layer and around the part of described second gate dielectric layer.
10. fin grids transistor surrounded with grid electrodes device according to claim 9 is characterized in that the thickness of described first insulating barrier is greater than the thickness of second insulating barrier.
11. fin grids transistor surrounded with grid electrodes device according to claim 9 is characterized in that, described first conduction type is the N type, and second conduction type is the P type.
12. fin grids transistor surrounded with grid electrodes device according to claim 11 is characterized in that, described first crystal face is (110), and described second crystal face is (100).
13. fin grids transistor surrounded with grid electrodes device according to claim 9 is characterized in that, described first conduction type is the P type, and second conduction type is the N type.
14. fin grids transistor surrounded with grid electrodes device according to claim 13 is characterized in that, described first crystal face is (100), and described second crystal face is (110).
15. a method of making device described in the claim 9 is characterized in that, comprises the steps
Substrate is provided, described substrate surface is disposed with first insulating barrier, first semiconductor layer, second insulating barrier and second semiconductor layer, in described first semiconductor layer, the pre-part that forms source and drain areas has first conduction type, remainder has second conduction type, in described second semiconductor layer, the pre-part that forms source and drain areas has second conduction type, remainder has first conduction type, described first semiconductor layer surface has first crystal face, and described second semiconductor layer surface has second crystal face;
Form in second semiconductor layer, second insulating barrier and first semiconductor layer and run through two above-mentioned three layers corrosion windows, described two windows are arranged in the pre-top that forms recess of first insulating barrier;
Adopt the method for isotropic etch remove first semiconductor layer below between two corrosion windows first insulating barrier and, second insulating barrier between two corrosion windows, thereby in first insulating barrier, form a depression, in second insulating barrier, form through hole, and make first semiconductor layer and second semiconductor layer between two corrosion windows unsettled;
Adopt depositing operation, make the first grid dielectric layer and second gate dielectric layer respectively around first semiconductor layer and the second semiconductor layer overhanging portion in first semiconductor layer and second semiconductor layer surface;
Adopt depositing operation, make control gate at first surface of insulating layer around the first grid dielectric layer and second gate dielectric layer by corrosion window.
16. method according to claim 15 is characterized in that, adopts following steps to obtain first and second semiconductor layers with described dopant states:
Substrate is provided, and described substrate surface has first insulating barrier and first semiconductor layer successively, and in described first semiconductor layer, the part that forms source and drain areas in advance has first conduction type, and remainder has second conduction type;
Provide support substrate, described support substrates surface has the corrosion barrier layer and second semiconductor layer successively, and in described second semiconductor layer, the part that forms source and drain areas in advance has second conduction type, and remainder has first conduction type;
At superficial growth second insulating barrier of described first semiconductor layer away from substrate;
Is bonding face away from the surface and second semiconductor layer of first semiconductor layer away from the surface of corrosion barrier layer with second insulating barrier, and substrate and support substrates are bonded together;
Support substrates and corrosion barrier layer are removed in corrosion.
17. method according to claim 16, it is characterized in that, adopt ion implantation technology to form second conduction type in by first semiconductor layer of first grid dielectric layer circle segment, and form first conduction type in by second semiconductor layer of the second gate dielectric layer circle segment in described pre-formation in described pre-formation.
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| CN102569074B (en) * | 2010-12-08 | 2014-07-02 | 中国科学院微电子研究所 | Surrounding-gate field effect transistor fabrication method |
| CN102280454B (en) * | 2011-08-22 | 2013-02-06 | 中国科学院半导体研究所 | Semiconductor transistor structure and making method thereof |
| CN103021854B (en) | 2011-09-28 | 2015-09-16 | 中国科学院微电子研究所 | The method making fin formula field effect transistor and the semiconductor structure formed thus |
| CN103247624B (en) * | 2012-02-01 | 2016-03-02 | 中国科学院微电子研究所 | A kind of semiconductor structure and manufacture method thereof |
| US8866204B2 (en) * | 2013-01-30 | 2014-10-21 | Stmicroelectronics, Inc. | Method to form finFET/trigate devices on bulk semiconductor wafers |
| CN105261646A (en) * | 2014-07-16 | 2016-01-20 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN108231594B (en) * | 2017-12-21 | 2020-10-02 | 上海集成电路研发中心有限公司 | Manufacturing method of FinFET device |
| CN116033741A (en) * | 2021-10-25 | 2023-04-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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