CN103021857B - The manufacture method of multiple gate field effect transistor - Google Patents
The manufacture method of multiple gate field effect transistor Download PDFInfo
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- CN103021857B CN103021857B CN201110301132.4A CN201110301132A CN103021857B CN 103021857 B CN103021857 B CN 103021857B CN 201110301132 A CN201110301132 A CN 201110301132A CN 103021857 B CN103021857 B CN 103021857B
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Abstract
Present invention is disclosed a kind of manufacture method of multiple gate field effect transistor, by forming autoregistration spacer side walls in described grid both sides, in the process of carrying out ion implantation formation source area and drain region, the fin structure can sheltering these grid both sides is not doped injection, add the length being arranged in fin structure raceway groove below grid, to realize suppressing short-channel effect, reducing leakage current, and reach the object of the power consumption reducing multiple gate field effect transistor, the device performance improving multiple gate field effect transistor.By forming barrier layer on multiple gate field effect transistor, and utilizing barrier layer described in dry etching, forming the autoregistration block mask of ramped shaped in the hard mask layer both sides of described patterning; Utilize autoregistration block mask to etch form autoregistration spacer side walls thus utilize self-aligned technology, do not need to utilize photoetching and etching technics definition in forming process, namely form autoregistration spacer side walls, thus reduce process costs, improve process efficiency.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor technology device, particularly a kind of manufacture method of multiple gate field effect transistor.
Background technology
Mos field effect transistor (MOSFET) is constantly to the trend development of minification in recent years, this is to gather way, improving Components integration degree and the cost reducing integrated circuit, transistor scales ground reduce, transistor reduce the limit reaching various performance.Wherein the thickness of gate oxide and source/drain junction depth all reach the limit.
Therefore, industry have developed multiple grid or multi gate fet (Multi-GateTransistors), and multiple gate field effect transistor technology is a kind of novel circuit configuration technology.Conventional transistor be each transistor only have grid be used for controlling electric current between two construction units by or interrupt, and then formed calculate in required " 0 " and " 1 ".And multiple-gate transistor technology is each transistor two or three grid, thus improve the ability of transistor controls electric current, i.e. computing capability, and significantly reduce power consumption, decrease the mutual interference between electric current.Wherein, multiple gate field effect transistor is a kind of device architecture be incorporated into by more than one grid in the MOFET of individual devices, this means, raceway groove is on multiple surfaces by several gate wraps, thus leakage current when can suppress " cut-off " state more, and the drive current that can strengthen under " conducting " state, so just obtain the device architecture of lower power consumption and performance enhancement.
J.P.Colinge is called in the Americana of " FinFETsandotherMulti-GateTransistors " one section of name and describes polytype multiple gate field effect transistor, comprise double-gated transistor (Double-Gate, FinFET), tri-gate transistors (Tri-Gate), ohm-shaped gate transistor (Ω-Gate) and quadrangle gate transistor (Quad-Gate) etc.
Wherein, for double-gated transistor, double-gated transistor employs two grids to control raceway groove, greatly inhibits short-channel effect.A concrete distortion of double-gated transistor is exactly fin transistor (FinFET), described FinFET comprises vertical fin structure and across the grid in described fin structure side, be respectively source electrode and drain electrode at the both ends of the fin structure of grid both sides, in the fin structure under grid, form raceway groove.As nonplanar device, the size of the fin structure of FinFET determines the length of effective channel of transistor device.FinFET is compacter compared with the MOS transistor of conventional plane, can realize higher transistor density and less overall microelectric technique.In addition, tri-gate transistors is another Common Shape of multiple-gate transistor, and wherein said grid, across at the side of described fin structure and top surface, controls raceway groove to form three, improves the overall performance of device further.
The vertical direction height of fin structure and horizontal direction width and length have tremendous influence to the performance of drive current, short-channel effect and leakage current etc.The fin structure that such as vertical direction height is higher provides higher drive current, the fin structure that horizontal direction width is less can suppress leakage current better, wherein, the source electrode at fin structure two ends that cross-directional length have impact on and the distance of drain-to-gate, and this distance affects the channel length of device.But due to the restriction of size, fin structure cross-directional length can reduce gradually, the channel length of device can be affected.Therefore, how by a kind of technical method, provide enough channel lengths, fully to suppress short-channel effect and leakage current, thus the performance improving multiple gate field effect transistor becomes the problem that industry is urgently studied.
Summary of the invention
The object of this invention is to provide a kind of manufacture method of multiple gate field effect transistor, with the distance of the source/drain to grid that increase multiple gate field effect transistor, to improve the performance of multiple gate field effect transistor.
The invention provides a kind of manufacture method of multiple gate field effect transistor, comprise
One substrate is provided, forms fin structure on the substrate, and be formed with grid film and hard mask layer successively on described fin structure surface;
Hard mask layer described in patterning, to form the hard mask layer of patterning, and with the hard mask layer of patterning for grid film described in mask etching, to form the grid being located at described fin structure sidewall and top surface;
Form the wall of hard mask layer, grid and the fin structure covering described patterning;
Carry out chemical mechanical milling tech, until expose the end face of the hard mask layer of described patterning;
Carry out back etching technics, until expose whole sides of the hard mask layer of described patterning;
Formed and cover the hard mask layer of described patterning and the barrier layer of wall;
Etch described barrier layer, form autoregistration block mask with the hard mask both sides at described patterning;
Be hard mask with described autoregistration block mask, etch described wall to form autoregistration spacer side walls;
Remove the hard mask layer of described autoregistration block mask and patterning.
Further, after the step of hard mask layer removing described autoregistration block mask and patterning, also comprise: carry out ion implantation technology, form source area and drain region respectively with the end being positioned at described grid both sides at described fin structure.
Further, described substrate is silicon-on-insulator substrate.
Further, described silicon-on-insulator substrate comprises silicon substrate, is positioned at burying oxygen insulating barrier and burying the semiconductor layer on oxygen insulating barrier described in being positioned on described silicon substrate.
Further, the height of described fin structure is 30nm ~ 100nm, and the width of described fin structure is 10nm ~ 25nm.
Further, the material of described wall is one or its combination of silicon nitride, silicon oxynitride or silicon nitride.
Further, described wall comprises oxide layer and is positioned at the nitration case in described oxide layer.
Further, the thickness of described autoregistration spacer side walls is 30nm ~ 100nm.
Further, the material of described hard mask layer is one in silicon oxynitride, titanium, titanium nitride, tantalum or tantalum nitride or its combination.
Further, the thickness of described hard mask layer is 50 dust ~ 200 dusts.
Compared to prior art, multiple gate field effect transistor of the present invention is by forming autoregistration spacer side walls in grid both sides, thus in the process of carrying out ion implantation formation source area and drain region, the fin structure that this autoregistration spacer side walls can shelter these grid both sides is not doped injection, and then add the length of the fin structure raceway groove be arranged in below grid, to suppress short-channel effect, to reduce leakage current, thus reach the object of the power consumption reducing multiple gate field effect transistor, the device performance improving multiple gate field effect transistor.
Simultaneously, the present invention forms barrier layer on multiple gate field effect transistor, and barrier layer described in dry etching, thus the autoregistration block mask of ramped shaped is formed in the hard mask layer both sides of described patterning, and utilize described autoregistration block mask as hard mask to etch described wall, form autoregistration spacer side walls, thus utilize self-aligned technology, do not need to utilize photoetching and etching technics definition in forming process, namely autoregistration spacer side walls is formed, thus reduce process costs, improve process efficiency.
Accompanying drawing explanation
Fig. 1 is the Making programme figure of the manufacture method of multiple gate field effect transistor in one embodiment of the invention.
Fig. 2 is the structural representation of multiple gate field effect transistor in one embodiment of the invention.
Fig. 3 ~ Figure 12 is the structural representation along A '-A directional profile in Fig. 2 in the manufacturing step of multiple gate field effect transistor in one embodiment of the invention.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Core concept of the present invention is, by forming barrier layer on multiple gate field effect transistor, and barrier layer described in dry etching, form autoregistration block mask in described hard mask both sides, be hard mask with described autoregistration block mask, autoregistration spacer side walls can be formed; When the end that described fin structure is positioned at described grid both sides forms source area and drain region respectively, the fin structure that this autoregistration spacer side walls (Spacer) can shelter described grid both sides is not doped injection, thus increase source area and the drain region distance to described grid, and then add the length being arranged in fin structure raceway groove below grid, achieve and suppress short-channel effect, reduction leakage current, reach the object of the power consumption reducing multiple gate field effect transistor, the device performance improving multiple gate field effect transistor.
Fig. 1 is the Making programme figure of the manufacture method of multiple gate field effect transistor in one embodiment of the invention, as shown in Figure 1, the invention provides a kind of manufacture method of multiple gate field effect transistor, comprising:
Step S01: provide a substrate, and form fin structure on the substrate, forms grid film and hard mask layer successively on described fin structure surface;
Step S02: hard mask layer described in patterning, to form the hard mask layer of patterning, and with the hard mask layer of patterning for grid film described in mask etching, to form the grid being located at described fin structure sidewall and top surface;
Step S03: the wall forming hard mask layer, grid and the fin structure covering described patterning;
Step S04: carry out chemical mechanical milling tech, until expose the end face of the hard mask layer of described patterning;
Step S05: carry out back etching technics, until the whole sides exposing the hard mask layer of described patterning;
Step S06: formed and cover the hard mask layer of described patterning and the barrier layer of wall;
Step S07: etch described barrier layer, forms autoregistration block mask with the hard mask both sides at described patterning;
Step S08: be hard mask with described autoregistration block mask, etches described wall to form autoregistration spacer side walls;
Step S09: the hard mask layer removing described autoregistration block mask and patterning.
Further, after the step of hard mask layer removing described autoregistration block mask and patterning, also comprise: carry out ion implantation technology, form source area and drain region respectively with the end being positioned at described grid both sides at described fin structure.Due to covering of autoregistration spacer side walls, increase the distance between source area and drain region to grid, thus further suppress short-channel effect, reduce leakage current, thus greatly improve the performance of described multiple gate field effect transistor.
Multiple gate field effect transistor of the present invention is by forming autoregistration spacer side walls in described grid both sides, thus in the process of carrying out ion implantation formation source area and drain region, the fin structure that this autoregistration spacer side walls can shelter these grid both sides is not doped injection, thus increase source area and the distance between drain region and described grid, further suppression short-channel effect, and reduce leakage current, thus greatly improve the performance of described multiple gate field effect transistor.
Meanwhile, by forming barrier layer on multiple gate field effect transistor, and utilizing barrier layer described in dry etching, forming the autoregistration block mask of ramped shaped in described hard mask both sides; Utilize autoregistration block mask as wall described in hard mask etching, thus utilize self-aligned technology, do not need to utilize photoetching and etching technics definition in forming process, namely form autoregistration spacer side walls, thus reduce process costs, improve process efficiency.When the end that described fin structure is positioned at described grid both sides forms source area and drain region respectively, thus increase source area and the drain region distance to described grid, and then add the length being arranged in fin structure raceway groove below grid, to realize suppressing short-channel effect, reducing leakage current, thus reach the object of the power consumption reducing multiple gate field effect transistor, the device performance improving multiple gate field effect transistor.
Fig. 3 ~ Figure 12 is the structural representation along A ' A directional profile in Fig. 2 in the manufacturing step of multiple gate field effect transistor in one embodiment of the invention.The manufacturing process of each step above is described in detail below in conjunction with Fig. 3 ~ Figure 12:
First, in described step S01, described substrate is such as silicon-on-insulator (SOI) substrate, as shown in Figure 2, described SOI silicon base comprises silicon substrate (not indicating in figure), is arranged in burying oxygen insulating barrier (BOX) 100 and being positioned at the semiconductor layer (figure does not indicate) buried on oxygen insulating barrier 100 on silicon substrate, and the material of described semiconductor layer can be silicon, germanium or silicon Germanium compound etc.In the present embodiment, utilize electron beam lithography to carry out photoetching and etching technics to described semiconductor layer, with formed vertically stand on described in bury fin structure 104 on oxygen insulating barrier 100.Composition graphs 2, the both ends of this fin structure 104 will form source area 202 and drain region 204 in follow-up technique, the middle part sidewall of this fin structure 104 and top surface can form grid 106, raceway groove (not indicating in figure) in the middle part of this fin structure 104, will be formed.The height H of the fin structure 104 formed
1preferably scope is 30nm ~ 100nm, the width W of described fin structure 104
1preferably scope is 10nm ~ 25nm.At the fin structure 104 of the size range of above-mentioned height and width, there is good drive current performance, and short-channel effect and leakage current can be suppressed.
Then, as shown in Figure 3, carry out chemical vapour deposition (CVD), with described fin structure 104 and described in bury on oxygen insulating barrier (BOX) 100 deposition and form grid film 106a and hard mask layer 108a.Wherein, the material of described grid film 106a can be polysilicon, and the material of described hard mask layer 108a can be one in silicon oxynitride, titanium, titanium nitride or tantalum or tantalum nitride or its combination.If select silicon oxynitride or metal hardmask material (as titanium, titanium nitride or tantalum or tantalum nitride) as the material of hard mask layer 108a, in subsequent etching processes, the Other substrate materials used in the polycrystalline silicon material of itself and grid 106, photoetching process and the autoregistration block mask of follow-up formation all have good etching selection ratio, can be conducive to the selective etch of etching technics.The thickness of described hard mask layer 108a preferably scope is 50 dust ~ 200 dusts, and its height is equal with the height of grid or differ within 10 dusts, with in subsequent step, and the autoregistration spacer side walls 111 that the figure of formation ramped shaped is good.
Then, utilize photoetching and etching technics to form the hard mask layer 108 of patterning, the hard mask layer 108 of described patterning cover will form grid position above.As shown in Figure 4, particularly, in described step S02, described hard mask layer 108a applies photoresist (not indicating in figure), utilize mask plate to expose this photoresist, after then this photoresist being developed, form the photoresist of patterning, then with the photoresist of this patterning for mask, etch described hard mask layer 108a, thus form the hard mask layer 108 of patterning.Can the hard mask layer 108 of patterning be hard mask subsequently, etch described grid film 106a, grid film 106a has good etching ratio relative to the hard mask layer 108 of patterning, and grid film 106a has good etching ratio equally relative to fin structure 104, thus formation is connected across the sidewall of described fin structure 104 and the grid 106 of top surface, concrete structure as shown in Figure 5.
As shown in Figure 6, in described step S03, utilize chemical vapor deposition wall 110, described wall 110 covers the hard mask layer 108 of described patterning, described grid 106 and described fin structure 104; Wherein, the material of described wall 110 can be silica, the one of silicon nitride or its combination, and in the present embodiment, described wall 110 comprises oxide layer and is positioned at the nitration case in described oxide layer.
As shown in Figure 7, in described step S04, carry out chemical mechanical milling tech and remove part wall, until expose the end face of the hard mask layer 108 of described patterning.
As shown in Figure 8, in described step S05, carry out back etching technics, continue etched portions wall 110, etching technics until the hard mask layer 108 exposing whole described patterning stops, to expose whole sides of the hard mask layer 108 of described patterning; Returning in etch step, adopt dry etching, etch thicknesses is preferably 50 dust ~ 200 dusts; Wall 110 has good etching ratio with the hard mask layer 108 of described patterning, therefore in etching process, the thickness of the hard mask layer 108 of patterning has almost no change.
As shown in Figure 9, in described step S06, chemical vapour deposition technique is utilized to form barrier layer 112, to cover hard mask layer 108 and the wall 110 of described patterning;
As shown in Figure 10, in described step S07, barrier layer 112 described in dry etching, due to the characteristic of dry etching, ramp-like barrier layer is remained on the barrier layer of hard mask layer 108 both sides of described patterning, thus the barrier layer of ramped shaped becomes autoregistration block mask 112a in the both sides of the hard mask layer 108 of described patterning; Wherein, the width W of described autoregistration block mask 112a bottom
2scope is 10nm ~ 25nm.
As shown in figure 11, in described step S08, with described autoregistration block mask 112a for mask, etch described wall 110, thus form autoregistration spacer side walls 111.The width of described autoregistration spacer side walls is namely in the width W of described autoregistration block mask 112a bottom
2identical, be 10nm ~ 25nm.
As shown in figure 12, in described step S09, remove the hard mask layer 108 of described autoregistration block mask 112a and patterning, form structure as shown in figure 12, the thickness range of described autoregistration spacer side walls 111 is preferably 10nm ~ 25nm, the autoregistration spacer side walls 111 of this preferred thickness is in the process of carrying out subsequent ion injection technology formation source area and drain region, and the thickness sheltering described grid 106 is moderate, moderately adds the length being arranged in fin structure raceway groove below grid.
In the present embodiment, after the step of hard mask layer 108 removing described block mask 112a and patterning, form structure as shown in Figure 2, then, also can carry out ion implantation to described fin structure both ends, to form source area 202 and drain region 204 respectively, due to the stop of described autoregistration spacer side walls 111 in the end of described grid 106 both sides, add the distance of the raceway groove under described source area 202 and drain region 204 to grid 106, thus fully suppress short-channel effect and leakage current.
Compared to prior art, multiple gate field effect transistor of the present invention is by forming autoregistration spacer side walls in described grid both sides, thus in the process of carrying out ion implantation formation source area and drain region, the fin structure that this autoregistration spacer side walls can shelter these grid both sides is not doped injection, and then add the length being arranged in fin structure raceway groove below grid, to realize suppressing short-channel effect, reducing leakage current, thus reach the object of the power consumption reducing multiple gate field effect transistor, the device performance improving multiple gate field effect transistor.
Meanwhile, by forming barrier layer on multiple gate field effect transistor, and utilizing barrier layer described in dry etching, forming the autoregistration block mask of ramped shaped; And utilize autoregistration block mask to form autoregistration spacer side walls as hard mask etching, thus utilize self-aligned technology, do not need to utilize photoetching and etching technics definition in forming process, namely form autoregistration spacer side walls, thus reduce process costs, improve process efficiency.When the end that described fin structure is positioned at described grid both sides forms source area and drain region respectively, thus increase source area and the drain region distance to described grid, and then add the length being arranged in fin structure raceway groove below grid, to realize suppressing short-channel effect, reducing leakage current, thus reach the object of the power consumption reducing multiple gate field effect transistor, the device performance improving multiple gate field effect transistor.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (10)
1. a manufacture method for multiple gate field effect transistor, comprises
One substrate is provided, forms fin structure on the substrate, and be formed with grid film and hard mask layer successively on described fin structure surface;
Hard mask layer described in patterning, to form the hard mask layer of patterning, and with the hard mask layer of patterning for grid film described in mask etching, to form the grid being located at described fin structure sidewall and top surface;
Form the wall of hard mask layer, grid and the fin structure covering described patterning;
Carry out chemical mechanical milling tech, until expose the end face of the hard mask layer of described patterning;
Carry out back etching technics, until expose whole sides of the hard mask layer of described patterning;
Formed and cover the hard mask layer of described patterning and the barrier layer of wall;
Etch described barrier layer, to form the barrier layer of sloped sides shape at the hard mask of described patterning, the barrier layer of ramped shaped becomes autoregistration block mask;
Be hard mask with described autoregistration block mask, etch described wall to form autoregistration spacer side walls, wherein, the width of described autoregistration spacer side walls is identical with the width of described autoregistration block mask bottom;
Remove the hard mask layer of described autoregistration block mask and patterning.
2. the manufacture method of multiple gate field effect transistor as claimed in claim 1, it is characterized in that, after the step of hard mask layer removing described autoregistration block mask and patterning, also comprise: carry out ion implantation technology, form source area and drain region respectively with the end being positioned at described grid both sides at described fin structure.
3. the manufacture method of multiple gate field effect transistor as claimed in claim 1 or 2, it is characterized in that, described substrate is silicon-on-insulator substrate.
4. the manufacture method of multiple gate field effect transistor as claimed in claim 3, is characterized in that, described silicon-on-insulator substrate comprises silicon substrate, be positioned at burying oxygen insulating barrier and burying the semiconductor layer on oxygen insulating barrier described in being positioned on described silicon substrate.
5. the manufacture method of multiple gate field effect transistor as claimed in claim 1 or 2, it is characterized in that, the height of described fin structure is 30nm ~ 100nm, and the width of described fin structure is 10nm ~ 25nm.
6. the manufacture method of multiple gate field effect transistor as claimed in claim 1 or 2, is characterized in that, the material of described wall is one or its combination of silicon nitride, silicon oxynitride or silica.
7. the manufacture method of multiple gate field effect transistor as claimed in claim 6, is characterized in that, described wall comprises oxide layer and is positioned at the nitration case in described oxide layer.
8. the manufacture method of multiple gate field effect transistor as claimed in claim 1 or 2, it is characterized in that, the thickness of described autoregistration spacer side walls is 30nm ~ 100nm.
9. the manufacture method of multiple gate field effect transistor as claimed in claim 1 or 2, is characterized in that, the material of described hard mask layer is one in silicon oxynitride, titanium, titanium nitride, tantalum or tantalum nitride or its combination.
10. the manufacture method of multiple gate field effect transistor as claimed in claim 1 or 2, it is characterized in that, the thickness of described hard mask layer is 50 dust ~ 200 dusts.
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| CN1992185A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Method of fabricating a fin field effect transistor in a semiconductor device |
| CN101969061A (en) * | 2010-09-27 | 2011-02-09 | 复旦大学 | Fin-type tunneling transistor integrated circuit and manufacturing method thereof |
| CN102099902A (en) * | 2008-07-21 | 2011-06-15 | 超威半导体公司 | Method of forming finned semiconductor devices with trench isolation |
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| US7186603B2 (en) * | 2004-11-15 | 2007-03-06 | Grace Semiconductor Manufacturing Corporation | Method of forming notched gate structure |
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| CN1992185A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Method of fabricating a fin field effect transistor in a semiconductor device |
| CN102099902A (en) * | 2008-07-21 | 2011-06-15 | 超威半导体公司 | Method of forming finned semiconductor devices with trench isolation |
| CN101969061A (en) * | 2010-09-27 | 2011-02-09 | 复旦大学 | Fin-type tunneling transistor integrated circuit and manufacturing method thereof |
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