CN103187289B - The manufacture method of multiple gate field effect transistor - Google Patents
The manufacture method of multiple gate field effect transistor Download PDFInfo
- Publication number
- CN103187289B CN103187289B CN201110458039.4A CN201110458039A CN103187289B CN 103187289 B CN103187289 B CN 103187289B CN 201110458039 A CN201110458039 A CN 201110458039A CN 103187289 B CN103187289 B CN 103187289B
- Authority
- CN
- China
- Prior art keywords
- sacrifice layer
- fin structure
- field effect
- effect transistor
- gate field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
Present invention is disclosed a kind of manufacture method of multiple gate field effect transistor, comprise the following steps, substrate forms fin structure; Form the first sacrifice layer; Fin structure in the first sacrifice layer is other forms welding pad structure; Remove described first sacrifice layer, cover the second sacrifice layer; Form the grid be located on fin structure end face and sidewall, described grid is connected with described welding pad structure simultaneously; Remove described second sacrifice layer.The manufacture method of described multiple gate field effect transistor defines welding pad structure and grid by utilizing the first sacrifice layer and the second sacrifice layer respectively; reduce the requirement to window size; and protect fin structure and fin structure when etching and fill and form grid; the top corner regions in source area and drain region is protected not to be subject to etching injury; thus define the good fin structure of interface profile; avoid the generation of punchthrough effect, improve the performance of multiple gate field effect transistor.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, particularly relate to a kind of manufacture method of multiple gate field effect transistor.
Background technology
Metal-oxide semiconductor fieldeffect transistor (MOSFET) is constantly to the trend development of minification in recent years, to gather way, improving Components integration degree and the cost reducing integrated circuit, along with transistor scales reduce, transistor reduce the limit reaching the various performance of device, wherein, the thickness of gate oxide and source/drain junction depth all reach the limit.
Therefore, industry have developed multiple grid or multi gate fet (Multi-GateTransistors).Wherein, multiple gate field effect transistor technology is a kind of novel circuit configuration technology, multiple gate field effect transistor is a kind of device architecture be incorporated into by more than one grid in the MOSFET of individual devices, this means, raceway groove is on multiple surfaces by several gate wraps, thus leakage current when can suppress " cut-off " state more, and the drive current under " conducting " state can be strengthened, so just obtain the device architecture of lower power consumption and performance enhancement.Conventional transistor be each transistor only have grid be used for controlling electric current between two construction units by or interrupt, and then formed calculate in required " 0 " and " 1 ".And multiple-gate transistor technology is each transistor two or three grid, thus improve the ability of transistor controls electric current, i.e. computing capability, and significantly reduce power consumption, decrease the mutual interference between electric current.
J.P. Colinge is called one section of name in the Americana of " FinFETs and other Multi-Gate Transistors " and describes polytype multiple gate field effect transistor, comprise double-gated transistor (Double-Gate, FinFET), tri-gate transistors (Tri-Gate), ohm-shaped gate transistor (Ω-Gate) and quadrangle gate transistor (Quad-Gate) etc.Wherein, for double-gated transistor, double-gated transistor employs two grids to control raceway groove, greatly inhibits short-channel effect.A concrete distortion of double-gated transistor is exactly fin transistor (FinFET), FinFET comprises vertical fin structure and across the grid in described fin structure side, be respectively source electrode and drain electrode at the both ends of the fin structure of grid both sides, in the fin structure under grid, form raceway groove.As nonplanar device, the size of the fin structure of FinFET determines the length of effective channel of transistor device.FinFET is compacter compared with the MOS transistor of conventional plane, can realize higher transistor density and less overall microelectric technique.In addition, tri-gate transistors is another Common Shape of multiple-gate transistor, and wherein said grid, across at the side of described fin structure and top surface, controls raceway groove to form three, improves the overall performance of device further.
Fin structure, the device performance tool of interface profile (Profile) to multiple gate field effect transistor of grid has a great impact, in the manufacture process forming multiple gate field effect transistor, owing to forming the etching technics that fin structure and grid need to carry out repeatedly, wherein especially the interface profile impact of dry etching on fin structure and grid is very big, the poor grid of interface profile can affect the cut-in voltage of grid, the interface profile of fin structure can affect the size of its zone line raceway groove, the poor source area at its two ends and the drain region of even causing of the vertical interface profile of fin structure forms punchthrough effect (Punch Trough), and, certain etching injury can be had to fin structure in the process of carrying out gate etch, the upper dihedral of fin structure is made to become the drift angle of certain circular arc degree, make the interface surface out-of-flatness of fin structure, thus form corner region (Top CornerArea), in subsequent technique, the metal formed thereon is drawn between line and fin structure and is produced cavity, metal is caused to draw line poor electrical contact, affect the performance of multiple gate field effect transistor.
Summary of the invention
The object of this invention is to provide the manufacture method of a kind of reduction to the multiple gate field effect transistor that fin structure and grid etch damage.
For solving the problem, the manufacture method of a kind of multiple gate field effect transistor of the present invention, comprises the following steps:
Substrate is provided, forms fin structure on the substrate;
Described fin structure and described substrate form the first sacrifice layer;
Welding pad structure is formed in the first sacrifice layer that described fin structure is other;
Remove the first sacrifice layer, and cover the second sacrifice layer in described fin structure, welding pad structure and substrate;
In described second sacrifice layer formed be located at fin structure end face with on sidewall and the grid be connected with described welding pad structure;
Remove the second sacrifice layer.
Further, formed in the step of welding pad structure in the first sacrifice layer that described fin structure is other, comprise the following steps: utilize photoetching and etching technics, in described first sacrifice layer, form the first groove; Deposition bonding pad materials, fills described first groove; Carry out cmp, until expose described fin structure, to form welding pad structure in the first groove.
Further, in described second sacrifice layer formed be located at fin structure end face with on sidewall and in the step of the grid be connected with described welding pad structure, comprise: utilize photoetching and etching technics, the second groove is formed in described second sacrifice layer, described second groove exposes the zone line of described fin structure, and welding pad structure described in expose portion; Deposition of gate material, fills described second groove; Carry out cmp, until expose described second sacrifice layer, with formed be located at fin structure end face with on sidewall and the grid be connected with described welding pad structure.
Further, the material of described first sacrifice layer is high silicon content polymer, and described first sacrifice layer adopts the method for coating to be formed, and adopts wet etching to remove.
Further, in described high silicon content polymer, the molar content of silicon is greater than 35%.
Further, the material of described first sacrifice layer is amorphous carbon, and described first sacrifice layer adopts chemical vapour deposition technique to be formed, and adopts plasma ashing method to remove.
Further, the thickness of described first sacrifice layer is greater than the thickness of described fin structure, and thickness difference is 10 ~ 20nm.
Further, the material of described second sacrifice layer is high silicon content polymer, and described second sacrifice layer adopts the method for coating to be formed, and adopts wet etching to remove.
Further, in described high silicon content polymer, the molar content of silicon is greater than 35%.
Further, the material of described second sacrifice layer is amorphous carbon, and described second sacrifice layer adopts chemical vapour deposition technique to be formed, and adopts plasma ashing method to remove.
Further, the large 10 ~ 20nm of thickness of fin structure described in the Thickness Ratio of described second sacrifice layer.
Further, the material of described fin structure is monocrystalline silicon, germanium or silicon Germanium compound.
Further, the height of described fin structure is 30nm ~ 100nm, and the width of described fin structure is 10nm ~ 30nm.
Further, described grid is polysilicon gate or metal gates.
Further, the thickness of described grid is greater than the thickness of described welding pad structure.
Further, described substrate comprises silicon substrate and is positioned at silicon substrate buries oxygen insulating barrier.
In sum, multiple gate field effect transistor of the present invention defines welding pad structure and grid by utilizing the first sacrifice layer and the second sacrifice layer, reduce the requirement of window size, simultaneously, when forming welding pad structure, first sacrifice layer blocks fin structure, protect fin structure, when forming grid, second sacrifice layer has blocked two end regions of fin structure, avoid the etching injury of the top corner regions in source area and drain region, thus the good fin structure of interface profile and grid can be formed, reduce the generation of punchthrough effect, improve the performance of multiple gate field effect transistor.
In addition, because the material of the first sacrifice layer and the second sacrifice layer selects high silicon content polymer or amorphous carbon material, can using plasma ashing method or wet etching remove in removal process, avoid adopting dry etching, reduce the damage to fin structure, welding pad structure and grid, thus enable said structure form the size of good interface profile Sum fanction, improve the performance of multiple gate field effect transistor.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacture method of multiple gate field effect transistor in one embodiment of the invention.
Fig. 2 ~ Figure 12 is the cross-sectional view in the manufacture process of multiple gate field effect transistor in one embodiment of the invention.
Figure 13 ~ Figure 14 is the vertical view in the manufacture process of multiple gate field effect transistor in one embodiment of the invention.
Figure 15 is the perspective view of multiple gate field effect transistor in one embodiment of the invention.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Fig. 1 is the schematic flow sheet of the manufacture method of multiple gate field effect transistor in one embodiment of the invention.As shown in Figure 1, the invention provides a kind of manufacture method of multiple gate field effect transistor, comprise the following steps:
Step S01: provide substrate, forms fin structure on the substrate;
Step S02: form the first sacrifice layer on described fin structure and described substrate;
Step S03: form welding pad structure in the first sacrifice layer that described fin structure is other;
Step S04: remove the first sacrifice layer, and the second sacrifice layer is covered in described fin structure, welding pad structure and substrate;
Step S05: in described second sacrifice layer formed be located at fin structure end face with on sidewall and the grid be connected with described welding pad structure;
Step S06: remove the second sacrifice layer.
Fig. 2 ~ Figure 12 is the cross-sectional view in the manufacture process of multiple gate field effect transistor in one embodiment of the invention.Figure 13 ~ Figure 14 is the vertical view in the manufacture process of multiple gate field effect transistor in one embodiment of the invention.Figure 15 is the perspective view of multiple gate field effect transistor in one embodiment of the invention.The manufacture method of multiple gate field effect transistor is described in detail below in conjunction with Fig. 2 ~ Figure 15.
As shown in Figure 2, in step S01, provide substrate 100, described substrate 100 forms fin structure 103; In the present embodiment, described substrate 100 comprises silicon substrate 101 and is positioned at, and silicon substrate 101 buries oxygen insulating barrier (BOX) 102, semiconductor layer (not indicating in figure) is formed described burying on oxygen insulating barrier 102, the material of described semiconductor layer can be silicon, germanium or silicon Germanium compound etc., then, electron beam lithography is utilized to carry out photoetching and etching technics to described semiconductor layer, semiconductor layer described in patterning, with formed vertically stand on described in bury fin structure 103 on oxygen insulating barrier 102.In follow-up technique, will form source area, drain region and channel region, source area and drain region are positioned at fin structure 103 both ends, and channel region is positioned at the middle part of fin structure 103, in addition the middle part sidewall of fin structure 103 and top surface will form grid.
As shown in Figure 2, the thickness H of fin structure 103
1preferably scope is 30nm ~ 100nm, the width W of described fin structure 103
1preferably scope is 10nm ~ 30nm.At the fin structure 103 of the size range of above-mentioned height and width, there is good drive current performance, and short-channel effect and leakage current can be suppressed.
Then, as shown in Figure 2, in step S02, described fin structure 103 and described substrate 102 form the first sacrifice layer 105; The thickness H of the first sacrifice layer 105 in substrate 102
2than the thickness H of described fin structure 103
1large 10nm ~ 20nm, not to be etched damage to protect fin structure 103 in subsequent technique process.In one embodiment, the material of described first sacrifice layer 105 is high silicon content polymer, such as being easy to the bottom antireflective coating of the fluidised form high silicon content solidified, the method of rotary coating can be adopted to be formed at described fin structure 103 and described substrate 102, after coagulation fix, wherein in high silicon content polymer, the molar content of silicon is greater than 35%, and the polymer of high silicon content has and better solidifies character, and is easier to be removed in subsequent technique.In another embodiment; the material of described first sacrifice layer 105 is amorphous carbon; such as APF (Advanced Pattern Film) material; the mode of chemical vapour deposition (CVD) can be adopted to be formed, and amorphous carbon has certain mechanical strength, can resist follow-up chemical mechanical milling tech better; protect fin structure 103 better; and can controlling dimension accurately, the method for plasma ashing can remove in subsequent technique, the damage to fin structure 103 can be reduced.
In step S03, the fin structure 105 in described first sacrifice layer 105 is other forms welding pad structure 107, and exposes described fin structure 103.Concrete steps comprise: as shown in Figure 3, first photoetching and etching technics is utilized, described first sacrifice layer 105 is formed the first bottom antireflective coating 201 and the first photoresist layer 203 of patterning, then with the first bottom antireflective coating 201 and the first photoresist layer 203 for the first sacrifice layer 105 described in mask etching, thus the first groove 106 formed in the first sacrifice layer 105 as shown in Figure 4, after etching, remove remaining first photoresist layer 203 and the first bottom antireflective coating 201; Then, as shown in Figure 5, deposition bonding pad materials 107a, fill described first groove 106, the material of welding pad structure 107a can be polysilicon or metal material, identical with the grid material of follow-up formation, such as copper; Then, carry out cmp, until expose described fin structure 103, form structure as shown in Figure 6.
As shown in Figure 7, in step S04, remove remaining first sacrifice layer 105, described fin structure 103, welding pad structure 107 and substrate 100 cover the second sacrifice layer 109; The first sacrifice layer 105 for high silicon content polymer can adopt wet etching to remove; the first sacrifice layer 105 for amorphous carbon can adopt plasma ashing method to remove; above-mentioned two kinds of methods can both be avoided using dry etching; reduce the etching injury of fin structure 103 and welding pad structure 107; the good interface profile of protection fin structure 103 and welding pad structure 107; avoid the etching injury of the top corner regions in source area and drain region, improve the performance of multiple gate field effect transistor.
After removing described first sacrifice layer 105, at described substrate 102, fin structure 103 and welding pad structure 107 surface coverage second sacrifice layer 109, the thickness H of the second sacrifice layer 109 in substrate 102
3than the thickness H of described fin structure 103
1large 10nm ~ 20nm, with in subsequent technique process, protection fin structure 103 and welding pad structure 107 are not etched damage.In one embodiment, the material of the second sacrifice layer 109 is high silicon content polymer, the method of rotary coating can be adopted to be formed at the after coagulation of described fin structure 103 and described substrate 102, wherein in high silicon content polymer, the molar content of silicon is greater than 35%, the polymer of high silicon content has and better solidifies character, and is easier to be removed in subsequent technique.In another embodiment, the material of described second sacrifice layer 109 is amorphous carbon, and such as APF (Advanced Pattern Film) material, can adopt chemical vapour deposition technique to be formed in described fin structure 103 and described substrate 102.
In step S05, in described second sacrifice layer 109 formed be located at fin structure 103 end face with on sidewall and the grid 111 be connected with described welding pad structure 107.Specifically comprise the following steps: as shown in Figure 8, first photoetching and etching technics is utilized, described second sacrifice layer 109 is formed the second bottom antireflective coating 205 and the second photoresist 207 of patterning, with described second bottom antireflective coating 205 and the second photoresist 207 for mask, etch described second sacrifice layer 109, thus the second groove 109a formed in the second sacrifice layer 109 as shown in Figure 9, shown in Figure 13, described second groove 109a exposes the zone line of described fin structure 103, and welding pad structure 107 described in expose portion; Then, as shown in Figure 10, deposition of gate material 111a fills described second groove 109a; Then, carry out cmp, until expose described second sacrifice layer 109, thus formation grid 111 as shown in figure 11, shown in Figure 14, described grid 111 is across on described fin structure 103, and is connected with described welding pad structure 107, and grid 111 can be polysilicon gate or metal gates.Wherein, the thickness H of described grid 111
4be greater than the thickness H of described welding pad structure 107
5, grid 111 is taken on Welding Structure 107.
In step S06, remove described second sacrifice layer 109, form structure as shown in figure 12.The second sacrifice layer 109 for high silicon content polymer can adopt wet etching to remove; the second sacrifice layer 109 for amorphous carbon can adopt plasma ashing method to remove; above-mentioned two kinds of methods can both be avoided using dry etching; reduce the etching injury to grid 111, fin structure 103 and welding pad structure 107; the good interface profile of protection grid 111, fin structure 103 and welding pad structure 107, and then improve the performance of multiple gate field effect transistor.Final formation structure as shown in figure 15.
In sum, multiple gate field effect transistor of the present invention defines welding pad structure and grid by utilizing the first sacrifice layer and the second sacrifice layer, reduce the requirement of window size, simultaneously, when forming welding pad structure, first sacrifice layer blocks fin structure, protect fin structure, when forming grid, second sacrifice layer has blocked two end regions of fin structure, avoid the etching injury of the top corner regions in source area and drain region, thus the good fin structure of interface profile and grid can be formed, reduce the generation of punchthrough effect, improve the performance of multiple gate field effect transistor.
In addition, because the material of the first sacrifice layer and the second sacrifice layer selects high silicon content polymer or amorphous carbon material, can using plasma ashing method or wet etching remove in removal process, avoid adopting dry etching, reduce the damage to fin structure, welding pad structure and grid, thus enable said structure form the size of good interface profile Sum fanction, improve the performance of multiple gate field effect transistor.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (16)
1. a manufacture method for multiple gate field effect transistor, is characterized in that, comprising:
Substrate is provided, forms fin structure on the substrate;
Described fin structure and described substrate form the first sacrifice layer;
Welding pad structure is formed in the first sacrifice layer that described fin structure is other;
Remove the first sacrifice layer, and cover the second sacrifice layer in described fin structure, welding pad structure and substrate;
In described second sacrifice layer formed be located at fin structure end face with on sidewall and the grid be connected with described welding pad structure;
Remove the second sacrifice layer.
2. the manufacture method of multiple gate field effect transistor as claimed in claim 1, is characterized in that, is formed in the step of welding pad structure, comprising in the first sacrifice layer that described fin structure is other:
Utilize photoetching and etching technics, in described first sacrifice layer, form the first groove;
Deposition bonding pad materials, fills described first groove;
Carry out cmp, until expose described fin structure, to form welding pad structure in the first groove.
3. the manufacture method of multiple gate field effect transistor as claimed in claim 1, is characterized in that, formed in described second sacrifice layer be located at fin structure end face with on sidewall and in the step of the grid be connected with described welding pad structure, comprising:
Utilize photoetching and etching technics, in described second sacrifice layer, form the second groove, described second groove exposes the zone line of described fin structure, and welding pad structure described in expose portion;
Deposition of gate material, fills described second groove;
Carry out cmp, until expose described second sacrifice layer, with formed be located at fin structure end face with on sidewall and the grid be connected with described welding pad structure.
4. as the manufacture method of the multiple gate field effect transistor in claims 1 to 3 as described in any one, it is characterized in that, the material of described first sacrifice layer is high silicon content polymer, and described first sacrifice layer adopts the method for coating to be formed, and described first sacrifice layer adopts wet etching to remove.
5. the manufacture method of multiple gate field effect transistor as claimed in claim 4, it is characterized in that, in described high silicon content polymer, the molar content of silicon is greater than 35%.
6. as the manufacture method of the multiple gate field effect transistor in claims 1 to 3 as described in any one, it is characterized in that, the material of described first sacrifice layer is amorphous carbon, and described first sacrifice layer adopts chemical vapour deposition technique to be formed, and described first sacrifice layer adopts plasma ashing method to remove.
7. as the manufacture method of the multiple gate field effect transistor in claims 1 to 3 as described in any one, it is characterized in that, the thickness of described first sacrifice layer is greater than the thickness of described fin structure, and thickness difference is 10 ~ 20nm.
8. as the manufacture method of the multiple gate field effect transistor in claims 1 to 3 as described in any one, it is characterized in that, the material of described second sacrifice layer is high silicon content polymer, and described second sacrifice layer adopts the method for coating to be formed, and described second sacrifice layer adopts wet etching to remove.
9. the manufacture method of multiple gate field effect transistor as claimed in claim 8, it is characterized in that, in described high silicon content polymer, the molar content of silicon is greater than 35%.
10. as the manufacture method of the multiple gate field effect transistor in claims 1 to 3 as described in any one, it is characterized in that, the material of described second sacrifice layer is amorphous carbon, and described second sacrifice layer adopts chemical vapour deposition technique to be formed, and described second sacrifice layer adopts plasma ashing method to remove.
11. as the manufacture method of the multiple gate field effect transistor in claims 1 to 3 as described in any one, and it is characterized in that, the thickness of described second sacrifice layer is greater than the thickness of described fin structure, and thickness difference is 10 ~ 20nm.
12. as the manufacture method of the multiple gate field effect transistor in claims 1 to 3 as described in any one, and it is characterized in that, the material of described fin structure is monocrystalline silicon, germanium or silicon Germanium compound.
13. as the manufacture method of the multiple gate field effect transistor in claims 1 to 3 as described in any one, and it is characterized in that, the height of described fin structure is 30nm ~ 100nm, and the width of described fin structure is 10nm ~ 30nm.
14. as the manufacture method of the multiple gate field effect transistor in claims 1 to 3 as described in any one, and it is characterized in that, described grid is polysilicon gate or metal gates.
15. as the manufacture method of the multiple gate field effect transistor in claims 1 to 3 as described in any one, and it is characterized in that, the thickness of described grid is greater than the thickness of described welding pad structure.
16., as the manufacture method of the multiple gate field effect transistor in claims 1 to 3 as described in any one, is characterized in that, described substrate comprises silicon substrate and is positioned at, and silicon substrate buries oxygen insulating barrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110458039.4A CN103187289B (en) | 2011-12-31 | 2011-12-31 | The manufacture method of multiple gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110458039.4A CN103187289B (en) | 2011-12-31 | 2011-12-31 | The manufacture method of multiple gate field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103187289A CN103187289A (en) | 2013-07-03 |
| CN103187289B true CN103187289B (en) | 2015-08-19 |
Family
ID=48678395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110458039.4A Active CN103187289B (en) | 2011-12-31 | 2011-12-31 | The manufacture method of multiple gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103187289B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576392B (en) * | 2013-10-18 | 2018-05-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of preparation method of fin field effect pipe |
| CN104979202B (en) * | 2014-04-04 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| US7795669B2 (en) * | 2007-05-30 | 2010-09-14 | Infineon Technologies Ag | Contact structure for FinFET device |
| CN101939830A (en) * | 2008-02-11 | 2011-01-05 | Nxp股份有限公司 | Finfet with separate gates and method for fabricating a FinFET with separate gates |
| CN102074506A (en) * | 2009-11-19 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Method for fabricating fin-like field effect transistor |
| CN102129982A (en) * | 2010-12-29 | 2011-07-20 | 北京大学深圳研究生院 | Manufacturing method of fine pattern of semiconductor and FIN body of fin type field effect transistor |
-
2011
- 2011-12-31 CN CN201110458039.4A patent/CN103187289B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| US7795669B2 (en) * | 2007-05-30 | 2010-09-14 | Infineon Technologies Ag | Contact structure for FinFET device |
| CN101939830A (en) * | 2008-02-11 | 2011-01-05 | Nxp股份有限公司 | Finfet with separate gates and method for fabricating a FinFET with separate gates |
| CN102074506A (en) * | 2009-11-19 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Method for fabricating fin-like field effect transistor |
| CN102129982A (en) * | 2010-12-29 | 2011-07-20 | 北京大学深圳研究生院 | Manufacturing method of fine pattern of semiconductor and FIN body of fin type field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103187289A (en) | 2013-07-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101633225B1 (en) | FIN STRUCTURE FOR A FinFET DEVICE | |
| US8889497B2 (en) | Semiconductor devices and methods of manufacture thereof | |
| CN110517989A (en) | Semiconductor structure and forming method thereof | |
| CN113555285A (en) | Method for forming semiconductor structure | |
| US9076870B2 (en) | Method for forming fin-shaped structure | |
| CN103367131B (en) | The formation method of fin, fin and fin formula field effect transistor | |
| KR20080061989A (en) | Semiconductor device and manufacturing method of the same | |
| US10707305B2 (en) | Method of fabricating tunneling transistor | |
| CN108807179B (en) | Semiconductor structure and forming method thereof | |
| CN106409748B (en) | Semiconductor element and manufacturing method thereof | |
| CN103187289B (en) | The manufacture method of multiple gate field effect transistor | |
| TWI728966B (en) | Semiconductor device and method for fabricating the same | |
| CN103378005B (en) | The manufacture method of multiple gate field effect transistor fin structure | |
| CN107546127B (en) | Semiconductor element and manufacturing method thereof | |
| CN113838934B (en) | Semiconductor structure and forming method thereof | |
| CN113130311B (en) | Semiconductor structure and forming method thereof | |
| CN113314605B (en) | Semiconductor structure and forming method thereof | |
| CN104347416A (en) | Finned field-effect transistor (FET) and forming method thereof | |
| CN103367432B (en) | Multiple gate field effect transistor and manufacture method thereof | |
| CN111261517B (en) | Semiconductor structure and forming method thereof | |
| CN105448968B (en) | Method for manufacturing fin field effect transistor | |
| CN103021857B (en) | The manufacture method of multiple gate field effect transistor | |
| CN108630752B (en) | Semiconductor structure and forming method thereof | |
| CN112652578B (en) | Method for forming semiconductor structure and transistor | |
| CN111383917B (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |