CN102129982A - Manufacturing method of fine pattern of semiconductor and FIN body of fin type field effect transistor - Google Patents
Manufacturing method of fine pattern of semiconductor and FIN body of fin type field effect transistor Download PDFInfo
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- CN102129982A CN102129982A CN2010106128570A CN201010612857A CN102129982A CN 102129982 A CN102129982 A CN 102129982A CN 2010106128570 A CN2010106128570 A CN 2010106128570A CN 201010612857 A CN201010612857 A CN 201010612857A CN 102129982 A CN102129982 A CN 102129982A
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Abstract
The invention discloses a manufacturing method of a fine pattern, and the method comprises the following steps: forming a sacrificial layer on the surface of a material to be processed, performing rough machining on the sacrificial layer to form a rough-machined pattern, and forming a covering layer on the surface of the sacrificial layer; performing selective corrosion on the sacrificial layer from the side surface of the formed rough-machined pattern, reducing the plane size of the sacrificial layer to the required scale, and getting the fine pattern of the sacrificial layer; removing the covering layer; and on the basis of taking the fine pattern of the sacrificial layer as a mask, etching the material to be processed for forming the fine pattern of the material to be processed. The concept from rough to fine is adopted in the manufacturing method, the rough-machined pattern of the sacrificial layer is firstly obtained, then the fine pattern of the sacrificial layer is obtained through corrosion of the side surface, the fine pattern is further used as the mask for etching the material to be processed so as to form the fine pattern of the material to be processed, the fine pattern formed in the whole scheme is not limited by photoetching and the etching technical level, and the manufacturing method is simple to implement, compatible with the traditional manufacturing process, good in controllability, low in cost and very strong in practical value.
Description
Technical field
The present invention relates to microfabrication manufacturing technology field, relate in particular to the manufacture method of the FIN body of a kind of manufacture method of fine pattern and a kind of fin-shaped field effect transistor (FinFET, Fin Field Effect Transistor).
Background technology
In recent years, the technology manufacture method of fine pattern receives the concern in a lot of fields, and especially semiconductor integrated circuit is made the field.Since the integrated circuit invention, its performance steadily improves always.The raising of performance mainly is to realize by the size of constantly dwindling integrated circuit (IC)-components.At present, the characteristic size of integrated circuit (IC)-components (MOSFET, Metal-Oxide-Semiconductor or Field-Effect Transistor) is to narrow down to nanoscale.Under this yardstick, the various basic restrictions with reality begin to occur, and make the development that is based upon the integrated circuit technique on silicon planar CMOS (the Complementary Metal Oxide Semiconductor) technology just suffer unprecedented challenge.It is generally acknowledged that through great efforts, the CMOS technology still might be advanced to 20 nanometers even 10 nm technology node, multiple-grid MOS device technology is considered to be hopeful most the technology that is applied after inferior 20 nanometer nodes.This be because, compare with the single gate device of tradition, the multiple-grid device has stronger short channel and suppresses ability, better subthreshold characteristic, higher driving force and can bring higher current densities.
At present, the FINFET device can be realized by the planar CMOS technology of routine because of its self-alignment structure, thereby is become most promising multiple-grid device.FINFET structurally can be divided into double grid FINFET and three grid FINFET.Concerning double grid FINFET, for obtaining acceptable device performance, the thickness that requires its FIN body is 1/2～1/3 of grid length, and like this, the level of microfabrication must develop in advance significantly.On the other hand, with regard to three grid FINFET, because three faces of FIN body all are subjected to the control of gate electrode, ought to have stronger short channel control ability, therefore the thickness of FIN body can be worked as with the grid appearance or is bigger, (minimum) characteristic size that is device is still long for grid, and the microfabrication level is not proposed extraordinary requirement, thereby more compatible with the traditional cmos process technology.Yet, theoretical and experimental study shows that all under channel doping concentration condition with higher, three grid FINFET have presented more good short-channel properties really, but at raceway groove is under the situation of light (nothing) doping, and three grid structures are not compared with double-gate structure and significantly improved.And under the nanoscale situation, for fear of the dispersion of the discrete device threshold voltage that causes of amount of impurities, the MOS device can not adopt highly doped raceway groove, promptly must adopt light (nothing) doped channel.In addition, under the situation of identical channel area, the device of three grid structures is than double-gate structure, even the device of single grid structure takies more chip area.Therefore, comprehensive, double grid FINFET is preferable new device structure.
Although it seems that at present double grid FINFET more promises to be follow-on integrated circuit (IC)-components than three grid FINFET, before entering practicability, must solve some crucial technical barriers.The processing of ultra-thin Fin body is exactly one of topmost difficult problem.The Experiment Preparation technology of being reported at present all can not become big production technology.The manufacture method of the FIN body of being demonstrated is so far normally passed through certain means again on the basis of photoetching, as litho pattern being carried out ashing processing such as (Ashing), to reach further dwindling of figure.This technology can not be used for the making of circuit because the uniformity of the descriptive geometry size that forms and repeatability are very poor.Side wall figure transfer technology (spacer image transfer) can be used to make individual devices though be a kind of easy nanoscale process technology, and this technology can produce numerous parasitic figures, thereby can not be used for the making of circuit.
Summary of the invention
Technical problem to be solved by this invention is, a kind of manufacture method of fine pattern is provided, and do not need high accuracy and high resolution lithography technology just can make fine pattern.
For solving the problems of the technologies described above, the present invention proposes a kind of manufacture method of fine pattern, comprising: form sacrifice layer on the surface of material to be processed, described sacrifice layer is carried out roughing with formation roughing figure, and form cover layer on the surface of sacrifice layer; From the side of the roughing figure that forms described sacrifice layer is carried out selective corrosion, make it planar dimension and be reduced to needed yardstick, obtain the sacrifice layer fine pattern; Remove described cover layer; With described sacrifice layer fine pattern is mask, and the described material to be processed of etching is to form fine pattern.
Further, described sacrifice layer is carried out roughing and comprises forming cover layer on the surface of sacrifice layer: the photoresist of the pre-sizing of coating one deck on the surface at described sacrifice layer, the described sacrifice layer of photoetching and etching, described photoresist forms the lip-deep cover layer of sacrifice layer.
Preferably, the cover layer on the described removal sacrifice layer fine pattern comprises: use dry method or wet method to remove described photoresist.
Further, described sacrifice layer is carried out roughing and form cover layer on the surface of sacrifice layer comprising: at described sacrifice layer growth one deck dielectric layer; The photoresist of the pre-sizing of coating one deck on described dielectric layer; Described dielectric layer of photoetching and etching and sacrifice layer, described photoresist and dielectric layer form the lip-deep cover layer of sacrifice layer.
Preferably, described dielectric layer is a nitration case; Described removal cover layer comprises: use dry method or wet method to remove described photoresist; Use hot phosphoric acid to remove described dielectric layer.
Further, described material to be processed is body silicon materials or silicon-on-insulator material, and described sacrifice layer is an oxide layer; Described side from the roughing figure that forms is carried out selective corrosion to described sacrifice layer and is meant: use the silica erosion liquid of buffering, from the side of the roughing figure that forms described sacrifice layer is corroded.
Further, described etching material to be processed comprises: use the described material to be processed of dry etching.
According to another aspect of the present invention, a kind of manufacture method of FIN body of fin-shaped field effect transistor also is provided, comprise: on the surface of Semiconductor substrate, form sacrifice layer, described sacrifice layer is carried out roughing with formation roughing figure, and on the surface of sacrifice layer, form cover layer; From the side of the roughing figure that forms described sacrifice layer is carried out selective corrosion, make it planar dimension and be reduced to needed yardstick, obtain the sacrifice layer fine pattern; Remove the cover layer on the sacrifice layer fine pattern; With the described sacrifice layer fine pattern after the corrosion is mask, and the described Semiconductor substrate of etching is to form the FIN body of fin-shaped field effect transistor.
Further, described sacrifice layer is carried out roughing and comprises forming cover layer on the surface of sacrifice layer: the photoresist of the pre-sizing of coating one deck on the surface at described sacrifice layer, the described sacrifice layer of photoetching and etching, described photoresist forms the lip-deep cover layer of sacrifice layer.
Further, described sacrifice layer is carried out roughing and form cover layer on the surface of sacrifice layer comprising: at described sacrifice layer growth one deck dielectric layer; The photoresist of the pre-sizing of coating one deck on described dielectric layer; Described dielectric layer of photoetching and etching and sacrifice layer, described photoresist and dielectric layer form the lip-deep cover layer of sacrifice layer.
Beneficial effect of the present invention is: obtain the roughing figure by first roughing sacrifice layer, on sacrifice layer, form cover layer, be needed yardstick by this sacrifice layer of side etch until its planar dimension then, remove cover layer, with the sacrifice layer after the corrosion as mask etching material to be processed to form fine pattern, need not high accuracy and high-resolution photoetching technique in the whole proposal, it is the restriction that formed fine pattern is not subjected to photoetching and lithographic technique level, manufacture method realizes simple, with the traditional manufacturing technique compatibility, controllability is good, and cost is low, has very strong practical value.
Description of drawings
Fig. 1 is the schematic flow sheet of a kind of fine pattern manufacture method of the present invention;
The generalized section of the backing material that Fig. 2 is adopted for the embodiment of the invention one;
Fig. 3 is the generalized section behind the formation silicon oxide layer of the embodiment of the invention one;
Fig. 4 is the generalized section after photoetching and the etching of carrying out of the embodiment of the invention one;
Fig. 5 carries out generalized section after the side direction selective etching for the embodiment of the invention one to silicon oxide layer;
Fig. 6 is the generalized section behind the removal photoresist of the embodiment of the invention one;
Fig. 7 is generalized section behind the mask etching silicon fiml with the oxide layer for the embodiment of the invention one;
The generalized section of the backing material that Fig. 8 is adopted for the embodiment of the invention two;
Fig. 9 is the formation silicon oxide layer of the embodiment of the invention two and the generalized section behind the silicon nitride layer;
Figure 10 is the generalized section after photoetching and the etching of carrying out of the embodiment of the invention two;
Figure 11 carries out generalized section after the side direction selective etching for the embodiment of the invention two to silicon oxide layer;
Figure 12 is the removal photoresist of the embodiment of the invention two and the generalized section behind the nitration case;
Figure 13 is generalized section behind the mask etching silicon fiml with the oxide layer for the embodiment of the invention two;
Figure 14 is that the FIN system of employing FINFET of the present invention is made a kind of FINFET structural representation after method is made, and wherein (A) is the FINFET schematic perspective view, (B) is the exploded view of (A).
Embodiment
In conjunction with the accompanying drawings the present invention is described in further detail below by embodiment.
The manufacture method of fine pattern of the present invention adopts thinking from coarse to fine, earlier on material to be processed, form sacrifice layer, to its roughing to form the roughing figure, and on sacrificial layer surface, to form cover layer, so that its upper surface is unaffected during the side etch sacrifice layer, make the planar dimension of sacrifice layer reach required yardstick by the side selective etching, obtain the sacrifice layer fine pattern, remove cover layer, again with this sacrifice layer fine pattern as mask etching material to be processed to form the fine pattern of material to be processed.
As shown in Figure 1, the manufacture method of fine pattern of the present invention comprises the steps:
Step S10 forms sacrifice layer on the surface of material to be processed, described sacrifice layer is carried out roughing with formation roughing figure, and form cover layer on the surface of sacrifice layer;
Step S20 carries out selective corrosion from the side of the roughing figure that forms to sacrifice layer, makes it planar dimension and is reduced to needed yardstick, obtains the sacrifice layer fine pattern;
Step S30 removes cover layer;
Step S40 is a mask with the sacrifice layer fine pattern, and etching material to be processed is to form the fine pattern of material to be processed.
On the basis of above-mentioned manufacture method flow process, describe some embodiments of the present invention in detail below in conjunction with accompanying drawing 2-13.In the accompanying drawings, painstakingly do not draw accompanying drawing in proportion, focus on illustrating purport of the present invention.Identical Reference numeral is represented identical part in whole accompanying drawings.For the purpose of cheer and bright, amplified the thickness in each layer and zone, should be with this as limitation of the invention.The three dimensions size that in the manufacturing process of reality, should comprise in addition, length, width and the degree of depth; And processing method such as the mentioned photoetching of the present invention, etching all can adopt preparation technology's method of standard to realize.
Embodiment one:
The manufacture craft process of present embodiment is shown in Fig. 2-7.It is backing material that present embodiment adopts semiconductor wafer, this backing material is silicon SOI (Silicon On Insulator, a silicon-on-insulator) silicon chip, comprise silicon body region 100 ', buried oxidation layer (BOX, Buried Oxide) 200 ' and monocrystalline silicon membrane 300 ', as shown in Figure 2.
At first form material to be processed, and then form sacrifice layer in substrate material surface; To backing material processing, directly form sacrifice layer thereon in this way.As shown in Figure 3, at first form on the surface of backing material layer of oxide layer 400 as sacrifice layer ', its formation method can be any conventional method, as conventional thermal oxidation, chemical vapor deposition (CVD, Chemical Vapor Deposition), physical vapor deposition (PVD, PhysicalVapor Deposition) etc.Oxide layer is 10nm～30nm in the present embodiment.
Then, oxide layer 400 ' on coating one deck pre-sizing photoresist 600 ', photoetching and etching oxidation layer 400 ' forming the roughing figure then, photoresist 600 ' then form the cover layer of sacrifice layer (be oxide layer 400 '), as shown in Figure 4.
To photoetching and the formed oxide layer 400 of etching ' the roughing figure carry out the side direction selective etching, promptly from the side etch oxide layer 400 of the roughing figure that forms ', make it to be reduced to needed yardstick, as shown in Figure 5.The planar dimension of oxide layer can constantly reduce like this, and the amount that specifically reduces was determined by the time.Corrosive liquid is the silica erosion liquid (BOE, Buffer Oxide Etcher) of buffering in the present embodiment; BOE is to the monocrystalline silicon membrane 300 of backing material ' do not corrode, to photoresist 600 ' corrosion rate very slow.
As shown in Figure 6, remove photoresist 600 '.Can adopt in the present embodiment dry method (oxygen plasma) or wet method (mixed liquor of sulfuric acid and hydrogen peroxide) remove photoresist 600 '.
As shown in Figure 7, with the oxide layer 400 of having dwindled after the corrosion ' be mask, the monocrystalline silicon membrane 300 of etched substrate material ', form high meticulous silicon FIN3.Use dry etching silicon fiml 300 in the present embodiment '.After silicon FIN3 forms, can be further used for making the FINFET transistor of extra small size.
Embodiment two:
The manufacture craft process of present embodiment is shown in Fig. 8-13.It is backing material that present embodiment adopts semiconductor wafer equally, and this backing material is the silicon soi wafer, comprises silicon body region 100, buried oxidation layer 200 and monocrystalline silicon membrane 300, as shown in Figure 8.
Then, surface at backing material forms one deck sacrifice layer, growth one deck dielectric layer on sacrifice layer then, as shown in Figure 9, sacrifice layer is an oxide layer 400, and dielectric layer is a nitration case 500, and detailed process is: the layer of oxide layer 400 of at first growing, growing method can be any conventional method, as conventional thermal oxidation, chemical vapor deposition, physical vapor deposition etc.; And then generating one deck nitration case 500, its generation method can be any conventional method, as chemical vapor deposition, physical vapor deposition etc.Oxide layer is 10nm～30nm in the present embodiment; Nitration case is 10nm～30nm.Dielectric layer among other embodiment can also be that other materials is made, as long as guarantee when carrying out the side etch sacrifice layer, this dielectric layer is not subjected to or is subjected to hardly infection.
Then, the photoresist 600 that is coated with the pre-sizing of one deck on dielectric layer (being nitration case 500) carries out photoetching, etching nitration case 500 and oxide layer 400 are to form the roughing figure continuously then, and photoresist 600 and nitration case 500 then are the cover layer on the sacrificial layer surface, as shown in figure 10.
From the side of the roughing figure that forms sacrifice layer is carried out selective corrosion, the oxide layer 400 roughing figures of the present invention after to photoetching and etching carry out the side direction selective etching, make it to be reduced to needed yardstick, as shown in figure 11.The planar dimension of silica can constantly reduce like this, and the amount that reduces was determined by the time.Corrosive liquid is the silica erosion liquid (BOE, Buffer Oxide Etcher) of buffering in the present embodiment; BOE does not all corrode the monocrystalline silicon membrane 300 and the nitration case 500 of backing material.
Then, remove cover layer (be photoresist 600 and as the nitration case 500 of dielectric layer), as shown in figure 12.Adopt dry method (oxygen plasma) or wet method (mixed liquor of sulfuric acid and hydrogen peroxide) to remove photoresist 600 in the present embodiment; Because of hot phosphoric acid corrodes silicon and silica hardly, so adopt hot phosphoric acid to remove nitration case 500, hot phosphoric acid is 140 to spend to 160 degree among the embodiment.If the dielectric layer among other embodiment is an other materials, when then removing this dielectric layer, can adopts other can remove this medium and do not corrode oxide layer 400 and the material of monocrystalline silicon membrane 300 is removed.
As shown in figure 13, be mask with the oxide layer 400 of having dwindled after the corrosion, the monocrystalline silicon membrane 300 of etched substrate material forms high meticulous silicon FIN3.Use dry etching silicon fiml 300 in the present embodiment.After silicon FIN3 forms, can be used for making the FINFET transistor of extra small size.
Among other embodiment, the selection of backing material can be not limited to semi-conducting material, can also be other material, as metal etc.; And the process of above-mentioned manufacture craft also can be: at first form sacrifice layer on the surface of semi-conducting material to be processed, on sacrifice layer, form one deck dielectric layer then, adopt other process meanses that sacrifice layer and dielectric layer are carried out roughing, this moment, dielectric layer was cover layer.
The present invention obtains the roughing figure by first roughing sacrifice layer, on sacrifice layer, form simultaneously cover layer, then formed sacrifice layer roughing figure is carried out the side direction selective etching, make it to be reduced to needed yardstick, with the sacrifice layer that dwindles as mask etching material to be processed to form the fine pattern of material to be processed, need not high accuracy and high-resolution photoetching technique in the whole proposal, it is the restriction that formed fine pattern is not subjected to photoetching and lithographic technique level, compatible fully with traditional manufacturing technique, controllability is good, cost is low, have very strong practical value, be suitable for being used in the occasion that does not adopt high accuracy and high-resolution photoetching technique but need to make fine pattern.
Based on the manufacture method of above-mentioned fine pattern, the present invention also provides a kind of manufacture method of FIN body of FINFET device, comprises the steps:
Step S10 ' forms sacrifice layer on the surface of Semiconductor substrate, this sacrifice layer is carried out roughing with formation roughing figure, and form cover layer on the surface of sacrifice layer;
Step S20 ' carries out selective corrosion from the side of the roughing figure that forms to sacrifice layer, makes it planar dimension and is reduced to needed yardstick, obtains the sacrifice layer fine pattern;
Step S30 ' removes cover layer;
Step S40 ' is a mask with the described sacrifice layer fine pattern after the corrosion, and the described Semiconductor substrate of etching is to form the transistorized FIN body of FINFET.
Above-mentioned steps S10 ' can repeat no more with reference to the specific embodiment of aforementioned making fine pattern to the detailed process of S40 ' herein.As Figure 14 (A) with (B) be depicted as the structural representation of a kind of FINFET, wherein, the FIN body 50 that adopts the inventive method to make is positioned at substrate 10 tops, has constituted the active area of FINFET, grid 40 is perpendicular to FIN body 50, and what be positioned at FIN body 50 both sides is source electrode 30 and drain electrode 20.Though manufacture method provided by the invention is specially adapted to the FINFET transistor, this method can also be used for not adopting high accuracy and high-resolution photoetching technique but the occasion of needs making fine pattern.
The foregoing description is of the present invention giving an example, although disclose most preferred embodiment of the present invention and accompanying drawing for the purpose of illustration, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various replacements, variation and modification all are possible.Therefore, the present invention should not be limited to most preferred embodiment and the disclosed content of accompanying drawing.
Claims (10)
1. the manufacture method of a fine pattern is characterized in that, comprising:
On the surface of material to be processed, form sacrifice layer, described sacrifice layer is carried out roughing with formation roughing figure, and on the surface of sacrifice layer, form cover layer;
From the side of the roughing figure that forms described sacrifice layer is carried out selective corrosion, make it planar dimension and be reduced to needed yardstick, obtain the sacrifice layer fine pattern;
Remove described cover layer;
With described sacrifice layer fine pattern is mask, and the described material to be processed of etching is to form the fine pattern of material to be processed.
2. the method for claim 1, it is characterized in that, described sacrifice layer is carried out roughing and comprises forming cover layer on the surface of sacrifice layer: the photoresist of the pre-sizing of coating one deck on the surface at described sacrifice layer, the described sacrifice layer of photoetching and etching, described photoresist forms the lip-deep cover layer of sacrifice layer.
3. method as claimed in claim 2 is characterized in that, described removal cover layer comprises: use dry method or wet method to remove described photoresist.
4. the method for claim 1 is characterized in that, described sacrifice layer is carried out roughing and form cover layer on the surface of sacrifice layer comprising:
At described sacrifice layer growth one deck dielectric layer;
The photoresist of the pre-sizing of coating one deck on described dielectric layer;
Described dielectric layer of photoetching and etching and sacrifice layer, described photoresist and dielectric layer form the lip-deep cover layer of sacrifice layer.
5. method as claimed in claim 4 is characterized in that, described dielectric layer is a nitration case; Described removal cover layer comprises: use dry method or wet method to remove described photoresist; Use hot phosphoric acid to remove described dielectric layer.
6. as each described method among the claim 1-5, it is characterized in that, described material to be processed is body silicon materials or silicon-on-insulator material, described sacrifice layer is an oxide layer, described side from the roughing figure that forms is carried out selective corrosion to described sacrifice layer and is meant: use the silica erosion liquid of buffering, from the side of the roughing figure that forms described sacrifice layer is corroded.
7. as each described method among the claim 1-6, it is characterized in that described etching material to be processed comprises: use the described material to be processed of dry etching.
8. the manufacture method of the FIN body of a fin-shaped field effect transistor is characterized in that, comprising:
On the surface of Semiconductor substrate, form sacrifice layer, described sacrifice layer is carried out roughing with formation roughing figure, and on the surface of sacrifice layer, form cover layer;
From the side of the roughing figure that forms described sacrifice layer is carried out selective corrosion, make it planar dimension and be reduced to needed yardstick, obtain the sacrifice layer fine pattern;
Remove cover layer;
With the described sacrifice layer fine pattern after the corrosion is mask, and the described Semiconductor substrate of etching is to form the FIN body of fin-shaped field effect transistor.
9. method as claimed in claim 8, it is characterized in that, described sacrifice layer is carried out roughing and comprises forming cover layer on the surface of sacrifice layer: the photoresist of the pre-sizing of coating one deck on the surface at described sacrifice layer, the described sacrifice layer of photoetching and etching, described photoresist forms the lip-deep cover layer of sacrifice layer.
10. method as claimed in claim 8 is characterized in that, described sacrifice layer is carried out roughing and form cover layer on the surface of sacrifice layer comprising:
At described sacrifice layer growth one deck dielectric layer;
The photoresist of the pre-sizing of coating one deck on described dielectric layer;
Described dielectric layer of photoetching and etching and sacrifice layer, described photoresist and dielectric layer form the lip-deep cover layer of sacrifice layer.
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| CN104393037A (en) * | 2014-09-22 | 2015-03-04 | 苏州能讯高能半导体有限公司 | Sub-micron gate length GaN HEMT device and preparation method thereof |
| CN113838753A (en) * | 2020-06-24 | 2021-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
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Application publication date: 20110720 |