CN103021857A - Manufacturing method of multi-grid field effect transistor - Google Patents
Manufacturing method of multi-grid field effect transistor Download PDFInfo
- Publication number
- CN103021857A CN103021857A CN2011103011324A CN201110301132A CN103021857A CN 103021857 A CN103021857 A CN 103021857A CN 2011103011324 A CN2011103011324 A CN 2011103011324A CN 201110301132 A CN201110301132 A CN 201110301132A CN 103021857 A CN103021857 A CN 103021857A
- Authority
- CN
- China
- Prior art keywords
- hard mask
- field effect
- effect transistor
- grid
- patterning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a manufacturing method of a multi-grid field effect transistor. The manufacturing method is characterized in that autocollimation interval sidewalls are formed on the two sides of a grid, and in the process of carrying out ion implantation to form a source electrode region and a drain region, a fin-shaped structure at the two sides of the grid can be shielded so as to prevent adulteration and injection of the ion, and the length of a channel in the fin-shaped structure positioned below the grid is increased, so as to realize the purposes that a short channel effect is restrained, the leakage current is reduced, the power consumption of the multi-grid field effect transistor is reduced, and the device property of the multi-grid field effect transistor is improved; by forming a blocking layer on the multi-grid field effect transistor and utilizing a dry method to sculpture the blocking layer and inclined autocollimation blocking masks can be formed on the two sides of a patterned hard mask layer; the autocollimation interval sidewalls are formed by utilizing the autocollimation blocking mask to sculpture, thereby utilizing an autocollimation technology to form the autocollimation interval sidewalls without utilizing photoetching and sculpture process to define in a forming process, thereby reducing the process cost, and improving the process efficiency.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor technology device, particularly a kind of manufacture method of multiple gate field effect transistor.
Background technology
Mos field effect transistor (MOSFET) is constantly to the trend development of minification in recent years, this is in order to gather way, improve assembly integrated level and the cost that reduces integrated circuit, transistorized size reduces constantly, the transistorized limit that has reached various performances of dwindling.Wherein the thickness of gate oxide and source/drain junction depth have all reached the limit.
Therefore, industry has been developed a plurality of grids or multi gate fet (Multi-Gate Transistors), and the multiple gate field effect transistor technology is a kind of novel circuit configuration technology.Conventional transistor be each transistor only have grid be used for controlling electric current between two construction units by or interrupt, and then form calculate in required " 0 " and " 1 ".And the multiple-gate transistor technology is each transistor two or three grid are arranged, thereby improved the ability of transistor controls electric current, i.e. computing capability, and significantly reduced power consumption, reduced the phase mutual interference between electric current.Wherein, multiple gate field effect transistor is the device architecture among a kind of MOFET that an above grid is incorporated into individual devices, this means, raceway groove is surrounded by several grids on a plurality of surfaces, thereby the leakage current in the time of can suppressing more " cut-off " state, and can strengthen drive current under " conducting " state, so just obtained the device architecture of lower power consumption and property enhancement.
J.P.Colinge is called one piece of name in the Americana of " FinFETs and other Multi-Gate Transistors " and has introduced polytype multiple gate field effect transistor, comprise double-gated transistor (Double-Gate, FinFET), tri-gate transistors (Tri-Gate), ohm-shaped gate transistor (Ω-Gate) and quadrangle gate transistor (Quad-Gate) etc.
Wherein, take double-gated transistor as example, double-gated transistor has used two grids with the control raceway groove, has greatly suppressed short-channel effect.A concrete distortion of double-gated transistor is exactly fin transistor npn npn (FinFET), described FinFET comprises vertical fin structure and across the grid in described fin structure side, both ends at the fin structure of grid both sides are respectively source electrode and drain electrode, form raceway groove in the fin structure under the grid.As nonplanar device, the size of the fin structure of FinFET has determined the length of effective channel of transistor device.FinFET compares compacter with the MOS transistor on conventional plane, can realize higher transistor density and less whole microelectric technique.In addition, tri-gate transistors is another Common Shape of multiple-gate transistor, and wherein said grid to form three control raceway grooves, further improves the overall performance of device across side and top surface at described fin structure.
The vertical direction height of fin structure and horizontal direction width and length have tremendous influence to performance, short-channel effect and the leakage current etc. of drive current.The fin structure that for example the vertical direction height is higher provides higher drive current, the fin structure that the horizontal direction width is less can suppress leakage current better, wherein, the source electrode at the fin structure two ends that cross-directional length has affected and the distance of drain-to-gate, and the channel length of this distance affects device.Yet because the restriction of size, the fin structure cross-directional length can reduce gradually, and the channel length of device can be affected.Therefore, how by a kind of technical method, provide enough channel lengths, with abundant inhibition short-channel effect and leakage current, thereby the performance that improves multiple gate field effect transistor becomes the problem that industry is demanded urgently studying.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of multiple gate field effect transistor is with the source/drain that the increases multiple gate field effect transistor distance to grid, with the performance of raising multiple gate field effect transistor.
The invention provides a kind of manufacture method of multiple gate field effect transistor, comprise
One substrate is provided, forms fin structure in described substrate, and be formed with successively grid film and hard mask layer on described fin structure surface;
The described hard mask layer of patterning forming the hard mask layer of patterning, and take the hard mask layer of patterning as the described grid film of mask etching, is located at the grid of described fin structure sidewall and top surface with formation;
Form the wall of the hard mask layer, grid and the fin structure that cover described patterning;
Carry out chemical mechanical milling tech, until expose the end face of the hard mask layer of described patterning;
Return etching technics, until expose whole sides of the hard mask layer of described patterning;
Form the hard mask layer of the described patterning of covering and the barrier layer of wall;
The described barrier layer of etching forms the autoregistration block mask with the hard mask both sides at described patterning;
Take described autoregistration block mask as hard mask, the described wall of etching is to form the autoregistration spacer side walls;
Remove the hard mask layer of described autoregistration block mask and patterning.
Further, after the step of the hard mask layer of removing described autoregistration block mask and patterning, also comprise: carry out ion implantation technology, form respectively source area and drain region with the end that is positioned at described grid both sides at described fin structure.
Further, described substrate is the silicon-on-insulator substrate.
Further, described silicon-on-insulator substrate comprises silicon substrate, is positioned at burying the oxygen insulating barrier and being positioned at the described semiconductor layer that buries on the oxygen insulating barrier on the described silicon substrate.
Further, the height of described fin structure is 30nm～100nm, and the width of described fin structure is 10nm～25nm.
Further, the material of described wall is a kind of of silicon nitride, silicon oxynitride or silicon nitride or its combination.
Further, described wall comprises oxide layer and the nitration case that is positioned on the described oxide layer.
Further, the thickness of described autoregistration spacer side walls is 30nm～100nm.
Further, the material of described hard mask layer is a kind of or its combination in silicon oxynitride, titanium, titanium nitride, tantalum or the tantalum nitride.
Further, the thickness of described hard mask layer is 50 dusts～200 dusts.
Than prior art, multiple gate field effect transistor of the present invention is by forming the autoregistration spacer side walls in the grid both sides, thereby in the process of carrying out Implantation formation source area and drain region, the fin structure that this autoregistration spacer side walls can be sheltered these grid both sides is not doped injection, and then increased the length of the fin structure raceway groove that is arranged in grid below, with inhibition short-channel effect, reduction leakage current, thereby reach the power consumption that reduces multiple gate field effect transistor, the purpose that improves the device performance of multiple gate field effect transistor.
Simultaneously, the present invention forms the barrier layer at multiple gate field effect transistor, and the described barrier layer of dry etching, thereby form the autoregistration block mask of ramped shaped in the hard mask layer both sides of described patterning, and utilize described autoregistration block mask to come the described wall of etching as hard mask, form the autoregistration spacer side walls, thereby utilize self-aligned technology, in forming process, do not need to utilize the definition of photoetching and etching technics, namely form the autoregistration spacer side walls, thereby reduced process costs, improved process efficiency.
Description of drawings
Fig. 1 is the making flow chart of the manufacture method of multiple gate field effect transistor in one embodiment of the invention.
Fig. 2 is the structural representation of multiple gate field effect transistor in one embodiment of the invention.
Fig. 3～Figure 12 is along the structural representation of A ' among Fig. 2-A directional profile in the manufacturing step of multiple gate field effect transistor in one embodiment of the invention.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Core concept of the present invention is, by forming the barrier layer at multiple gate field effect transistor, and the described barrier layer of dry etching, the autoregistration block mask formed in described hard mask both sides, take described autoregistration block mask as hard mask, can form the autoregistration spacer side walls; When the end that described fin structure is positioned at described grid both sides forms respectively source area and drain region, the fin structure that this autoregistration spacer side walls (Spacer) can be sheltered described grid both sides is not doped injection, thereby increase source area and drain region to the distance of described grid, and then increased the length that is arranged in grid below fin structure raceway groove, realize the inhibition short-channel effect, reduced leakage current, reached the power consumption that reduces multiple gate field effect transistor, the purpose that improves the device performance of multiple gate field effect transistor.
Fig. 1 is the making flow chart of the manufacture method of multiple gate field effect transistor in one embodiment of the invention, as shown in Figure 1, the invention provides a kind of manufacture method of multiple gate field effect transistor, comprising:
Step S01 a: substrate is provided, and forms fin structure in described substrate, form successively grid film and hard mask layer on described fin structure surface;
Step S02: the described hard mask layer of patterning forming the hard mask layer of patterning, and take the hard mask layer of patterning as the described grid film of mask etching, is located at the grid of described fin structure sidewall and top surface with formation;
Step S03: the wall that forms the hard mask layer, grid and the fin structure that cover described patterning;
Step S04: carry out chemical mechanical milling tech, until expose the end face of the hard mask layer of described patterning;
Step S05: return etching technics, until expose whole sides of the hard mask layer of described patterning;
Step S06: form the hard mask layer of the described patterning of covering and the barrier layer of wall;
Step S07: the described barrier layer of etching forms the autoregistration block mask with the hard mask both sides at described patterning;
Step S08: take described autoregistration block mask as hard mask, the described wall of etching is to form the autoregistration spacer side walls;
Step S09: the hard mask layer of removing described autoregistration block mask and patterning.
Further, after the step of the hard mask layer of removing described autoregistration block mask and patterning, also comprise: carry out ion implantation technology, form respectively source area and drain region with the end that is positioned at described grid both sides at described fin structure.Because covering of autoregistration spacer side walls increased source area and drain region to the distance between the grid, thereby further suppressed short-channel effect, reduce leakage current, thereby greatly improve the performance of described multiple gate field effect transistor.
Multiple gate field effect transistor of the present invention is by forming the autoregistration spacer side walls in described grid both sides, thereby in the process of carrying out Implantation formation source area and drain region, the fin structure that this autoregistration spacer side walls can be sheltered these grid both sides is not doped injection, thereby increase the distance between source area and drain region and the described grid, further suppress short-channel effect, and the reduction leakage current, thereby greatly improve the performance of described multiple gate field effect transistor.
Simultaneously, by forming the barrier layer at multiple gate field effect transistor, and utilize the described barrier layer of dry etching, form the autoregistration block mask of ramped shaped in described hard mask both sides; Utilize the autoregistration block mask as the described wall of hard mask etching, thereby utilize self-aligned technology, in forming process, do not need to utilize the definition of photoetching and etching technics, namely form the autoregistration spacer side walls, thereby reduced process costs, improved process efficiency.When the end that described fin structure is positioned at described grid both sides forms respectively source area and drain region, thereby increase source area and drain region to the distance of described grid, and then increased the length that is arranged in grid below fin structure raceway groove, suppress short-channel effect, reduce leakage current with realization, thereby reach the power consumption that reduces multiple gate field effect transistor, the purpose that improves the device performance of multiple gate field effect transistor.
Fig. 3～Figure 12 is along the structural representation of A ' A directional profile among Fig. 2 in the manufacturing step of multiple gate field effect transistor in one embodiment of the invention.Describe the manufacturing process of above each step in detail below in conjunction with Fig. 3～Figure 12:
At first, in described step S01, described substrate for example is silicon-on-insulator (SOI) substrate, as shown in Figure 2, described SOI silicon base comprises silicon substrate (not indicating among the figure), is arranged in burying oxygen insulating barrier (BOX) 100 and being positioned at the semiconductor layer (figure does not indicate) that buries on the oxygen insulating barrier 100 on the silicon substrate, and the material of described semiconductor layer can be silicon, germanium or silicon Germanium compound etc.In the present embodiment, utilize the electron beam lithography process that described semiconductor layer is carried out photoetching and etching technics, vertically stand on the described fin structure 104 that buries on the oxygen insulating barrier 100 to form.In conjunction with Fig. 2, the both ends of this fin structure 104 will form source area 202 and drain region 204 in follow-up technique, grid 106 can be formed on the middle part sidewall of this fin structure 104 and the top surface, raceway groove (not indicating among the figure) will be formed with in the middle part of this fin structure 104.The height H of the fin structure 104 that forms
1Better scope is 30nm～100nm, the width W of described fin structure 104
1Better scope is 10nm～25nm.Fin structure 104 in the size range of above-mentioned height and width has good drive current performance, and can suppress short-channel effect and leakage current.
Then, as shown in Figure 3, carry out chemical vapour deposition (CVD), to form grid film 106a and hard mask layer 108a at described fin structure 104 and described oxygen insulating barrier (BOX) 100 depositions of burying.Wherein, the material of described grid film 106a can be polysilicon, and the material of described hard mask layer 108a can be a kind of or its combination in silicon oxynitride, titanium, titanium nitride or tantalum or the tantalum nitride.If select silicon oxynitride or metal hard mask material (such as titanium, titanium nitride or tantalum or tantalum nitride) as the material of hard mask layer 108a, in subsequent etching technique, the photoresist material that uses in the polycrystalline silicon material of itself and grid 106, the photoetching process and the autoregistration block mask of follow-up formation all have good etching selection ratio, can be conducive to the selective etch of etching technics.The better scope of the thickness of described hard mask layer 108a is 50 dusts～200 dusts, and its height equates with the height of grid or differs within 10 dusts, with in subsequent step, forms the good autoregistration spacer side walls 111 of figure of ramped shaped.
Then, utilize photoetching and etching technics to form the hard mask layer 108 of patterning, the hard mask layer 108 of described patterning covers the top, position that will form grid.As shown in Figure 4, particularly, in described step S02, apply photoresist (not indicating among the figure) at described hard mask layer 108a, utilize mask plate that this photoresist is exposed, then to the develop photoresist of rear formation patterning of this photoresist, again take the photoresist of this patterning as mask, the described hard mask layer 108a of etching, thereby the hard mask layer 108 of formation patterning.Hard mask layer 108 that subsequently can patterning is hard mask, the described grid film of etching 106a, grid film 106a has good etching ratio with respect to the hard mask layer 108 of patterning, and grid film 106a has good etching ratio equally with respect to fin structure 104, thereby form and be connected across the sidewall of described fin structure 104 and the grid 106 of top surface, concrete structure as shown in Figure 5.
As shown in Figure 6, in described step S03, utilize chemical vapour deposition technique deposition wall 110, described wall 110 covers hard mask layer 108, described grid 106 and the described fin structure 104 of described patterning; Wherein, the material of described wall 110 can be a kind of of silica, silicon nitride or its combination, and in the present embodiment, described wall 110 comprises oxide layer and the nitration case that is positioned on the described oxide layer.
As shown in Figure 7, in described step S04, carry out chemical mechanical milling tech and remove the part wall, until expose the end face of the hard mask layer 108 of described patterning.
As shown in Figure 8, in described step S05, return etching technics, continue etched portions wall 110, etching technics is until expose the hard mask layer 108 of whole described patternings and stop, with whole sides of the hard mask layer 108 that exposes described patterning; In returning etch step, adopt dry etching, etch thicknesses is preferably 50 dusts～200 dusts; Wall 110 has good etching ratio with the hard mask layer 108 of described patterning, so in etching process, the thickness of the hard mask layer 108 of patterning does not almost change.
As shown in Figure 9, in described step S06, utilize chemical vapour deposition technique to form barrier layer 112, with hard mask layer 108 and the wall 110 that covers described patterning;
As shown in figure 10, in described step S07, the described barrier layer 112 of dry etching, because the characteristic of dry etching, residual ramp-like barrier layer, barrier layer in hard mask layer 108 both sides of described patterning, thereby the barrier layer of ramped shaped becomes autoregistration block mask 112a in the both sides of the hard mask layer 108 of described patterning; Wherein, the width W of described autoregistration block mask 112a bottom
2Scope is 10nm～25nm.
As shown in figure 11, in described step S08, take described autoregistration block mask 112a as mask, the described wall 110 of etching, thus form autoregistration spacer side walls 111.The width of described autoregistration spacer side walls is namely in the width W of described autoregistration block mask 112a bottom
2Identical, be 10nm～25nm.
As shown in figure 12, in described step S09, remove the hard mask layer 108 of described autoregistration block mask 112a and patterning, form as shown in figure 12 structure, the thickness range of described autoregistration spacer side walls 111 is preferably 10nm～25nm, the autoregistration spacer side walls 111 of this preferred thickness is in the process of carrying out follow-up ion implantation technology formation source area and drain region, and the thickness of sheltering described grid 106 is moderate, has moderately increased the length that is arranged in grid below fin structure raceway groove.
In the present embodiment, after the step of the hard mask layer 108 of removing described block mask 112a and patterning, form as shown in Figure 2 structure, then, also can carry out Implantation to described fin structure both ends, form respectively source area 202 and drain region 204 with the end in described grid 106 both sides, owing to stopping of described autoregistration spacer side walls 111, increase the distance of the raceway groove of described source area 202 and drain region 204 under the grid 106, thereby fully suppressed short-channel effect and leakage current.
Than prior art, multiple gate field effect transistor of the present invention is by forming the autoregistration spacer side walls in described grid both sides, thereby in the process of carrying out Implantation formation source area and drain region, the fin structure that this autoregistration spacer side walls can be sheltered these grid both sides is not doped injection, and then increased the length that is arranged in grid below fin structure raceway groove, suppress short-channel effect, reduce leakage current with realization, thereby reach the power consumption that reduces multiple gate field effect transistor, the purpose that improves the device performance of multiple gate field effect transistor.
Simultaneously, by forming the barrier layer at multiple gate field effect transistor, and utilize the described barrier layer of dry etching, form the autoregistration block mask of ramped shaped; And utilize the autoregistration block mask to form the autoregistration spacer side walls as hard mask etching, thereby utilize self-aligned technology, in forming process, do not need to utilize the definition of photoetching and etching technics, namely form the autoregistration spacer side walls, thereby reduced process costs, improved process efficiency.When the end that described fin structure is positioned at described grid both sides forms respectively source area and drain region, thereby increase source area and drain region to the distance of described grid, and then increased the length that is arranged in grid below fin structure raceway groove, suppress short-channel effect, reduce leakage current with realization, thereby reach the power consumption that reduces multiple gate field effect transistor, the purpose that improves the device performance of multiple gate field effect transistor.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; have in the technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. the manufacture method of a multiple gate field effect transistor comprises
One substrate is provided, forms fin structure in described substrate, and be formed with successively grid film and hard mask layer on described fin structure surface;
The described hard mask layer of patterning forming the hard mask layer of patterning, and take the hard mask layer of patterning as the described grid film of mask etching, is located at the grid of described fin structure sidewall and top surface with formation;
Form the wall of the hard mask layer, grid and the fin structure that cover described patterning;
Carry out chemical mechanical milling tech, until expose the end face of the hard mask layer of described patterning;
Return etching technics, until expose whole sides of the hard mask layer of described patterning;
Form the hard mask layer of the described patterning of covering and the barrier layer of wall;
The described barrier layer of etching forms the autoregistration block mask with the hard mask both sides at described patterning;
Take described autoregistration block mask as hard mask, the described wall of etching is to form the autoregistration spacer side walls;
Remove the hard mask layer of described autoregistration block mask and patterning.
2. the manufacture method of multiple gate field effect transistor as claimed in claim 1, it is characterized in that, after the step of the hard mask layer of removing described autoregistration block mask and patterning, also comprise: carry out ion implantation technology, form respectively source area and drain region with the end that is positioned at described grid both sides at described fin structure.
3. the manufacture method of multiple gate field effect transistor as claimed in claim 1 or 2 is characterized in that, described substrate is the silicon-on-insulator substrate.
4. the manufacture method of multiple gate field effect transistor as claimed in claim 3 is characterized in that, described silicon-on-insulator substrate comprises silicon substrate, is positioned at burying the oxygen insulating barrier and being positioned at the described semiconductor layer that buries on the oxygen insulating barrier on the described silicon substrate.
5. the manufacture method of multiple gate field effect transistor as claimed in claim 1 or 2 is characterized in that, the height of described fin structure is 30nm～100nm, and the width of described fin structure is 10nm～25nm.
6. the manufacture method of multiple gate field effect transistor as claimed in claim 1 or 2 is characterized in that, the material of described wall is a kind of of silicon nitride, silicon oxynitride or silicon nitride or its combination.
7. the manufacture method of multiple gate field effect transistor as claimed in claim 6 is characterized in that, described wall comprises oxide layer and the nitration case that is positioned on the described oxide layer.
8. the manufacture method of multiple gate field effect transistor as claimed in claim 1 or 2 is characterized in that, the thickness of described autoregistration spacer side walls is 30nm～100nm.
9. the manufacture method of multiple gate field effect transistor as claimed in claim 1 or 2 is characterized in that, the material of described hard mask layer is a kind of or its combination in silicon oxynitride, titanium, titanium nitride, tantalum or the tantalum nitride.
10. the manufacture method of multiple gate field effect transistor as claimed in claim 1 or 2 is characterized in that, the thickness of described hard mask layer is 50 dusts～200 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110301132.4A CN103021857B (en) | 2011-09-28 | 2011-09-28 | The manufacture method of multiple gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110301132.4A CN103021857B (en) | 2011-09-28 | 2011-09-28 | The manufacture method of multiple gate field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103021857A true CN103021857A (en) | 2013-04-03 |
| CN103021857B CN103021857B (en) | 2015-12-16 |
Family
ID=47970325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110301132.4A Active CN103021857B (en) | 2011-09-28 | 2011-09-28 | The manufacture method of multiple gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103021857B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105632936A (en) * | 2016-03-22 | 2016-06-01 | 上海华力微电子有限公司 | Fabrication method for dual-gate fin field effect transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060105531A1 (en) * | 2004-11-15 | 2006-05-18 | Huh Yun J | Method of forming notched gate structure |
| CN1992185A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Method of fabricating a fin field effect transistor in a semiconductor device |
| CN101969061A (en) * | 2010-09-27 | 2011-02-09 | 复旦大学 | Fin-type tunneling transistor integrated circuit and manufacturing method thereof |
| CN102099902A (en) * | 2008-07-21 | 2011-06-15 | 超威半导体公司 | Method of forming finned semiconductor devices with trench isolation |
-
2011
- 2011-09-28 CN CN201110301132.4A patent/CN103021857B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060105531A1 (en) * | 2004-11-15 | 2006-05-18 | Huh Yun J | Method of forming notched gate structure |
| CN1992185A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Method of fabricating a fin field effect transistor in a semiconductor device |
| CN102099902A (en) * | 2008-07-21 | 2011-06-15 | 超威半导体公司 | Method of forming finned semiconductor devices with trench isolation |
| CN101969061A (en) * | 2010-09-27 | 2011-02-09 | 复旦大学 | Fin-type tunneling transistor integrated circuit and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105632936A (en) * | 2016-03-22 | 2016-06-01 | 上海华力微电子有限公司 | Fabrication method for dual-gate fin field effect transistor |
| CN105632936B (en) * | 2016-03-22 | 2018-10-16 | 上海华力微电子有限公司 | A kind of preparation method of bigrid fin formula field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103021857B (en) | 2015-12-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8357569B2 (en) | Method of fabricating finfet device | |
| CN203967092U (en) | Finfet structure | |
| US20140054723A1 (en) | Isolation structures for finfet semiconductor devices | |
| US20130161744A1 (en) | Finfet with merged fins and vertical silicide | |
| TWI503980B (en) | Double gated fin transistors and methods of fabricating and operating the same | |
| CN111223779A (en) | Semiconductor structure and forming method thereof | |
| CN111223778A (en) | Semiconductor structure and forming method thereof | |
| US10714469B2 (en) | Electrostatic discharge protection structure | |
| CN102969345B (en) | Fin field-effect tube with T-shaped fin portion and forming method of fin field-effect tube | |
| CN105551958A (en) | Formation method of transistor | |
| CN103165428A (en) | Method for manufacturing semiconductor device | |
| US10043675B2 (en) | Semiconductor device and method for fabricating the same | |
| CN103515283A (en) | Semiconductor device manufacturing method | |
| EP3244444A1 (en) | Fin-fet devices and fabrication methods thereof | |
| CN103378005B (en) | The manufacture method of multiple gate field effect transistor fin structure | |
| CN106409748B (en) | Semiconductor element and manufacturing method thereof | |
| US10916479B2 (en) | Fabrication method for fin-based semiconductor device | |
| US20190164831A1 (en) | Semiconductor device and fabrication method thereof | |
| CN103021857B (en) | The manufacture method of multiple gate field effect transistor | |
| CN103187289B (en) | The manufacture method of multiple gate field effect transistor | |
| CN111383994B (en) | Semiconductor structure and forming method thereof | |
| CN103632978A (en) | Formation method for semiconductor structure | |
| CN108630752B (en) | Semiconductor structure and forming method thereof | |
| CN108155100B (en) | Method for forming semiconductor device | |
| CN103367432B (en) | Multiple gate field effect transistor and manufacture method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |