CN101719517B - Preparation method of schottky tunneling transistor structure - Google Patents
Preparation method of schottky tunneling transistor structure Download PDFInfo
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- CN101719517B CN101719517B CN2009101990455A CN200910199045A CN101719517B CN 101719517 B CN101719517 B CN 101719517B CN 2009101990455 A CN2009101990455 A CN 2009101990455A CN 200910199045 A CN200910199045 A CN 200910199045A CN 101719517 B CN101719517 B CN 101719517B
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- silicide
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Abstract
The invention belongs to the technical field of semiconductor devices, particularly discloses a schottky tunneling transistor and a preparation method thereof. The transistor comprises a semiconductor substrate, a source electrode, a drain electrode, a grid electrode, a schottky joint (metal semiconductor joint) and metal layers positioned in the source electrode and the drain electrode, wherein the reverse biased interband tunneling current of the schottky joint is controlled by the grid electrode for the schottky tunneling transistor, one end of the schottky joint is the source electrode, and the other end is the drain electrode. The schottky tunneling transistor has the advantage of simple making technology and automatic alignment of the formation of the source electrode and the drain electrode with the grid electrode. Compared with the traditional P-N joint tunneling transistor, the schottky tunneling transistor has smaller source-drain series resistance and favorable demagnification. Therefore, the performance of a semiconductor is greatly enhanced.
Description
Technical field
The invention belongs to technical field of semiconductor device, be specifically related to a kind of Schottky tunneling transistor (Schottky TFET), the present invention also relates to a kind of preparation method of Schottky tunneling transistor simultaneously.
Background technology
In recent years, be that the microelectric technique of core has obtained development rapidly with the silicon integrated circuit, Moore's Law is followed in the development of integrated circuit (IC) chip basically, and promptly the integrated level of semiconductor chip is with per speed increment of doubling in 18 months.Along with the continuous increase of semiconductor chip integrated level, the channel length of MOS transistor is also in continuous shortening, and when the channel length of MOS transistor becomes very in short-term, short-channel effect can make the semiconductor chip performance degradation, even can't operate as normal.
Integrated circuit (IC)-components technology of today has been in about 50nm, and leakage current is with the rapid rising of dwindling of channel length between the source-drain electrode of metal-oxide-semiconductor.Below 30nm, be necessary to use new device to obtain less leakage current, reduce chip power-consumption.One of solution of the above problems is exactly to adopt tunneling field-effect transistor (TFET) structure.Tunneling field-effect transistor is the very little transistor of a kind of leakage current, its operation principle is for controlling interband tunnelling (band-to-band tunneling) electric current of back-biased semiconductor P-N (or P-I-N) knot with grid, it is source electrode that this P-N ties an end, and an other end is drain electrode.Tunneling field-effect transistor can further dwindle size, the reduction voltage of circuit, reduces the power consumption of chip greatly.Compare with traditional field-effect transistor, tunneling field-effect transistor has low-leakage current, excellent specific properties such as low the subthreshold value amplitude of oscillation, low suppling voltage and low-power consumption.
But because the doping of the source of tunneling field-effect transistor and leakage transoid each other, the autoregistration source in traditional MOS device is leaked and is formed technology and can not be employed.What this greatly reduced tunneling field-effect transistor can miniature ability, has also reduced the performance of tunneling field-effect transistor.Therefore, leak and the autoregistration problem of grid becomes tunneling field-effect transistor and moves towards one of key obstacle of practicability in P-N knot source.
Summary of the invention
The objective of the invention is to propose the formation and the grid autoregistration of a kind of source electrode and drain electrode, simultaneously, but can improve tunneling field-effect transistor micro ability, improve Schottky tunneling transistor of performance of semiconductor device and preparation method thereof greatly.
A kind of Schottky tunneling transistor that the present invention proposes, its structure comprises a Semiconductor substrate, a source electrode, a drain electrode, grid, a schottky junction (metal semiconductor junction) and the metal level that is positioned at described source electrode and drain region.Described Schottky tunneling transistor is controlled the interband tunnelling current of back-biased schottky junction with grid, and this schottky junction one end is a source electrode, and an other end is drain electrode.Described grid structure has a conductive layer and the insulating barrier with conductive layer and Semiconductor substrate isolation at least.Described conductive layer is polysilicon, amorphous silicon, tungsten metal, titanium nitride, tantalum nitride or silicide, and described insulating barrier is SiO
2, HfO
2, HfSiO, HfSiON, SiON or Al
2O
3, perhaps be several mixture among them.
Formed shallow-trench isolation on the Semiconductor substrate of the present invention; Backing material is silicon (SOI) on silicon, germanium, SiGe, the insulator or the germanium (GOI) on the insulator; Described metal level is a silicide, and this silicide is titanium silicide, cobalt silicide, nickle silicide, platinum silicide or germanium nickle silicide, or several mixture among them.Compare with traditional P-N or P-I-N knot tunneling transistor, the Schottky tunneling transistor that the present invention proposes has littler source-drain series resistance and better can miniature property.
The invention allows for the preparation method of above-mentioned Schottky tunneling transistor (Schottky TFET), specifically comprise the following steps:
A Semiconductor substrate that has formed shallow-trench isolation is provided;
On described substrate, form the rhythmic structure of the fence of device; This rhythmic structure of the fence has a conductive layer and the insulating barrier with conductive layer and Semiconductor substrate isolation at least;
Rhythmic structure of the fence is carried out photoetching and etching, and form an opening thereon;
The sacrificial dielectric layer that deposit one deck is made of first kind of dielectric is carried out anisotropic dry etch to it then;
Inject ion and form doped regions;
Remove sacrificial dielectric layer and deposit and form second kind of dielectric, then it is carried out anisotropic etching and form sidewall structure;
Form metal level in source region and drain region;
Carry out electrode isolation and electrode and form, promptly make Schottky tunneling transistor.
The thickness of described sacrificial dielectric layer needs half greater than described A/F; Described first kind and second kind of dielectric are SiO
2, Si
3N
4The perhaps insulating material that mixes mutually between them; The described n type that is doped to perhaps is the p type.
The present invention also provides a kind of integrated circuit (IC) chip, has a Schottky tunneling transistor as the aforementioned on this chip at least.
The Schottky tunneling transistor manufacturing process that the present invention proposes is simple, the formation of source electrode and drain electrode and grid autoregistration.Compare with traditional P-N knot tunneling transistor, the Schottky tunneling transistor that the present invention proposes has littler source-drain series resistance and better can miniature property, thereby can improve the performance of semiconductor device greatly.
Description of drawings
Fig. 1 is the sectional view of a semiconductor integrated circuit substrate in the example of the present invention.
Fig. 2 is the sectional view after forming gate oxide, insulating medium layer, conductive layer, hard mask layer and photoresist layer successively on the substrate that is providing behind Fig. 1.
Fig. 3 a is the sectional view after behind Fig. 2 gate oxide, insulating medium layer, conductive layer, hard mask layer and photoresist layer being carried out etching.
Fig. 3 b is the sectional view that gate oxide, insulating medium layer, conductive layer, hard mask layer and photoresist layer is carried out the another kind of grid separation scheme of another kind of etching behind Fig. 2.
Fig. 4 is the sectional view that deposit forms sacrificial dielectric layer after removing photoresist layer behind Fig. 3 a.
Fig. 5 a is etching sacrificial dielectric layer behind Fig. 4, and carries out ion and inject, and forms the sectional view of impurity profile region in Semiconductor substrate.
Fig. 5 b is the sectional view that forms metal level behind Fig. 5 a in doped region.
Fig. 6 removes old sacrificial dielectric layer and deposit to form new dielectric layer behind Fig. 5 a, then it is carried out the sectional view of etching.
Fig. 7 is the sectional view that forms metal level behind Fig. 6 in source region and drain region.
Number in the figure: 10 is wafer (substrate), and 11 is the isolation channel dielectric layer, and 12 is oxide layer, 13 is high K dielectric layer, and 14 is conductive layer, 15 hard mask layers, 16 is photoresist layer, 17 is sacrificial dielectric layer, and 18 is doped region, and 19 is dielectric layer, 20a and 20b are the silicide layer in source and drain region, 20c is the silicide layer that forms in the doped region 18, and 31 is opening, and 32 is second opening.
Embodiment
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment.In the drawings, for convenience of description, amplified or dwindled the size in different layers and zone, shown in size do not represent actual size, do not reflect the proportionate relationship of size yet.Reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of etching has crooked or mellow and full characteristics usually, but in embodiments of the present invention, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.Simultaneously in the following description, employed term wafer and substrate can be understood as and comprise the just semiconductor wafer in processes, may comprise other prepared thin layer thereon.
Step 1: as Fig. 1, provide a semiconductor integrated circuit substrate, 10 is wafer, and 11 is the isolation channel dielectric layer.Wafer 10 can be silicon or other semi-conducting material on silicon chip, germanium wafer, SiGe, the insulator.The semiconductor substrate materials of wafer 10 can mix for the n type, also can also be non-impurity-doped (intrinsic semiconductor) for the p type mixes.
Step 2:, on the substrate that provides, form film 12, film 13, film 14, film 15 and film 16 successively as Fig. 2.Film 12 is oxide layer SiO
2 Film 13 is high K dielectric layer, can be SiO
2, HfO
2, HfSiO, HfSiON, SiON or Al
2O
3, perhaps be several mixture among them; Oxide layer 12 and high K dielectric layer 13 are formed gate insulation layer here jointly.It is pointed out that gate insulation layer also can only be made up of oxide layer 12 or high K dielectric layer 13, therefore also can remove the technology that forms film 12 or film 13 in the step in Fig. 2.Film 14 is conductive layer such as highly doped polysilicon, metal level or their combination.Film 15 hard mask layers, this layer can be that metal level, dielectric layer, semiconductor layer or their combination are formed, and are mainly used to protect in follow-up etching process the conductive layer 14 as gate electrode.Film 16 is a photoresist layer.
Step 3: as Fig. 3 a, utilize photoetching technique and lithographic technique, form an opening 31 in film 12, film 13, film 14, film 15 and film 16, the width of opening 31 is designated as s1.
Step 4: as Fig. 4, remove photoresist layer 16, deposit forms sacrificial dielectric layer 17 such as being SiO then
2, Si
3N
4Perhaps be their mixture, the thickness of sacrificial dielectric layer 17 needs half (promptly greater than the s1/2) greater than the width of opening 31.
Step 5: as Fig. 5 a, utilize anisotropic dry etch that sacrificial dielectric layer 17 is carried out etching according to pattern, carrying out p type or n type ion then inject to form the source electrode of device or drain electrode (if this side forms is source electrode, a then other side need form drain electrode, vice versa), 18 for injecting the doped region that forms behind the ion.It should be noted that in addition the ionic type that then injects needs consistent with the doping type of original Semiconductor substrate if the semiconductor integrated circuit substrate that provides is the Semiconductor substrate of doping type in this step in step 1.
Step 6:, get rid of sacrificial dielectric layer 17 back deposits and form new dielectric layer 19 such as being SiO as Fig. 6
2, Si
3N
4Or be their mixture, and dielectric layer 19 is carried out anisotropic etching formation sidewall structure according to pattern.
Step 7:, form silicide 20a and 20b in source and drain region as Fig. 7.This silicide can be titanium silicide, cobalt silicide, nickle silicide, platinum silicide, germanium nickle silicide or the mixture between them.Silicide 20a forms schottky junction in the left side, and silicide 20b forms ohmic contact on the right side with original high-doped zone, and self aligned like this Schottky tunneling transistor has just formed.
It is to be noted, when carrying out above-mentioned steps 5, also can in doped region 18, form silicide 20c, if in above-mentioned steps 5, formed silicide 20c (as Fig. 5 b), when then in above-mentioned steps 7, forming silicide, different according to material and process conditions may form silicide again on silicide 20c, also may not can form new silicide.And, in above-mentioned steps 7, before forming silicide, can inject to mix and make it by ion and activate, be used for the doping content of the Schottky junction semi-conductor side that forms is later modulated, the dopant type of injection needs and the dopant type of the Semiconductor substrate that above-mentioned steps 1 provides is consistent.After forming silicide, also can inject and mix by ion, this doping does not need to be activated, and main purpose is in order to adjust work function difference between silicide and the Semiconductor substrate.
It is also to be noted that simultaneously, for form can operate as normal Schottky tunneling transistor, the work function of the silicide that forms will meet certain requirement, if the n type that is doped to of the semiconductor integrated circuit substrate that provides, then the work function of the silicide of Xing Chenging should be than higher; If the p type that is doped to of the semiconductor integrated circuit substrate that provides, then the work function of the silicide of Xing Chenging should be lower.
In addition, please refer to Fig. 3 b, after the step 2 in example, can carry out etching to film 12, film 13, film 14, film 15 and film 16 according to Fig. 3 b pattern and form the opening 31 and second opening 32, the width s1 of described opening 31 is less than the width s2 of described second opening 32.This is the scheme that another grid in the Schottky tunneling transistor structure of the present invention separates, and technical process and the described technical process of previous examples that its back forms Schottky tunneling transistor structure are similar, and we do not remake and are described in detail at this.
As mentioned above, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in the specification.
Claims (7)
1. the preparation method of a Schottky tunneling transistor, described Schottky tunneling transistor comprises a Semiconductor substrate, a source electrode, a drain electrode, a grid, a schottky junction and the metal level that is positioned at described source electrode and drain region; Described grid is controlled the interband tunnelling current of back-biased described schottky junction; Described source electrode and drain electrode are positioned at the two ends of described schottky junction; Formed shallow-trench isolation on the described Semiconductor substrate; Described grid structure has a conductive layer and the insulating barrier with conductive layer and Semiconductor substrate isolation at least;
It is characterized in that described preparation method comprises the following steps:
A Semiconductor substrate that has formed shallow-trench isolation is provided;
On described substrate, form the rhythmic structure of the fence of device; This rhythmic structure of the fence has a conductive layer and the insulating barrier with this conductive layer and Semiconductor substrate isolation at least;
By photoetching and etching technics, described rhythmic structure of the fence is carried out etching and forms an opening thereon;
The sacrificial dielectric layer that deposit one deck is made of first kind of dielectric is carried out anisotropic dry etch to it then;
Inject ion and form doped region;
Remove described sacrificial dielectric layer, second kind of dielectric of deposit afterwards carries out anisotropic etching to described second kind of dielectric again and forms sidewall structure;
Form metal level in source region and drain region;
Carry out electrode isolation and electrode and form, form Schottky tunneling transistor.
2. preparation method as claimed in claim 1 is characterized in that, described Semiconductor substrate is silicon on silicon, germanium, SiGe, the insulator or the germanium on the insulator.
3. preparation method as claimed in claim 1 is characterized in that, described conductive layer is polysilicon, amorphous silicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide.
4. preparation method as claimed in claim 1 is characterized in that, described insulating barrier is SiO
2, HfO
2, HfSiO, HfSiON, SiON or Al
2O
3, perhaps be several mixture among them.
5. preparation method's pipe as claimed in claim 1 is characterized in that, described metal level is a silicide, and this silicide is titanium silicide, cobalt silicide, nickle silicide, platinum silicide or nickle silicide, or several mixture among them.
6. preparation method according to claim 1 is characterized in that, the thickness of described sacrificial dielectric layer is greater than half of described A/F.
7. preparation method according to claim 1 is characterized in that, described n type or the p type of being doped to.
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| CN2009101990455A CN101719517B (en) | 2009-11-19 | 2009-11-19 | Preparation method of schottky tunneling transistor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887917A (en) * | 2010-06-10 | 2010-11-17 | 复旦大学 | Field-effect transistor and preparation method thereof |
| CN102054870A (en) * | 2010-10-26 | 2011-05-11 | 清华大学 | Semiconductor structure and forming method thereof |
| CN102074583B (en) * | 2010-11-25 | 2012-03-07 | 北京大学 | Low power consumption composite source structure MOS (Metal Oxide for and preparation method thereof |
| US8507959B2 (en) | 2011-01-19 | 2013-08-13 | Peking University | Combined-source MOS transistor with comb-shaped gate, and method for manufacturing the same |
| CN102117834B (en) * | 2011-01-19 | 2012-12-19 | 北京大学 | Multiple source MOS transistor with impurity segregation and production method thereof |
| CN102117833B (en) * | 2011-01-19 | 2012-07-25 | 北京大学 | Comb-shaped gate composite source MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof |
| CN102148255B (en) * | 2011-03-15 | 2013-07-31 | 清华大学 | Grid-control schottky junction field effect transistor with tunneling dielectric layer and formation method |
| CN111584539B (en) * | 2019-02-18 | 2023-05-12 | 联华电子股份有限公司 | Magnetoresistive memory structure |
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