CN102306660A - MOS (metal oxide semiconductor) device structure and manufacturing method thereof - Google Patents
MOS (metal oxide semiconductor) device structure and manufacturing method thereof Download PDFInfo
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- CN102306660A CN102306660A CN201110266253A CN201110266253A CN102306660A CN 102306660 A CN102306660 A CN 102306660A CN 201110266253 A CN201110266253 A CN 201110266253A CN 201110266253 A CN201110266253 A CN 201110266253A CN 102306660 A CN102306660 A CN 102306660A
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Abstract
The invention discloses an MOS (metal oxide semiconductor) device structure. The side wall of the structure is a lower K dielectric layer, thus the effect that a trench is influenced by the edge electric field of the source leakage of a high K thick grid MOS device through the capacitance coupling of the side wall can be weakened, and the short trench effect of the high K thick grid dielectric MOS device is restrained effectively, and the performances of the MOS device are improved. At the same time, the invention discloses a manufacturing method of the MOS device. Through carbon doping in the side wall material deposition process by the method, thus the effect that a trench is influenced by the edge electric field of the source leakage of a high K thick grid MOSFET (metal oxide semiconductor field effect transistor) through the capacitance coupling of the side wall can be weakened, the short trench effect of the high K thick grid dielectric layer MOSFET is restrained effectively, the performances of the MOS device are improved, and the method is simple and convenient.
Description
Technical field
The present invention relates to technical field of semiconductor device, relate in particular to a kind of MOS device architecture and preparation method thereof.
Background technology
Since first transistor invention, through the develop rapidly of decades, transistorized horizontal and vertical size is all dwindled rapidly.(ITRS, International Technology Roadmap for Semiconductors) predictions in 2004, will reach 7nm to transistorized characteristic size in 2018 according to ITRS.The continuing to dwindle of size improves constantly transistorized performance (speed), also make we can be on chip of the same area integrated more device, the function of integrated circuit is more and more stronger, has also reduced the unit functional cost simultaneously.
Yet constantly the reducing of device feature size also brought a series of challenge.After the characteristic size of device entered into deep-submicron, the short-channel effect of device (SCE, Short Channel Effect) was on the rise, thereby made the performance degradation of device.Short-channel effect (Short Channel Effect) is cmos device channel length common phenomena when dwindling; It can cause threshold voltage shift, source to leak break-through, DIBL (Drain induction barrier lower; Drain-induced barrier reduces) characteristics such as (higher leakage are depressed), can cause the cmos device performance failure when serious.
SCE can explain that promptly when raceway groove shortens, the ratio that source lining, leakage lining PN junction are shared raceway groove depletion region electric charge and raceway groove total electrical charge will increase, thereby cause the grid-control ability drop with the charge-sharing model that Yau proposes.
The threshold voltage shift formula of deriving according to charge-sharing model:
Can know that the conventional method that suppresses SCE is following three kinds (three parameters of regulating respectively to mark in the formula): (1) reduces t
Ox(2) reduce channel doping concentration N
b(3) reduce the junction depth X that the source serves as a contrast, leaks the lining PN junction
jWherein, to t
OxAdjusting, i.e. the adjusting of gate dielectric layer thickness is because dielectric layer tunnelling current and oxidated layer thickness exponent function relation; The gate dielectric layer thickness can not infinitely reduce; As for traditional Si O2 or SiON dielectric layer, when thickness is reduced to 1nm, will cause complete device failure.For the nano-device of high-order, the hafnium of HfO2, ZrO2, Al2O3 or its combination of having introduced high-k can keep big thickness situation to be issued to the effect of equivalent EOT as gate dielectric like this.
Do not influence the effect of raceway groove but traditional charge-sharing model is considered fringe field that device source leaks through the capacitive coupling of side wall, because traditional SiO2 or SiON dielectric layer are thinner, this effect is also not obvious.But when adopting the thick gate dielectric layer of hafnium, this effect will become big to the device influence, can cause the device property decline when serious.
For in the device of the thick gate dielectric layer of high K, how reducing this effect, can know that from theory analysis two kinds of methods are arranged: the one, the thickness of increase side wall, the 2nd, the dielectric constant of reduction side wall.In these two kinds of methods, the former is unfavorable for that integration density increases; The latter is a kind of effective way, can reduce the coupling capacitance of side wall, thereby weakens fringe field that device source leaks influences raceway groove through the capacitive coupling of side wall effect.
Yet; The spacer material of high-K gate dielectric layer device still rests on traditional side wall technology at present; Promptly adopt SiO2 or Si3N4 or its combination as spacer material, and the relative dielectric constant of SiO2 is 3.9, the relative dielectric constant of Si3N4 is the twice of SiO2 especially.
Thereby, how to reduce the relative dielectric constant of the spacer material of high-K gate dielectric layer device, become the key issue that present industry is needed solution badly.
Summary of the invention
The object of the present invention is to provide a kind of MOS device architecture and preparation method thereof, to improve the performance of MOS device.
For addressing the above problem, the present invention proposes a kind of MOS device architecture, and the gate oxide of said MOS device is the thick gate dielectric layer of high K, and its side wall is the low-K dielectric layer.
Optional, the relative dielectric constant of said low-K dielectric layer is 1.8～3.5.
Optional, this MOS device architecture specifically comprises:
Semiconductor substrate;
Gate oxide is formed on the said Semiconductor substrate;
Grid is formed on the said gate oxide, and the both sides of said grid are formed with said side wall; And
Source-drain area is formed in the said Semiconductor substrate of said grid both sides.
Optional, the material of said gate oxide is any or its combination among HfO2, ZrO2, the Al2O3.
Optional, the material of said side wall is SiO2 or Si3N4 or its combination, and mixes carbon therein.
Simultaneously, for addressing the above problem, the present invention also proposes a kind of MOS preparation of devices method, and this method comprises the steps:
Semiconductor substrate is provided;
On said Semiconductor substrate, prepare gate oxide;
On said gate oxide, prepare grid;
Two outgrowths and autoregistration etching at said grid form side wall;
Carry out the source and leak injection, in said Semiconductor substrate, form source-drain area;
Wherein, said gate oxide is the thick gate dielectric layer of high K, and said side wall is the low-K dielectric layer.
Optional, the relative dielectric constant of said low-K dielectric layer is 1.8～3.5.
Optional, the side wall that said low K is situated between forms through in the spacer material deposition process, mixing carbon impurity.
Optional, the material of said gate oxide is any or its combination among HfO2, ZrO2, the Al2O3.
Compared with prior art; MOS device architecture provided by the invention; Its side wall is the low-K dielectric layer; Thereby the fringe field that can weaken the leakage of the thick grate MOS device of high K source passes through the effect that the capacitive coupling of side wall influences raceway groove, effectively suppresses the short-channel effect of the thick grid medium MOS device of high K, improves the performance of MOS device.
Compared with prior art; MOS device preparation method provided by the invention mixes through in the spacer material deposition process, carrying out carbon; The dielectric constant of said spacer material is reduced greatly, influence the effect of raceway groove through the capacitive coupling of side wall, effectively suppress the short-channel effect of the thick gate dielectric layer MOSFET of high K thereby can weaken the fringe field that leaks in the thick gate MOSFET of high K source; Improve the performance of MOS device, this method is simple and convenient.
Description of drawings
The sketch map of the MOS device architecture that Fig. 1 provides for the embodiment of the invention.
Embodiment
MOS device architecture that the present invention is proposed below in conjunction with accompanying drawing and specific embodiment and preparation method thereof is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is; A kind of MOS device architecture is provided; Its side wall is the low-K dielectric layer; Thereby the fringe field that can weaken the leakage of the thick grate MOS device of high K source passes through the effect that the capacitive coupling of side wall influences raceway groove, effectively suppresses the short-channel effect of the thick grid medium MOS device of high K, improves the performance of MOS device; Simultaneously; A kind of MOS device preparation method also is provided, and this method is mixed through in the spacer material deposition process, carrying out carbon, and the dielectric constant of said spacer material is reduced greatly; Thereby can weaken the fringe field that leaks in the thick gate MOSFET of high K source influences raceway groove through the capacitive coupling of side wall effect; The short-channel effect that effectively suppresses the thick gate dielectric layer MOSFET of high K, the performance of raising MOS device, and this method is simple and convenient.
The MOS device architecture that the embodiment of the invention provides, its gate oxide are the thick gate dielectric layer of high K, and its side wall is the low-K dielectric layer.Concrete structure about this device please refer to Fig. 1, the sketch map of the MOS device architecture that Fig. 1 provides for the embodiment of the invention, and as shown in Figure 1, the MOS device architecture that the embodiment of the invention provides comprises:
Source-drain area 104/105 is formed in the said Semiconductor substrate 100 of said grid 102 both sides;
Wherein, said gate oxide 101 is the thick gate dielectric layer of high K, and said side wall 103 is the low-K dielectric layer.
The MOS device architecture that the embodiment of the invention provides; Its side wall is the low-K dielectric layer; Thereby the fringe field that can weaken the leakage of the thick grate MOS device of high K source passes through the effect that the capacitive coupling of side wall influences raceway groove, effectively suppresses the short-channel effect of the thick grid medium MOS device of high K, improves the performance of MOS device.
Further, the material of said side wall 103 is SiO2 or Si3N4 or its combination, and forms said low-K dielectric layer through mixing carbon therein; The relative dielectric constant of said low-K dielectric layer is 1.8～3.5.For instance, when the material of said side wall 103 was SiO2, the relative dielectric constant of the said low-K dielectric layer that forms behind the carbon dope reached below 2.7.
Further, the material of said gate oxide 101 is any or its combination among HfO2, ZrO2, the Al2O3.
In conjunction with Fig. 1, the MOS preparation of devices method that the embodiment of the invention provides comprises the steps:
Two outgrowths and autoregistration etching at said grid 102 form side wall 103;
Carry out the source and leak injection, in said Semiconductor substrate 100, form source-drain area 104/105;
Wherein, said gate oxide 101 is the thick gate dielectric layer of high K, and said side wall 103 is the low-K dielectric layer.
Further, the material of said side wall 103 is SiO2 or Si3N4 or its combination, and forms said low-K dielectric layer through mixing carbon therein; The relative dielectric constant of said low-K dielectric layer is 1.8～3.5.
The MOS device preparation method that the embodiment of the invention provides mixes through in the spacer material deposition process, carrying out carbon; The dielectric constant of said spacer material is reduced greatly; Thereby can weaken the fringe field that leaks in the thick gate MOSFET of high K source influences raceway groove through the capacitive coupling of side wall effect; The short-channel effect that effectively suppresses the thick gate dielectric layer MOSFET of high K, the performance of raising MOS device, and this method is simple and convenient.
Further, the material of said gate oxide 101 is any or its combination among HfO2, ZrO2, the Al2O3.
In sum; The invention provides provides a kind of MOS device architecture; Its side wall is the low-K dielectric layer; Thereby the fringe field that can weaken the leakage of the thick grate MOS device of high K source passes through the effect that the capacitive coupling of side wall influences raceway groove, effectively suppresses the short-channel effect of the thick grid medium MOS device of high K, improves the performance of MOS device; Simultaneously; A kind of MOS device preparation method also is provided, and this method is mixed through in the spacer material deposition process, carrying out carbon, and the dielectric constant of said spacer material is reduced greatly; Thereby can weaken the fringe field that leaks in the thick gate MOSFET of high K source influences raceway groove through the capacitive coupling of side wall effect; The short-channel effect that effectively suppresses the thick gate dielectric layer MOSFET of high K, the performance of raising MOS device, and this method is simple and convenient.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (9)
1. a MOS device architecture is characterized in that, the gate oxide of said MOS device is the thick gate dielectric layer of high K, and its side wall is the low-K dielectric layer.
2. MOS device architecture as claimed in claim 1 is characterized in that, the relative dielectric constant of said low-K dielectric layer is 1.8～3.5.
3. MOS device architecture as claimed in claim 2 is characterized in that, this MOS device architecture specifically comprises:
Semiconductor substrate;
Gate oxide is formed on the said Semiconductor substrate;
Grid is formed on the said gate oxide, and the both sides of said grid are formed with said side wall; And
Source-drain area is formed in the said Semiconductor substrate of said grid both sides.
4. MOS device architecture as claimed in claim 2 is characterized in that, the material of said gate oxide is any or its combination among HfO2, ZrO2, the Al2O3.
5. MOS device architecture as claimed in claim 2 is characterized in that, the material of said side wall is SiO2 or Si3N4 or its combination, and mixes carbon therein.
6. a MOS preparation of devices method is characterized in that, comprises the steps:
Semiconductor substrate is provided;
On said Semiconductor substrate, prepare gate oxide;
On said gate oxide, prepare grid;
Two outgrowths and autoregistration etching at said grid form side wall;
Carry out the source and leak injection, in said Semiconductor substrate, form source-drain area;
Wherein, said gate oxide is the thick gate dielectric layer of high K, and said side wall is the low-K dielectric layer.
7. MOS preparation of devices method as claimed in claim 6 is characterized in that the relative dielectric constant of said low-K dielectric layer is 1.8～3.5.
8. MOS preparation of devices method as claimed in claim 7 is characterized in that, the side wall that said low K is situated between forms through in the spacer material deposition process, mixing carbon impurity.
9. like right 8 described MOS preparation of devices methods, it is characterized in that the material of said gate oxide is any or its combination among HfO2, ZrO2, the Al2O3.
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| CN201110266253A CN102306660A (en) | 2011-09-08 | 2011-09-08 | MOS (metal oxide semiconductor) device structure and manufacturing method thereof |
| US13/339,422 US20130065385A1 (en) | 2011-09-08 | 2011-12-29 | Method for preparing spacer to reduce coupling interference in mosfet |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102543758A (en) * | 2012-02-17 | 2012-07-04 | 上海华力微电子有限公司 | Sidewall preparation method for reducing coupling interference of metal oxide semiconductor field effect transistor (MOSFET) |
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| CN1741274A (en) * | 2004-04-27 | 2006-03-01 | 台湾积体电路制造股份有限公司 | Integrated circuit component and forming method thereof |
| US20090001480A1 (en) * | 2007-06-27 | 2009-01-01 | International Business Machines Corporation | HIGH-k/METAL GATE MOSFET WITH REDUCED PARASITIC CAPACITANCE |
| CN101969061A (en) * | 2010-09-27 | 2011-02-09 | 复旦大学 | Fin-type tunneling transistor integrated circuit and manufacturing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1741274A (en) * | 2004-04-27 | 2006-03-01 | 台湾积体电路制造股份有限公司 | Integrated circuit component and forming method thereof |
| US20090001480A1 (en) * | 2007-06-27 | 2009-01-01 | International Business Machines Corporation | HIGH-k/METAL GATE MOSFET WITH REDUCED PARASITIC CAPACITANCE |
| CN101969061A (en) * | 2010-09-27 | 2011-02-09 | 复旦大学 | Fin-type tunneling transistor integrated circuit and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543758A (en) * | 2012-02-17 | 2012-07-04 | 上海华力微电子有限公司 | Sidewall preparation method for reducing coupling interference of metal oxide semiconductor field effect transistor (MOSFET) |
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Application publication date: 20120104 |