CN101958327B - Monopolar CMOS (Complementary Metal Oxide Semiconductor) device and manufacture method thereof - Google Patents
Monopolar CMOS (Complementary Metal Oxide Semiconductor) device and manufacture method thereof Download PDFInfo
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Abstract
The invention relates to a monopolar CMOS (Complementary Metal Oxide Semiconductor) device and a manufacture method thereof. The monopolar CMOS device comprises a silicon-on-insulator, a first field effect transistor and a second field effect transistor, wherein the silicon-on-insulator comprises a bottom silicon, as well as a buried oxide layer and a top silicon which are arranged on the bottom silicon in sequence; the first field effect transistor and the second field effect transistor are connected in series in the top silicon, doping types in a channel area are all a p type, the doping types of a source electrode and a drain electrode are both an N type, the source electrode and the drain electrode of the second field effect transistor are formed in the top silicon and on the surface of the buried oxide layer, a gap is reserved between the drain electrode and the bottom of a grid electrode, and the second field effect transistor is also provided with back gates which are formed at the bottom of the buried oxide layer and on one side in the bottom silicon corresponding to the channel area. In the monopolar CMOS device, NMOS (N-channel Metal Oxide Semiconductor) transistors are used for replacing the function of a PMOS (P-channel Metal Oxide Semiconductor) transistor, two NMOS transistors are connected in series for complementation, thereby improving the response speed of the device during logical conversion whiling realizing the same logical function.
Description
Technical field
The present invention relates to semiconductor CMOS technology, particularly a kind of one pole cmos device and manufacturing approach thereof.
Background technology
CMOS complementary metal-oxide-semiconductor (CMOS:Complementary Metal OxideSemiconductor) is the basis of modern semiconductors integrated circuit technique, forms the elementary cell of digital integrated circuit.Cmos device is the transistorized a kind of organic assembling of nmos pass transistor and PMOS, constitutes logical device, when its advantage is only logic state transition to be arranged; Just can produce big electric current; And under stable logic state, have only minimum electric current to pass through, therefore can significantly reduce the power consumption of logical circuit.
As shown in Figure 1, be the structure of existing a kind of typical C MOS device (inverter), comprise the nmos pass transistor M1 and the PMOS transistor M2 of series connection, an end ground connection, another termination power Vdd.M2 in nmos pass transistor M1 and the PMOS transistor, grid link to each other as input Vin, and the source is leaked and linked to each other as output end vo ut; Said nmos pass transistor M1 and PMOS transistor M2 have opposite threshold voltage; When input Vin input low level, PMOS transistor M2 conducting, nmos pass transistor M1 ends; Output voltage V out is regarded as exporting high level near Vdd; When input Vin input high level, nmos pass transistor M1 conducting, PMOS transistor M2 ends, and output voltage V out is 0V with approaching, is regarded as output low level.
As everyone knows, at room temperature the carrier mobility of silicon holes is 450cm
2/ Vs, and the carrier mobility of electronics is 1500cm
2/ Vs, for other semi-conducting materials such as GaInAs and InAs, the carrier mobility difference of hole and electronics is an one magnitude.Therefore use the hole always will be far below nmos pass transistor as the speed of carrier mobility in the PMOS transistor of main charge carrier; The PMOS transistor becomes the most important factor that influences the cmos device response speed, and the carrier mobility that how to improve in the cmos device becomes urgent problem.
Summary of the invention
The problem that the present invention solves provides a kind of cmos device, has higher carrier mobility, avoids influencing because the carrier mobility difference of PMOS transistor AND gate nmos pass transistor is excessive the response speed of cmos device.
A kind of one pole cmos device provided by the invention comprises:
Silicon-on-insulator, said silicon-on-insulator comprise bottom silicon, are positioned at oxygen buried layer and top layer silicon on the bottom silicon successively;
Be positioned at first field-effect transistor and second field-effect transistor of top layer silicon series connection, and the doping type of channel region is the P type, the doping type of source electrode and drain electrode is the N type;
The source electrode of said second field-effect transistor and drain electrode are formed in the top layer silicon, oxygen buried layer is surperficial, and wherein drain electrode leaves the gap with gate bottom;
Said second field-effect transistor also has back of the body grid, and said back of the body grid are formed at the oxygen buried layer bottom, bottom silicon is interior and a corresponding side of channel region.
As possibility, the source electrode of the source electrode of first field-effect transistor, drain electrode and second field-effect transistor all is formed with and the corresponding overlapping low-doped injection region NLDD of N type of gate bottom separately; The grid of said second field-effect transistor has double side walls; The drain electrode of said first field-effect transistor is connected with the source electrode of second field-effect transistor.
As preferred version, the source electrode of the drain electrode of said first field-effect transistor and second field-effect transistor is same one deck.
The present invention also provides a kind of manufacturing approach of one pole cmos device, comprising:
Silicon-on-insulator is provided, and said silicon-on-insulator comprises bottom silicon, is positioned at oxygen buried layer and top layer silicon on the bottom silicon successively, and the presumptive area in the said oxygen buried layer bottom, bottom silicon is formed with the back of the body grid that the N type mixes;
In top layer silicon, carry out plasma doping and form P type well region, and the said P type well region degree of depth equals top layer silicon thickness, and cover back of the body grid position;
Surface at P type well region deposits gate dielectric layer and gate electrode successively, and etching formation first grid and second grid, and said second grid is aimed at back of the body grid;
In the first grid both sides and second grid on the P type well region of first grid one side, form the low-doped injection region NLDD of N type;
Side at second grid forms the first side wall;
The side and the first side wall outside at first grid form second sidewall;
Ion injects in the P type well region of first grid both sides and second grid both sides, forms N type injection region, and said N type injection region is as the source electrode or the drain electrode of one pole cmos device.
As preferred version; The said N type injection region that in the P type well region of first grid and second grid both sides, forms; Be specially and adopt the asymmetry ion to inject, ion injection direction and P type well region surface form angle, and in ion implantation process, rotate semiconductor crystal wafer; Said ion injects and formation angular range in P type well region surface is 20 degree～45 degree.
As preferred version, when the P of second grid both sides type well region carries out the ion injection, to inject the degree of depth and be not less than top layer silicon thickness, the N type injection region that makes the second grid both sides form links to each other with oxygen buried layer.
As preferred version, form continuous N type injection region in the P type well region between first grid and second grid.
In the one pole cmos device of the present invention, the channel region doping type of field-effect transistor is the P type, and the doping type of source-drain electrode is the N type, and electronics is equivalent to two nmos pass transistor series connection as main charge carrier.Compare with existing C MOS device, avoided PMOS transistor, and influence the problem of the response speed of cmos device because of the slow carrier mobility of use.
Description of drawings
Through the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purposes, characteristic and advantage of the present invention will be more clear.The parts identical with prior art have used identical Reference numeral in the accompanying drawing.Accompanying drawing and not drawn on scale focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size of layer with the zone.
Fig. 1 is the structural representation of existing a kind of cmos device (inverter);
Fig. 2 is the sectional structure chart of one pole cmos device according to the invention;
Fig. 3 is the logically equivalent circuit of one pole cmos device according to the invention;
Fig. 4 to Figure 13 is the process section of one pole cmos device manufacturing approach according to the invention.
Embodiment
In the existing C MOS device; PMOS transistor and nmos pass transistor are owing to use hole and electronics as main charge carrier respectively; And in semi-conducting material of the same race; The carrier mobility of hole and electronics has big gap, so the slower PMOS transistor of carrier mobility has directly influenced the response speed of cmos device.
The principle of one pole cmos device of the present invention promptly uses nmos pass transistor to replace the transistorized effect of PMOS, with two nmos pass transistor series complementaries, when realizing equal logic function, improves the response speed of device when logical transition.
A kind of one pole cmos device provided by the invention is as shown in Figure 2, comprises basically:
Silicon-on-insulator 10, said silicon-on-insulator comprise bottom silicon 100, are positioned at oxygen buried layer 101 and top layer silicon 102 on the bottom silicon 100 successively;
Be positioned at the first field-effect transistor N1 and the second field-effect transistor N2 of top layer silicon 102 series connection; The source electrode 21 of the source electrode 11 of the said first field-effect transistor N1, the drain electrode 12 and second field-effect transistor N2, drain electrode 22 doping types are the N type; The doping type of the channel region 15 of the said first field-effect transistor N1 and the channel region 25 of the second field-effect transistor N2 is the P type;
The source electrode 21 of the said second field-effect transistor N2 and drain 22 be formed in the top layer silicon 102, the surface of oxygen buried layer 101, wherein drain and 22 leave the gap with grid 23 bottoms;
The said second field-effect transistor N2 also has back of the body grid 24, and said back of the body grid 24 are formed in the bottom, bottom silicon 100 of oxygen buried layer 101 the corresponding side with channel region 25.
As possibility, the source electrode 21 of the source electrode 11 of the first field-effect transistor N1, the drain electrode 12 and second field-effect transistor N2 all is formed with and corresponding grid 13 or the overlapping low-doped injection region of N type (NLDD) 14, grid 23 bottoms; The grid 23 of the said second field-effect transistor N2 has double side walls; The drain electrode 12 of the said first field-effect transistor N1 is connected with the source electrode 21 of the second field-effect transistor N2, and drain electrode 12 is electrically connected through interconnection line with source electrode 21 in Fig. 2.
As preferred version, the drain electrode 12 of the said first field-effect transistor N1 and the source electrode 21 of second field-effect transistor can also be same one deck.
Do introduction in the face of the operation principle of one pole cmos device of the present invention down.
The threshold voltage of supposing the said first field-effect transistor N1 is V
T1The threshold voltage of the second field-effect transistor N2 is V
T2, because the first field-effect transistor N1 and the second field-effect transistor N1 are nmos pass transistor, so V
T1And V
T2For just.
The grid 13 of the first field-effect transistor N1 and the grid 23 of the second field-effect transistor N2 are connected, as the input Vin of one pole cmos device; The drain electrode 12 of the first field-effect transistor N1 and the source electrode 21 of the second field-effect transistor N2 are connected, as the output end vo ut of one pole cmos device; With source electrode 11 ground connection of the first field-effect transistor N1, the drain electrode 22 of the second field-effect transistor N2 meets forward power supply Vdd, and back of the body grid 24 meet forward fixed voltage V
T2
Because among the second field-effect transistor N2; Drain electrode 22 leaves the gap with grid 23 bottoms; Therefore on grid 23, add under the normal condition positive bias-voltage can not be directly at source electrode 21 and drain between 22, the raceway groove that conducts electricity is formed on grid 23 bottoms; Positive bias-voltage on the grid 23 can only make channel region 25 tops that transoid takes place, and assembles negative electrical charge (electronics).
In addition source electrode 21 and drain 22 be formed in the top layer silicon 102, the surface of oxygen buried layer 101; Be that source electrode 21, drain electrode 22 and channel region between the two 25 all contact with oxygen buried layer 101; And back of the body grid 24 are corresponding with channel region 25, and oxygen buried layer 101 is equivalent to play the effect of gate dielectric layer.Only need on back of the body grid 24, add enough positive bias-voltages, make the bottom of channel region 25, at source electrode 21 and drain and to form conducting channel between 22, thereby open the second field-effect transistor N2 near oxygen buried layer 101 place's transoids.So the second field-effect transistor N2 should equivalence be an inverted nmos pass transistor, back of the body grid 24 are control gate, and the top of channel region 25 is equivalent to substrate.
The equivalent circuit diagram of one pole cmos device of the present invention is as shown in Figure 3.
In conjunction with Fig. 2 and shown in Figure 3, when input Vin inserts high level (logic input 1), promptly make Vin＞V
T1＞0 o'clock; At first the first field-effect transistor N1 opens; Electronics flows to drain electrode 12 from the source electrode 11 of the first field-effect transistor N1, and simultaneously, the source electrode 21 of the second field-effect transistor N2 that is connected with the drain electrode 12 of the first field-effect transistor N1 will be assembled electronics; And, influence the electromotive force position at channel region 25 tops through the shallow doping of N type injection region 14; And also imported high level among the second field-effect transistor N2 on the grid 23, and making the top transoid of channel region 25, electronics is also assembled at channel region 25 tops; Under effect aspect above-mentioned two, the electromotive force position at channel region 25 tops is dragged down is tending towards negative value, and according to the principle of substrate bias effect, the threshold voltage of the said second field-effect transistor N2 will improve, and the voltage of back of the body grid 24 is former threshold voltage V
T2, the second field-effect transistor N2 is closed.Output end vo ut output low level (logic output 0);
When input Vin inserts low level (logic input 0); Make Vin＜0 o'clock; At first the first field-effect transistor N1 closes, and grid 23 is a low level among the second field-effect transistor N2, and the electronics of channel region 25 tops and near gathering thereof disappears; The electromotive force bit recovery makes substrate bias effect eliminate, and threshold voltage also is reset to V
T2, the second field-effect transistor N2 is unlocked.Output end vo ut output high level Vdd (logic output 1).
Can know that from said process one pole cmos device of the present invention can be realized the logic function of existing C MOS inverter equally; And through using two nmos pass transistors, be main charge carrier with electronics, improved response speed greatly.
Based on the structure of above-mentioned one pole cmos device, the present invention also provides a kind of manufacturing approach of one pole cmos device, and basic step comprises:
S1, silicon-on-insulator is provided, said silicon-on-insulator comprises bottom silicon, is positioned at oxygen buried layer and top layer silicon on the bottom silicon successively, and the presumptive area in the said oxygen buried layer bottom, bottom silicon is formed with the back of the body grid that the N type mixes;
S2, in top layer silicon, carry out plasma doping and form P type well region, and the said P type well region degree of depth equals top layer silicon thickness, and cover back of the body grid position;
S3, deposit gate dielectric layer and gate electrode successively, and etching forms first grid and second grid on the surface of P type well region, said second grid with carry on the back grid and aim at;
S4, in the first grid both sides and second grid in the P type well region of first grid one side, form the low-doped injection region NLDD of N type;
S5, form the first side wall in the side of second grid; Form second sidewall in the side and the first side wall outside of first grid then;
S6, ion injection in the P type well region of first grid both sides and second grid both sides form N type injection region, and said N type injection region is as the source electrode or the drain electrode of one pole cmos device; Specifically can inject for adopting the asymmetry ion, ion injection direction and P type well region surface form angle, and in ion implantation process, rotate semiconductor crystal wafer.
To process section shown in Figure 13, the specific embodiment of the manufacturing process of one pole cmos device according to the invention is done further introduction below in conjunction with Fig. 4.
As shown in Figure 4, form bottom silicon 100, in the presumptive area of bottom silicon 100, be formed with the back of the body grid 24 that the N type mixes.
As shown in Figure 5, on bottom silicon 100, form oxygen buried layer 101 and top layer silicon 102 successively, said bottom silicon 100, oxygen buried layer 101 and top layer silicon 102 form silicon-on-insulators 10.
The material of said bottom silicon 100 and top layer silicon 102 can be monocrystalline silicon or polysilicon, and the material of said oxygen buried layer 101 can be silica, and above-mentioned three layers can form through chemical vapour deposition (CVD) CVD.
As shown in Figure 6; In the presumptive area of top layer silicon 102, form P type well region 201, said P type well region 201 can inject through ion and form the energy that the control ion injects; Make the degree of depth of P type well region 201 equal the thickness of top layer silicon 102, and cover back of the body grid 24 positions.
As shown in Figure 7; Form gate dielectric layer 202 and gate electrode 203 successively on the surface of P type well region 201; Said gate dielectric layer 202 materials can be silica, and said gate electrode 203 materials can be polysilicon, above-mentioned two-layer can formation through chemical vapour deposition (CVD) CVD.
As shown in Figure 8, use said gate dielectric layer 202 of mask etching and gate electrode 203, form first grid 13 and second grid 23 in presumptive area, wherein second grid 23 is aimed at the back of the body grid 24 of oxygen buried layer 101 bottoms.
As shown in Figure 9, use mask to shelter from second grid 23 and two side areas thereof, on the both sides of the first grid 13 P type well region 201 and second grid 23 on a side P type well region 201 of first grid 13, form N type light dope injection region (NLDD) 204; In the present embodiment, the N type light dope injection region on the P type well region 201 can link to each other between said first grid 13 and the second grid 23; Said N type light dope injection region 204 can be injected through reverse ion and form, the degree of depth and concentration that energy that said reverse ion injects and dosage have determined N type light dope injection region 204, and concrete technological parameter is set as required.
Shown in figure 10, form wall 205 on the surface of first grid 13, second grid 23 and P type well region 201, said wall 205 can be silicon nitride or silica, can form through chemical vapour deposition (CVD).Etch away the wall 205 on first grid 13 and both sides P type well region 201 surfaces thereof then, keep the part of second grid 23 and both sides thereof.
Shown in figure 11; Both sides at second grid 23 form the first side wall 206; Said the first side wall 206 can form through wall 205 being carried out the RIE plasma etching, and in RIE plasma etching process, need not influenced by etching with mask protection first grid 13 and both sides P type well region 201 thereof.
Shown in figure 12, in the both sides of first grid 13, the outside of the first side wall 206 forms second sidewall 207.Said second sidewall 207 can be silicon nitride or silica, and the formation method can be similar with the first side wall 206.Make said second grid 23 be formed with two-layer sidewall.
Shown in figure 13, ion injects in the P type well region 201 of first grid 13 both sides and second grid 23 both sides, forms N type injection region 210, N type injection region 208 and N type injection region 209, as the source electrode or the drain electrode of one pole cmos device.
Wherein the N type injection region of first grid 13 and both sides thereof has constituted first field-effect transistor; The N type injection region of second grid 23 and both sides thereof has constituted second field-effect transistor; Wherein N type injection region 210 is as the source electrode of first field-effect transistor; N type injection region 209 drain electrodes as second field-effect transistor, and N type injection region 208 is the drain electrode of first field-effect transistor are also as the source electrode of second field-effect transistor.
Because the sidewall of second grid 23 has two-layer sidewall than first grid 13 thicker, and drain electrode one side of second grid 23 bottoms do not form the shallow doping of N type injection region NLDD, so there are the gap in the bottom of second grid 23 and drain electrode.
In addition, between N type injection region 210 and the N type injection region 208 and the P type well region between N type injection region 208 and the N type injection region 209 become the channel region of first field-effect transistor and second field-effect transistor respectively.
In the present embodiment, said ion injects the formation source electrode, drain electrode can adopt the asymmetry ion to inject, and ion injection direction and P type well region surface form angle, and in ion implantation process, rotate semiconductor crystal wafer; Said ion injects and formation angular range in P type well region surface is 20 degree～45 degree.And when the P type well region 201 in second grid 23 both sides carries out the ion injection; Inject the degree of depth and be not less than top layer silicon 102 thickness; The N type injection region 209 and the N type injection region 208 that make the formation of second grid 23 both sides, i.e. the source of second field-effect transistor, drain electrode links to each other with oxygen buried layer 101.
Remove above-mentioned through the primary ions injection; Outside the source of formation one pole cmos device, the method for drain electrode; Can also use mask to adopt different ion injection parameters; Substep forms source electrode, drain electrode on the P type well region 201 of first grid 13 and second grid 23 both sides, the drain region with first field-effect transistor is connected with the source region of second field-effect transistor then.Be merely optional embodiment here, those skilled in the art should know concrete processing step easily by inference, repeat no more here.
After accomplishing above-mentioned technology, the surface that also is included in the one pole cmos device forms insulation and isolates, and leads to the step of the interconnection line in source region.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (8)
1. an one pole cmos device is characterized in that, comprising:
Silicon-on-insulator, said silicon-on-insulator comprise bottom silicon, are positioned at oxygen buried layer and top layer silicon on the bottom silicon successively;
Be positioned at first field-effect transistor and second field-effect transistor of top layer silicon series connection, and the doping type of channel region is the P type, the doping type of source electrode and drain electrode is the N type; The drain electrode of said first field-effect transistor is connected with the source electrode of second field-effect transistor, and the source electrode of the drain electrode of said first field-effect transistor and second field-effect transistor is same one deck;
The source electrode of said second field-effect transistor and drain electrode are formed in the top layer silicon, oxygen buried layer is surperficial, and wherein drain electrode leaves the gap with gate bottom;
Said second field-effect transistor also has back of the body grid, and said back of the body grid are formed at the oxygen buried layer bottom, bottom silicon is interior and a corresponding side of channel region.
2. one pole cmos device as claimed in claim 1 is characterized in that, the source electrode of said first field-effect transistor, drain electrode are formed with the N type low-doped injection region overlapping with gate bottom; The source electrode of said second field-effect transistor is formed with the N type low-doped injection region overlapping with gate bottom.
3. one pole cmos device as claimed in claim 1 is characterized in that the grid of said second field-effect transistor has double side walls.
4. the manufacturing approach of an one pole cmos device is characterized in that, comprising:
Silicon-on-insulator is provided, and said silicon-on-insulator comprises bottom silicon, is positioned at oxygen buried layer and top layer silicon on the bottom silicon successively, and the presumptive area in the said oxygen buried layer bottom, bottom silicon is formed with the back of the body grid that the N type mixes;
In top layer silicon, carry out plasma doping and form P type well region, and the said P type well region degree of depth equals top layer silicon thickness, and cover back of the body grid position;
Surface at P type well region deposits gate dielectric layer and gate electrode successively, and etching formation first grid and second grid, and said second grid is aimed at back of the body grid;
In the first grid both sides and second grid on the P type well region of first grid one side, form the low-doped injection region of N type;
Side at second grid forms the first side wall;
The side and the first side wall outside at first grid form second sidewall;
Ion injects in the P type well region of first grid both sides and second grid both sides, forms N type injection region.
5. the manufacturing approach of one pole cmos device as claimed in claim 4; It is characterized in that; The said N type injection region that in the P type well region of first grid and second grid both sides, forms; Be specially and adopt the asymmetry ion to inject, ion injection direction and P type well region surface form angle, and in ion implantation process, rotate semiconductor crystal wafer.
6. the manufacturing approach of one pole cmos device as claimed in claim 5 is characterized in that, said ion injects and formation angular range in P type well region surface is 20 degree～45 degree.
7. the manufacturing approach of one pole cmos device as claimed in claim 4; It is characterized in that; When the P of second grid both sides type well region carries out the ion injection, to inject the degree of depth and be not less than top layer silicon thickness, the N type injection region that makes the second grid both sides form links to each other with oxygen buried layer.
8. the manufacturing approach of one pole cmos device as claimed in claim 7 is characterized in that, forms continuous N type injection region in the P type well region between first grid and second grid.
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| CN103050526B (en) * | 2011-10-12 | 2015-07-15 | 中国科学院微电子研究所 | MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and manufacturing method thereof |
| CN103985749B (en) | 2013-02-08 | 2016-12-28 | 中国科学院微电子研究所 | Quasiconductor is arranged and manufacture method |
| US20230178624A1 (en) * | 2021-12-07 | 2023-06-08 | International Business Machines Corporation | Unipolar-fet implementation in stacked-fet cmos |
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