CN102544106B - Introduce the LDMOS device of local stress - Google Patents
Introduce the LDMOS device of local stress Download PDFInfo
- Publication number
- CN102544106B CN102544106B CN201210038047.8A CN201210038047A CN102544106B CN 102544106 B CN102544106 B CN 102544106B CN 201210038047 A CN201210038047 A CN 201210038047A CN 102544106 B CN102544106 B CN 102544106B
- Authority
- CN
- China
- Prior art keywords
- stress
- region
- ldmos device
- film
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to LDMOS device.The invention discloses one utilizes stress to improve device performance, and reduces its dysgenic LDMOS device introducing local stress.Technical scheme of the present invention is, introduce the LDMOS device of local stress, comprise body substrate, substrate is formed the well region and drift region that adjoin each other, in well region and drift region, forms source region and drain region respectively, the well region superficial growth gate oxide between source region and drift region, growing polycrystalline silicon grid on gate oxide, at source region and/or gate surface cover film, utilize the intrinsic stress that described film has, in the raceway groove of LDMOS device, introduce stress.The present invention can not affect the band gap E of device drift region substantially
g, and the source and drain conducting resistance R to device
onreduction but have obvious effect.The present invention has given full play to the positive role of stress to device performance, reduces the negative influence of stress to device performance, is particularly suitable for manufacturing power device.
Description
Technical field
The present invention relates to semiconductor device, particularly a kind of lateral double diffusion metal oxide semiconductor (LDMOS) device.
Background technology
LDMOS device is a kind of semiconductor device got up based on SOI (SemiconductorOnInsulator) technology and MOSFET (MetalOxideSemiconductorFieldEffectTransistor) technical development, and LDMOS device is usually used as power device.A desirable power device, should have following desirable static and dynamic c haracteristics: can bear high voltage when cut-off state; When conducting state, there is big current and very low pressure drop; When switch transition, there is the short open and close time, the Rapid Variable Design of electric current and voltage can be born, and there is full control function etc.The electrode of LDMOS device is positioned at chip surface, connects that to realize with low-voltage signal circuit and other device mutually integrated easily through inside.Due to the existence of these advantages, LDMOS device obtains very fast development.
Compared with common MOSFET (mos field effect transistor), traditional LDMOS device adds a longer low concentration drift region between raceway groove and drain electrode.The existence of this drift region improves puncture voltage, and reduces the parasitic capacitance Lou, between the two poles of the earth, source, is conducive to improving frequency characteristic.Wherein the length of drift region and concentration affect LDMOS puncture voltage and source and drain conducting resistance R
ontwo key factors, drift region length is longer, and concentration is less, and puncture voltage is higher, and source and drain conducting resistance R
onlarger, this driving force for raising device is disadvantageous.Thus, while improving puncture voltage, less source and drain conducting resistance R is obtained
onit is the target of those skilled in the art's unremitting pursue.
In modern semiconductor technology, improve the mobility of charge carrier by introducing stress in MOS transistor raceway groove, the source and drain conducting resistance reducing device is a measure effectively.As to P type insulated-gate type field effect transistor (PMOSFET), introduce the mobility that compression can improve hole in channels.To N-type insulated-gate type field effect transistor (NMOSFET), introduce the mobility that tensile stress can improve electronics in channels.Same, for LDMOS device, in P type LDMOS raceway groove, introduce the mobility that compression can improve hole; In N-type LDMOS raceway groove, introduce the mobility that tensile stress can improve electronics, thus reduce the source and drain conducting resistance of LDMOS device.But make the band gap E of material after introducing stress
greduce, the formula for abrupt junction and gradual junction breakdown voltage VB is respectively
Obviously, after introducing stress, due to band gap E
greduce, the puncture voltage of device also can reduce.For LDMOS device, puncture voltage mainly affects by drift region, while thus needing to introduce effective stress in channels, avoids introducing stress in drift region as far as possible, thus reaches while guarantee puncture voltage is almost constant, reduce the source and drain conducting resistance R of device
onobject.
Summary of the invention
Technical problem to be solved by this invention, is just to provide one and utilizes stress to improve device performance, and reduce its dysgenic LDMOS device introducing local stress.
The present invention solve the technical problem, the technical scheme adopted is, introduce the LDMOS device of local stress, comprise body substrate, substrate is formed the well region and drift region that adjoin each other, source region and drain region is formed respectively in well region and drift region, well region superficial growth gate oxide between source region and drift region, growing polycrystalline silicon grid on gate oxide, it is characterized in that, at source region and/or gate surface cover film, utilize the intrinsic stress that described film has, in the raceway groove of LDMOS device, introduce stress.
LDMOS device of the present invention, only at the source region of device and/or gate surface cover film, utilizes the intrinsic stress that film has, introduces effective stress in channels.Because drift region and surface, drain region do not have cover film, the film that source region and/or gate surface cover, introduces stress hardly or only introduces very little stress, thus weaken or avoid because stress is to band gap E in distant drift region
gimpact and reduce the puncture voltage of device.
Concrete, described substrate is P or n type material; Corresponding well region is P or n type material, and drift region is N or P-type material, and source region is N or P-type material, and polysilicon is N or P-type material.
Technical scheme of the present invention, goes for P-type material substrate or n type material backing material.According to the manufacturing process of LDMOS device, various substrates material type (P type or N-type), corresponding well region, drift region, source region and polygate electrodes material thereof also have different conduction types.
Preferably, described film is silicon nitride film.
Adopt silicon nitride film as the film covering source region and/or grid, its generating process and silicon-based semiconductor material processing compatibility high, the film of generation has suitable intrinsic stress.
Further, the generating process of described film is first at source region and/or gate surface growth layer of silicon dioxide film, then on silica membrane grown silicon nitride film; Or not silicon dioxide thin film growth, direct growth silicon nitride film.
For silicon-based semiconductor material, silicon nitride film of the present invention can adopt two kinds of generating process, and a kind of technique first grows layer of silicon dioxide film, then on silica membrane grown silicon nitride film.Another kind of technique is not silicon dioxide thin film growth, long silicon nitride film of directly delivering a child in source region and/or gate surface.Silica membrane mainly plays stress buffer effect, so be also called buffer film (be different from stress film---silicon nitride), can regulate the stress that silicon nitride film applies.Because gate surface distance raceway groove is comparatively far away, the Stress transmit that gate surface silicon nitride applies is more weak to raceway groove, there is no need to adopt buffer film again, only adopts silica membrane to add the technique of silicon nitride film in source region so general.
Concrete, the thickness of described silicon dioxide film is 5 ~ 100nm.
More specifically, low-pressure chemical vapor deposition method or plasma enhanced chemical vapor deposition method grown silicon nitride film is adopted.
Adopt above-mentioned two kinds of different process, adjusting process parameter change stress intensity and kind can be passed through as required, meet the device needs of different conduction-types.
Further, the range of stress adopting the silicon nitride film of low-pressure chemical vapor deposition method growth is 0.1 ~ 10GPa, and the range of stress that using plasma strengthens the silicon nitride film of chemical vapor deposition method growth is-8 ~+8GPa.
The above-mentioned range of stress easily reaches, and technique is also uncomplicated, and device performance promotes also obvious.
Concrete, described silicon nitride film thickness is 20nm ~ 2 μm.
The thicker stress of usual silicon nitride film is larger, and the silicon nitride film thickness of 20nm ~ 2 μm, can meet most devices requirement, technique also easily realizes, can not produce destruction again.
The invention has the beneficial effects as follows, local stress is introduced can significantly improve LDMOS device performance, reduces source and drain conducting resistance R
on, improve device drive ability, and effectively can reduce stress to drift region band gap E
gharmful effect, guarantee the high voltage endurance of device, technical scheme of the present invention is suitable for manufacturing power LDMOS device very much.
Accompanying drawing explanation
Fig. 1 is the device architecture schematic diagram of embodiment 1;
Fig. 2 is the another kind of device architecture schematic diagram of embodiment 1;
Fig. 3 is the device architecture schematic diagram of embodiment 2;
Fig. 4 is the device architecture schematic diagram of embodiment 3;
Fig. 5 is channel region stress simulation schematic diagram;
Fig. 6 is stresses of parts simulation result schematic diagram.
10---substrate; 12---well region; 14---drift region; 16---source region; 17---drain region; 18---gate oxide; 20---polysilicon gate; 22---silicon nitride film; 24 silicon oxide layers.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail.
In the following examples, substrate 10 material type is P type, and corresponding well region 12 is P-type material, and drift region 14 is n type material, and source region 16 is n type material, and polysilicon 20 is n type material, and introducing stress is tensile stress.For n type material substrate, except respective regions material type, introduce stress types different except, device architecture is identical.
Embodiment 1
This routine LDMOS device cross-section structure as shown in Figure 1.Comprise body substrate 10, form the well region 12 and drift region 14 that adjoin each other over the substrate 10, source region 16 and drain region 17 is formed respectively, the well region 12 superficial growth gate oxide 18 between source region 16 and drift region 14, growing polycrystalline silicon grid 20 on gate oxide 18 in well region 12 and drift region 14.This routine device is only at source region 16 surface coverage silicon nitride (Si
3n
4) film 22, utilize the intrinsic stress that silicon nitride film 22 has, in the raceway groove of LDMOS device, introduce stress.Because silicon nitride film 22 is only present in surface, source region 16, it introduces stress only to neighbouring raceway groove generation effect, substantially can not have influence on drift region 14 far away.This example cmos device manufacturing process traditionally completes device body making, comprises the preparation of substrate 10, the formation of well region 12, growth gate oxide 18, growing polycrystalline silicon grid 20, channel ion injection, drift region 14 ion implantation, source region 16 and drain region 17 ion implantation etc.Then chemical vapor deposition (CVD) technique is adopted, as LPCVD (low pressure chemical vapor deposition) method or PECVD (plasma reinforced chemical vapor deposition) method, in source region 16, surface deposition thickness is 120nm, has the silicon nitride film 22 of 2GPa tensile stress.Next the making of whole device is completed by conventional process such as local interlinkages.This routine stresses of parts distribution is as shown in curve A in accompanying drawing 5, and be about 232.6MPa the channel region mean stress of 1 ~ 1.5 μm, very little at the drift region stress of 1.5 ~ 5 μm, mean stress is about 43.09Mpa.This routine LDMOS device, silicon nitride film 22 also can cover polysilicon gate 20 surface, and as shown in Figure 2, shown in its effect produced and Fig. 1, device is suitable, when the cushioning effect due to polysilicon gate 20 and gate oxide 18, the stress that raceway groove introduced by silicon nitride film 22 is relatively low.
Embodiment 2
Fig. 3 is the LDMOS device structural representation in source region 16 and grid 20 surface coverage silicon nitride film 22.This routine device fabrication is identical with embodiment 1, also be the making that cmos device manufacturing process traditionally completes device main body, comprise the preparation of substrate 10, the formation of well region 12, growth gate oxide 18, growing polycrystalline silicon grid 20, channel ion injection, drift region 14 ion implantation, source region 16 and drain region 17 ion implantation, then adopting chemical vapor deposition process, is the silicon nitride film (22) that 120nm has 2GPa tensile stress in source region 16 and grid 20 surface deposition thickness.Next the making of whole device is completed by conventional process such as local interlinkages.The stresses of parts distribution of this example is as shown in curve B in Fig. 5, and the mean stress of channel region (1 ~ 1.5 μm) is about 230MPa, and very little at drift region (1.5 ~ 5 μm) stress, mean stress is about 45.94MPa.
Embodiment 3
Fig. 4 is this routine device cross-section schematic diagram.This routine device source region 16 and grid 20 surface coverage have silicon nitride film 22, and have layer of silicon dioxide (SiO between source region 16 and silicon nitride film 22
2) film 24.The Main Function of silica membrane 24, is introduce stress to the silicon nitride covering its surface to cushion, makes channel region (1 ~ 1.5 μm) stress distribution more even.This routine device main body manufacturing process is see the description of above-described embodiment, the manufacturing process of this routine silicon nitride film 22 is first thick at source region 16 superficial growth one deck 20nm silica membranes (24), then chemical vapor deposition (CVD) technique is adopted, be 120nm at silica membrane (24) surface deposition thickness, there is the silicon nitride film (22) of 2GPa tensile stress.Next the making of whole device is completed by traditional processing steps such as local interlinkages.This routine stresses of parts distribution is as shown in curve C in accompanying drawing 5, and the mean stress of channel region (1 ~ 1.5 μm) is about 187.17MPa, and very little at drift region (1.5 ~ 5 μm) stress, mean stress is about 43.99MPa.
The LDMOS device introducing local stress of the present invention, the stress film due to local complexity, the mean stress of device channel region (1 ~ 1.5 μm) mean stress comparatively device drift region (1.5 ~ 5 μm) adds Δ P (stresses of parts simulation result as shown in Figure 6).The increase of this stress can not affect the band gap E of device drift region (1.5 ~ 5 μm) substantially
g, and the source and drain conducting resistance R to device
onreduction but have obvious effect.Technical scheme of the present invention, has given full play to the positive role of stress to device performance, reduces the negative influence of stress to device performance.
Claims (8)
1. introduce the LDMOS device of local stress, comprise body substrate, substrate is formed the well region and drift region that adjoin each other, source region and drain region is formed respectively, the well region superficial growth gate oxide between source region and drift region, growing polycrystalline silicon grid on gate oxide in well region and drift region, it is characterized in that, at area surface cover film, utilize the intrinsic stress that described film has, in the raceway groove of LDMOS device, introduce stress.
2. the LDMOS device introducing local stress according to claim 1, is characterized in that, described substrate is P or n type material; Corresponding well region is P or n type material, and drift region is N or P-type material, and source region is N or P-type material, and polysilicon is N or P-type material.
3. the LDMOS device introducing local stress according to claim 1, is characterized in that, described film is silicon nitride film.
4. the LDMOS device introducing local stress according to claim 1, is characterized in that, the generating process of described film is first at area surface growth layer of silicon dioxide film, then on silica membrane grown silicon nitride film; Or not silicon dioxide thin film growth, direct growth silicon nitride film.
5. according to the LDMOS device introducing local stress described in claim 4, it is characterized in that, the thickness of described silicon dioxide film is 5 ~ 100nm.
6. the LDMOS device introducing local stress according to claim 3 ~ 5 any one, is characterized in that, adopts low-pressure chemical vapor deposition method or plasma enhanced chemical vapor deposition method grown silicon nitride film.
7. the LDMOS device introducing local stress according to claim 6, it is characterized in that, the range of stress adopting the silicon nitride film of low-pressure chemical vapor deposition method growth is 0.1 ~ 10GPa, and the range of stress that using plasma strengthens the silicon nitride film of chemical vapor deposition method growth is-8 ~+8GPa.
8. the LDMOS device introducing local stress according to claim 6, is characterized in that, described silicon nitride film thickness is 20nm ~ 2 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210038047.8A CN102544106B (en) | 2012-02-20 | 2012-02-20 | Introduce the LDMOS device of local stress |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210038047.8A CN102544106B (en) | 2012-02-20 | 2012-02-20 | Introduce the LDMOS device of local stress |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102544106A CN102544106A (en) | 2012-07-04 |
| CN102544106B true CN102544106B (en) | 2016-01-27 |
Family
ID=46350561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210038047.8A Active CN102544106B (en) | 2012-02-20 | 2012-02-20 | Introduce the LDMOS device of local stress |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102544106B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104269436B (en) * | 2014-08-28 | 2017-12-01 | 电子科技大学 | Using the strain LDMOS device of the eigenstrain film of two kinds of property |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574395A (en) * | 2003-06-12 | 2005-02-02 | 英特尔公司 | Gate-induced strain for mos performance improvement |
| CN101111942A (en) * | 2004-12-15 | 2008-01-23 | 德州仪器公司 | Drain extended pmos transistors and methods for making the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003086708A (en) * | 2000-12-08 | 2003-03-20 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
| US7335544B2 (en) * | 2004-12-15 | 2008-02-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making MOSFET device with localized stressor |
| US7585735B2 (en) * | 2005-02-01 | 2009-09-08 | Freescale Semiconductor, Inc. | Asymmetric spacers and asymmetric source/drain extension layers |
-
2012
- 2012-02-20 CN CN201210038047.8A patent/CN102544106B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574395A (en) * | 2003-06-12 | 2005-02-02 | 英特尔公司 | Gate-induced strain for mos performance improvement |
| CN101111942A (en) * | 2004-12-15 | 2008-01-23 | 德州仪器公司 | Drain extended pmos transistors and methods for making the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102544106A (en) | 2012-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100578790C (en) | Bcd semiconductor device and manufacturing method thereof | |
| CN104992942B (en) | Stacked vertical strain Si/SiGe Heterojunction CMOS devices structures and preparation method thereof | |
| CN102130012B (en) | LDD, LDS and buffer layer integrated manufacturing method for SOI super-junction LDMOS device | |
| CN104201175B (en) | Thin film transistor based phase inverter | |
| CN104064475A (en) | High Mobility Power Metal-oxide Semiconductor Field-effect Transistors | |
| JP2015523723A (en) | High voltage junction field effect transistor | |
| WO2018041208A1 (en) | Device integrating a junction field effect transistor and manufacturing method therefor | |
| US7859051B2 (en) | Semiconductor device with a reduced band gap and process | |
| CN102446966B (en) | IGBT ((Insulated Gate Bipolar Transistor) structure of integrated anti-parallel diode and manufacturing method thereof | |
| CN103872054B (en) | A kind of integrated device and manufacture method, discrete device, CDMOS | |
| CN102208448B (en) | Polycrystalline Si1-xGex/metal parallel covering double-gate strained SiGe-on-insulator (SSGOI) n metal oxide semiconductor field effect transistor (MOSFET) device structure | |
| CN102130176B (en) | SOI (silicon-on-insulator) super-junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with buffer layer | |
| CN102544106B (en) | Introduce the LDMOS device of local stress | |
| CN106298943B (en) | A kind of lateral double diffusion metal oxide semiconductor field-effect tube with bulk electric field modulation | |
| CN101834202A (en) | N-type lateral insulated gate bipolar device capable of reducing hot carrier effect | |
| CN102891088A (en) | Method for manufacturing vertical double diffusion metal oxide semiconductor field effect transistor device | |
| CN103681859A (en) | A silicon carbide semiconductor device and a manufacturing method thereof | |
| CN101447432A (en) | Manufacturing method of double diffusion field effect transistor | |
| CN101958327B (en) | Monopolar CMOS (Complementary Metal Oxide Semiconductor) device and manufacture method thereof | |
| CN103367431A (en) | Ldmos transistor and manufacturing method thereof | |
| CN102130013B (en) | Method for manufacturing SOI (silicon on insulator) super junction LDMOS (lateral double-diffused metal oxide semiconductor) device with buffer layer | |
| CN101819993A (en) | P type lateral insulated gate bipolar device for reducing hot carrier effect | |
| CN105047702B (en) | A kind of manufacturing method of LDMOS device | |
| CN103872111A (en) | IGBT and manufacturing method thereof | |
| CN105244279B (en) | A kind of plane VDMOS device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |