CN102544106B - Introduce the LDMOS device of local stress - Google Patents

Abstract

The present invention relates to LDMOS devices. The invention discloses an LDMOS device which introduces local stress to improve device performance by using stress and reduce its bad influence. The technical scheme of the present invention is that the LDMOS device that introduces local stress includes a bulk substrate, and a well region and a drift region adjacent to each other are formed on the substrate, and a source region and a drain region are respectively formed in the well region and the drift region. A gate oxide layer is grown on the surface of the well region between the source region and the drift region, a polysilicon gate is grown on the gate oxide layer, and a thin film is covered on the surface of the source region and/or gate, and the intrinsic stress of the thin film is used to form a LDMOS Stress is induced in the channel of the device. The invention basically does not affect the band gap EG of the device drift region, but has a relatively obvious effect on reducing the source-drain on-resistance _{R on} of the device. The invention fully exerts the positive effect of stress on device performance, reduces the negative influence of stress on device performance, and is especially suitable for manufacturing power devices.

Description

LDMOS Devices Introduced Local Stress

technical field

The invention relates to a semiconductor device, in particular to a lateral double-diffused metal oxide semiconductor (LDMOS) device.

Background technique

The LDMOS device is a semiconductor device developed based on SOI (SemiconductorOnInsulator) technology and MOSFET (MetalOxideSemiconductorFieldEffectTransistor) technology, and the LDMOS device is usually used as a power device. An ideal power device should have the following ideal static and dynamic characteristics: it can withstand high voltage in the off state; it has a large current and a very low voltage drop in the on state; , off time, can withstand rapid changes in current and voltage, and has a full control function. The electrodes of the LDMOS device are located on the surface of the chip, and it is easy to realize mutual integration with low-voltage signal circuits and other devices through internal connections. Due to the existence of these advantages, LDMOS devices have been developed rapidly.

Compared with ordinary MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), traditional LDMOS devices add a longer low-concentration drift region between the channel and the drain. The existence of the drift region increases the breakdown voltage and reduces the parasitic capacitance between the drain and the source, which is beneficial to improve the frequency characteristic. The length and concentration of the drift region are two important factors affecting the LDMOS breakdown voltage and the source-drain on-resistance R _on . The bigger _on is, this is unfavorable for improving the driving capability of the device. Therefore, obtaining a smaller source-drain on-resistance R _on while increasing the breakdown voltage is an unremitting goal pursued by those skilled in the art.

In modern semiconductor technology, it is an effective measure to increase the carrier mobility and reduce the source-drain on-resistance of the device by introducing stress into the channel of the MOS transistor. For example, for a P-type insulated gate field effect transistor (PMOSFET), introducing compressive stress in the channel can improve the mobility of holes. For N-type insulated gate field effect transistors (NMOSFETs), the introduction of tensile stress in the channel can improve the mobility of electrons. Similarly, for LDMOS devices, the introduction of compressive stress in the P-type LDMOS channel can increase the mobility of holes; the introduction of tensile stress in the N-type LDMOS channel can increase the mobility of electrons, thereby reducing the source-drain on-resistance of LDMOS devices . However, after the stress is introduced, the band gap _EG of the material decreases, and the formulas for the breakdown voltage VB of the abrupt junction and the slowly varying junction are respectively $V_B\≈5.2\×{10}^{13}{\mathrm{E.}}_G^{\frac{3}{2}}{N}_0^{-\frac{3}{4}},V_B\≈{10}^{10}{\mathrm{E.}}_G^{\frac{6}{5}}{a}^{-\frac{2}{5}}.$ Obviously, after the stress is introduced, the breakdown voltage of the device will also decrease due to the reduction of the band gap _EG . For LDMOS devices, the breakdown voltage is mainly affected by the drift region, so it is necessary to introduce effective stress in the channel while avoiding the introduction of stress in the drift region, so as to reduce the source and drain of the device while ensuring that the breakdown voltage is almost constant. purpose of on-resistance R _on .

Contents of the invention

The technical problem to be solved by the present invention is to provide an LDMOS device which introduces local stress to improve device performance by using stress and reduce its adverse effects.

The present invention solves the above-mentioned technical problem, and adopts the technical scheme that the LDMOS device with local stress is introduced, including a bulk substrate, and a well region and a drift region adjacent to each other are formed on the substrate, and a well region and a drift region are respectively formed in the well region and the drift region. A source region and a drain region, a gate oxide layer is grown on the surface of the well region between the source region and the drift region, and a polysilicon gate is grown on the gate oxide layer, which is characterized in that the source region and/or gate surface is covered with a film, and the The thin film has intrinsic stress that induces stress in the channel of the LDMOS device.

In the LDMOS device of the present invention, only the source region and/or gate surface of the device is covered with a thin film, and the intrinsic stress of the thin film is used to introduce effective stress into the channel. Since there is no covering film on the surface of the drift region and the drain region, the film covering the surface of the source region and/or the gate will introduce almost no stress or only a small stress in the drift region with a long distance, thereby weakening or avoiding the impact caused by the stress. The impact of the band gap _EG reduces the breakdown voltage of the device.

Specifically, the substrate is made of P or N type material; the corresponding well region is made of P or N type material, the drift region is made of N or P type material, the source region is made of N or P type material, and the polysilicon is made of N or P type material .

The technical scheme of the present invention can be applied to P-type material substrates or N-type material substrate materials. According to the manufacturing process of LDMOS devices, different substrate material types (P-type or N-type), corresponding well regions, drift regions, source regions and their polysilicon gate electrode materials also have different conductivity types.

Preferably, the thin film is a silicon nitride thin film.

The silicon nitride thin film is used as the thin film covering the source region and/or the gate, and its formation process is highly compatible with the silicon-based semiconductor material process, and the formed thin film has appropriate intrinsic stress.

Further, the formation process of the film is to first grow a layer of silicon dioxide film on the surface of the source region and/or gate, and then grow a silicon nitride film on the silicon dioxide film; or do not grow the silicon dioxide film, directly Growth of silicon nitride films.

For the silicon-based semiconductor material, the silicon nitride film of the present invention can adopt two production processes, one process is to first grow a layer of silicon dioxide film, and then grow a silicon nitride film on the silicon dioxide film. Another technique is to directly grow a silicon nitride film on the surface of the source region and/or gate without growing a silicon dioxide film. The silicon dioxide film mainly acts as a stress buffer, so it is also called a buffer film (different from the stress film-silicon nitride), which can adjust the stress applied by the silicon nitride film. Since the gate surface is far away from the channel, the stress exerted by silicon nitride on the gate surface is transmitted to the channel relatively weakly, and there is no need to use a buffer film, so generally only silicon dioxide film plus silicon nitride film is used in the source area craft.

Specifically, the silicon dioxide film has a thickness of 5-100 nm.

More specifically, the silicon nitride film is grown by low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition.

Using the above two different processes, the magnitude and type of stress can be changed by adjusting the process parameters as required to meet the needs of devices with different conductivity types.

Further, the stress range of the silicon nitride film grown by the low pressure chemical vapor deposition method is 0.1-10 GPa, and the stress range of the silicon nitride film grown by the plasma enhanced chemical vapor deposition method is -8-+8 GPa.

The above stress range is easy to achieve, the process is not complicated, and the performance of the device is also significantly improved.

Specifically, the thickness of the silicon nitride film is 20 nm˜2 μm.

Generally, the thicker the silicon nitride film is, the greater the stress will be. A silicon nitride film thickness of 20 nm to 2 μm can meet the requirements of most devices, and it is easy to implement in terms of technology without causing damage.

The beneficial effect of the present invention is that the introduction of local stress can significantly improve the performance of LDMOS devices, reduce the source-drain on-resistance _{R on} , improve the drive capability of the device, and effectively reduce the adverse effects of stress on the bandgap EG of the drift region, ensuring the stability of the device. With high withstand voltage characteristics, the technical solution of the invention is very suitable for manufacturing power LDMOS devices.

Description of drawings

Fig. 1 is the device structure schematic diagram of embodiment 1;

Fig. 2 is another kind of device structure schematic diagram of embodiment 1;

Fig. 3 is the device structure schematic diagram of embodiment 2;

Fig. 4 is the device structure schematic diagram of embodiment 3;

Fig. 5 is a schematic diagram of stress simulation in the channel region;

Fig. 6 is a schematic diagram of device stress simulation results.

10—substrate; 12—well region; 14—drift region; 16—source region; 17—drain region; 18—gate oxide layer; 20—polysilicon gate; 22—silicon nitride film ; 24 silicon oxide layer.

detailed description

The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

In the following embodiments, the material type of the substrate 10 is P-type, the corresponding well region 12 is a P-type material, the drift region 14 is an N-type material, the source region 16 is an N-type material, and the polysilicon 20 is an N-type material, introducing stress is the tensile stress. For N-type material substrates, the device structure is the same except that the material type and the type of stress introduced in the corresponding regions are different.

Example 1

The cross-sectional structure of the LDMOS device in this example is shown in Figure 1. Including a bulk substrate 10, a well region 12 and a drift region 14 adjacent to each other are formed on the substrate 10, a source region 16 and a drain region 17 are respectively formed in the well region 12 and the drift region 14, and a source region 16 and a drain region 14 are formed in the well region 12 and the drift region 14 A gate oxide layer 18 is grown on the surface of the well region 12 between them, and a polysilicon gate 20 is grown on the gate oxide layer 18 . In this example, the device only covers the surface of the source region 16 with a silicon nitride (Si ₃ N ₄ ) film 22 , and the intrinsic stress of the silicon nitride film 22 is used to introduce stress into the channel of the LDMOS device. Since the silicon nitride film 22 only exists on the surface of the source region 16 , the stress introduced by it only acts on the nearby channel, and basically does not affect the far drift region 14 . In this example, the fabrication of the main body of the device is completed according to the traditional CMOS device manufacturing process, including the preparation of the substrate 10, the formation of the well region 12, the growth of the gate oxide layer 18, the growth of the polysilicon gate 20, the ion implantation of the channel, the ion implantation of the drift region 14, the source Region 16 and drain region 17 ion implantation and so on. Then adopt chemical vapor deposition (CVD) process, such as LPCVD (low pressure chemical vapor deposition) method or PECVD (plasma enhanced chemical vapor deposition) method, deposit thickness on the surface of source region 16 to be 120nm, have 2GPa Tensile-stressed silicon nitride film 22 . Next, the fabrication of the entire device is completed through traditional process steps such as local interconnection. The stress distribution of the device in this example is shown in curve A in Figure 5. The average stress in the channel region of 1-1.5 μm is about 232.6 MPa, and the stress in the drift region of 1.5-5 μm is very small, with an average stress of about 43.09 MPa. In the LDMOS device of this example, the silicon nitride film 22 can also cover the surface of the polysilicon gate 20, as shown in FIG. As a result, the stress introduced by the silicon nitride film 22 into the channel is relatively low.

Example 2

FIG. 3 is a schematic diagram of the structure of an LDMOS device covered with a silicon nitride film 22 on the surface of the source region 16 and the gate 20 . The manufacturing process of the device of this example is the same as that of Embodiment 1, and the manufacturing of the device body is completed according to the traditional CMOS device manufacturing process, including the preparation of the substrate 10, the formation of the well region 12, the growth of the gate oxide layer 18, the growth of the polysilicon gate 20, the trench ion implantation, drift region 14 ion implantation, source region 16 and drain region 17 ion implantation, and then chemical vapor deposition process is used to deposit nitride with a thickness of 120nm and a tensile stress of 2GPa on the surface of source region 16 and gate 20 Silicon film (22). Next, the fabrication of the entire device is completed through traditional process steps such as local interconnection. The device stress distribution in this example is shown in curve B in Figure 5. The average stress in the channel region (1-1.5 μm) is about 230 MPa, and the stress in the drift region (1.5-5 μm) is very small, with an average stress of about 45.94 MPa.

Example 3

Figure 4 is a schematic cross-sectional view of the device of this example. In this example, the surface of the source region 16 and the gate 20 of the device is covered with a silicon nitride film 22 , and there is a silicon dioxide (SiO ₂ ) film 24 between the source region 16 and the silicon nitride film 22 . The main function of the silicon dioxide film 24 is to buffer the stress introduced by the silicon nitride covering the surface, so that the stress distribution in the channel region (1-1.5 μm) is relatively uniform. Refer to the description of the above-mentioned embodiment for the manufacturing process of the device body of this example. The manufacturing process of the silicon nitride film 22 of this example is to grow a layer of 20nm thick silicon dioxide film (24) on the surface of the source region 16 first, and then use chemical vapor deposition. A silicon nitride film (22) with a thickness of 120nm and a tensile stress of 2GPa is deposited on the surface of the silicon dioxide film (24) by a deposition (CVD) process. Next, the fabrication of the entire device is completed through traditional process steps such as local interconnection. The stress distribution of the device in this example is shown in the curve C in Figure 5. The average stress in the channel region (1-1.5 μm) is about 187.17 MPa, and the stress in the drift region (1.5-5 μm) is very small, and the average stress is about 43.99 MPa .

In the LDMOS device with local stress introduced in the present invention, since the stress film is partially covered, the average stress of the device channel region (1-1.5 μm) is increased by ΔP compared with the average stress of the device drift region (1.5-5 μm) (see Figure 6 The device stress simulation results shown). The increase of the stress basically does not affect the bandgap EG of the device drift region (1.5-5 μm), but has a more obvious effect on the reduction of the source-drain on-resistance _{R on} of the device. The technical scheme of the invention fully exerts the positive effect of stress on device performance and reduces the negative influence of stress on device performance.

Claims (8)

1. The LDMOS device that introduces local stress, including a bulk substrate, forms a well region and a drift region adjacent to each other on the substrate, and forms a source region and a drain region in the well region and the drift region, respectively, and in the source region and the drift region A gate oxide layer is grown on the surface of the well region between them, and a polysilicon gate is grown on the gate oxide layer, which is characterized in that a thin film is covered on the surface of the source region, and stress is introduced into the channel of the LDMOS device by using the intrinsic stress of the thin film. . 2. The LDMOS device introducing local stress according to claim 1, wherein the substrate is a P or N type material; the corresponding well region is a P or N type material, and the drift region is an N or P type material material, the source region is N or P type material, and the polysilicon is N or P type material. 3. The LDMOS device with localized stress according to claim 1, wherein the film is a silicon nitride film. 4. the LDMOS device that has introduced local stress according to claim 1, is characterized in that, the generation process of described thin film is to grow a layer of silicon dioxide thin film on source area surface earlier, grow nitrogen on silicon dioxide thin film again Silicon oxide film; or do not grow silicon dioxide film, directly grow silicon nitride film. 5. The LDMOS device introducing local stress according to claim 4, characterized in that the thickness of the silicon dioxide film is 5-100 nm. 6. The LDMOS device introducing local stress according to any one of claims 3-5, characterized in that the silicon nitride film is grown by a low-pressure chemical vapor deposition method or a plasma-enhanced chemical vapor deposition method. 7. The LDMOS device introducing local stress according to claim 6, characterized in that, the stress range of the silicon nitride film grown by the low-pressure chemical vapor deposition method is 0.1-10GPa, and the plasma-enhanced chemical vapor The stress range of the silicon nitride film grown by deposition method is -8～+8GPa. 8 . The LDMOS device introducing local stress according to claim 6 , wherein the thickness of the silicon nitride film is 20 nm˜2 μm.