KR20070002664A - Dual gate manufacturing method of semiconductor device - Google Patents

Dual gate manufacturing method of semiconductor device Download PDF

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KR20070002664A
KR20070002664A KR1020050058284A KR20050058284A KR20070002664A KR 20070002664 A KR20070002664 A KR 20070002664A KR 1020050058284 A KR1020050058284 A KR 1020050058284A KR 20050058284 A KR20050058284 A KR 20050058284A KR 20070002664 A KR20070002664 A KR 20070002664A
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polysilicon
gate region
hard mask
dual gate
gate
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KR1020050058284A
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Korean (ko)
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홍재옥
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

A method for manufacturing a dual gate of a semiconductor device is provided to prevent the diffusion between an n+ poly gate and a p+ poly gate by performing ion-implantation and annealing after gate regions are entirely isolated. A hard mask nitride layer is formed on a substrate(101) to expose a dual gate region. A gate oxide layer(106) is deposited on the resultant structure. A first and a second polysilicon layer doped with n-type ions are stacked in the dual gate region. P-type impurity ions are implanted into the exposed second polysilicon layer(108) of a p-channel gate region in the dual gate region. Then, an annealing process is performed to activate the impurity ions.

Description

반도체 소자의 듀얼게이트 제조방법{Dual gate manufacturing method of Semiconductor device}Dual gate manufacturing method of semiconductor device

도 1 내지 도 11은 본 발명의 실시예에 따른 셀 트랜지스터의 공정단면도.1 to 11 are process cross-sectional views of a cell transistor according to an embodiment of the present invention.

본 발명은 반도체 소자의 듀얼게이트 제조 방법에 관한 것으로서, 보다 상세하게는 n+ 게이트영역과 p+ 게이트영역을 분리한 후, n 타입 이온이 도핑된 폴리실리콘을 형성한 후, p+ 게이트영역에 이온주입을 하고 열처리를 함으로써, n+ 게이트영역과 p+ 게이트영역간의 상호확산을 방지하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a dual gate of a semiconductor device, and more particularly, by separating an n + gate region and a p + gate region, forming polysilicon doped with n-type ions, and then implanting ion into a p + gate region. And heat treatment to prevent mutual diffusion between the n + gate region and the p + gate region.

일반적으로, 디램(dynamic random access memory)은 필드 산화막 등의 분리구조를 기판에 형성하여 소자형성영역을 정의하고 그 소자형성영역에 모스 트랜지스터를 제조한 후, 모스 트랜지스터의 드레인에 저속되는 캐패시터를 형성함과 아울러 모스 트랜지스터의 소스에 비트라인을 접속하여 제조되는 다수의 셀 트랜지스터와 페리 트랜지스터를 포함하여 구성된다.In general, a dynamic random access memory (DRAM) forms an isolation structure, such as a field oxide film, on a substrate to define an element formation region, fabricate a MOS transistor in the element formation region, and then form a capacitor at a low speed of the MOS transistor. In addition, a plurality of cell transistors and a ferry transistor are manufactured by connecting a bit line to a source of a MOS transistor.

특히, CMOS 소자에서 n+ 도핑된 폴리실리콘 게이트전극을 사용하는 p 채널 MOSFET는 실리콘기판 표면 하부로 매립채널(buried channel)이 형성되는데, 이러한 상황하에서는 실리콘기판 표면에 채널이 형성되는 n채널 MOSFET과 p 채널 MOSFET간에 문턱전압이 차이가 나게 되어 소자의 설계나 제작에 여러가지 제한 요인이 작용한다. 따라서, n채널 MOSFET의 게이트 폴리실리콘에는 n + 도핑을 적용하고, p 채널 MOSFET의 게이트 폴리실리콘에는 p+ 도핑을 적용하는 바, 이러한 구조를 통상 듀얼-게이트 구조라 부른다.In particular, p-channel MOSFETs using n + doped polysilicon gate electrodes in CMOS devices have buried channels formed under the surface of the silicon substrate. In this situation, n-channel MOSFETs and p are formed on the surface of the silicon substrate. Threshold voltages vary between channel MOSFETs, which can limit the design and fabrication of devices. Therefore, n + doping is applied to the gate polysilicon of the n-channel MOSFET and p + doping is applied to the gate polysilicon of the p-channel MOSFET. Such a structure is commonly referred to as a dual-gate structure.

종래기술에 따른 듀얼-폴리실리콘 게이트 형성방법은 먼저, 실리콘기판 상에 소자분리막을 형성하고, 게이트산화막을 성장시킨 후 게이트산화막 상부에 게이트 전극용 전도막 재료인 폴리실리콘을 순차적으로 증착한다. 그 후, n채널 MOSFET 영역의 폴리실리콘에 인(P)을 선택적으로 이온주입한 후에 p채널 MOSFET 영역의 폴리실리콘에 붕소(B)를 선택적으로 이온주입한다. 이어서, 열처리를 실시하여 폴리실리콘내의 도펀트(dopant)를 활성화시킨 후 마스크 및 식각 공정을 통해 게이트를 패터닝한다.In the method of forming a dual-silicon gate according to the prior art, first, a device isolation film is formed on a silicon substrate, a gate oxide film is grown, and polysilicon, which is a conductive film material for a gate electrode, is sequentially deposited on the gate oxide film. Thereafter, after phosphorus (P) is selectively ion implanted into the polysilicon of the n-channel MOSFET region, boron (B) is selectively ion implanted into the polysilicon of the p-channel MOSFET region. Subsequently, heat treatment is performed to activate the dopant in polysilicon, and then the gate is patterned through a mask and an etching process.

이와 같은, 종래 기술에 따른 듀얼-게이트 제조방법은 n+ 게이트영역과 p+ 폴리게이트 영역에 각각 이온을 주입한 후 열처리 공정시에 n+ 게이트영역과 p+ 폴리게이트 영역간에 상호 확산(inter-diffusion)현상이 발생한다.In the dual-gate manufacturing method according to the related art, inter-diffusion between the n + gate region and the p + polygate region occurs during the heat treatment process after implanting ions into the n + gate region and the p + polygate region. Occurs.

따라서, 종래와 같이 상호확산이 발생하는 트랜지스터를 링 오실레이터의 회로에 적용하는 경우 링 오실레이터 딜레이를 증가시켜 결국 디램의 처리 속도를 감소시키는 문제점이 있다.Therefore, in the case of applying a transistor having interdiffusion to a circuit of a ring oscillator as in the related art, there is a problem in that a ring oscillator delay is increased and eventually a processing speed of a DRAM is reduced.

상기와 같은 문제점을 해결하기 위한 본 발명의 목적은, n+ 게이트영역과 p+ 게이트영역을 분리한 후, n+ 게이트영역과 p+ 게이트영역에 각각 이온주입을 하고 열처리를 함으로써, n+ 게이트영역과 p+ 게이트영역간의 상호확산을 방지하는데 있다.An object of the present invention for solving the above problems, after separating the n + gate region and the p + gate region, by ion implantation and heat treatment respectively in the n + gate region and p + gate region, between the n + gate region and p + gate region To prevent interdiffusion.

상기 과제를 달성하기 위한 본 발명의 반도체 소자의 듀얼게이트 제조방법은, 반도체 기판 상부에 듀얼게이트영역을 노출시키는 하드마스크 질화막을 형성하는 제 1 공정과, 전면에 게이트 산화막을 증착하는 제 2 공정과, 상기 듀얼게이트영역내에만 게이트 산화막, n 타입 이온이 도핑된 제 1 및 제 2 폴리실리콘의 적층구조를 형성하는 제 3 공정과, 듀얼게이트영역 중 p 채널 게이트영역의 노출된 제 2 폴리실리콘에 p타입 불순물 이온 주입을 각각 수행하는 4 공정과, 불순물 이온을 활성화시키기 위한 열처리를 실시하는 제 5 공정을 포함함을 특징으로 한다.A dual gate manufacturing method of a semiconductor device of the present invention for achieving the above object is a first step of forming a hard mask nitride film exposing the dual gate region on the semiconductor substrate, and a second step of depositing a gate oxide film on the entire surface; And a third process of forming a stacked structure of a gate oxide layer and first and second polysilicon doped with n-type ions only in the dual gate region, and exposing the second polysilicon of the p-channel gate region among the dual gate regions. and a fifth step of performing p-type impurity ion implantation, respectively, and a fifth step of performing heat treatment to activate impurity ions.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 11은 본 발명의 실시예에 따른 셀 트랜지스터의 공정단면도이다. 1 to 11 are process cross-sectional views of a cell transistor according to an embodiment of the present invention.

먼저, 도 1을 참조하면, 반도체 기판(101) 상부에 하드마스크 질화막(102)이 증착되고 그 상부에 게이트전극 형성을 위한 감광막(103)을 형성한다. 이때, 감광막(103)은 n+ 게이트영역과 p+ 게이트영역을 분리하기 위해 소정 거리 이격시켜 복수개로 배열된다.First, referring to FIG. 1, a hard mask nitride layer 102 is deposited on a semiconductor substrate 101, and a photoresist layer 103 for forming a gate electrode is formed thereon. In this case, the photoresist film 103 is arranged in plurality in a predetermined distance to separate the n + gate region and the p + gate region.

도 2를 참조하면, 감광막(103)을 마스크로 하여 사진 식각공정을 통해 하드 마스크 질화막(102)의 일부를 식각하여 반도체 기판(101)의 일부가 노출되도록 하여 게이트영역(104, 105)을 형성한다.Referring to FIG. 2, a portion of the hard mask nitride layer 102 is etched through a photolithography process using the photoresist layer 103 as a mask to expose a portion of the semiconductor substrate 101 to form gate regions 104 and 105. do.

도 3을 참조하면, 전면에 소정 두께의 게이트 산화막(106)을 증착하고, 게이트영역(104, 105)내와 그 전면에 폴리실리콘(107)을 증착한다. 이때, 폴리실리콘(107)은 n 타입의 이온이 도핑된 상태로 증착된다.Referring to FIG. 3, a gate oxide film 106 having a predetermined thickness is deposited on the entire surface, and polysilicon 107 is deposited on and in the gate regions 104 and 105. At this time, the polysilicon 107 is deposited with the n type of ions doped.

도 4를 참조하면, 평탄화식각공정(Chemical Mechanical Polishing;CMP)을 통해 폴리실리콘(107) 및 게이트산화막(106)의 소정두께를 식각하여 하드 마스크 질화막(102)이 노출되도록 한 후 전면을 평탄화 시킨다. 이때, 게이트영역(104, 105) 내에 폴리실리콘(107)이 매립되어 있다.Referring to FIG. 4, a predetermined thickness of the polysilicon 107 and the gate oxide layer 106 is etched through a chemical mechanical polishing (CMP) to expose the hard mask nitride layer 102 and then planarize the entire surface. . At this time, polysilicon 107 is embedded in the gate regions 104 and 105.

도 5를 참조하면, 식각공정을 통해 게이트영역(104, 105)내의 폴리실리콘(107)의 일부 및 게이트영역(104, 105)내의 하드마스크 질화막(102) 측벽의 게이트 산화막(106)을 식각한다.Referring to FIG. 5, a portion of the polysilicon 107 in the gate regions 104 and 105 and the gate oxide layer 106 on the sidewalls of the hard mask nitride layer 102 in the gate regions 104 and 105 are etched through an etching process. .

도 6을 참조하면, 게이트영역(104, 105) 및 전면에 폴리실리콘(108)을 증착한다. 이때, 폴리실리콘(108)은 n 타입의 이온이 도핑된 상태로 증착된다.Referring to FIG. 6, polysilicon 108 is deposited on the gate regions 104 and 105 and the entire surface thereof. At this time, the polysilicon 108 is deposited with the n type of ions doped.

도 7을 참조하면, 평탄화식각공정을 통해 하드 마스크 질화막(102)이 노출되도록 한 후, 식각공정을 통해 게이트영역(104, 105) 내의 폴리실리콘(108)을 식각하여 게이트 산화막(106)의 상부에 소정 두께의 폴리실리콘(108)만 남긴다.Referring to FIG. 7, after the hard mask nitride layer 102 is exposed through the planarization etching process, the polysilicon 108 in the gate regions 104 and 105 is etched through the etching process to form an upper portion of the gate oxide layer 106. Leaves only polysilicon 108 of a predetermined thickness.

도 8을 참조하면, p 채널 MOSFET 영역의 폴리실리콘 게이트 형성을 위하여 n채널 MOSFET 영역을 덮는 감광막(110)을 형성한 후 p 채널 MOSFET 영역의 노출된 폴리실리콘(108)에 이온주입을 실시한다. 그 후, 감광막(110)을 제거하고, 전면에 열처리를 하여 주입된 이온들을 활성화시킨다.Referring to FIG. 8, the photoresist layer 110 covering the n-channel MOSFET region is formed to form a polysilicon gate of the p-channel MOSFET region, and then ion implantation is performed to the exposed polysilicon 108 of the p-channel MOSFET region. Thereafter, the photoresist layer 110 is removed and heat-treated on the entire surface to activate the implanted ions.

이때, 열처리는 800 ~ 1000℃ 정도의 온도에서 30 ~ 120초 동안 실시하는 급속열처리(Rapid Thermal Process, RTP)방식 또는 750 ~ 850℃ 정도의 온도에서 10 ~ 30분 동안 실시하는 노(furnace) 열처리방식을 사용하여 실시한다. At this time, the heat treatment is a rapid thermal process (Rapid Thermal Process, RTP) method carried out for 30 to 120 seconds at a temperature of about 800 ~ 1000 ℃ or furnace heat treatment carried out for 10 to 30 minutes at a temperature of about 750 ~ 850 ℃ Implement using the method.

도 9를 참조하면, 전면에 텅스텐 실리사이드(111)를 증착한 후, CMP 및 식각공정공정을 통해 게이트영역(104, 105)의 폴리실리콘(108) 상부의 소정 두께의 텅스텐실리사이드(111)만 남기고 식각한다.Referring to FIG. 9, after depositing the tungsten silicide 111 on the front surface, only the tungsten silicide 111 having a predetermined thickness on the polysilicon 108 of the gate regions 104 and 105 is left through CMP and etching processes. Etch it.

도 10을 참조하면, 하드 마스크 폴리(112)를 증착한 후, CMP 및 식각공정을 통해 게이트 영역(104, 105)의 텅스텐 실리사이드(111)의 상부에 소정 두께의 하드마스크 폴리(112)만 남기고 식각한다. Referring to FIG. 10, after the hard mask poly 112 is deposited, only the hard mask poly 112 having a predetermined thickness is left on the tungsten silicide 111 of the gate regions 104 and 105 through CMP and etching processes. Etch it.

도 11을 참조하면, 사진 식각공정을 통해 하드 마스크 질화막(102)을 모두 식각하여, 듀얼게이트 전극을 형성한다. Referring to FIG. 11, all of the hard mask nitride layers 102 are etched through a photolithography process to form dual gate electrodes.

이와같이, n+ 게이트영역과 p+ 게이트영역이 분리된 상태에서 이온주입 및 열처리 공정을 함으로써 n+ 폴리게이트와 p+ 폴리게이트간의 확산을 방지할 수 있다. As described above, ion implantation and heat treatment may be performed while the n + gate region and the p + gate region are separated to prevent diffusion between the n + polygate and the p + polygate.

이상에서 살펴본 바와 같이, 본 발명은 n+ 게이트영역과 p+ 게이트영역을 분리한 후, n+ 게이트영역과 p+ 게이트영역에 각각 이온주입을 하고 열처리를 함으로써, n+ 게이트영역과 p+ 게이트영역간의 상호확산을 방지하는 효과가 있다.As described above, in the present invention, after the n + gate region and the p + gate region are separated, ion implantation and heat treatment are performed in the n + gate region and the p + gate region, respectively, to prevent mutual diffusion between the n + gate region and the p + gate region. It is effective.

또한, 본 발명은 상호확산을 방지하는 듀얼게이트를 갖는 트랜지스터를 링오 실레이터에 적용하여 링오실레이터의 딜레이를 감소시킴으로써 디램의 속도를 향상시키는 효과가 있다.In addition, the present invention has the effect of improving the speed of the DRAM by applying a transistor having a dual gate to prevent the interdiffusion to the ring oscillator to reduce the delay of the ring oscillator.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허 청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허 청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

반도체 기판 상부에 듀얼게이트영역을 노출시키는 하드마스크 질화막을 형성하는 제 1 공정;A first step of forming a hard mask nitride film exposing the dual gate region over the semiconductor substrate; 전면에 게이트 산화막을 증착하는 제 2 공정;A second step of depositing a gate oxide film on the entire surface; 상기 듀얼게이트영역내에만 상기 게이트 산화막, n 타입 이온이 도핑된 제 1 및 제 2 폴리실리콘의 적층구조를 형성하는 제 3 공정;A third step of forming a stacked structure of the first and second polysilicon doped with the gate oxide film and n-type ions only in the dual gate region; 상기 듀얼게이트영역 중 p 채널 게이트영역의 노출된 상기 제 2 폴리실리콘에 p타입 불순물 이온 주입을 각각 수행하는 4 공정; 및Performing p-type impurity ion implantation into the exposed second polysilicon of the p-channel gate region of the dual gate region, respectively; And 상기 불순물 이온을 활성화시키기 위한 열처리를 실시하는 제 5 공정을 포함하는 것을 특징으로 하는 반도체 소자의 듀얼게이트 제조방법.And a fifth step of performing a heat treatment for activating the impurity ions. 제 1항에 있어서, The method of claim 1, 상기 제 5 공정후 상기 듀얼게이트영역을 소정 두께의 텅스텐 실리사이드 및 하드마스크 폴리로 매립하는 제 6 공정; 및A sixth process of filling the dual gate region with tungsten silicide and a hard mask poly having a predetermined thickness after the fifth process; And 상기 하드마스크 폴리를 마스크로 상기 하드마스크 질화막을 식각하여 듀얼게이트전극을 형성하는 제 7 공정을 더 포함하는 것을 특징으로 하는 반도체 소자의 듀얼게이트 제조방법.And forming a dual gate electrode by etching the hard mask nitride layer using the hard mask poly as a mask. 제 1항에 있어서, 상기 제 1 공정은, The method of claim 1, wherein the first step, 상기 반도체 기판의 상부에 하드마스크 질화막을 증착하는 공정;Depositing a hard mask nitride film on the semiconductor substrate; 상기 하드마스크 질화막의 상부에 상기 듀얼게이트영역을 형성하기 위해 소정거리 이격시켜 감광막을 형성하는 공정; 및 Forming a photoresist film at a predetermined distance apart to form the dual gate region on the hard mask nitride film; And 상기 감광막을 마스크로 하여 상기 하드마스크 질화막을 식각하여 분리된 상기 듀얼게이트영역을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 듀얼게이트 제조방법.And etching the hard mask nitride film to form the separated dual gate region using the photosensitive film as a mask. 제 1항에 있어서, 상기 제 3공정은,The method of claim 1, wherein the third step, 상기 게이트 산화막의 전면에 상기 제 1 폴리실리콘을 증착하고, 평탄화식각공정을 통해 상기 하드마스크 질화막의 상부가 노출되도록 한 후, 식각공정을 통해 상기 듀얼게이트영역내 측벽의 게이트산화막 및 제 1 폴리실리콘을 일부 식각하는 공정; 및The first polysilicon is deposited on the entire surface of the gate oxide layer, and the top surface of the hard mask nitride layer is exposed through a planarization etching process, and then the gate oxide layer and the first polysilicon of the sidewalls of the dual gate region are formed through an etching process. Etching part of it; And 전면에 상기 제 2 폴리실리콘을 증착하고, 상기 하드 마스크 질화막을 식각장벽으로 하여 실리콘을 평탄화식각공정을 한 후, 식각공정을 통해 상기 제 2 폴리실리콘을 식각하여 상기 제 1 폴리실리콘 상부의 제 2폴리실리콘을 소정두께 식각하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 듀얼게이트 제조방법.Depositing the second polysilicon on the entire surface, and performing a planarization etching process of silicon using the hard mask nitride layer as an etching barrier, and then etching the second polysilicon through an etching process to form a second upper portion of the first polysilicon. A method of manufacturing a dual gate of a semiconductor device, comprising the step of etching polysilicon a predetermined thickness. 제 1항에 있어서, 상기 제 4 공정은,The method of claim 1, wherein the fourth step, 상기 n 채널 게이트영역의 상부에 감광막을 형성한 후, 상기 p 채널 게이트영역상에 노출된 상기 제 2 폴리실리콘에 붕소(B) 이온을 주입하는 것을 특징으로 하는 반도체 소자의 듀얼게이트 제조방법.And forming boron (B) ions into the second polysilicon exposed on the p-channel gate region after forming a photoresist on the n-channel gate region. 제 1항에 있어서, 상기 제 4 공정의 열처리 공정은,The method of claim 1, wherein the heat treatment step of the fourth step, 800 ~ 1000℃ 범위내의 온도에서 실시됨을 특징으로 하는 반도체 소자의 듀얼게이트 제조방법.A method of manufacturing a dual gate of a semiconductor device, characterized in that carried out at a temperature in the range of 800 ~ 1000 ℃.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130099850A (en) * 2012-02-29 2013-09-06 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
US9236439B2 (en) 2014-01-02 2016-01-12 SK Hynix Inc. Semiconductor device and method for forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130099850A (en) * 2012-02-29 2013-09-06 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
US9236439B2 (en) 2014-01-02 2016-01-12 SK Hynix Inc. Semiconductor device and method for forming the same

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