JP2008028098A - Semiconductor device and repairing method for its side wall - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable the side wall of a layer formed in contact with an insulating film to be selectively restored. <P>SOLUTION: The Y-direction width of the lower part of a first conductive layer 6 becomes narrower than the Y-direction width of the upper part, because the side wall of the first conductive layer 6 is subjected to etching or the reaction product of the etching is removed. Thereafter, an outer wall 6b is formed through a selective growth technology in the region where the side wall is removed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a sidewall repair method for a semiconductor device for repairing sidewalls such as a gate electrode layer, a wiring layer, and an element isolation insulating layer using a selective growth technique, and a semiconductor device in which the sidewalls are repaired by this method.

In general, a technique of repairing a layer defect using a selective growth technique is provided (see, for example, Patent Document 1 and Patent Document 2). According to the technique disclosed in Patent Document 1, the silicon supply layer is selectively formed so as to cover the exposed side wall surface of the gate. When forming the gate, the conductive layer is anisotropically etched until the gate oxide film is exposed.
According to the technique disclosed in Patent Document 2, a local thin film defect is corrected. It is formed in a self-aligned manner with respect to minute missing portions of the amorphous silicon film formed on the substrate or the insulating film.
US Pat. No. 6,333,251 (FIG. 6) JP 2005-252209 A

  By the way, sidewalls such as a gate electrode layer, a wiring layer, and an element isolation insulating layer of the nonvolatile semiconductor memory device are dry-etched or cleaned, for example, with BHF or HF (hydrogen fluoride) chemical solution or hydrofluoric acid vapor. May be processed. In this case, the side wall of the layer recedes due to the influence of these treatments, and there is a possibility that a void is generated when an insulating film is buried between the side walls of the layer. For this reason, it is necessary to repair the shape of the side wall of the layer.

  In this case, even if the process disclosed in Patent Document 1 is applied, the repair film cannot be formed on the side wall surface where the silicon oxide film is exposed, and thus the repair film cannot be formed on the silicon oxide film. For this reason, this process cannot be adopted. In the configuration disclosed in Patent Document 2, a local thin film defect is corrected and can be formed in a self-aligned manner with respect to the entire surface of a minute missing portion on the insulating film. It is not possible to grow selectively. Therefore, this process cannot be adopted.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for repairing a side wall of a semiconductor device and a method for selectively repairing a side wall of a predetermined layer formed in contact with an insulating film. A semiconductor device formed by the method is provided.

  One aspect of a method for repairing a sidewall of a semiconductor device according to the present invention includes a step of forming an insulating film on a semiconductor substrate and forming a conductive layer on the insulating film, and at least part of the conductive layer from the upper end side to the lower end portion. And etching to the side to expose the insulating film, and forming a growth portion by selective growth in a junction region between the insulating film and the side wall of the conductive layer formed by the etching. Yes.

  According to one aspect of the method for repairing a sidewall of a semiconductor device of the present invention, an insulating film is formed on a semiconductor substrate, a conductive layer is formed on the insulating film, and the conductive layer is exposed from the upper end side. Etching and forming an electrode, and a step of forming an outer wall portion by selective growth on a side surface of the electrode, in a region where the width of the electrode gradually increases from the lower end portion of the electrode. It is characterized by that.

  One embodiment of a method for repairing a sidewall of a semiconductor device according to the present invention includes a step of forming a first insulating film on a surface of a semiconductor substrate, and a step of etching and removing the first insulating film and the semiconductor to form a groove on the semiconductor surface. A step of forming an element isolation insulating film in which the second insulating film is buried in the trench, the side wall is in contact with the first insulating film, and protrudes upward from the first insulating film; And a step of forming an outer wall portion by selective growth in a region where the width of the element isolation insulating film gradually increases from the vicinity of the first insulating film in the upward direction.

  One embodiment of a semiconductor device of the present invention is a semiconductor substrate, an insulating film formed on the semiconductor substrate, a conductive layer formed on the insulating film, a sidewall of the conductive layer, and from a lower end portion of the conductive layer And an outer wall portion formed in a region where the width of the conductive layer gradually increases toward the upper side.

  One embodiment of a semiconductor device of the present invention is a semiconductor substrate, an insulating film formed on the semiconductor substrate, and an electrode formed on the insulating film, and the width of the electrode gradually increases from the lower end to the upper side. It is characterized by comprising an electrode having a taper portion that becomes larger, and a repair portion formed in a region defined by the taper surface of the taper portion and the insulating film.

  According to the present invention, the side wall of the predetermined layer formed in contact with the insulating film can be selectively repaired. Further, according to the present invention, a structure in which the side wall is repaired can be obtained.

(First embodiment)
Hereinafter, a first embodiment in which a semiconductor device of the present invention is applied to a flash memory device having a stacked gate structure will be described with reference to FIGS.

  A NAND flash memory device (nonvolatile semiconductor memory device) 1 includes a memory cell region M in which a memory cell array Ar is formed and a peripheral circuit region in which a peripheral circuit for driving the memory cell array Ar in the memory cell region is formed. (Not shown). In the present embodiment, since the structure of the memory cell region M is characterized, the structure related to the characteristic part of the memory cell region M will be described in detail below.

  FIG. 1 is an equivalent circuit of a memory cell array in the memory cell region of the flash memory device, and FIG. 2 is a plan view schematically showing the structure in the region A1 of FIG. In the NAND flash memory device 1 as a semiconductor device, the memory cell array Ar is configured by arranging NAND cell units SU in a matrix. The NAND cell unit SU includes two select gate transistors Trs, and a plurality of these connected in series by sharing an impurity diffusion layer (source / drain region) 2a (see FIG. 3) between the select gate transistors Trs. (For example, 8: n to the power of 2) memory cell transistors Trn.

  The gate electrodes of the memory cell transistors Trn arranged in the X direction (word line direction, gate width direction) in FIG. 1 are commonly connected by a word line (control gate line) WL. Further, the selection gate electrodes (not shown) of the selection gate transistors Trs arranged in the X direction in FIG. 1 are commonly connected by the selection gate line SL. Further, the select gate transistor Trs is connected to the bit line BL.

  The plurality of NAND cell units SU are separated from each other in the X direction by an element isolation region Sb having an STI (Shallow Trench Isolation) structure, as shown in FIGS. The floating gate electrode FG (see FIG. 3) of the memory cell transistor Trn is an intersection of an element formation region (active region: active area) Sa extending in the Y direction and a word line WL extending in the Y direction formed at a predetermined interval. It is formed in the position.

<Regarding Gate Electrode Structure in Memory Cell Region M of Flash Memory Device 1>
Hereinafter, description will be made with reference to FIGS. 3A to 3C with a focus on the characteristic portions of the structure according to the present embodiment. FIG. 3A shows a schematic perspective view of a gate electrode formation region and a gate electrode isolation region in the memory cell region. FIG. 3B is a schematic longitudinal sectional view taken along the line CC in FIG. FIG. 3C is a schematic longitudinal sectional view taken along line DD in FIG.

  The flash memory device 1 is partitioned and formed in both a memory cell region M and a peripheral circuit region (not shown) with respect to a p-type silicon substrate 2 as a semiconductor substrate. Hereinafter, the stacked gate electrode structure formed in the memory cell region M will be described. As shown in FIGS. 3A and 3C, element isolation grooves 3 are formed on the surface layer side of the silicon substrate 2 for a plurality of element isolation regions Sb. Is embedded with an element isolation insulating film 4. The element isolation insulating film 4 is made of, for example, a silicon oxide film, and is provided to electrically isolate adjacent floating gate electrode layers FG, and constitutes an element isolation region Sb having a so-called STI structure.

  The element isolation insulating film 4 is formed so as to be embedded in the element isolation groove 3 formed in the silicon substrate 2 and to protrude above the silicon substrate 2. The element isolation insulating film 4 is configured to isolate the element formation region Sa (active region: active area) of the silicon substrate 2 into a plurality of portions.

  A silicon oxide film 5 is formed on the element formation region Sa separated by the element isolation insulating film 4. The silicon oxide film 5 is composed of a thermal oxide film, functions as a gate oxide film, a tunnel insulating film, and a first gate insulating film, and corresponds to the insulating film of the present invention.

  A first conductive layer 6 is formed on the silicon oxide film 5. The first conductive layer 6 is made of, for example, polycrystalline silicon or amorphous silicon doped with an impurity such as phosphorus, and functions as a floating gate electrode FG and a first gate electrode. The height of the upper surface of the first conductive layer 6 from the silicon substrate 2 is higher than the height of the upper surface of the adjacent element isolation insulating film 4 from the silicon substrate 2.

  A second gate insulating film 7 is formed on the upper surface of the first conductive layer 6. As shown in FIG. 3C, the second gate insulating film 7 is formed over the upper surface and side surfaces of the first conductive layer 6 and the upper surface of the element isolation insulating film 4 in the X direction. The second gate insulating film 7 is constituted by a laminated structure of an oxide film layer or a nitride film layer made of, for example, an ONO film (Oxide (oxide film layer) -Nitride (nitride film layer) -Oxide (oxide film layer)). Yes. The second gate insulating film 7 is formed by being sandwiched between a first conductive layer 6 and a second conductive layer 8 described later, and is configured as a conductive interlayer insulating film. The second gate insulating film 7 functions as an inter-gate insulating film for maintaining the insulating performance between the floating gate electrode FG and the control gate electrode CG.

  A second conductive layer 8 is formed on the second gate insulating film 7 so as to cover the second gate insulating film 7. The second conductive layer 8 includes, for example, a lower conductive layer 9 made of polycrystalline silicon doped with an impurity such as phosphorus or arsenic or amorphous silicon, and an upper conductive layer formed on the lower conductive layer 9. 10. The upper conductive layer 10 is formed of, for example, tungsten silicide and functions as a low resistance metal layer. The second conductive layer 8 functions as a control gate electrode CG and a second gate electrode. The control gate electrode CG is formed over the plurality of element formation regions Sa and element isolation regions Sb so as to cover the second gate insulating film 7.

A silicon nitride film 11 is formed on the second conductive layer 8.
As described above, the flash memory device 1 according to this embodiment includes the stacked gate structure 12 including the silicon oxide film 5, the first conductive layer 6, the second gate insulating film 7, and the second conductive layer 8. ing. Although not shown, a structure that forms an interlayer insulating film and a bit line BL is formed on the silicon nitride film 11 to constitute the flash memory device 1.

  As shown in FIG. 3B, the first conductive layer 6 has a second gate insulation formed above the first conductive layer 6 from the lower end 6aa whose Y-direction cross section is in contact with the silicon oxide film 5. A taper portion 6a whose width in the Y direction widens toward the upper end portion 6ab in contact with the film 7 is provided. The tapered portion 6a has a shape that is generated when the side wall of the first conductive layer 6 is dry-etched by RIE or treated with a chemical solution or hydrofluoric acid vapor.

  The outer wall portion 6b is formed as a growth portion (repair portion) using a selective growth technique along the taper surface 6ac of the taper portion 6a of the first conductive layer 6. At this time, the taper portion 6 a of the first conductive layer 6 has the first width as the first conductive layer 6 in contact with the silicon oxide film 5 and the width of the outer wall portion 6 b in contact with the silicon oxide film 5. Assuming the second width, the second width is formed to be narrower than the first width. The outer wall portion 6b is formed so that the width in the Y direction is the largest immediately above the silicon oxide film 5 (in contact with the silicon oxide film 5) and the width in the Y direction becomes narrower toward the upper side. This is because the selective growth is particularly easy on the silicon oxide film 5 as will be described later. By this selective growth, the outer wall 6 b is formed in a plane whose outer wall surface 6 ba is substantially perpendicular to the upper surface of the silicon substrate 2.

  According to the configuration of the present embodiment, the tapered portion 6a is formed with respect to the first conductive layer 6 on the silicon oxide film 5, and the tapered portion 6a is repaired by the outer wall portion 6b. . In addition, the taper of the first conductive layer 6 formed immediately above the silicon oxide film 5 is not formed on the side wall surface of the second conductive layer 8 or the second gate insulating film 7 and a repair film is formed. A structure in which only the surface 6ac (particularly the lower side thereof) is repaired can be obtained. In this case, a particularly effective repair structure can be obtained.

<About manufacturing method>
Hereinafter, a method of manufacturing the stacked gate structure 12 related to the memory cell region M of the flash memory device 1 will be described with reference to FIGS. As long as the present invention can be realized, any of the steps described later may be omitted as necessary, the manufacturing method may be changed, or a process may be added if it is a general process. .

  As shown in FIG. 4, a silicon oxide film 5 as a first gate insulating film is formed on a silicon substrate 2 as a semiconductor substrate to a thickness of, for example, 10 [nm] by a thermal oxidation method. Next, as shown in FIG. 5, the first conductive layer is deposited on the silicon oxide film 5 by depositing polycrystalline silicon doped with impurities such as phosphorus and arsenic by a low pressure CVD (Chemical Vapor Deposition) method. The layer 6 is formed with a film thickness of, for example, 140 [nm].

  Next, as shown in FIG. 6, a silicon nitride film 13 is formed on the first conductive layer 6 with a film thickness of, for example, 70 [nm] by low pressure CVD. Next, as shown in FIG. 7, a resist 14 is applied on the silicon nitride film 13, and patterning is performed on a region G (gate electrode formation region) for forming the floating gate electrode FG. Next, as shown in FIG. 8, the silicon nitride film 13 is removed by RIE (Reactive Ion Etching) using the patterned resist 14 as a mask.

  Next, as shown in FIG. 9, the first conductive layer 6, the silicon oxide film 5, and the silicon substrate 2 are etched by the RIE method, and an element is formed along a predetermined direction (Y-axis direction in FIGS. 1 and 2). A plurality of separation grooves 3 are formed in parallel to each other. Thereby, each of the first conductive layer 6 and the silicon oxide film 5 is divided into a plurality. Thereafter, the resist 14 is removed by an ashing technique.

Next, as shown in FIG. 10, a silicon oxide film such as a TEOS material is embedded as an element isolation insulating film 4 in the element isolation trench 3 by low pressure CVD. The element isolation insulating film 4 may be formed by a high density plasma CVD method. Further, as the element isolation insulating film 4, a TEOS-O ₃ film may be applied, or a coating type insulating film obtained by converting a polysilazane solution (a kind of coating liquid for forming a silica-based film) into a silicon oxide film, or the like is applied. May be.

  Next, as shown in FIG. 11, the element isolation insulating film 4 is planarized by CMP (Chemical Mechanical Polishing) until the surface of the silicon nitride film 13 is exposed, and the silicon nitride film 13 is removed by wet etching. The surface of the element isolation insulating film 4 is etched by about 150 [nm] by RIE.

Then, as shown in FIG. 11, the upper surface of the element isolation insulating film 4 is formed so as to be located above the upper surface of the silicon oxide film 5 and below the upper surface of the first conductive layer 6.
Next, as shown in FIG. 12, the second gate insulation so as to cover the upper surface and side walls of the first conductive layer 6 and the upper surface of the element isolation insulating film 4 with respect to the exposed surface of the first conductive layer 6. A film 7 is formed. When an ONO film (a laminated structure of silicon oxide film-silicon nitride film-silicon oxide film) is applied as the second gate insulating film 7, it is formed by a low pressure CVD method.

  Next, as shown in FIG. 13, on the second gate insulating film 7, polycrystalline silicon doped with an impurity such as phosphorus or arsenic is formed as the lower conductive layer 9 by the CVD method, and the lower conductive layer A tungsten silicide film having a thickness of about 300 nm is formed as an upper conductive layer 10 on the substrate 9 by sputtering. Next, although not shown, a silicon nitride film is formed on the upper conductive layer 10 by low pressure CVD.

  Next, a resist 16 is applied on the silicon nitride film, and the resist 16 is patterned. The patterning region of the resist 16 is a gate electrode formation region GC as shown in FIG. This resist pattern is a mask pattern for removing the stacked films 5 to 11 in the gate electrode isolation region GV (see FIGS. 2 and 3A).

  Next, as shown in FIG. 14, the silicon nitride film 11 on the upper conductive layer 10 is removed by etching using the patterned resist 16 as a mask, and the silicon nitride film 11 is removed from the gate electrode formation region GC. To remain. This is performed by etching the silicon nitride film 11 under conditions with high selectivity to polycrystalline silicon.

  Next, as shown in FIG. 15A, the upper conductive layer 10 formed in the gate electrode isolation region GV is removed by etching the upper conductive layer 10 using the patterned resist 16 as a mask. Thereby, the upper conductive layer 10 remains in the gate electrode formation region GC. Although an embodiment is shown in which the etching process is continued using the patterned resist 16 as a mask, the resist 16 may be removed and the upper conductive layer 10 may be removed using the silicon nitride film 11 as a mask.

  At this time, as shown in FIG. 15A, the upper conductive layer 10 of the gate electrode isolation region GV is removed, and at the same time, the lower conductive layer 9 of the gate electrode isolation region GV, the second gate insulating film 7 and the first conductive layer 10 are removed. Layer 6 is also removed. By this etching process, the lower conductive layer 9 formed in the gate electrode isolation region GV is removed, and the control gate electrode CG formed in the gate electrode formation region GC is left. As a result, the second conductive layer 8 (control gate electrode CG, upper conductive layer 10 and lower conductive layer 9) is structurally divided with respect to the Y direction (cross direction with respect to the X direction in the upper surface of the silicon substrate 2). .

  Also, the first conductive layer 6 formed in the gate electrode isolation region GV is removed by this etching process, and the first conductive layer 6 formed in the gate electrode formation region GC is left. Thereby, the first conductive layer 6 is structurally divided with respect to the Y direction.

  It has been confirmed that when the side wall surface 6ac is irradiated with radicals for a long time during the processing by the RIE method, the lower end portion of the first conductive layer 6 is easily removed as shown in FIG. . This tendency occurs regardless of the processed material. As described above, when the gate electrode isolation region GV is etched, the lower sidewall of the first conductive layer 6 is excessively processed, and the first conductive layer 6 is a silicon oxide film in the Y-direction cross section of the first conductive layer 6. 5 has a tapered portion 6a whose width in the Y direction increases from the lower end portion 6aa in contact with 5 toward the upper end portion 6ab in contact with the second gate insulating film 7 formed above the first conductive layer 6. As a result, a space (empty wall) 6 c defined by the surface along the upper side wall of the first conductive layer 6, the tapered surface 6 ac and the silicon oxide film 5 is formed.

  After the processing by the RIE method, a reaction product (not shown) is generated on the side wall of the first conductive layer 6 during the etching process, and this reaction product is removed with an HF (hydrogen fluoride) chemical solution. . In this case, the removal process is particularly accelerated for a portion having a large defect on the side wall of the first conductive layer 6. In particular, a hydrofluoric acid vapor is also introduced when removing the reaction product, but this effect further tends to cause defects. It has also been confirmed that when the concentration of impurities (for example, phosphorus) introduced into the first conductive layer 6 is high, the over-etching processing speed tends to increase. Further, it has been confirmed that even when the sidewall of the first conductive layer 6 is vertically etched when processed by the RIE method, a step is generated. In addition, when the impurity concentration contained in the first conductive layer 6 is high, the step becomes large.

  Therefore, in this embodiment, as shown in FIGS. 3A and 3B, the space 6c is repaired to form the outer wall 6b as a growth portion. This repair process uses a selective growth technique. Specifically, as selective growth conditions, for example, temperature: 500 to 1000 ° C., pressure: 10 to 100 Torr, dichlorosilane gas: 0.1 to 1.0 slm, HCl gas: 0.1 to 0.5 slm Is used. In this case, repair is possible at a growth rate of 10 nm to 15 nm / min. The growth rate and uniformity can be changed by changing various parameters such as time, pressure, temperature, and gas flow rate.

  It has been confirmed that the selective growth rate increases as the silicon density increases in the selective growth. In the case of this embodiment, since the silicon density of the junction region of the space 6c between the silicon oxide film 5 and the tapered surface 6ac of the first conductive layer 6 made of polycrystalline silicon is high, the selective growth rate of this junction region is high. It is the highest and the selective growth rate decreases as the distance from the junction region increases. Due to the difference in the selective growth rate, the space portion 6 c is filled with the outer wall portion 6 b, and the outer wall surface 6 ba of the outer wall portion 6 b is formed in a plane substantially perpendicular to the upper surface of the silicon substrate 2.

  After the repair of the sidewall of the first conductive layer 6, the source / drain region 2a is formed on the surface layer side of the silicon substrate 2 immediately below the silicon oxide film 5 in the gate electrode isolation region GV, and the gate electrode isolation region GV On the other hand, an interlayer insulating film (not shown) is embedded. At this time, if the tapered portion 6a of the first conductive layer 6 is not repaired by the selective growth technique, a void may be generated in the region of the space portion 6c.

  When voids are generated, the resistance value of the film increases, which causes the desired characteristics not to be obtained. In the manufacturing method of the present embodiment, the outer wall portion 6b is formed in the space portion 6c formed in the tapered portion 6a of the first conductive layer 6 by the selective growth technique to repair the side wall of the first conductive layer 6. Therefore, the interlayer insulating film can be formed without generating voids. Since the subsequent process is a general process, a detailed description thereof is omitted, but the NAND flash memory device 1 can be configured through a process of forming the bit line BL and the like.

  As described above, according to the manufacturing method according to the present embodiment, the lower portion of the first conductive layer 6 is removed by removing the first conductive layer 6 by an etching process, a subsequent removal process of reaction products, and the like. Even if the width in the Y direction at the lower end portion of the conductive layer 6 is formed to be narrower than the width in the Y direction at the upper portion, the outer wall portion 6b can be formed by the selective growth technique for the region of the removed space portion 6c. The first conductive layer 6 can be selectively repaired.

  At the time of the selective growth process, the growth rate in the vicinity of the junction between the silicon-containing silicon oxide film 5 and the first conductive layer 6 made of polycrystalline silicon is increased, and can be selectively grown faster than other parts. The side wall of the first conductive layer 6 can be formed in a plane perpendicular to the silicon substrate 2, and the generation of voids can be prevented.

(Second Embodiment)
FIG. 16A to FIG. 16B show a second embodiment of the present invention, and a different part from the first embodiment is to repair the second conductive layer 9. The same parts as those of the above-described embodiment are denoted by the same reference numerals, description thereof is omitted, and only different parts will be described below.

  In the above-described embodiment, the silicon nitride film 11 in the gate electrode isolation region GV is removed as described with reference to FIG. Thereafter, in the present embodiment, as shown in FIG. 16A, the second conductive layer 8 (the upper conductive layer 10 and the conductive layer 10) in the gate electrode isolation region GV under a condition having high selectivity with respect to the silicon oxide film. The lower conductive layer 9) is removed by the RIE method, and the process is temporarily stopped immediately above the second gate insulating film 7.

  Then, as shown in FIG. 16A, the lower region of the lower conductive layer 9 constituting the second conductive layer 8 (see the space 9b in FIG. 16B) is removed. This is because when the etching process is performed by the RIE method, the side wall surface of the conductive layer located particularly below is easily removed as described above. In the case of the present embodiment, since the process is temporarily stopped immediately above the second gate insulating film 7, the space 9b of the lower conductive layer 9 is particularly easily removed.

  Therefore, in order to repair the space 9b of the lower conductive layer 9, the selective growth process is performed under the conditions described in the above embodiment. Then, as shown in FIG. 16B, even if the space portion 9b of the lower conductive layer 9 is once removed, the outer wall portion 9c can be grown as a growth portion along the side wall surface of the lower conductive layer 9. Thus, it is possible to obtain substantially the same operational effects as in the above-described embodiment. Therefore, the performance of the control gate electrode CG can be maintained.

(Third embodiment)
FIG. 17 shows a third embodiment of the present invention. The difference from the previous embodiment is that the side wall of the element isolation insulating film is selectively grown and repaired. The same parts as those of the above-described embodiment are denoted by the same reference numerals, description thereof is omitted, and only different parts will be described below.

  FIG. 17 schematically shows a cross-sectional view along the X direction in the gate electrode isolation region GV. An element isolation insulating film 20 instead of the element isolation insulating film 4 is embedded in an element isolation groove 21 formed in the silicon substrate 2 and is formed so as to protrude upward from the upper surface of the silicon oxide film 5. The element isolation insulating film 20 is formed with an upper portion 20a whose width gradually increases from the vicinity of the side end portion of the silicon oxide film 5 upward. An outer wall portion 20c is formed on the side wall 20b of the upper portion 20a. The outer wall portion 20c is formed along the side wall 20b by the selective growth process described in the above embodiment. According to such an embodiment, the defect of the side wall 20b of the upper part 20a of the element isolation insulating film 20 can be repaired, and the substantially same effect as the above-described embodiment can be obtained.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
Although the embodiment applied to the flash memory device 1 is shown, it can also be applied to other semiconductor devices.
Although an embodiment in which the present invention is applied to the silicon oxide film 5 and the second gate insulating film 7 has been shown, the insulating film is an insulating film containing silicon (for example, a silicon nitride film). desirable. This is because when the silicon-based insulating film is formed directly under the layer, the selective growth degree of the side wall surface of the layer is high. Note that the insulating film of the present invention may not contain silicon.

  An embodiment in which the first conductive layer 6 is formed on the silicon oxide film 5 and the tapered surface (side wall surface) 6ac of the tapered portion (core portion) 6a of the first conductive layer 6 is selectively grown; In the embodiment, the conductive layer 8 is formed on the second gate insulating film 7 and the side wall surface of the second conductive layer 8 is selectively grown. However, if the conductive layer 8 is formed on the main surface of the insulating film, The present invention can be applied to any layer (for example, a wiring layer).

Electrical configuration diagram of a semiconductor device showing a first embodiment of the present invention Plan view schematically (A) is a schematic perspective view showing a part of the memory cell region, (b) is a schematic cross-sectional view (part 1) showing a part of the memory cell region, and (c) is a part of the memory cell region. (2) showing a schematic cross-sectional view Sectional drawing which shows typically a part of memory cell area | region in one manufacturing process (the 1) Sectional drawing which shows typically a part of memory cell area | region in one manufacturing process (the 2) Sectional drawing which shows typically a part of memory cell area | region in one manufacturing process (the 3) Sectional drawing which shows typically a part of memory cell area | region in one manufacturing process (the 4) Sectional drawing which shows typically a part of memory cell area | region in one manufacturing process (the 5) Sectional drawing which shows typically a part of memory cell area | region in one manufacturing process (the 6) Sectional drawing which shows typically a part of memory cell area | region in one manufacturing process (the 7) Sectional drawing which shows typically a part of memory cell area | region in one manufacturing process (the 8) Sectional drawing which shows typically a part of memory cell area | region in one manufacturing process (the 9) Sectional drawing which shows typically a part of memory cell area | region in one manufacturing process (the 10) A perspective view schematically showing a part of a memory cell region in one manufacturing process (No. 1) (A) is a perspective view schematically showing a part of a memory cell region in one manufacturing process (part 2), and (b) is a cross-sectional view schematically showing a part of the memory cell region in one manufacturing process (part 11). ) (A) FIG. 15 (a) equivalent view and (b) FIG. 3 (b) equivalent view showing a second embodiment of the present invention. Sectional drawing which shows typically a part of memory cell area | region which shows the 3rd Embodiment of this invention

Explanation of symbols

In the drawings, 1 denotes a flash memory device (semiconductor device), 5 denotes a silicon oxide film (insulating film), 6 denotes a first conductive layer, and 6b and 20c denote outer wall portions (growth portions).

Claims (5)

Forming an insulating film on the semiconductor substrate and forming a conductive layer on the insulating film;
Etching and removing at least a part of the conductive layer from the upper end side to the lower end side to expose the insulating film;
And a step of forming a growth portion by selective growth in a junction region between the insulating film and the side wall of the conductive layer formed by the etching. Forming an insulating film on the semiconductor substrate and forming a conductive layer on the insulating film;
Etching away the conductive layer from the upper end side until the insulating film is exposed, and forming an electrode;
A step of forming an outer wall portion by selective growth on a side surface of the electrode and in a region where the width of the electrode gradually increases from the lower end portion of the electrode upward. Sidewall repair method. Forming a first insulating film on the surface of the semiconductor substrate;
Etching the first insulating film and the semiconductor to form a groove in the semiconductor surface;
Embedding a second insulating film in the trench, forming a device isolation insulating film whose side wall is in contact with the first insulating film and projecting upward from the first insulating film;
Forming an outer wall portion by selective growth on a side wall of the element isolation insulating film, in a region where the width of the element isolation insulating film gradually increases from the vicinity of the first insulating film. A method of repairing a sidewall of a semiconductor device, comprising: A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
A conductive layer formed on the insulating film;
A semiconductor device, comprising: a side wall of the conductive layer, and an outer wall portion formed in a region where the width of the conductive layer gradually increases from a lower end portion of the conductive layer. A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
An electrode formed on the insulating film, the electrode having a tapered portion in which the width of the electrode gradually increases from the lower end to the upper side;
A semiconductor device, comprising: a repair portion formed in a region defined by a taper surface of the taper portion and the insulating film.

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