CN109524312A - The surface correcting principle and modification method of semiconductor structure - Google Patents

The surface correcting principle and modification method of semiconductor structure Download PDF

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Publication number
CN109524312A
CN109524312A CN201811356888.7A CN201811356888A CN109524312A CN 109524312 A CN109524312 A CN 109524312A CN 201811356888 A CN201811356888 A CN 201811356888A CN 109524312 A CN109524312 A CN 109524312A
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CN
China
Prior art keywords
semiconductor structure
notacoria
surface
opening
stressor layers
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CN201811356888.7A
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Chinese (zh)
Inventor
罗世金
胡明
鲍琨
夏志良
程纪伟
孙中旺
张坤
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长江存储科技有限责任公司
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Priority to CN201811356888.7A priority Critical patent/CN109524312A/en
Publication of CN109524312A publication Critical patent/CN109524312A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11551Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11578Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

This application discloses the surface correcting principle and modification method of a kind of semiconductor structure, the surface correcting principle of the semiconductor structure includes: notacoria, and the notacoria is located at the surface of semiconductor structure and abuts therewith;And stressor layers, the stressor layers and the notacoria are adjacent.The correcting principle provides even curface for subsequent coating, suitable for the surface warp of various directionality, so as to improve the yield and reliability of semiconductor devices.

Description

The surface correcting principle and modification method of semiconductor structure

Technical field

The present invention relates to semiconductor technology, more particularly, to semiconductor structure surface warp (bow) correcting principle with And modification method.

Background technique

The developing direction of semiconductor technology is the reduction of characteristic size and the raising of integrated level.For memory device, The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With the spy of semiconductor fabrication process Sign size is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density, three have been developed Tie up the memory device (that is, 3D memory device) of structure.3D memory device includes the multiple storage units stacked along vertical direction, Integrated level can be doubled up on the chip of unit area, and can reduce cost.

The 3D memory device is, for example, the semiconductor structure for including wafer and rhythmic structure of the fence, wherein uses gate stack knot Structure provides the grid conductor of selection transistor and memory transistor, provides selection transistor using the channel column through laminated construction And memory transistor channel layer and the gate-dielectric that is clipped between grid conductor and channel layer.Since stacking is multiple not With the film of material composition, semiconductor structure generates the stress of accumulation, causes semiconductor structure perpendicular to the flat of stacking direction Warpage occurs in face.In a practical situation, the asymmetry due to wafer frontside by stress often will cause the various shapes of wafer The asymmetric warpage of state, for example, saddle type warpage, lead to problems such as wafer be easy to happen fragment.It is partly led it is expected that being further improved The surface correcting principle and its modification method of body structure, to improve the yield and reliability of 3D memory device.

Summary of the invention

In view of the above problems, the purpose of the present invention is to provide a kind of surface correcting principle of semiconductor structure and amendments Method, wherein form notacoria at semiconductor structure back, and design the opening of notacoria according to the directionality of warpage, formation is filled out The stressor layers of opening are filled, to restore even curface again.

According to an aspect of the present invention, a kind of surface correcting principle of semiconductor structure is provided, comprising: notacoria, it is described Notacoria is located at the surface of semiconductor structure and abuts therewith;And stressor layers, the stressor layers and the notacoria are adjacent.

It preferably, include opening in the notacoria, the stressor layers are located in the opening.

Preferably, the semiconductor structure includes chip and the rhythmic structure of the fence positioned at the chip first surface, institute The second surface that notacoria is located at the chip is stated, the first surface and second surface of the chip are relative to each other.

Preferably, the quantity of the opening is at least one, the shape of the opening include polygon, circle, annular and Any combination thereof.

Preferably, the opening is distributed about the central symmetry of the semiconductor structure.

Preferably, center asymmetric distribution of the opening about the semiconductor structure.

Preferably, described be open extends to any depth of the inside of the notacoria from the surface of the notacoria.

Preferably, the opening runs through the notacoria, extends to the surface of the semiconductor structure.

Preferably, the material of the stressor layers includes the material with shrinkage stress, the material with expansion stresses and tool There is at least one of the material of low stress.

Preferably, the surface of the stressor layers is covered with film, and the thickness of the film does not influence the semiconductor structure Macro-stress.

According to another aspect of the present invention, a kind of surface modification method of semiconductor structure is provided, comprising: form back Film, the notacoria are located at the surface of semiconductor structure and abut therewith;Form the opening being located on the notacoria;And form position Stressor layers in the opening, to restore to even curface.

Preferably, the step of forming the opening being located on the notacoria includes: to measure the surface of the semiconductor structure to stick up It is bent;According to the directionality designing mask pattern of warpage;And the etching notacoria, form the opening being located on the notacoria.

Preferably, film is formed on the surface of the stressor layers, the thickness of the film does not influence the semiconductor structure Macro-stress.

Preferably, after forming the stressor layers being located in the opening, further includes: to the surface of the semiconductor structure Planarization process is carried out, the planarization process includes chemically mechanical polishing.

The surface correcting principle and modification method of semiconductor structure according to an embodiment of the present invention, semiconductor structure is for example For 3D memory device, wherein form notacoria at semiconductor structure back, and be located at notacoria according to the design of the directionality of warpage Opening forms the stressor layers of filling opening, to restore even curface again.The modification method provides for subsequent coating Even curface is applicable not only to isotropic surface warp, and is suitable for anisotropic surface warp, thus can To improve the yield and reliability of semiconductor devices.

The surface warp of semiconductor structure can be obviously reduced in the surface correcting principle, and semiconductor structure is, for example, 3D storage Device, to allow the grid conductor in semiconductor structure including more levels.Since the surface modification method is with each to different Property surface warp capability for correcting, therefore, though in the semiconductor structure comprising complex pattern generate stress, cause each to different Property surface warp, can also reform into flat surface.The surface modification method can increase the stacking number of 3D memory device And labyrinth improves storage density to be conducive to further reduce the chip area footprints of storage unit.

Further, which passes through the thickness of control notacoria and depth, the location and shape of stressor layers Etc. parameters, can be convenient ground proof stress size and location distribution, reduce control the modified technology difficulty in surface.And it should Surfacing method does not discharge stress by increasing heat, and be not heated budget limit (thermal budget Limitation), to keep the modified window in surface bigger, technology difficulty is reduced, promotes the modified quality in surface.

Further, which, will not be right by forming notacoria and stressor layers at the back of semiconductor structure Device architecture positioned at semicon-ductor structure surface damages.And the surface modification method does not etch semiconductor structure directly, To will not the mechanical strength of double of conductor structure impact, to reach surface amendment and will not have been made to semiconductor structure At the purpose of damage.

Detailed description of the invention

By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and Advantage will be apparent from, in the accompanying drawings:

The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.

Fig. 2 shows the perspective views of 3D memory device.

Fig. 3 a to 3e shows the sectional view in each stage of the correcting principle manufacturing method of the embodiment of the present invention.

The sectional view of the correcting principle provided according to a first embodiment of the present invention is shown respectively in Fig. 4 a and 4b.

The sectional view of the correcting principle provided according to a second embodiment of the present invention is shown respectively in Fig. 5 a and 5b.

The sectional view of the correcting principle provided according to a third embodiment of the present invention is shown respectively in Fig. 6 a to 6c.

The stress simulation data that the semiconductor structure provided according to a first embodiment of the present invention is shown respectively in Fig. 7 a to 7c are sat It marks on a map.

Fig. 8 shows the inline experimental data coordinate diagram of the semiconductor structure provided according to a first embodiment of the present invention.

Specific embodiment

Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.

It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another Layer, another region " following " or " lower section ".

If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario Above " or " ... abut above and therewith " form of presentation.

Many specific details of the invention, such as structure, material, size, the processing work of device is described hereinafter Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press The present invention is realized according to these specific details.

In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads The general designation of body structure, including all layers formed or region.Hereinafter, unless otherwise indicated, " semiconductor structure " refers to Be the intermediate structure for including chip and the rhythmic structure of the fence formed thereon.

The inventors of the present application found that forming the semiconductor after rhythmic structure of the fence on chip in 3D memory device Structure is easy to happen warpage, as a result, the coating (for example, wiring layer) and conductive channel subsequently formed is difficult to and runs through gate stack The channel column of structure is aligned, and may make wafer that the more serious problems such as fragment occur.The warpage of semiconductor structure makes most End form at 3D memory device yield and reliability reduce.As the number of plies of grid conductor in rhythmic structure of the fence increases, such as 64 layers are increased to from 32 layers, the stress accumulated in semiconductor structure also will increase, and cause warpage increasingly severe.Therefore, it improves It is exactly to correct the warpage of semiconductor structure that the storage density of 3D memory device, which needs the major issue solved, flat to regain Whole surface.

Existing sectional warping theory method includes thermal annealing, the additional stress film of deposition, carries out additional erosion to back surface of the wafer It carves.Stress can be discharged using thermal annealing and additional etch, so that semiconductor structure regains even curface.However, hot Annealing may cause dopant in the doped region formed in chip in itself and spreads again, be formed in chip to damage Cmos circuit, additional etch then may cause the mechanical strength deterioration of chip, to be broken in the next steps.Using attached The stress film added can offset original stress in semiconductor structure, however, the material selection of stress film and thickness control are necessary It is highly precisely controlled, the difficulty realized so as to cause technique.

Present inventor notices that above-mentioned existing sectional warping theory method is not met by the 3D storage of high storage density The demand of device even results in the new problem of the yield and reliability that influence 3D memory device, and especially above-mentioned existing method is only It is only applicable to isotropic sectional warping theory.However, the semiconductor structure used in the manufacturing method of 3D memory device is stuck up Song is in practice likely to be directive.Above-mentioned existing method cannot correct anisotropic warpage.Thus, the hair of the application Bright people proposes further improved sectional warping theory method, which is applicable not only to 3D memory device, is also applied for various The semiconductor structure of type.

The present invention can be presented in a variety of manners, some of them example explained below.

The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string Number of memory cells can be to be any number of, for example, 32 or 64.

As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line BL, and second end is connected to source electrode line SL.It deposits Storage unit string 100 includes the multiple transistors being connected in series between the first end and a second end, comprising: first choice transistor Q1, memory transistor M1 to M4 and the second selection transistor Q2.The grid of first choice transistor Q1 is connected to string selection line The grid of SSL, the second selection transistor Q2 are connected to the ground selection line GSL.The grid of memory transistor M1 to M4 is respectively connected to The respective word of wordline WL1 to WL4.

As shown in Figure 1 b, the first choice transistor Q1 of memory cell string 100 and the second selection transistor Q2 are respectively included Grid conductor 122 and 123, memory transistor M1 to M4 respectively include grid conductor 121.Grid conductor 121,122 and 123 with deposit The stacking order of transistor in storage unit string 100 is consistent, is separated each other using interlayer insulating film between adjacent grid conductor, To form rhythmic structure of the fence.Further, memory cell string 100 includes channel column 110.Channel column 110 runs through gate stack knot Structure.In the middle section of channel column 110, tunneling medium layer 112, charge storage are accompanied between grid conductor 121 and channel layer 111 Layer 113 and block media layer 114, to form memory transistor M1 to M4.At the both ends of channel column 110,122 He of grid conductor Block media layer 114 is accompanied between 123 and channel layer 111, to form first choice transistor Q1 and the second selection transistor Q2。

In this embodiment, channel layer 111 is for example made of DOPOS doped polycrystalline silicon, tunneling medium layer 112 and block media layer 114 are made of oxide respectively, such as silica, and charge storage layer 113 is by the insulating layer comprising quantum dot or nanocrystal Composition, such as the silicon nitride of the particle comprising metal or semiconductor, grid conductor 121,122 and 123 are made of metal, such as Tungsten.Channel layer 111 is used to provide the channel region of control selection transistor and memory transistor, the doping type of channel layer 111 and choosing It is identical with the type of memory transistor to select transistor.For example, for the selection transistor and memory transistor of N-type, channel layer 111 It can be the polysilicon of n-type doping.

In this embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer Block media layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of channel column 110 is attached The insulating layer added, channel layer 111, tunneling medium layer 112, charge storage layer 113 and block media layer 114 are formed around core Laminated construction.

In this embodiment, first choice transistor Q1 and the second selection transistor Q2, memory transistor M1 to M4 are used Public channel layer 111 and block media layer 114.In channel column 110, channel layer 111 provides the source-drain area of multiple transistors And channel layer.In alternate embodiments, step independent of one another can be used, first choice transistor Q1 and the is respectively formed The semiconductor layer and block media layer of two selection transistor Q2 and the semiconductor layer and block media of memory transistor M1 to M4 Layer.

In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling efficiency Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, ground selection line GSL is biased to greatly About zero volts, so that the selection transistor Q2 for corresponding to ground selection line GSL is disconnected, string selection line SSL is biased to high voltage VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SSL.Further, bit line BIT2 is grounded, wordline WL2 biasing In program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor M2's Word line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 is reached via tunneling medium layer 112 Charge storage layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.

In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example, Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2 Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL The on state of transistor M2, to obtain the data stored in memory transistor M2.

Fig. 2 shows the perspective views of 3D memory device.For the sake of clarity, it is not shown in Fig. 2 each in 3D memory device A insulating layer.

The 3D memory device shown in this embodiment includes that 4*4 amounts to 16 memory cell strings 100, each storage unit String 100 includes 4 storage units, to form the memory array that 4*4*4 amounts to 64 storage units.It is appreciated that this hair Bright without being limited thereto, 3D memory device may include any number of memory cell strings, for example, 1024, in each memory cell string Number of memory cells can be to be any number of, for example, 32 or 64.

In 3D memory device, memory cell string respectively includes respective channel column 110 and public grid conductor 121,122 and 123.Grid conductor 121,122 and 123 is consistent with the stacking order of transistor in memory cell string 100, adjacent Grid conductor between separated each other using interlayer insulating film, to form rhythmic structure of the fence 120.It is exhausted interlayer is not shown in the figure Edge layer.

The internal structure of channel column 110 is as shown in Figure 1 b, is no longer described in detail herein.Channel column 110 is folded through grid Layer structure 120, and it is arranged in array, the first end of multiple channel columns 110 of same row is commonly connected to same bit line (i.e. One of bit line BL1 to BL4), second end is commonly connected to chip 101, and second end forms common source via chip 101 and connects.

The grid conductor 122 of first choice transistor Q1 is divided into difference by grid line gap (gate line slit) 102 Grid line.With multiple channel columns 110 of a line grid line be commonly connected to same string selection line (i.e. string selection line SSL1 extremely One of SSL4).

The grid conductor 121 of memory transistor M1 and M4 are respectively connected to corresponding wordline.If memory transistor M1 and The grid conductor 121 of M4 is divided into different grid lines by grid line gap 161, then the grid line of same level is via respective conductive logical Road 131 reaches interconnection layer 132, thus it is interconnected amongst one another, then same wordline (i.e. wordline WL1 is connected to via conductive channel 133 One of to WL4).

The grid conductor of second selection transistor Q2 links into an integrated entity.If the grid conductor of the second selection transistor Q2 123 are divided into different grid lines by grid line gap 161, then grid line reaches interconnection layer 132 via respective conductive channel 131, from And it is interconnected amongst one another, then via with the being connected to same selection line GSL of conductive channel 133.

Fig. 3 a to 3e shows the sectional view in each stage of the correcting principle manufacturing method of the embodiment of the present invention, the section Figure is intercepted along AA line in Fig. 1.

The present invention starts from being formed the semiconductor structure 100 including chip and rhythmic structure of the fence, and notacoria 201 is in semiconductor junction Structure 100 abuts below and therewith, as shown in Figure 3a.

Rhythmic structure of the fence is located at the top of semiconductor structure 100, the i.e. first surface of semiconductor structure 100.Gate stack knot Grid conductor of the structure for example including many levels and by the grid conductor of adjacent level interlayer insulating film separated from each other.Scheming In the details of rhythmic structure of the fence 120 is not shown, however, the grid that rhythmic structure of the fence 120 may further include many levels is led Body and interlayer insulating film are separated from each other between adjacent grid conductor by interlayer insulating film.Grid conductor is for example made of tungsten, layer Between insulation layers be such as made of silica.Notacoria 201 is located at the lower section of semiconductor structure 100, i.e. the second of semiconductor structure 100 Surface, notacoria 201 and semiconductor structure 100 are adjacent.Chip is, for example, silicon single crystal wafer, in other specific embodiments, institute Stating chip can also be other wafers of semiconductor material, such as silicon-on-insulator (SIO) etc..

Further, semiconductor structure 100 is overturn, according to the directionality designing mask figure of the warpage of semiconductor structure 100 Case, as shown in Figure 3b.

Before designing mask pattern, the surface warp of semiconductor structure 100 is measured.For example, being surveyed using surface topography The surface topography parameters of instrument measurement semiconductor structure 100 are measured, to obtain the surface of semiconductor structure 100 in a plurality of directions Angularity.In alternate embodiments, it is pre-formed linear mark in the dicing lane of semiconductor structure 100, then according to straight line The deflection and shape of label obtain the angularity of the surface of semiconductor structure 100 in a plurality of directions.The semiconductor structure 100 Angularity be deflection of the surface of the semiconductor structure 100 in stacking direction relative to main surface.The warpage of the first kind E.g. negative deflection, the i.e. surface of semiconductor structure 100 are recessed relative to main surface.The warpage of Second Type is, for example, positive becomes Shape amount, the i.e. surface of semiconductor structure 100 are relative to main surface protrusion.In this application, using the periphery of semiconductor structure 100 Region defines main surface.Therefore, which is deflection of the intermediate region relative to neighboring area of semiconductor structure 100. Since the multiple directions on the surface of semiconductor structure 100 measure angularity, which can also measure warpage Directionality.If angularity in a plurality of directions is identical, the surface warp of semiconductor structure 100 is isotropic.Such as The angularity of fruit in a plurality of directions is different, then the surface warp of semiconductor structure 100 is anisotropic.

Mask 202 is, for example, the photoresist mask being covered on notacoria 201, or positioned above notacoria 201 Block masks (such as sheet metal).

According to the shape of the measurement result designing mask 202 of warpage, if the surface warp of semiconductor structure 100 be it is each to The same sex, then the mask of isotropism pattern, such as the mask of circular ring shape, circular pattern can be used, or without using any Mask.If the surface warp of semiconductor structure 100 be it is anisotropic, can use anisotropy pattern mask, cover Center asymmetric distribution of the mould about semiconductor structure 100, mask are, for example, rectangle, polygon, ellipse or any combination thereof The mask of the pattern of formation is designed according to the etched figure to be formed on 201 back side of notacoria.

Further, etching notacoria 201 exposes the part of the surface of semiconductor structure 100 to form opening 203, such as schemes Shown in 3c.

The shape of opening 203 and distribution are controlled by mask 202, and in this embodiment, be open 203 tables from notacoria 201 Face extends to the second surface of semiconductor structure 100.For example, by using gas phase etching, opening 203 is formed.For example, by notacoria exposure In hydrogen fluoride gas, hydrogen fluoride gas carries out gas phase etching reaction as etchant in process cavity, and makes to protect in process cavity Low-pressure state is held so that the water that reaction generates exists in a gaseous form.Preferably, mask 202 is removed after the etching, such as is adopted Made with dry etching, such as ion beam milling etching, plasma etching, reactive ion etching, laser ablation by controlling etching period 201 surface of notacoria must be etched in nearby to stop.In other embodiments, opening 203 can extend to the inside of notacoria 201 Any position.

Further, stressor layers 204 are formed in opening 203, so that the surface recovery of semiconductor structure is to smooth shape, such as Shown in Fig. 3 d.

The method for forming stressor layers 204 is, for example, atomic layer deposition (Atomic Layer Deposition, ALD), physics Be vapor-deposited (Physical Vapor Deposition, PVD) or chemical vapor deposition (Chemical Vapor Deposition, CVD), preferred using plasma chemical vapor deposition.

In this embodiment, the material of stressor layers 204 is the material with low stress, and stressor layers 204 are for example, amorphous Carbon, the stressor layers 204 with low stress have the opening 203 of different pattern by filling, to discharge semiconductor structure in the side X/Y To stress, achieve the purpose that restore semiconductor structure to flat surface.In alternative embodiment, the material of stressor layers 204 Can also have shrinkage stress or expansion stresses, to apply stress to the semiconductor structure 100, for example, the material of stressor layers 204 Material includes at least one of silicon nitride, silica, silicon oxynitride, polysilicon, agraphitic carbon and aluminium oxide.Work as stressor layers 204 when having shrinkage stress, and the semiconductor structure 100 has edge, and rearwardly direction is bent, and center becomes to positive protrusion Gesture.When stressor layers 204 have expansion stresses, there is the semiconductor structure 100 edge to be bent to positive direction, and center is supported or opposed The trend of face protrusion.During due to forming rhythmic structure of the fence on the front of semiconductor structure 100, wafer frontside can be applied Add stress, causes semiconductor structure that warpage occurs.It can select to have and properly answer according to the warpage type of semiconductor structure 100 The stressor layers 204 of power so that semiconductor structure 100 restores flat, or the warped state of semiconductor structure 100 are adjusted to respectively The consistent symmetry warped structures of direction warpage degree.In this embodiment, stressor layers 204 also cover the whole table of notacoria 201 Face further increases the stress to 100 back side of semiconductor structure.

Preferably, it is formed after stressor layers 204 in opening 203, forms thin film 205 in stress layer surface, make to answer The surfacing of power layer 204.Film 205 is, for example, oxidation film, and the thickness of oxidation film should not influence the macroscopic view of semiconductor structure 100 Stress.

Preferably, after forming the oxidation film for being located at 204 surface of stressor layers, stress layer material is made annealing treatment. Annealing can individually carry out after forming stressor layers, can also carry out in the subsequent technique of 3D memory device.May be used also With technological parameter by adjusting annealing, such as annealing time, temperature etc., shrinking percentage or spreading rate to stressor layers are carried out Adjustment, to adjust the stress intensity of stressor layers 204.

Further, semiconductor structure 100 is overturn, and planarization process is carried out to semicon-ductor structure surface, such as Fig. 3 e institute Show.Semiconductor structure is carried out for example, by using chemically mechanical polishing (Chemical Mechanical Polishing, CMP) flat Smoothization processing.

The sectional view of the correcting principle provided according to a first embodiment of the present invention is shown respectively in Fig. 4 a and 4b.The sectional view It is intercepted along the direction parallel with semiconductor structure, the cutting plane of sectional view passes through notacoria 201.First embodiment of the invention provides With the 3D memory device of equally distributed rectangular stress layer in notacoria.

As shown in fig. 4 a, equally distributed rectangular aperture is formed on notacoria 201, and stress is formed in rectangular aperture Layer 204.Along the X direction, width direction along the Y direction, is uniformly distributed, with being formed along X the length direction of rectangular aperture in the Y direction The stressor layers that direction extends, to correct the warpage of semiconductor structure in the Y direction.

As shown in Figure 4 b, equally distributed rectangular aperture is formed on notacoria 201, and stress is formed in rectangular aperture Layer 204.Along the Y direction, width direction along the X direction, is uniformly distributed, with being formed in X-direction along Y the length direction of rectangular aperture The stressor layers that direction extends, to correct the warpage of semiconductor structure in the X direction.

The sectional view of the correcting principle provided according to a second embodiment of the present invention is shown respectively in Fig. 5 a and 5b.The sectional view It is intercepted along the direction parallel with semiconductor structure, the cutting plane of sectional view passes through notacoria 201.Second embodiment of the invention provides The correcting principle of rectangular stress layer in notacoria with non-uniform Distribution.

As shown in Figure 5 a, the cross section that non-uniform Distribution is formed on notacoria 201 is the opening of rectangle, and in opening Form stressor layers 204.Along the X direction, width direction is along the Y direction, non-equal in the Y direction to be formed for the length direction of rectangular aperture Even distribution, the stressor layers extended in X direction, to correct the non-homogeneous warpage of semiconductor structure in the Y direction.

As shown in Figure 5 b, on notacoria 201 shape it is non-at equally distributed cross section be rectangle opening, and in opening Form stressor layers 204.Along the Y direction, width direction is along the X direction, non- to be formed in X-direction for the length direction of rectangular aperture Even distribution, the stressor layers extended along Y-direction, to correct the non-homogeneous warpage of semiconductor structure in the X direction.

The sectional view of the correcting principle provided according to a third embodiment of the present invention is shown respectively in Fig. 6 a to 6c.The sectional view It is intercepted along the direction parallel with semiconductor structure, the cutting plane of sectional view passes through notacoria 201.Third embodiment of the invention provides The correcting principle of stressor layers in notacoria with circular ring shape, rectangle and any combination thereof.

As shown in Figure 6 a, the opening that cross section is circular ring shape is formed on notacoria 201, the center of circle of annulus is located at semiconductor junction The center of structure, and stressor layers 204 are formed in opening.The stressor layers 204 of circular ring shape are to correct semiconductor structure respectively to same The warpage of property.

As shown in Figure 6 b, the opening that multiple cross sections are rectangle is formed on notacoria 201, and stress is formed in opening Layer 204.Multiple rectangular apertures are distributed in the surface any position of notacoria, can design rectangle according to the warpage properties of semiconductor structure The distributing position of opening.Stressor layers 204 are to correct the anisotropic warpage of semiconductor structure.

As fig. 6 c, multiple cross sections not of uniform size are formed on notacoria 201 and are the opening of rectangle, and are being opened Stressor layers 204 are formed in mouthful.Multiple rectangular apertures not of uniform size are distributed in the surface any position of notacoria, can be according to half The distributing position of the warpage properties design rectangular aperture of conductor structure.Stressor layers 204 are anisotropic to correct semiconductor structure Warpage.

However, the present invention is not limited to this, in other embodiments, the cross section of opening can also for polygon, Poroid, the strip of the shapes such as rectangle, arc, annular and these shape any combination of the shapes such as annular.

The stress simulation data that the semiconductor structure provided according to a first embodiment of the present invention is shown respectively in Fig. 7 a to 7c are sat It marks on a map.The sectional view of the 3D memory device is as shown in fig. 4 a.

Fig. 7 a shows stress that the semiconductor structure discharges in the Y direction with the situation of change of the spacing of stressor layers.Such as figure Shown in 7a, the stress release on specific direction can be realized by adjusting the spacing of stressor layers, reach and repair some certain party To warpage purpose.The spacing of stressor layers is bigger, and the variable quantity of warpage is bigger.

Fig. 7 b show the semiconductor structure respectively X, the warpage of Y-direction and warpage when not forming correcting principle with The situation of change of notacoria thickness.As shown in Figure 7b, which has when not forming correcting principle (NO Trench) Biggish warpage.After being modified in the Y direction, the warpage of Y-direction is obviously inhibited, and the warpage of X-direction slightly reduces, but is changed It is unobvious, illustrate that the correcting principle of the embodiment of the present invention can effectively correct warpage on some specific direction, and can be with The amendment to different degrees of warpage is realized by adjusting the thickness of notacoria.Warpage is bigger, and required notacoria thickness is thicker.

Fig. 7 c show the semiconductor devices respectively X, Y-direction warpage with stressor layers insertion notacoria depth variation Situation.As shown in Figure 7 c, the warpage of X-direction is little with the variable quantity of stressor layers insertion notacoria depth, and Y-direction is inserted into stressor layers The variable quantity of notacoria depth is particularly evident, therefore the depth that can be inserted into notacoria by adjusting stressor layers carrys out the big of proof stress It is small.Wherein, the depth of stressor layers insertion notacoria is deeper, and the variable quantity of warpage is bigger.

Fig. 8 is shown provides the inline experimental data coordinate diagram of semiconductor structure according to a first embodiment of the present invention.The 3D is deposited The sectional view of memory device is as shown in fig. 4 a.

As shown in figure 8, warpage of the correcting principle in the direction X-Y is zero before correcting semicon-ductor structure surface warpage, repair The surface of positive structure is plane.After in conjunction with the semiconductor structure with warpage, warpage of the correcting principle in the direction X-Y is -67. The change of the warpage of correcting principle shows that the correcting principle can effectively correct the anisotropy warpage of semiconductor structure.

In the above description, the technical details such as composition, the etching of each layer are not described in detail.But It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method. In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous Ground is used in combination.

The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention Within the scope of.

Claims (14)

1. a kind of surface correcting principle of semiconductor structure, comprising:
Notacoria, the notacoria are located at the surface of semiconductor structure and abut therewith;And
Stressor layers, the stressor layers and the notacoria are adjacent.
2. correcting principle according to claim 1, wherein include opening in the notacoria, the stressor layers are located at described In opening.
3. correcting principle according to claim 1, wherein the semiconductor structure include chip and be located at the chip The rhythmic structure of the fence of first surface,
The notacoria is located at the second surface of the chip, and the first surface and second surface of the chip are relative to each other.
4. correcting principle according to claim 2, wherein the quantity of the opening is at least one, the shape of the opening Shape includes polygon, circle, annular and any combination thereof.
5. correcting principle according to claim 2, wherein central symmetry point of the opening about the semiconductor structure Cloth.
6. correcting principle according to claim 2, wherein the opening is asymmetric about the center of the semiconductor structure Distribution.
7. correcting principle according to claim 2, wherein the opening extends to the notacoria from the surface of the notacoria Inside any depth.
8. correcting principle according to claim 2, wherein the opening runs through the notacoria, extends to the semiconductor The surface of structure.
9. correcting principle according to claim 1, wherein the material of the stressor layers includes the material with shrinkage stress At least one of material, the material with expansion stresses and material with low stress.
10. correcting principle according to claim 1, wherein the surface of the stressor layers is covered with film, the film Thickness does not influence the macro-stress of the semiconductor structure.
11. a kind of surface modification method of semiconductor structure, comprising:
Notacoria is formed, the notacoria is located at the surface of semiconductor structure and abuts therewith;
Form the opening being located on the notacoria;And
The stressor layers being located in the opening are formed, to restore to even curface.
12. modification method according to claim 11, wherein formed be located at the notacoria on opening the step of include:
Measure the surface warp of the semiconductor structure;
According to the directionality designing mask pattern of warpage;And
The notacoria is etched, the opening being located on the notacoria is formed.
13. modification method according to claim 11, further includes: film is formed on the surface of the stressor layers, it is described thin The thickness of film does not influence the macro-stress of the semiconductor structure.
14. modification method according to claim 11, after forming the stressor layers being located in the opening, further includes: Planarization process is carried out to the surface of the semiconductor structure, the planarization process includes chemically mechanical polishing.
CN201811356888.7A 2018-11-15 2018-11-15 The surface correcting principle and modification method of semiconductor structure CN109524312A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040241946A1 (en) * 2003-03-24 2004-12-02 Won-Jin Kim Methods of fabricating a semiconductor substrate for reducing wafer warpage
CN201758117U (en) * 2010-06-22 2011-03-09 中微半导体设备(上海)有限公司 Structure capable of reducing stress
CN104253127A (en) * 2013-06-25 2014-12-31 台湾积体电路制造股份有限公司 Integrated circuit with backside structures to reduce substrate wrap
US20160327743A1 (en) * 2015-05-05 2016-11-10 Ecole polytechnique fédérale de Lausanne (EPFL) Waveguide Fabrication Method
CN106298683A (en) * 2015-06-24 2017-01-04 华亚科技股份有限公司 Semiconductor device
CN108649021A (en) * 2018-07-19 2018-10-12 长江存储科技有限责任公司 Silicon wafer warpage adjusts structure and forming method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040241946A1 (en) * 2003-03-24 2004-12-02 Won-Jin Kim Methods of fabricating a semiconductor substrate for reducing wafer warpage
CN201758117U (en) * 2010-06-22 2011-03-09 中微半导体设备(上海)有限公司 Structure capable of reducing stress
CN104253127A (en) * 2013-06-25 2014-12-31 台湾积体电路制造股份有限公司 Integrated circuit with backside structures to reduce substrate wrap
US20160327743A1 (en) * 2015-05-05 2016-11-10 Ecole polytechnique fédérale de Lausanne (EPFL) Waveguide Fabrication Method
CN106298683A (en) * 2015-06-24 2017-01-04 华亚科技股份有限公司 Semiconductor device
CN108649021A (en) * 2018-07-19 2018-10-12 长江存储科技有限责任公司 Silicon wafer warpage adjusts structure and forming method thereof

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