TW201701429A - Wafer level package and fabrication method thereof - Google Patents

Abstract

A semiconductor device includes a chip having an active surface and a rear surface that is opposite to the active surface; a molding compound covering and encapsulating the chip except for the active surface; a redistribution layer (RDL) on the active surface and on the molding compound, wherein the RDL is electrically connected to the chip; and a stress-relief features embedded in the molding compound.

Description

Wafer level package and manufacturing method thereof

The present invention relates to the field of semiconductor packaging technology, and more particularly to a wafer level package (WLP) having stress-relief features disposed on the upper portion of a molding compound. .

Wafer level packaging processes are well known to those skilled in the art. In a wafer-level packaging process, the wafer containing the integrated circuit formed therein or the wafer mounted thereon is subjected to a series of processes such as grinding, die-alignment bonding, and die-molding, and finally, the final product is cut. . Today's industry is widely recognized as a wafer-level packaging process that is best suited for small-scale and high-speed chip packaging.

Typically, when wafer level packaging is performed, a relatively thick molding compound is used to cover the wafer and the die mounted on the wafer. Since the coefficient of thermal expansion (CTE) of the molding material differs from that of the wafer, the package formed of a molding material having a certain thickness is easily warped when subjected to heat change. Moreover, the presence of the molding die also increases the overall thickness of the package. The problem of wafer warpage has been an attempt by technicians in the field.

Wafer warpage makes it difficult to maintain the connection between the die and the wafer, resulting in failure of the die-to-wafer stack assembly. The warpage problem is even more pronounced on large-size wafers, making wafer-level packaging of large-size wafers more difficult. Therefore, the industry still needs an improved wafer level packaging method that can solve the above prior art problems.

SUMMARY OF THE INVENTION A primary object of the present invention is to provide an improved semiconductor device that can alleviate or eliminate the problem of wafer or package warpage and provide better reliability of the resulting semiconductor package.

An embodiment of the present invention provides a semiconductor device including a wafer having an active surface and a back surface opposite to the active surface; a molding die covering a portion of the wafer other than the active surface; and a redistribution layer And disposed on the active surface and the molding die, wherein the redistribution layer is electrically connected to the wafer; and a stress relieving structural feature is embedded in the molding die.

According to an embodiment of the invention, the semiconductor device further includes a through via (TSV) interposer connected to the redistribution layer. A plurality of solder balls are disposed on a bottom surface of the TSV interposer for subsequent connection, for example, to a motherboard or a printed circuit board.

It will be apparent to those skilled in the art that the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

The detailed description that follows is to be understood by reference to the accompanying drawings,

These embodiments provide sufficient detail to enable those skilled in the art to fully understand and practice the invention. Structural, logical, and electrical modifications may be applied to other embodiments without departing from the scope of the invention.

Therefore, the following detailed description is not to be construed as limiting. The scope of the invention is defined by the claims. It is also within the scope of the present invention to have the same meaning as the claims of the present invention.

The drawings referred to in the embodiments of the present invention are schematic and not drawn to scale, and the same or similar features are generally described with the same reference numerals.

In the present specification, "die", "semiconductor wafer" and "semiconductor die" have the same meaning and may be used interchangeably.

In the present specification, "wafer" and "substrate" mean any structure including an exposed face on which a material can be deposited and a rewiring layer (RDL) circuit structure such as the embodiment of the present invention is fabricated.

It should be understood that the "substrate" includes a semiconductor wafer, but is not limited thereto. In the process, "substrate" is also used to mean a semiconductor structure comprising a layer of material fabricated thereon.

In this specification, the term "through-via via (TSV)" is broadly defined to include holes or perforations in the die of any wafer or integrated circuit that are filled with a conductive filler material (eg, copper or tungsten). Waiting for metal). The TSV vias provide electrical connections from the bottom surface of the wafer or integrated circuit die to the contact layer or any metal interconnect layer on the top side of the wafer or on the surface of the wafer.

Please refer to Figures 1 to 8. 1 through 8 are schematic cross-sectional views illustrating a method of fabricating a wafer level package having a through substrate via (TSV) in accordance with an embodiment of the present invention.

As shown in FIG. 1, a wafer 100 is first provided. The wafer 100 includes a germanium wafer, a semiconductor wafer, or an interposer wafer, but is not limited thereto. For example, wafer 100 can be an interposer wafer. The wafer 100 has a front side 100a and a back side 100b opposite to the front side 100a. On the front surface 100a of the wafer 100, a plurality of through-holes 102 are formed.

Methods of making through-holes 102 are well known to those of ordinary skill in the art. For example, the method of fabricating the through vias 102 includes first forming a TSV hole at a predetermined depth from the front surface 100a of the wafer 100 at a predetermined depth, and then depositing a metal layer, such as a diffusion barrier metal layer, in the TSV holes. With copper layer, but not limited to this. A polishing process is then performed on the front side 100a of the wafer 100 to remove excess metal layers outside the TSV holes.

Next, as shown in FIG. 2, a redistribution layer (RDL) 110 is formed on the front surface 100a of the wafer 100. The redistribution layer 110 may include at least one dielectric layer 112 and at least one metal layer 114. The through via 102 can be electrically connected to the metal layer 114. The redistribution layer 110 may include a build-up interconnect structure.

Next, a plurality of bumps 116, such as micro-bumps, are formed on the redistribution layer 110 for subsequent connections. The bumps 116 may be formed directly on the contact pads of the metal layer 114, respectively.

As shown in FIG. 3, after the bumps 116 are formed, the individual flip chip or die 120 is then actively face down, and the bumps 116 are mounted on the redistribution layer 110 to obtain a wafer-to-wafer stack. structure. A plurality of output/input (I/O) pads 121 are disposed on the active faces of the respective wafers or die 120. When mounted, the bumps 116 are aligned with the output/input pads 121.

Next, a primer 118 can be selectively filled between each wafer or die 120 and the front side 100a of the wafer 100. Then, a heat treatment is performed to re-weld the bumps 116.

As shown in FIG. 4, after the die bonding is completed, a molding die 200 is then overlaid on the front surface 100a of the wafer 100. The molding die 200 covers the bonded wafer or die 120 and covers the upper surface of the redistribution layer 110. Next, the molding die 200 can be subjected to a curing process.

According to the illustrated embodiment, the molding die 200 can be formed using, for example, a transfer mold and a thermosetting compound. Other means can be used to dispense the molding compound. Epoxy resins, resins and compounds that are liquid at elevated temperatures or ambient temperatures can also be used. Molding molding 200 is an electrical insulator and may be a thermal conductor. Different fillers may be added to enhance the heat transfer, stiffness or adhesion properties of the molding die 200.

As shown in FIG. 5, after the molding die 200 is formed, a plurality of grooves 202 are continuously formed in the upper portion of the molding die 200. The trench 202 may be formed by cutting, wire saw, laser, or etching, but is not limited thereto. According to the illustrated embodiment, the trench 202 can be directly over the wafer or die 120.

9A through 9C are schematic top views showing some exemplary layouts of the trenches 202 on the molding die 200. As shown in FIG. 9A, the trenches 202 may be arranged in a grid pattern. As shown in FIG. 9B, the trenches 202 can be arranged in separate hole patterns. As shown in FIG. 9C, the trenches 202 may be arranged in a concentric circular pattern. However, it should be understood that other patterns may be employed depending on design requirements.

As shown in FIG. 6, subsequently, stress relieving structural features 204 are formed in each of the trenches 202 of the molding die. In accordance with the illustrated embodiment, the stress relief structure feature 204 can completely fill the trench 202. The stress relief structural feature 204 can include an elastomeric material having a relatively low Young's Modulus. For example, the above elastic material may include an organic material such as a photoresist, a polyimide or a benzocyclobutene.

As shown in FIG. 7, after forming the molding die 200 and the stress relaxation structure feature 204, the wafer 100 is subjected to a crystal back grinding process to polish a portion of the wafer 100 from the back surface 100b to form a TSV interposer. 101. For example, wafer 100 can be loaded first into a wafer grinder (not shown). Then, the polishing pad is brought into contact with the back surface 100b of the wafer 100, and the back surface 100b is started to be polished. The above-described polishing process reduces the thickness of the wafer 100 to expose the lower end of the through-hole 102.

As shown in FIG. 8, the metallization process can continue on the back side 100b of the wafer 100 to form a plurality of bump pads 210 in the insulating layer 212. Solder bumps or solder balls 220 may then be formed on each of the bump pads 210. The wafer 100 can then be diced into individual wafer level packages 10 that are separated from one another.

According to the illustrated embodiment, the stress relief structure feature 204 embedded in the upper portion of the molding die 200 can improve or avoid warpage of the wafer 100 at the wafer level or at the wafer level.

Please refer to Figures 10 to 17. 10 through 17 are schematic cross-sectional views illustrating a method of fabricating a wafer level package in accordance with another embodiment of the present invention.

As shown in FIG. 10, a carrier 300 is provided which may be a tearable substrate material and may have an adhesive layer 302 thereon. At least one dielectric layer 310 may be formed on the carrier 300.

As shown in FIG. 11, next, a redistribution layer (RDL) 410 is formed on the dielectric layer 310. The redistribution layer 410 can include at least one dielectric layer 412 and at least one metal layer 414. Next, a plurality of bumps 416, such as micro-bumps, are formed on the redistribution layer 410 for subsequent connections. Bumps 416 can be formed directly on the contact pads of metal layer 414, respectively.

As shown in FIG. 12, after the bumps 416 are formed, the individual flip chip or die 420 is then actively face down, and the bumps 416 are mounted on the redistribution layer 410 to obtain a wafer-to-wafer overlap. structure. A plurality of output/input (I/O) pads 421 are provided on the active faces of the respective wafers or dies 420, and the bumps 416 are aligned with the output/input pads 421 during mounting. Next, a primer 418 can be optionally filled under each wafer or die 420. Then, a heat treatment is performed to re-weld the bumps 416.

As shown in Fig. 13, after the die bonding is completed, a molding die 500 is next covered. The molding die 500 covers the bonded wafer or die 420 and covers the upper surface of the redistribution layer 410. Next, the molding die 500 can be subjected to a curing process.

As shown in Fig. 14, after the molding die 500 is formed, a plurality of grooves 502 are continuously formed in the upper portion of the molding die 500. The trench 502 may be formed by cutting, wire saw, laser, or etching, but is not limited thereto. According to the illustrated embodiment, the trench 502 can be directly over the wafer or die 420.

As shown in FIG. 15, subsequently, stress relieving structural features 504 are formed in each of the grooves 502 of the molding die 500. In accordance with the illustrated embodiment, the stress relief structural feature 504 can completely fill the trench 502. The stress relief structural feature 504 can include an elastomeric material having a relatively low Young's modulus. For example, the above elastic material may include an organic material such as a photoresist, polyimide or benzocyclobutene.

As shown in FIG. 16, after the molding die 500 and the stress relaxation structure feature 504 are formed, the carrier 300 and the adhesive layer 302 are removed or removed to reveal the dielectric layer 310.

As shown in FIG. 17, the metallization process can continue on the dielectric layer 310 to form a plurality of bump pads 510 in the insulating layer 512. Solder bumps or solder balls 520 may then be formed on each bump pad 510. The process can then be diced to form individual wafer level packages 10 that are separated from one another. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧ Wafer level packaging
100‧‧‧ wafer
100a‧‧‧ positive
100b‧‧‧back
101‧‧‧TSV Intermediary
102‧‧‧through through hole
110, 410‧‧‧Rewiring layer
112, 412‧‧‧ dielectric layer
114, 414‧‧‧ metal layer
116, 416‧‧ ‧ bumps
118, 418‧‧ ‧ primer
120, 420‧‧‧ wafers or grains
121, 421‧‧‧Output/Input (I/O) pads
200, 500‧‧‧ molding materials
202, 502‧‧‧ trench
204, 504‧‧‧ stress mitigation structural features
210, 510‧‧‧ bump pads
212, 512‧‧‧ insulation
220, 520‧‧‧ solder balls
300‧‧‧ Carrier
302‧‧‧Adhesive layer
310‧‧‧Dielectric layer

The drawings provide a more in-depth understanding of this embodiment and are incorporated in this specification. These drawings and description are used to illustrate the principles of some embodiments. 1 through 8 are schematic cross-sectional views illustrating a method of fabricating a wafer level package having through vias in accordance with an embodiment of the present invention. Figures 9A through 9C are schematic top views showing an exemplary layout of the grooves on the molding die. 10 through 17 are schematic cross-sectional views illustrating a method of fabricating a wafer level package in accordance with another embodiment of the present invention.

10‧‧‧ Wafer level packaging

100a‧‧‧ positive

100b‧‧‧back

101‧‧‧TSV Intermediary

102‧‧‧through through hole

110‧‧‧Rewiring layer

112‧‧‧ dielectric layer

114‧‧‧metal layer

116‧‧‧Bumps

118‧‧‧Bottom glue

120‧‧‧ wafer or die

121‧‧‧Output/Input (I/O) pads

200‧‧‧ molding compound

202‧‧‧ trench

204‧‧‧stress mitigation structural features

210‧‧‧Bump pads

212‧‧‧Insulation

220‧‧‧ solder balls

Claims (9)

A semiconductor device comprising: a wafer having an active surface and a back surface opposite to the active surface; a molding die covering a portion of the wafer other than the active surface; a redistribution layer disposed on the On the active surface and the molding die, wherein the redistribution layer is electrically connected to the wafer; and a stress relieving structural feature is embedded in the molding die. The semiconductor device of claim 1, wherein the stress relaxation structure feature is directly above the back surface of the wafer. The semiconductor device according to claim 1, wherein the stress relaxation structure is provided in a plurality of trenches in an upper portion of the redistribution layer. The semiconductor device according to claim 1, wherein the stress relaxation structure is composed of an elastic material having a relatively low Young's modulus. The semiconductor device according to claim 4, wherein the elastic material comprises a photoresist, polyimine or benzocyclobutene. The semiconductor device according to claim 1, wherein the redistribution layer is electrically connected to the wafer via a plurality of bumps. The semiconductor device of claim 1, wherein the redistribution layer comprises at least one dielectric layer and at least one metal layer. The semiconductor device according to claim 1, further comprising a through via (TSV) interposer connected to the redistribution layer. The semiconductor device of claim 8, further comprising a plurality of solder balls disposed on a bottom surface of the TSV interposer.