US20200295023A1 - Vertical memory devices and methods of manufacturing the same - Google Patents
Vertical memory devices and methods of manufacturing the same Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H01L27/11565—
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- H01L27/11568—
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- H01L27/11575—
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- H01L27/11578—
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Abstract
A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.
Description
- This application is a continuation of U.S. application Ser. No. 15/401,486, filed on Jan. 9, 2017, and claims priority under 35 USC § 119 to Korean Patent Application No. 10-2016-0043335 filed on Apr. 8, 2016 in the Korean Intellectual Property Office (KIPO), the contents of each of which are incorporated by reference herein in their entirety.
- Example embodiments relate to vertical memory devices and methods of manufacturing the same. More particularly, example embodiments relate to vertical memory devices including vertically extending channels and methods of manufacturing the same.
- Recently, a vertical memory device including a plurality of memory cells stacked vertically with respect to a surface of a substrate has been developed in order to achieve a high degree of integration. In the vertical memory device, a channel having a pillar shape or a cylindrical shape may protrude vertically from the surface of the substrate, and gate lines surrounding the channel may be repeatedly stacked in a staircase shape.
- As the degree of integration of the vertical memory device becomes greater, the number of the gate lines, and the number of steps of the staircase shape may increase. Thus, the complexity of the process for forming the steps may increase.
- Example embodiments provide a vertical memory device having enhanced structural and electrical reliability.
- Example embodiments provide a method of manufacturing a vertical memory device having enhanced structural and electrical reliability.
- According to example embodiments, a vertical memory device may include a substrate, a channel, gate lines, and a cutting pattern. The channel is on the substrate and extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are on the substrate and are spaced apart from each other in the first direction. Each of the gate lines may surround the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern may include a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.
- According to example embodiments, a vertical memory device may include a substrate, a plurality of gate line stack structures spaced apart from each other on the substrate, and a common source line (CSL). in a third direction on the substrate, and a common source line (CSL). Each of the gate line stack structures may include a channel extending in a first direction substantially perpendicular to an upper surface of the substrate, and gate lines spaced apart from each other in the first direction. Each of the gate lines may surround the channel and extend in a second direction substantially parallel to the upper surface of the substrate and crossing a third direction. The third direction is substantially parallel to the upper surface of the substrate. The gate line stack structures may be spaced apart from each other in the third direction. The CSL may surround sidewalls of the gate line stack structures along the second and third directions.
- According to example embodiments, a vertical memory device may include
- According to an example embodiment, a vertical memory device includes a substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of vertical channels on the substrate, and a common source line (CSL) on the substrate. The gate lines include end portions that extend different lengths parallel to the upper surface of the substrate to define a staircase shape. The plurality of vertical channels are spaced apart from each other and extend through the plurality of gate lines. The CSL includes first portions that cross into a second portion of the CSL on the substrate, extend through the plurality of gate lines, and are spaced apart from each other. The second portion of the CSL extends through a lowermost one of the plurality of gate lines and is spaced apart from the end portions of the plurality of gate lines.
- In the vertical memory device in accordance with example embodiments, after forming the stepped mold structure, the step portions for the GSL may be simultaneously formed with the opening for the gate line cutting. Thus, the photo mask for forming the stepped mold structure may be reduced. In the opening, the cutting pattern may be formed, and the cutting pattern may include first cutting portions dividing the gate line stack structure, and a second cutting portion crossing the first cutting portions and connecting the first cutting portions to each other. According to the operation design through the gate line stack structure, the first and second cutting portions may be designed.
- Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
FIGS. 1 to 30 represent non-limiting, example embodiments as described herein. -
FIGS. 1 to 3 are a plan view and cross-sectional views illustrating a vertical memory device in accordance with example embodiments; -
FIGS. 4 to 21 are cross-sectional views and plan views illustrating a method of manufacturing a vertical memory device in accordance with example embodiments; -
FIG. 22 is a cross-sectional view illustrating a vertical memory device in accordance with example embodiments; -
FIG. 23 is a cross-sectional view illustrating a vertical memory device in accordance with example embodiments; -
FIG. 24 is a plan view illustrating a vertical memory device in accordance with example embodiments; -
FIGS. 25 and 26 are a plan view and a cross-sectional view illustrating a vertical memory device in accordance with example embodiments; -
FIGS. 27 and 28 are plan views illustrating a vertical memory device in accordance with example embodiments; -
FIG. 29 is a plan view illustrating a vertical memory device in accordance with example embodiments; and -
FIG. 30 is a plan view illustrating a vertical memory device in accordance with example embodiments. - A direction substantially vertical to an upper surface of a substrate is referred to as a first direction, and two directions substantially parallel to the upper surface of the substrate and crossing each other are referred to as second and third directions, respectively. For example, the second direction and the third direction are substantially perpendicular to each other. Additionally, a direction indicated by an arrow and a reverse direction thereof are considered as the same direction. The above mentioned definitions of the directions are the same throughout all the figures in this specification.
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FIGS. 1 to 3 are a plan view and cross-sectional views illustrating a vertical memory device in accordance with example embodiments. Particularly,FIG. 1 is a plan view, andFIGS. 2 and 3 are cross-sectional views taken along lines I-I′ and II-II′, respectively, ofFIG. 1 . - For the convenience of explanations, some elements, e.g., a first
upper insulation layer 140, a secondupper insulation layer 190, aplug 195, etc. are omitted inFIG. 1 . - Referring to
FIGS. 1 to 3 , the vertical memory device may include avertical channel structure 128 extending from an upper surface of asubstrate 100 in the first direction,gate lines 170 andinsulating interlayers 102, which may surround thevertical channel structure 128 and are alternately stacked in the first direction in a staircase shape, acutting pattern 180 cutting thegate lines 170 and theinsulating interlayers 102, and contacts 192 electrically connected to thegate lines 170 in the respective levels. - The
substrate 100 may include a semiconductor material, e.g., silicon, germanium, etc. In some example embodiments, thesubstrate 100 may include single crystalline silicon. For example, thesubstrate 100 may serve as a body for the vertical memory device. In some example embodiments, a p-type well may be formed in thesubstrate 100. - The vertical memory device may have first, second and third regions I, II and III. Thus, the
substrate 100 may be also divided into the first, second and third regions I, II and III (refer toFIG. 2 ). - The first region I may serve as a cell region where the
vertical channel structure 128 may be formed. For example, thevertical channel structure 128 and thegate lines 170 surrounding thevertical channel structure 128 may define a cell string. The second region II may serve as an extension region wherein step portions of thegate lines 170 and thecontacts 192 are formed. The third region III may serve as a dummy region. - In some example embodiments, a pair of second regions II may be symmetrically formed at opposite sides, respectively, of the first region I in the second direction.
- The
vertical channel structure 128 may extend through thegate lines 170 and the insulatinginterlayers 102 in the first direction. As shown inFIG. 2 , thevertical channel structure 128 may directly contact the upper surface of thesubstrate 100. - The
vertical channel structure 128 may include achannel 124, adielectric layer structure 122 and afilling pattern 126. - The
channel 124 may have a cup-like shape. Thechannel 124 may contact the upper surface of thesubstrate 100. The fillingpattern 126 may have a pillar shape in an inner space formed by thechannel 124 having the cup-like shape. Alternatively, thechannel 124 may have a pillar shape, and in this case, the fillingpattern 126 may not be formed. - The
channel 124 may include a semiconductor such as polysilicon or single crystalline silicon, and may include, e.g., p-type impurities such as boron (B) in a portion thereof. The fillingpattern 126 may include an insulation material, e.g., silicon oxide. - The
dielectric layer structure 122 may have a hollow cylindrical shape, which may cover an outer sidewall of thechannel 124. Thedielectric layer structure 122 may include a tunnel insulation layer, a charge storage layer and a blocking layer sequentially stacked from the outer sidewall of thechannel 124. - The tunnel insulation layer may include an oxide, e.g., silicon oxide. The charge storage layer may include a nitride, e.g., silicon nitride or a metal oxide. The blocking layer may include silicon oxide or a metal oxide, e.g., hafnium oxide or aluminum oxide. For example, the
dielectric layer structure 122 may have an oxide-nitride-oxide (ONO) layered structure. - A
capping pad 130 may be formed on thevertical channel structure 128. In example embodiments, thecapping pad 130 may be electrically connected to a bit line of the vertical memory device, and may serve as a source/drain pattern for moving electrons into thechannel 124. Thecapping pad 130 may include a semiconductor (e.g., polysilicon or single crystalline silicon), and may further include n-type impurities, e.g., phosphorus, arsenic, etc. - As illustrated in
FIG. 1 , a plurality of cappingpads 130 may be arranged along the second direction in the first region I such that a capping pad row may be defined, and a plurality of capping pad rows may be arranged in the third direction. Thevertical channel structures 128 may be also arranged according to the arrangement of thecapping pads 130. For example, a plurality ofvertical channel structures 128 may be arranged along the second direction in the first region I to form a channel row, and a plurality of channel rows may be arranged in the third direction. - The capping
pads 130 in neighboring ones of the capping pad rows or thevertical channel structures 128 in neighboring ones of the channel rows may be arranged in a zigzag pattern along the second direction and/or the third direction. Thus, morevertical channel structures 128 may be formed in a unit area of thesubstrate 100. - The gate lines 170 (for example, 170 a˜170 f) may cover an outer sidewall of the
vertical channel structure 128, and may be spaced apart from each other along the first direction. In example embodiments, eachgate line 170 may partially surround thechannels 124 or thevertical channel structures 128 included in at least one of the channel rows and may extend in the second direction. - In some embodiments, each
gate line 170 may surround a given number of channel rows, e.g., 4 channel rows. In this case, a gate line stack structure may be defined by the 4 channel rows and thegate lines 170 surrounding the 4 channel rows. A plurality of gate line stack structures may be arranged along the third direction. However, the number of the channel rows included in the gate line stack structure may be varied according to the circuit design of the vertical memory device. - In example embodiments, widths or lengths of the
gate lines 170 may decrease along the first direction from the upper surface of thesubstrate 100. For example, as illustrated inFIG. 2 , a plurality ofgate lines 170 may be stacked in a pyramidal shape or a staircase shape, and the lengths of thegate lines 170 in the second direction may gradually decrease. - Each of the
gate lines 170 may include a step portion protruding in the second direction from an overlying one of the gate lines 170. The step portion of each of thegate lines 170 may serve as a contact pad for being connected to thecontact 192. The step portions may be disposed in the second region II. - The gate lines 170 may include a ground selection line (GSL), a word line and a string selection line (SSL). For example, a
lowermost gate line 170 a may serve as the GSL. Anuppermost gate line 170 f may serve as the SSL. The gate lines 170 b to 170 e between the GSL and the SSL may serve as the word lines. -
FIGS. 1 to 3 show that thegate lines 170 are disposed at 6 levels, however, thegate lines 170 may be formed at more levels in consideration of a circuit design and a degree of integration of the vertical memory device, e.g., 16 levels, 24 levels, 32 levels, 48 levels, etc. The SSLs may be formed at two or more levels. - The
gate line 170 may include a metal, e.g., tungsten (W), a metal nitride and/or a metal silicide. In some embodiments, thegate line 170 may have a multi-layered structure including a metal nitride, e.g., tungsten nitride, and a metal, e.g., tungsten. - The gate line stack structure may further include the insulating
interlayers 102, e.g., 102 a to 102 g. The insulatinginterlayers 102 may be disposed between neighboring ones of thegate lines 170 in the first direction. The insulatinginterlayers 102 may be stacked along the first direction in a pyramidal shape or a staircase shape substantially the same as or similar to that of the gate lines 170. - Accordingly, each of the insulating
interlayers 102 may also include a step portion corresponding to that of each of the gate lines 170. In example embodiments, as shown inFIG. 2 , the step portions of thegate lines 170 may be covered by those of the insulatinginterlayers 102. - In example embodiments, the
gate line 170 may be covered by aninterface layer 175. Theinterface layer 175 may be formed between thedielectric layer structure 122 and thegate line 170, and between the insulatinginterlayer 102 and thegate line 170. - The
interface layer 175 may be inserted to control the workfunction between thegate line 170 and thechannel 124. Theinterface layer 175 may include, e.g., a metal oxide and/or a metal nitride. The metal oxide may include, e.g., aluminum oxide, and the metal nitride may include titanium nitride, tantalum nitride and/or tungsten nitride. - A
mold protection layer 115 may at least partially cover the gate line stack structure. In example embodiments, themold protection layer 115 may cover the step portions of the gate line stack structure, and may also cover an uppermost insulatinginterlayer 102 g. For example, thecapping pad 130 may be formed in themold protection layer 115. - The first
upper insulation layer 140 may be formed on themold protection layer 115. The firstupper insulation layer 140 may cover thecapping pads 130. For example, the firstupper insulation layer 140 and themold protection layer 115 may include silicon oxide. - An
opening 150 may be formed through the firstupper insulation layer 140 and themold protection layer 115, and may cut thegate lines 170 and the insulatinginterlayers 102. Thecutting pattern 180 may be formed in theopening 150. - In example embodiments, the
opening 150 may include afirst opening portion 150 a and asecond opening portion 150 b, and thecutting pattern 180 may include afirst cutting portion 182 in thefirst opening portion 150 a and asecond cutting portion 184 in thesecond opening portion 150 b. - The
first opening portion 150 a may extend in the second direction through thegate lines 170 and the insulatinginterlayers 102. A plurality of first openingportions 150 a may be formed in the third direction. Thus, thefirst cutting portion 182 may extend in the second direction, and a plurality offirst cutting portions 182 may be formed between neighboring ones of the gate line stack structures. - The
second opening portion 150 b may extend in the third direction, and may be connected to end portions of the plurality of first openingportions 150 a, respectively. Thus, thesecond cutting portion 184 may extend in the third direction, and may be connected to end portions of the plurality offirst cutting portions 182, respectively. The plurality offirst cutting portions 182 may be connected by thesecond cutting portion 184, and the first andsecond cutting portions - In example embodiments, the
lowermost gate line 170 a may be defined by thesecond cutting portion 184. For example, thesecond cutting portion 184 may extend in the third direction, and may restrict thelowermost gate lines 170 a included in different gate line stack structures. For example, the step portion of the GSL of the vertical memory device may be defined by thesecond cutting portion 184. - In some example embodiments, the
second cutting portion 184 may be disposed at a boundary between the second and third regions II and III. For example, the extension region and the dummy region may be divided by thesecond cutting portion 184. - As shown in
FIG. 2 , adummy gate line 171, adummy interface layer 176 and adummy insulating interlayers 102 a′ and 102 b′ may be defined in the third region III by thesecond cutting portion 184. - In example embodiments, the
cutting pattern 180 may serve as a common source line CSL of the vertical memory device. Thecutting pattern 180 may include a metal, e.g., tungsten, copper, aluminum, etc., a metal silicide, a metal nitride and/or doped polysilicon. - A
spacer 185 may be formed on a sidewall of theopening 150. Thecutting pattern 180 may be insulated from thegate lines 170 by thespacer 185. Thespacer 185 may include an insulation material, e.g., silicon oxide. - An upper surface of the
substrate 100 may be exposed by theopening 150, and animpurity region 103 may be formed at an upper portion of thesubstrate 100 exposed by theopening 150. Thecutting pattern 180 may directly contact theimpurity region 103. In some example embodiments, a metal silicide layer including, e.g., nickel silicide, cobalt silicide, etc. may be further formed between the cuttingpattern 180 and theimpurity region 103. - The second
upper insulation layer 190 may be formed on the firstupper insulation layer 140. The secondupper insulation layer 190 may cover thecutting pattern 180 and thespacer 185. For example, the secondupper insulation layer 190 may include, e.g., silicon oxide that may be substantially the same as that of the firstupper insulation layer 140. - The contacts 192 (e.g., 192 a˜192 e) may extend through the second
upper insulation layer 190, the firstupper insulation layer 140, themold protection layer 115 and the insulatinginterlayer 102 in the second region II, and may contact or be electrically connected to the gate lines 170. In some example embodiments, thecontact 192 may extend through theinterface layer 175 to contact an upper surface of thegate line 170. - The
contacts 192 a˜192 e may be electrically connected to step portions of theGSL 170 a and the word lines 170 b˜170 e, respectively. In some example embodiments, a contact electrically connected to theSSL 170 f may be formed in a portion of the second region II opposite to a portion of the second region II shown inFIG. 2 with respect to the first region I. - In some example embodiments, the
contacts 192 may be arranged in a zigzag layout along the second direction in a plan view as shown inFIG. 1 . Thus, distances between neighboring ones of thecontacts 192 may increase so that a process margin for forming thecontacts 192 may be secured. - The
plugs 195 may be formed in the first region I. Theplug 195 may extend through the first and second upper insulation layers 140 and 190, and may contact an upper surface of thecapping pad 130. For example, theplug 195 may serve as a bit line. - The
contact 192 and theplug 195 may include a metal, e.g., tungsten, copper, aluminum, etc., a metal silicide, a metal nitride and/or doped polysilicon. - Bit lines (not shown) and wirings (not shown) electrically connected to the
plugs 195 and thecontacts 192 may be formed on the secondupper insulation layer 190. - In example embodiments, the
cutting pattern 180 serving as a CSL may include first andsecond cutting portions second cutting portion 184 may be commonly provided for the gate line stack structures to define the GSL. An area of the CSL may be increased by thesecond cutting portion 184. Thus, the resistance by the CSL may increase, and the area for the contacts or wirings electrically connected to the CSL may be increased. - In some example embodiments, sidewalls of the gate line stack structure may be completely covered by the first and
second cutting portions - The
second cutting portion 184 may serve as a fence between the extension region and the dummy region. For example, thesecond cutting portion 184 may serve as a structure for blocking stress from the extension region and/or the cell region. -
FIGS. 4 to 21 are cross-sectional views and plan views illustrating a method of manufacturing a vertical memory device in accordance with example embodiments. For example,FIGS. 4 to 21 illustrate a method of manufacturing the vertical memory device illustrated inFIGS. 1 to 3 . - Specifically,
FIGS. 9, 12 and 19 are plan views illustrating the method.FIGS. 4-8, 10-11, 13, 15, 17 and 20 are cross-sectional views taken along a line I-I′ designated in the plan views and along the first direction.FIGS. 14, 16, 18 and 21 are cross-sectional views taken along a line II-II′ designated in the plan views and along the first direction. - Referring to
FIG. 4 , insulating interlayers 102 (e.g., 102 a˜102 g) and sacrificial layers 104 (e.g., 104 a˜104 f) may be alternately and repeatedly formed on asubstrate 100 to form amold structure 105. - The
substrate 100 may include a semiconductor material, e.g., silicon or germanium. In some example embodiments, a p-type well may be formed by implanting p-type impurities into thesubstrate 100. - The insulating
interlayer 102 may be formed of, e.g., silicon oxide. Thesacrificial layer 104 may be formed of a material that may have an etching selectivity with respect to the insulatinginterlayer 102 and may be easily removed by a wet etching process. For example, thesacrificial layer 104 may be formed of silicon nitride. In an example embodiment, thesacrificial layer 104 may be formed of polysilicon. - The insulating
interlayer 102 and thesacrificial layer 104 may be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, an atomic layer deposition (ALD) process or a sputtering process. - The
sacrificial layers 104 may be removed by a subsequent process to provide a space for forming a GSL, word lines and an SSL. Thus, the number of the insulatinginterlayers 102 and thesacrificial layers 104 may be determined in consideration of the number of the GSL, the word lines and the SSL.FIG. 4 illustrates that thesacrificial layers 104 and the insulatinginterlayers 102 are formed at 6 levels and 7 levels, respectively. However, the number of the insulatinginterlayers 102 and thesacrificial layers 104 may increase depending on a degree of integration of the vertical memory device. - Referring to
FIG. 5 , aphotoresist pattern 110 may be formed on an uppermost insulatinginterlayer 102 g. A length of thephotoresist pattern 110, e.g., in the second direction may be reduced by W1 indicated inFIG. 5 by a first photolithography process using a first photo mask. The uppermost insulatinginterlayer 102 g and an uppermostsacrificial layer 104 f may be removed using the reducedphotoresist pattern 110 as an etching mask. - Referring to
FIG. 6 , thephotoresist pattern 110 may be additionally reduced by, e.g., W2 by a second photolithography process using a second photo mask. - One of the insulating
interlayer 102 and one of thesacrificial layer 104 may be etched using the reducedphotoresist pattern 110 as an etching mask to form step portions in the insulatinginterlayer 102 f and thesacrificial layer 104 e, as shown inFIG. 6 . - In example embodiments, W1 may be greater than W2, and for example, W1 may be equal to or more than about 2 times W2.
- Referring to
FIG. 7 , the etching process substantially the same as or similar to that illustrated with reference toFIG. 5 may be repeatedly performed. Thus, a plurality of step portions may be formed in each of the insulatinginterlayers 102 and thesacrificial layers 104 to form a preliminary steppedmold structure 105 a. Each of the step portions of the insulatinginterlayers 102 and thesacrificial layers 104 may have a length of W2. - In example embodiments, in the preliminary stepped
mold structure 105 a, the lowermost insulatinginterlayer 102 a, e.g., a first insulatinginterlayer 102 a and the lowermostsacrificial layer 104 a, e.g., a firstsacrificial layer 104 a may not be etched but remain. In some example embodiments, a second insulatinginterlayer 102 b on the firstsacrificial layer 104 a may not be etched but remain. - The
photoresist pattern 110 may be removed by an ashing process and/or a stripping process after forming the preliminary steppedmold structure 105 a. - Referring to
FIG. 8 , amold protection layer 115 may be formed to cover the preliminary steppedmold structure 105 a. - In example embodiments, the
mold protection layer 115 may cover the uppermost insulatinginterlayer 102 g and the second insulatinginterlayer 102 b, and may also cover the step portions of the preliminary steppedmold structure 105 a. In some example embodiments, an upper portion of themold protection layer 115 may be planarized by a chemical mechanical polishing (CMP) process. - The
mold protection layer 115 may be formed by a CVD process, a spin coating process etc., using silicon oxide, e.g., TEOS, PEOX, siloxane, silsesquioxane, etc. - Referring to
FIGS. 9 and 10 , channel holes 120 may be formed through the preliminary steppedmold structure 105 a. - For example, a hard mask (not illustrated) may be formed on the
mold protection layer 115, and the insulatinginterlayers 102 and thesacrificial layers 104 of the preliminary steppedmold structure 105 a may be partially etched by performing, e.g., a dry etching process using the hard mask to form the channel holes 120. - The
channel hole 120 may extend in the first direction through the insulatinginterlayers 102 and thesacrificial layers 104 from the uppermost insulatinginterlayer 102 g to the lowermost insulatinginterlayer 102 a. An upper surface of thesubstrate 100 may be exposed by thechannel hole 120. In some example embodiments, an upper portion of thesubstrate 100 may be also etched by the dry etching process for forming thechannel hole 120. - The hard mask may be formed of silicon-based or carbon-based spin-on hardmask (SOH) materials, and/or a photoresist material.
- As illustrated in
FIG. 9 , a plurality of the channel holes 120 may be formed in the second direction to form a channel hole row. A plurality of channel hole rows may be formed in the third direction. The channel hole rows may be arranged such that the channel holes 120 may be formed in a zigzag layout along the second direction and/or the third direction. - The hard mask may be removed by an ashing process and/or a stripping process after forming the
channel hole 120. - Referring to
FIG. 11 , avertical channel structure 128 including adielectric layer structure 122, achannel 124 and afilling pattern 126 may be formed in thechannel hole 120. Acapping pad 130 may be formed on thevertical channel structure 128 to fill an upper portion of thechannel hole 120. - In example embodiments, a dielectric layer may be formed on a sidewall of the
channel hole 120, the exposed upper surface of thesubstrate 100 and an upper surface of themold protection layer 115. Portions of the dielectric layer on the exposed upper surface of thesubstrate 100 and the upper surface of themold protection layer 115 may be removed by an etch-back process to form adielectric layer structure 122 on the sidewall of thechannel hole 120. Thedielectric layer structure 122 may have a hollow cylindrical shape. - The dielectric layer may be formed by sequentially forming a blocking layer, a charge storage layer and a tunnel insulation layer. In some embodiments, the dielectric layer may be formed as an oxide-nitride-oxide (ONO) layered structure.
- A channel layer may be formed on the upper surface of the
mold protection layer 115, an inner sidewall of thedielectric layer structure 122 and the exposed upper surface of thesubstrate 100, and a filling layer may be formed on the channel layer to fill a remaining portion of thechannel hole 120. For example, upper portions of the filling layer and the channel layer may be planarized until the upper surface of themold protection layer 115 may be exposed to form thechannel 124 and thefilling pattern 126 in thechannel hole 120. - The
channel 124 may have a cup-like shape, and may contact the upper surface of thesubstrate 100. The fillingpattern 126 may have a pillar shape contained in a space formed by thechannel 124. In some example embodiments, the channel layer may be formed to fill thechannel hole 120, and in this case, the filling layer and thefilling pattern 126 may not be formed. - The channel layer may be formed of a semiconductor such as polysilicon or amorphous silicon, and may optionally be doped with impurities. In an embodiment, a heat treatment or a laser beam irradiation may be further performed on the channel layer. In this case, the channel layer may include single crystalline silicon. The filling insulation layer may be formed of, e.g., silicon oxide or silicon nitride. The channel layer and the filling layer may be formed by a CVD process, a PECVD process, an ALD process, a PVD process, a sputtering process, etc.
- Upper portions of the
dielectric layer structure 122, thechannel 124 and thefilling pattern 126 may be removed by, e.g., an etch-back process to form a recess. A pad layer may be formed on thedielectric layer structure 122, thechannel 124, the fillingpattern 126, and themold protection layer 115 to sufficiently fill the recess, and an upper portion of the pad layer may be planarized by, e.g., a CMP process until the upper surface of themold protection layer 115 may be exposed to form thecapping pad 130. - For example, the pad layer may be formed of polysilicon optionally doped with n-type impurities by a sputtering process or an ALD process. In an embodiment, a preliminary pad layer including amorphous silicon may be formed, and then a crystallization process may be performed thereon to form the pad layer.
- According to the arrangement of the channel row, a plurality of capping
pads 130 may define a pad row in themold protection layer 115, and a plurality of the pad rows may be formed along the third direction. A channel row may be defined under the pad row, and a plurality of the channel rows may be arranged along the third direction. - Referring to
FIGS. 12 to 14 , a firstupper insulation layer 140 may be formed on themold protection layer 115 to cover thecapping pads 130. The firstupper insulation layer 140 may be formed of, e.g., silicon oxide by a CVD process. The firstupper insulation layer 140, themold protection layer 115 and the preliminary steppedmold structure 105 a may be etched by, e.g., a dry etching process to form anopening 150. - In example embodiments, the
opening 150 may be formed through themold protection layer 115 and the preliminary steppedmold structure 105 a, and may include first and second openingportions substrate 100 may be exposed by theopening 150. Sidewalls of the insulatinginterlayers 102 and thesacrificial layers 104 may be exposed by theopening 150. - The
first opening portion 150 a may extend in the second direction, and may cut the preliminary steppedmold structure 105. A plurality of first openingportions 150 a may be formed in the third direction. - The channel rows may be divided into a channel block or channel group by the first opening
portions 150 a in the third direction. For example, as shown inFIG. 12 , four channel rows may be included between neighboring ones of the first openingportions 150 a. However, the number of the channel rows between the first openingportions 150 a may be properly adjusted in consideration of a circuit design or a degree of integration of the vertical memory device. - The
second opening portion 150 b may cross the first openingportions 150 a, and may be connected thereto. For example, thesecond opening portion 150 b may extend in the third direction, and may be connected to end portions of the first openingportions 150 a. Thus, the first openingportions 150 a may be merged with thesecond opening portion 150 b via the end portions thereof. - In example embodiments, the
second opening portion 150 b may be formed through the firstupper insulation layer 140, themold protection layer 115, the second insulatinginterlayer 102 b, the firstsacrificial layer 104 a and the first insulatinginterlayer 102 a. As illustrated above, when the preliminary steppedmold structure 105 a shown inFIG. 7 is formed, the second insulatinginterlayer 102 b, the firstsacrificial layer 104 a and the first insulatinginterlayer 102 a may be cut by thesecond opening portion 150 b. - Thus, as shown in
FIG. 13 , a lowermost step portion may be formed in the preliminary steppedmold structure 105 a by thesecond opening portion 150 b to form a steppedmold structure 105 b. - In some example embodiments, portions of the first insulating
interlayer 102 a, the second insulatinginterlayer 102 b and the firstsacrificial layer 104 a divided from the steppedmold structure 105 b by thesecond opening portion 150 b may remain asdummy insulating interlayers 102 a′ and 102 b′ and a dummysacrificial layer 104 a′, respectively. - As illustrated above, the lowermost step portion of the stepped
mold structure 105 b may be formed when the etching process for forming theopening 150 is performed. Thus, the number of the photo masks used in the processes for forming the step portions illustrated with reference toFIGS. 5 to 7 may be reduced. Accordingly, the process cost for forming the steppedmold structure 105 b may be reduced, and the process margin for forming the step portions may be enhanced. - Referring to
FIGS. 15 and 16 , thesacrificial layers 104 exposed by theopening 150 may be removed. In example embodiments, thesacrificial layers 104 may be removed by a wet etching process using an etching solution having an etching selectivity with respect to silicon nitride. For example, the etching solution may include phosphoric acid. By the etching process, the dummysacrificial layer 104 a′ may be also removed. - In some example embodiments, when the
sacrificial layer 104 includes polysilicon, a gas phase etching (GPE) process may be performed using, e.g., chlorine gas. - As the
sacrificial layers 104 are removed, agap 160 may be formed between the insulatinginterlayers 102, and an outer sidewall of thevertical channel structure 128 or thedielectric layer structure 122 may be partially exposed by thegap 160. Thegap 160 may extend in the second direction, and may be blocked by themold protection layer 115. In example embodiments, a lowermost one of thegaps 160 may be connected to thesecond opening portion 150 b. - Referring to
FIGS. 17 and 18 , aninterface layer 175 and a gate line 170 (e.g., 170 a˜170 f) may be formed in each of thegaps 160. - The
interface layer 175 may be conformally formed on surfaces of the insulatinginterlayers 102 and themold protection layer 115, and the outer sidewall of thedielectric layer structure 122. - In some example embodiments, the
interface layer 175 may be also formed on the sidewall of the insulatinginterlayer 102 exposed by theopening 150. - The
interface layer 175 may be formed of a metal oxide and/or a metal nitride by an ALD process or a sputtering process. - A gate electrode layer may be formed on the
interface layer 175 to fill thegaps 160 and to at least partially fill theopening 150. The gate electrode layer may be also formed on an upper surface of the firstupper insulation layer 140. - The gate electrode layer may be formed of a metal or a metal nitride. For example, the gate electrode layer may be formed of tungsten, aluminum, copper, titanium, tantalum, etc., or a metal nitride thereof. In an embodiment, the gate electrode layer may be formed to have a multi-layered structure including a barrier layer formed of a metal nitride, and a metal layer. The gate electrode layer may be formed by a CVD process, a PECVD process, an ALD process, a PVD process, a sputtering process, etc.
- The gate electrode layer may be partially removed to form the
gate line 170 in thegap 160 at each level. For example, an upper portion of the gate electrode layer may be planarized by a CMP process until the upper surface of the firstupper insulation layer 140 may be exposed. Portions of the gate electrode layer formed in theopening 150 and on the upper surface of thesubstrate 100 may be etched to obtain the gate lines 170. - The gate lines 170 may include the GSL (e.g., the
gate line 170 a), the word lines (e.g., thegate lines 170 b˜170 e) and the SSL (e.g., thegate line 170 f) sequentially stacked and spaced apart from one another in the first direction. The number of the levels at which the GSL, the word lines and the SSL are formed may increase in consideration of a circuit design and a capacity of the vertical memory device. - In some example embodiments, a
dummy interface layer 176 and adummy gate line 171 may be formed in a space formed by removing the dummysacrificial layer 104 a′. - The gate lines 170, the insulating
interlayers 102, and the channel rows surrounded by thegate lines 170 and the insulatinginterlayers 102 may define a gate line stack structure. A plurality of gate line stack structures may be divided by the first openingportions 150 a, and may be arranged in the third direction. The GSL (e.g., 170 a) in each of the gate line stack structures may be defined by thesecond opening portion 150 b. - Referring to
FIGS. 19 to 21 , an ion-implantation process may be performed to form animpurity region 103 at an upper portion of thesubstrate 100 exposed by theopening 150. - The
impurity region 103 may extend in a direction in which theopening 150 may extend. A portion of theimpurity region 103 formed by thefirst opening portion 150 a may extend in the second direction, and a portion of theimpurity region 103 formed by thesecond opening portion 150 b may extend in the third direction. - A
spacer 185 may be formed on a sidewall of theopening 150. For example, a spacer layer may be formed of an insulating material, e.g., silicon oxide on the upper surface of the firstupper insulation layer 140 and a sidewall and a bottom of theopening 150 by an ALD process. For example, an anisotropic etching process or an etch back process may be performed to partially remove the spacer layer so that thespacer 185 may be formed on the sidewall of theopening 150. - In some example embodiments, the
spacer 185 may be formed on the sidewall of theopening 150, and then the ion implantation process may be performed through theopening 150 to form theimpurity region 103. - A
cutting pattern 180 may be formed to fill a remaining portion of theopening 150. In example embodiments, a first conductive layer may be formed on the firstupper insulation layer 140 to fill a remaining portion of theopening 150. An upper portion of the first conductive layer may be planarized by a CMP process to form thecutting pattern 180 extending in theopening 150. - The
cutting pattern 180 may include afirst cutting portion 182, which may fill thefirst opening portion 150 a and extend in the second direction, and asecond cutting portion 184, which may fill thesecond opening portion 150 b and extend in the third direction. Thesecond cutting portion 184 may be connected to a plurality offirst cutting portions 182. In some example embodiments, thecutting pattern 180 may serve as a single structure. - The
first cutting portion 182 may serve as a boundary pattern defining the gate line stack structure. Thesecond cutting portion 184 may serve as a boundary pattern defining the GSL. - The first conductive layer may be formed of a metal, a metal silicide and/or doped polysilicon by a sputtering process or an ALD process. The
cutting pattern 180 may serve as a CSL of the vertical memory device. - Referring to
FIGS. 1 to 3 again, a secondupper insulation layer 190 may be formed on the firstupper insulation layer 140 to cover thecutting pattern 180 and thespacer 185. The secondupper insulation layer 190 may include a material substantially the same as that of the firstupper insulation layer 140, e.g., silicon oxide by a CVD process. - Contacts 192 (e.g., 192 a˜192 e) may be formed through the first and second upper insulation layers 140 and 190, the
mold protection layer 115, and the insulatinginterlayers 102 to contact or be electrically connected to thegate lines 170 at respectively levels. In some example embodiments, thecontacts 192 may also penetrate through theinterface layer 175, and may directly contact an upper surface of each of the gate lines 170. - The
plug 195 may be formed through the first and second upper insulatinginterlayers capping pad 130. - In some example embodiments, contact holes for forming the
plugs 195 and thecontacts 192 may be formed by the same etching process. In this case, a second conductive layer may be formed to fill the contact holes, and an upper portion of the second conductive layer may be planarized until an upper surface of the secondupper insulation layer 190 may be exposed to form theplugs 195 and thecontacts 192 simultaneously. The second conductive layer may be formed of a metal, e.g., copper, tungsten, aluminum, etc., by a sputtering process or an ALD process. - Alternatively, the
plugs 195 and thecontacts 192 may be formed by different etching and deposition processes from each other. For example, after thecontacts 192 are formed, a third upper insulation layer (not shown) may be formed on the secondupper insulation layer 190 to cover thecontacts 192. Theplugs 195 may be formed through the first and second upper insulation layers 140 and 190 and the third upper insulation layer to contact or be electrically connected to thecapping pad 130. - In some example embodiments, bit lines (not shown) and wirings (not shown) may be further formed on the second
upper insulation layer 190 to be electrically connected to theplugs 195 and thecontacts 192, respectively. -
FIG. 22 is a cross-sectional view illustrating a vertical memory device in accordance with example embodiments. For example,FIG. 22 is a cross-sectional view taken along the line I-I′ ofFIG. 1 in the first direction. - The vertical memory device of
FIG. 22 may be substantially the same as or similar to that ofFIGS. 1 to 3 , except for achannel column 101. Thus, like reference numerals refer to like elements, and detailed descriptions thereon may be omitted below in the interest of brevity. - Referring to
FIG. 22 , thechannel column 101 may be formed by forming achannel hole 120 as illustrated with reference toFIGS. 9 and 10 , and performing a selective epitaxial growth (SEG) process on the exposed upper surface of thesubstrate 100 by thechannel hole 120. Avertical channel structure 128 a including adielectric layer structure 122 a, achannel 124 a and afilling pattern 126 a may be formed on thechannel column 102 by processes substantially the same as or similar to those illustrated with reference toFIG. 11 . - In example embodiments, an upper surface of the
channel column 101 may be located between an upper surface of thefirst gate line 170 a and a lower surface of thesecond gate line 170 b. For example, thechannel column 101 may serve as a channel of the GSL. Theinterface layer 175 may serve as a gate insulation layer of the GSL. - In some example embodiments, as shown in
FIG. 22 , a bottom of thechannel column 102 may be partially inserted into an upper portion of thesubstrate 100. -
FIG. 23 is a cross-sectional view illustrating a vertical memory device in accordance with example embodiments. For example,FIG. 23 is a cross-sectional view taken along the line II-II′ ofFIG. 1 in the first direction. - The vertical memory device of
FIG. 23 may be substantially the same as or similar to that ofFIGS. 1 to 3 , except for the shape of the vertical channel structure. Thus, like reference numerals refer to like elements, and detailed descriptions thereon may be omitted below in the interest of brevity. - Referring to
FIG. 23 , neighboring ones of the vertical channel structures may be connected to each other through an inner portion of thesubstrate 100. - In some example embodiments, a
trench 100 a may be formed at an upper portion of thesubstrate 100. A dielectric layer structure 122 b and a channel 124 b included in a pair of vertical channel structures may be formed on thetrench 100 a to be connected with each other. A fillingpattern 126 b may be formed on the channel 124 b to fill thetrench 100 a and remaining portions of the pair of vertical channel structures. -
FIG. 24 is a plan view illustrating a vertical memory device in accordance with example embodiments. The vertical memory device ofFIG. 24 may be substantially the same as or similar to that ofFIGS. 1 to 3 , except for the shape and/or structure of the cutting pattern. Thus, like reference numerals refer to like elements, and detailed descriptions thereon may be omitted below in the interest of brevity. - Referring to
FIG. 24 , thesubstrate 100 may include first, second and third regions I, II and III. Thecapping pad 130 and the vertical channel structure may be formed on the first region I of thesubstrate 100, and step portions of the insulatinginterlayers 102 and the gate lines may be formed on the second region II of thesubstrate 100. - The
cutting pattern 180 a may include afirst cutting portion 183 and thesecond cutting portion 184. Thefirst cutting portion 183 may extend in the second direction, and a plurality offirst cutting portions 183 may be formed in the third direction. The gate line stack structures may be divided by thefirst cutting portions 183. Thecontacts 192 may be connected to the step portions of the gate lines included in the gate line stack structure. - The
second cutting portion 184 may extend in the third direction, and a plurality offirst cutting portions 183 may be connected to each other via thesecond cutting portion 184. Thesecond cutting portion 184 may be disposed at a boundary between the second and third regions II and III, and may define or restrict the GSL. A sidewall of thecutting pattern 180 may be surrounded by aspacer 185 a. - In example embodiments, the
second cutting portion 184 may be connected to thefirst cutting portions 183 at inner sides of thefirst cutting portions 183 from end portions thereof. For example, thefirst cutting portion 183 may include afirst portion 183 a, which may extend toward the second region II from thesecond cutting portion 184, and asecond portion 183 b, which may extend toward the third region III from thesecond cutting portion 184. - The
second portion 183 b of thefirst cutting portion 183 may protrude to the third region III. Due to thesecond portion 183 b of thefirst cutting portion 183, an arrangement margin of thesecond cutting portion 184 may be increased. Additionally, the area or volume of the CSL may increase to reduce the resistance thereof, due to thesecond portion 183 b. In an example embodiment, thesecond portion 183 b may serve as a tab for connecting contacts or plugs connected to the CSL. -
FIGS. 25 and 26 are a plan view and a cross-sectional view illustrating a vertical memory device in accordance with example embodiments. For example,FIG. 26 is a cross-sectional view taken alone the line I-I′ ofFIG. 25 in the first direction. - The vertical memory device of
FIGS. 25 and 26 may be substantially the same as or similar to that ofFIGS. 1 to 3 , except for a dummy cutting pattern. Thus, like reference numerals refer to like elements, and detailed descriptions thereon may be omitted below in the interest of brevity. - Referring to
FIGS. 25 and 26 , the vertical memory device may further include adummy cutting pattern 186 on the third region III of thesubstrate 100. Adummy spacer 187 may be formed on a sidewall of thedummy cutting pattern 186. - The
dummy cutting pattern 186 may have a shape substantially the same as or similar to that of thesecond cutting portion 184, and may be spaced apart from the first andsecond cutting portions dummy cutting pattern 186 may extend in the third direction, and may penetrate through the firstupper insulation layer 140, themold protection layer 115, thedummy insulating interlayers 102 b′ and 102 a′, thedummy interface layer 176 and thedummy gate line 171. - In some example embodiments, a
dummy impurity region 103 a′ may be formed at an upper portion under thedummy cutting pattern 186, and thedummy cutting pattern 186 may contact thedummy impurity region 103 a′. - In example embodiments, the opening 150 (refer to
FIGS. 1 to 3 ) for forming thecutting pattern 180 and a dummy opening for forming thedummy cutting pattern 186 may be formed by the same etching process. Thus, the etching load on theopening 150 may be reduced by the dummy opening, and the structural and mechanical stability and reliability of thecutting pattern 180 may be enhanced. -
FIGS. 27 and 28 are plan views illustrating a vertical memory device in accordance with example embodiments. For example,FIG. 28 is a plan view of a cell block for showing the arrangement of the gate lines. The vertical memory device ofFIGS. 27 and 28 may include elements substantially the same as or similar to those ofFIGS. 1 to 3 . Thus, like reference numerals refer to like elements, and detailed descriptions thereon may be omitted below in the interest of brevity. - Referring to
FIGS. 27 and 28 , the vertical memory device may include first, second and third regions I, II and III. Insulatinginterlayers 202 andgate lines 270 may be alternately formed on the first and second regions I and II of a substrate. Vertical channel structures penetrating through the insulatinginterlayers 202 and thegate lines 270, and thecapping pads 130 may be formed on the first region I of the substrate. Step portions of the insulatinginterlayers 202 and thegate lines 270 may be formed on the second region II of the substrate. Adummy insulating interlayer 202 b′ and a dummy gate line (not shown) may be formed on the third region III of the substrate. - A cutting pattern may cut the insulating
interlayers 202 and thegate lines 270 by a given unit, and may includefirst cutting portion 200, asecond cutting portion 210, and asub-cutting portion 205. Aspacer 220 may be formed on sidewalls of thefirst cutting portion 200 and thesecond cutting portion 210, and a sub-spacer 225 may be formed on a sidewall of thesub-cutting portion 205. - The
first cutting portion 200 may extend in the second direction, and a plurality offirst cutting portions 200 may be formed in the third direction. In example embodiments, a cell block CB may be defined by neighboring ones of thefirst cutting portions 200 in the third direction. Thesecond cutting portion 210 may extend in the third direction, and may be connected to a plurality offirst cutting portions 200. A length of aGSL 270 a in the second direction may be restricted by thesecond cutting portion 210. - The
sub-cutting portion 205 may extend in the second direction as thefirst cutting portion 200. Thesub-cutting portion 205 may be disposed between neighboring ones of thefirst cutting portions 200 in the third direction, and may be physically divided from thesecond cutting portion 210. In example embodiments, thesub-cutting portion 205 may be spaced apart from thesecond cutting portion 210 in the second direction. - In example embodiments, as shown in
FIG. 28 , thesub-cutting pattern 205 may extend in the first direction. Thesub-cutting pattern 205 may cut, e.g., anSSL 270 g and word lines 270 f˜270 b, and theGSL 270 a may not completely divided by thesub-cutting portion 205. In some example embodiments, thesub-cutting pattern 205 may partially cut step portions of theGSL 270 a. - In some example embodiments, as shown in
FIG. 27 , the cell block CB may be defined by neighboring ones of thefirst cutting portions 200 in the third direction, and two sub-blocks, e.g., a first sub-block SUB1 and a second sub-block SUB2 may be defined in the cell block CB by thesub-cutting portion 205. - For example, the first and second sub-blocks SUB1 and SUB2 and the word lines 270 f˜270 b may be physically divided by the
sub-cutting portion 205. The first and second sub-blocks SUB1 and SUB2 may share theGSL 270 a. As shown inFIG. 28 , theGSL 270 a that is a single structure may be provided in the first and second sub-blocks SUB1 and SUB2. - Contacts 230 (e.g., 230 a˜230 e) may be connected to step portions of the gate lines 270. In some example embodiments, the contact connected to the
SSL 270 g and thecontacts 230 b˜230 e connected to the word lines 270 f˜270 b may be disposed in each of the first and second sub-blocks SUB1 and SUB2. Thecontact 230 a connected to theGSL 270 a may be provided in each cell block CB. For example, thecontact 230 a connected to theGSL 270 a may be commonly provided for the first and second sub-blocks SUB1 and SUB2. - As illustrated above, the cell block CB may be divided into sub-blocks sharing the
GSL 270 a by forming thesub-cutting portion 205, and the number of contacts for electrically connecting theGSL 270 a. Thus, the margin for forming thecontact 230 may be obtained, and the operation efficiency of the vertical memory device may be enhanced. -
FIG. 29 is a plan view illustrating a vertical memory device in accordance with example embodiments. The vertical memory device ofFIG. 29 may include elements substantially the same as or similar to those ofFIGS. 1 to 3 , except for anSSL cutting pattern 240. Thus, like reference numerals refer to like elements, and detailed descriptions thereon may be omitted below in the interest of brevity. - Referring to
FIG. 29 , anSSL cutting pattern 240 may be formed on the first region I of the substrate, and may penetrate through the insulatinginterlayers 102 and the gate lines in the first direction. - In example embodiments, the SSL, e.g., 170 f (refer to
FIG. 2 ) in each of the gate line stack structure may be cut by theSSL cutting pattern 240. For example, theSSL 170 f in each of the gate line stack structure may be divided into two pieces by theSSL cutting pattern 240. - In some example embodiments, the step portions of the word lines 170 e˜170 b and the
GSL 170 a may not be cut by theSSL cutting pattern 240. For example, theSSL cutting pattern 240 may be formed only on the first region I of the substrate. - For example, the
SSL cutting pattern 240, as illustrated with reference toFIGS. 5 to 7 , may be formed before forming the vertical channel structure 128 (refer toFIG. 11 ) after forming the preliminary steppedmold structure 105 a. In some example embodiments, theSSL cutting pattern 240 may be formed before forming the opening 150 (refer toFIG. 12 ) after forming thevertical channel structure 128. - The
SSL cutting pattern 128 may include an insulating material, e.g., silicon oxide. -
FIG. 30 is a plan view illustrating a vertical memory device in accordance with example embodiments. The vertical memory device ofFIG. 30 may include elements substantially the same as or similar to those ofFIGS. 1 to 3 ,FIGS. 27 and 28 , orFIG. 29 . Thus, like reference numerals refer to like elements, and detailed descriptions thereon may be omitted below in the interest of brevity. - Referring to
FIG. 30 , as illustrated with reference toFIGS. 27 and 28 , the cutting pattern may include the first andsecond cutting portions first cutting portions 200 adjacent to each other in the third direction. Thefirst cutting portion 200 may extend in the second direction, and may penetrate through the insulatinginterlayers 302 and the gate lines. - The
second cutting portion 220 may extend in the third direction, and may be merged with thefirst cutting portions 200. Thesecond cutting portion 210 may be formed at a boundary between the second and third regions II and III, and adummy insulating interlayer 302 b′ cut by thesecond cutting portion 210 may remain on the third region III of the substrate. - In example embodiments, a
sub-cutting portion 207 may be formed between neighboring ones of thefirst cutting portions 200 in the third direction. The cell block CB may be divided into the first and second sub-blocks SUB1 and SUB2 by thesub-cutting pattern 207. - In example embodiments, the
sub-cutting pattern 207 may include a cut-offarea 250. In some example embodiments, the cut-offarea 250 may overlap the first region I of the substrate in a plan view. The gate lines and the insulatinginterlayers 302 in each level may be connected to each other, respectively, in the cell block CB through the cut-off area. For example, as shown inFIG. 30 , each of the gate line and the insulatinginterlayer 302 in each level may have an H-like shape in a plan view. - In some example embodiments, as illustrated with reference to
FIG. 29 , theSSL cutting pattern 240 may be formed on the first region I of the substrate, and may divide the SSL. - Contacts 235 (e.g., 235 a˜235 e) may be connected to the step portions of the gate lines. The gate lines may be connected through the cut-off
area 250, and thus thecontacts 235 may be distributed into different sub-blocks SUB1 and SUB2 in the cell block CB. - As shown in
FIG. 30 , thecontacts 235 may be disposed in a zigzag layout in the first and second sub-blocks SUB1 and SUB2 in a plan view. - As illustrated above, according to the circuit design of the vertical memory device, the operation unit of the vertical memory device may be controlled by using the cutting pattern and/or the sub-cutting portion and the SSL cutting pattern. Additionally, the number of the contacts connected to the gate lines may be reduced to obtain the patterning margin for forming wirings.
- The vertical memory device may be applied to a 3-dimensional non-volatile memory device having a high-rise staircase structure including a large number of steps, e.g., 20 steps, 30 steps or 40 steps, and the convenience of process and operation and the reliability of the memory device may be enhanced.
- The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.
Claims (20)
1. A vertical memory device, comprising:
a channel on a substrate, the substrate including a cell region, an extension region and a dummy region, and the channel extending on the cell region of the substrate in a first direction substantially perpendicular to an upper surface of the substrate;
gate line stack structures spaced apart from each other on the cell region, the extension region and the dummy region of the substrate, each of the gate line stack structures including gate lines spaced apart from each other in the first direction on the substrate, each of the gate lines surrounding the channel and extending in a second direction substantially parallel to the upper surface of the substrate, and the gate line stack structures being spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction;
a cutting pattern including:
first cutting portions spaced apart from each other on the cell region and the extension region of the substrate in the third direction, each of the first cutting portions extending in the second direction and cutting the gate lines; and
a second cutting portion extending in the third direction on the substrate, the second cutting portion crossing the first cutting portions and being merged with respective end portions in the second direction of the first cutting portions;
sub-cutting patterns between the first cutting portions of the cutting pattern on the substrate, each of the sub-cutting patterns extending in the second direction and cutting at least one of the gate lines; and
a dummy cutting pattern extending in the third direction on the dummy region of the substrate, the dummy cutting pattern being spaced apart from portions of the gate line stacks on the extension region of the substrate and the second cutting portion of the cutting pattern in the second direction,
wherein each of the sub-cutting patterns and each of the first cutting portions are alternately disposed in the third direction.
2. The vertical memory device of claim 1 , wherein the extension region and the dummy region of the substrate is divided from each other by the second cutting portion of the cutting pattern.
3. The vertical memory device of claim 1 , wherein each of the sub-cutting patterns is spaced apart from the second cutting portion of the cutting pattern.
4. The vertical memory device of claim 1 , wherein each of the sub-cutting patterns is connected to the second cutting portion of the cutting pattern.
5. The vertical memory device of claim 1 , wherein:
the gate lines include a ground selection line (GSL), word lines, and a string selection line (SSL), and
each of the first cutting portions cuts the SSL, the word lines and the GSL in the first direction.
6. The vertical memory device of claim 5 , wherein each of the sub-cutting patterns cuts the SSL and the word lines in the first direction, and partially cuts the GSL in the first direction.
7. The vertical memory device of claim 5 , wherein the second cutting portion of the cutting pattern defines a length of the GSL in the second direction.
8. The vertical memory device of claim 1 , further comprising:
an insulation spacer on a sidewall of each of the first cutting portions and the second cutting portion of the cutting pattern, wherein the first cutting portions and the second cutting portion of the cutting pattern include a conductive material.
9. The vertical memory device of claim 1 , further comprising:
an insulation spacer on a sidewall of the dummy cutting pattern, wherein the dummy cutting pattern includes a conductive material.
10. The vertical memory device of claim 1 , wherein the second and third directions are substantially perpendicular to each other.
11. A vertical memory device, comprising:
a channel on a substrate, the substrate including a cell region, an extension region and a dummy region, and the channel extending on the cell region of the substrate in a first direction substantially perpendicular to an upper surface of the substrate;
gate line stack structures spaced apart from each other on the cell region, the extension region and the dummy region of the substrate, each of the gate line stack structures including gate lines spaced apart from each other in the first direction and stacked in a staircase shape on the substrate, each of the gate lines surrounding the channel, extending in a second direction substantially parallel to the upper surface of the substrate, and having a contact pad protruding in the second direction from overlying ones of the gate lines, and the gate line stack structures being spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction;
a cutting pattern including:
first cutting portions spaced apart from each other on the cell region and the extension region of the substrate in the third direction, each of the first cutting portions extending in the second direction and cutting the gate lines; and
a second cutting portion extending in the third direction on the substrate, the second cutting portion crossing the first cutting portions and being merged with respective end portions in the second direction of the first cutting portions; and
sub-cutting patterns between the first cutting portions of the cutting pattern on the substrate, each of the sub-cutting patterns extending in the second direction and cutting at least one of the gate lines, wherein:
each of the sub-cutting patterns is spaced apart from the second cutting portion of the cutting pattern,
a width in the third direction of the contact pad of a lowermost one of the gate lines of each of the gate line stack structures is substantially equal to a distance between ones of the first cutting portions of the cutting pattern neighboring in the third direction, and
each of the sub-cutting patterns and each of the first cutting portions are alternately disposed in the third direction.
12. The vertical memory device of claim 11 , wherein the extension region and the dummy region of the substrate is divided from each other by the second cutting portion of the cutting pattern.
13. The vertical memory device of claim 11 , wherein:
the gate lines include a ground selection line (GSL), word lines, and a string selection line (SSL), and
each of the first cutting portions cuts the SSL, the word lines and the GSL in the first direction.
14. The vertical memory device of claim 13 , wherein each of the sub-cutting patterns cuts the SSL and the word lines in the first direction, and partially cuts the GSL in the first direction.
15. The vertical memory device of claim 13 , wherein the second cutting portion of the cutting pattern defines a length of the GSL in the second direction.
16. The vertical memory device of claim 10 , further comprising:
an insulation spacer on a sidewall of each of the first cutting portions and the second cutting portion of the cutting pattern, wherein the first cutting portions and the second cutting portion of the cutting pattern include a conductive material.
17. A vertical memory device, comprising:
a channel on a substrate, the substrate including a cell region, an extension region and a dummy region, and the channel extending on the cell region of the substrate in a first direction substantially perpendicular to an upper surface of the substrate;
gate line stack structures spaced apart from each other on the cell region, the extension region and the dummy region of the substrate, each of the gate line stack structures including gate lines spaced apart from each other in the first direction and stacked in a staircase shape on the substrate, each of the gate lines surrounding the channel, extending in a second direction substantially parallel to the upper surface of the substrate, and having a contact pad protruding in the second direction from overlying ones of the gate lines, and the gate line stack structures being spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction;
a cutting pattern including a metal, the cutting pattern including:
first cutting portions spaced apart from each other on the cell region and the extension region of the substrate in the third direction, each of the first cutting portions extending in the second direction and cutting the gate lines; and
a second cutting portion extending in the third direction on the substrate, the second cutting portion crossing the first cutting portions and being merged with respective end portions in the second direction of the first cutting portions;
sub-cutting patterns between the first cutting portions of the cutting pattern on the substrate, each of the sub-cutting patterns extending in the second direction and cutting at least one of the gate lines; and
a dummy cutting pattern extending in the third direction on the dummy region of the substrate, the dummy cutting pattern being spaced apart from portions of the gate line stacks on the extension region of the substrate and the second cutting portion of the cutting pattern in the second direction, wherein:
each of the sub-cutting patterns is spaced apart from the second cutting portion of the cutting pattern,
a width in the third direction of the contact pad of a lowermost one of the gate lines of each of the gate line stack structures is substantially equal to a distance between ones of the first cutting portions of the cutting pattern neighboring in the third direction, and
each of the sub-cutting patterns and each of the first cutting portions are alternately disposed in the third direction.
18. The vertical memory device of claim 17 , wherein the extension region and the dummy region of the substrate is divided from each other by the second cutting portion of the cutting pattern.
19. The vertical memory device of claim 17 , wherein:
the gate lines include a ground selection line (GSL), word lines, and a string selection line (SSL), and
each of the first cutting portions of the cutting pattern cuts the SSL, the word lines and the GSL in the first direction.
20. The vertical memory device of claim 19 , wherein each of the sub-cutting patterns cuts the SSL and the word lines in the first direction, and partially cuts the GSL in the first direction.
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Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20180010368A (en) | 2016-07-20 | 2018-01-31 | 삼성전자주식회사 | Memory device |
KR102432379B1 (en) * | 2017-10-16 | 2022-08-12 | 삼성전자주식회사 | Semiconductor device |
US10868033B2 (en) * | 2017-11-16 | 2020-12-15 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabricating methods thereof |
US10147638B1 (en) * | 2017-12-29 | 2018-12-04 | Micron Technology, Inc. | Methods of forming staircase structures |
CN108649033B (en) * | 2018-03-20 | 2021-07-13 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
KR102633073B1 (en) | 2018-04-24 | 2024-02-06 | 삼성전자주식회사 | Semiconductor memory device |
KR102617961B1 (en) | 2018-05-09 | 2023-12-26 | 삼성전자주식회사 | Semiconductor devices |
US10763271B2 (en) * | 2018-06-27 | 2020-09-01 | Sandisk Technologies Llc | Three-dimensional memory device containing aluminum-silicon word lines and methods of manufacturing the same |
US11164883B2 (en) | 2018-06-27 | 2021-11-02 | Sandisk Technologies Llc | Three-dimensional memory device containing aluminum-silicon word lines and methods of manufacturing the same |
JP2020035926A (en) * | 2018-08-30 | 2020-03-05 | キオクシア株式会社 | Semiconductor storage device |
KR20200048233A (en) * | 2018-10-29 | 2020-05-08 | 삼성전자주식회사 | Methods of manufacturing a vertical memory device |
KR102546653B1 (en) * | 2018-12-11 | 2023-06-22 | 삼성전자주식회사 | Semiconductor device including contact plug |
CN109742083B (en) * | 2019-01-02 | 2021-08-31 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
CN109904166B (en) * | 2019-02-27 | 2020-05-12 | 长江存储科技有限责任公司 | Three-dimensional memory and method for forming three-dimensional memory |
KR20200145919A (en) | 2019-06-20 | 2020-12-31 | 삼성전자주식회사 | Semiconductor devices |
US11805645B2 (en) * | 2019-08-16 | 2023-10-31 | Micron Technology, Inc. | Integrated assemblies having rugged material fill, and methods of forming integrated assemblies |
KR20210043101A (en) | 2019-10-11 | 2021-04-21 | 삼성전자주식회사 | Nonvolatile memory device and method for fabricating the same |
KR20210043241A (en) | 2019-10-11 | 2021-04-21 | 에스케이하이닉스 주식회사 | Semiconductor memory device and manufacturing method thereof |
KR20210088836A (en) | 2020-01-07 | 2021-07-15 | 삼성전자주식회사 | Nonvolatile memory device and method for fabricating the same |
CN112885839B (en) * | 2020-06-18 | 2021-12-28 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method and electronic equipment |
US11825654B2 (en) | 2020-12-07 | 2023-11-21 | Macronix International Co., Ltd. | Memory device |
TWI771821B (en) * | 2020-12-07 | 2022-07-21 | 旺宏電子股份有限公司 | Memory device |
CN112992910B (en) * | 2021-03-24 | 2023-04-18 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
KR20220138899A (en) | 2021-04-06 | 2022-10-14 | 에스케이하이닉스 주식회사 | Three-Dimensional Semiconductor Device |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5016928B2 (en) * | 2007-01-10 | 2012-09-05 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
US8644046B2 (en) * | 2009-02-10 | 2014-02-04 | Samsung Electronics Co., Ltd. | Non-volatile memory devices including vertical NAND channels and methods of forming the same |
KR101559958B1 (en) * | 2009-12-18 | 2015-10-13 | 삼성전자주식회사 | 3 3 Method for manufacturing three dimensional semiconductor device and three dimensional semiconductor device manufactured by the method |
US9536970B2 (en) * | 2010-03-26 | 2017-01-03 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices and methods of fabricating the same |
US9111799B2 (en) * | 2010-05-25 | 2015-08-18 | Samsung Electronics Co., Ltd. | Semiconductor device with a pick-up region |
KR101713228B1 (en) | 2010-06-24 | 2017-03-07 | 삼성전자주식회사 | Semiconductor memory devices having asymmetric wordline pads |
DE102011084603A1 (en) * | 2010-10-25 | 2012-05-16 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor device |
KR101744127B1 (en) * | 2010-11-17 | 2017-06-08 | 삼성전자주식회사 | Semiconductor devices and methods for fabricating the same |
KR101787041B1 (en) * | 2010-11-17 | 2017-10-18 | 삼성전자주식회사 | Methods for forming semiconductor devices having etch stopping layers, and methods for fabricating semiconductor devices |
KR101805769B1 (en) * | 2010-11-29 | 2017-12-08 | 삼성전자주식회사 | Methods of fabricating three dimensional semiconductor memory devices |
KR101736454B1 (en) * | 2010-12-30 | 2017-05-29 | 삼성전자주식회사 | Nonvolatile memory device |
KR20120088360A (en) * | 2011-01-31 | 2012-08-08 | 삼성전자주식회사 | Operating method of nonvolatile memory device |
KR101751950B1 (en) * | 2011-03-03 | 2017-06-30 | 삼성전자주식회사 | Nonvolatile memory device and reading method thereof |
KR101907446B1 (en) * | 2011-04-27 | 2018-10-12 | 삼성전자주식회사 | Three dimensional semiconductor memory devices and methods of fabricating the same |
KR20130005430A (en) * | 2011-07-06 | 2013-01-16 | 에스케이하이닉스 주식회사 | Non-volatile memory device and method of manufacturing the same |
US8933502B2 (en) * | 2011-11-21 | 2015-01-13 | Sandisk Technologies Inc. | 3D non-volatile memory with metal silicide interconnect |
KR101936846B1 (en) * | 2012-10-24 | 2019-01-11 | 에스케이하이닉스 주식회사 | Semicondoctor device and manufacturing method of the same |
KR101986245B1 (en) * | 2013-01-17 | 2019-09-30 | 삼성전자주식회사 | Method of manufacturing a vertical type semiconductor device |
KR20140117212A (en) * | 2013-03-26 | 2014-10-07 | 에스케이하이닉스 주식회사 | Semiconductor device |
KR102114341B1 (en) * | 2013-07-08 | 2020-05-25 | 삼성전자주식회사 | Vertical semiconductor devices |
KR102161814B1 (en) * | 2013-11-19 | 2020-10-06 | 삼성전자주식회사 | Vertical memory devices and methods of manufacturing the same |
US9425208B2 (en) * | 2014-04-17 | 2016-08-23 | Samsung Electronics Co., Ltd. | Vertical memory devices |
KR102302092B1 (en) * | 2014-04-17 | 2021-09-15 | 삼성전자주식회사 | Vertical memory devices and methods of manufacturing the same |
KR102135181B1 (en) * | 2014-05-12 | 2020-07-17 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
KR102118159B1 (en) * | 2014-05-20 | 2020-06-03 | 삼성전자주식회사 | Semiconductor Device and Method of fabricating the same |
KR20160138765A (en) * | 2015-05-26 | 2016-12-06 | 에스케이하이닉스 주식회사 | Semiconductor memory device including slimming structure |
US20170018566A1 (en) | 2015-07-15 | 2017-01-19 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
-
2016
- 2016-04-08 KR KR1020160043335A patent/KR102591057B1/en active IP Right Grant
-
2017
- 2017-01-09 US US15/401,486 patent/US10741571B2/en active Active
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