DE102011084603A1 - Three-dimensional semiconductor device - Google Patents

Abstract

The invention relates to a three-dimensional (3D) semiconductor component with stacked structure regions in which gate and insulating patterns are stacked, in particular to a 3D semiconductor memory component. A 3-D semiconductor memory device of the invention includes a stacked structure (170) that includes gate and isolation patterns alternately and repeatedly stacked and extending in a first direction on a substrate (100), the stacked structure having a first region and a second region having a width smaller than that of the first region in a second direction substantially perpendicular to the first direction, vertical active patterns (130) penetrating the stacked structure, a dielectric multilayer (160) between a sidewall of one of the vertical active patterns and corresponding ones the gate pattern includes a common source region (150) in the substrate adjacent to a side of the stack structure, and a connection pin (180) formed on the common source region and adjacent to the second region of the stack structure. Use e.g. B. in semiconductor memory technology.

Description

The invention relates to a three-dimensional (3D) semiconductor device having stacked structure regions in which gate and isolation patterns are stacked, in particular to a 3D semiconductor memory device.

Semiconductor devices are attractive to the electronics industry because of their small size, multifunction capabilities, and / or low manufacturing cost. For example, high performance semiconductor devices and / or low cost semiconductor devices have experienced increased demand with the development of the electronics industry. To meet these requirements, semiconductor devices have become more integrated. In particular, the integration density of semiconductor memory devices has been increased to store more logical data.

A planar area occupied by a unit memory cell directly affects the integration density of two-dimensional (2D) semiconductor memory devices in which the memory cells are two-dimensionally arranged on the planar area, typically a main surface of a semiconductor substrate. In other words, the integration density of the 2D semiconductor memory devices is affected by a minimum element size related to a process technology for forming fine patterns. However, there may be limitations in improving the process technology for forming the fine patterns. In addition, expensive devices or devices are required to form the fine patterns. Thus, the manufacturing costs for highly integrated semiconductor memory devices are relatively high.

3D semiconductor memory devices have been proposed to address some of the above limitations. The 3D semiconductor memory devices include a plurality of memory cells arranged three-dimensionally. However, in the fabrication of the 3D semiconductor memory devices, there are various problems due to structural configurations thereof. As a result, the reliability and / or the electrical properties of the 3D semiconductor memory devices may be relatively weak.

As a technical problem, the invention is based on the provision of a 3D semiconductor component, in particular of a 3D semiconductor memory component, which is able to reduce or avoid the above-mentioned difficulties of the components of the prior art, and in particular with comparatively high reliability and / or high integration density can be realized.

The invention solves this problem by providing a 3D semiconductor memory device having the features of claim 1 and a 3D semiconductor device having the features of claim 16. Advantageous developments of the invention are specified in the subclaims.

Advantageous embodiments of the invention will be described below and shown in the accompanying drawings, in which:

1A is a plan view illustrating a 3D semiconductor memory device,

1B an enlarged view that is part of 1A is,

1C a composite cross-sectional view along lines II 'and II-II' of 1A is

2A a composite cross-sectional view along lines II 'and II-II' of 1A is to represent another 3D semiconductor memory device,

2 B is an enlarged view showing a part 'A' of 2A is,

3A is a plan view illustrating another 3D semiconductor memory device,

3B an enlarged view that is part of 3A is,

4A is a plan view illustrating another 3D semiconductor memory device,

4B a composite cross-sectional view along lines III-III 'and IV-IV' of 4A is

5A to 5F composite cross-sectional views along lines II 'and II-II' of 1A which illustrate a method for manufacturing a 3D semiconductor memory device,

6A and 6B composite cross-sectional views along lines II 'and II-II' of 1A are another method for manufacturing a 3D semiconductor memory device,

7 a composite cross-sectional view along lines III-III 'and IV-IV' of 4A which is another method of manufacturing a 3D semiconductor memory device,

8A is a plan view illustrating another 3D semiconductor memory device,

8B a composite cross-sectional view taken along lines II 'and I-II' of 8A is

8C a cross-sectional view along a line III-III 'of 8A is

8D is a plan view, the bit lines and a connection line to the 3D semiconductor memory device of 8A adds

9 a composite cross-sectional view along lines II 'and II-II' of 8A which is another 3D semiconductor memory device,

10A to 17A composite cross-sectional views along lines II 'and II-II' of 8A are another method for manufacturing a 3D semiconductor memory device,

10B to 17B Cross-sectional views along lines III-III 'of 8A are the method for producing a 3D semiconductor memory device according to the 10A to 17A represent

18A to 18C composite cross-sectional views along lines II 'and II-II' of 8A which are a method of manufacturing the 3D semiconductor memory device of 9 represent

19 is a schematic block diagram illustrating an electronic system with a 3D semiconductor memory device, and

20 is a schematic block diagram illustrating a memory card with a 3D semiconductor memory device.

Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Deviations from the forms of the representations, for example as a result of manufacturing techniques and / or tolerances, are expected. Thus, exemplary embodiments are not intended to be limited to the specific shapes of regions illustrated herein, but include variations in shapes that result, for example, from manufacturing. Like reference numerals refer to like elements throughout. It will be understood that when an element is referred to as being "coupled" to, "connected to" or "responsive" to or "on" another element, it may be directly coupled to, connected to, or responsive to or on the other element or intervening elements may be present. In contrast, there are no intervening elements when an element is referred to as being "directly coupled" to, "directly connected to" or "directly responsive" to, or "directly to" another element.

1A illustrates a 3D semiconductor memory device according to the invention. 1B is an enlarged view that is part of 1A represents, and 1C is an assembled cross-sectional view along lines II 'and II-II' of 1A , Referring to the 1A and 1C is a plurality of stack structures 170 on a semiconductor substrate, ie a substrate 100 arranged. The multiple stack structures 170 may extend substantially parallel to one another in a first direction, as in FIG 1A shown. The first direction may be substantially parallel to an upper surface of the substrate 100 and to a direction of an x-axis in 1A be. The substrate 100 may be doped with dopants of a first conductivity type.

Each of the stack structures 170 includes gate patterns GSG, CG and SSG and isolation patterns 110a which are stacked alternately and repeatedly. The gate patterns GSG, CG and SSG in each of the stack structures 170 include at least one ground selection gate pattern GSG, a plurality of cell gate patterns CG sequentially stacked on the ground selection gate pattern GSG, and at least one string selection gate pattern SSG stacked on a top cell gate pattern CG of the plurality of cell gate patterns CG. According to respective embodiments, a plurality of mass selection gate patterns GSG are interposed between a lower cell gate pattern CG of the plurality of cell gate patterns CG and the substrate 100 stacked. In addition, a plurality of string selection gate patterns SSG are stacked on the top cell gate pattern CG. However, the invention is not limited to the embodiments described above. For example, in alternative embodiments, each of the stack structures 170 include a single ground select gate pattern GSG and a single string select gate pattern SSG.

Referring to 1C can individual the isolation pattern 110a in each of the stack structures 170 have a suitable thickness to improve / optimize and / or adjust properties of 3D semiconductor memory devices according to the invention. For example, the isolation pattern 110a between the lowest cell gate pattern CG and the ground selection gate pattern GSG thereunder thicker than the isolation pattern 110a between the multiple cell pattern patterns CG. Similarly, the isolation pattern 110a between the uppermost cell grid pattern CG and the string selection gate pattern SSG thereon, also thicker than the isolation pattern 110a between the multiple cell pattern patterns CG. However, the invention is not limited to the above embodiments. In other words, the thickness of the insulation pattern 110a be executed in various forms.

Each of the isolation patterns 110a may include an oxide layer. The corresponding gate patterns GSG, CG or SSG may include a layer of conductive material. For example, each of the respective gate patterns GSG, CG, and SSG may include at least one element of the amount comprising a doped semiconductor (eg, a doped silicon layer or the like), a metal layer (eg, a tungsten layer, a copper layer, a Aluminum layer or the like), a conductive metal nitride layer (eg, a titanium nitride layer, a tantalum nitride layer, or the like), and a transition metal layer (eg, a titanium layer, a tantalum layer, or the like).

Still referring to the 1A to 1C Penetrates a plurality of vertical active patterns 130 each of the stack structures 170 , Each of the vertical active patterns 130 is with the substrate 100 in contact. Referring to 1C includes each of the vertical active patterns 130 in corresponding embodiments, a vertical semiconductor pattern 120 which has a tubular shape or a macaroni shape. Accordingly, each of the vertical active patterns 130 an empty space in it. The empty space in each of the vertical active patterns 130 is with a dielectric filling pattern 125 filled. Each of the vertical active patterns 130 further includes a capping semiconductor pattern 127 standing on the vertical semiconductor pattern 120 and on the dielectric fill pattern 125 is arranged. The vertical semiconductor patterns 120 and the cap semiconductor patterns 127 may be the same semiconductor element as the substrate 100 include. If, for example, the substrate 100 is a silicon substrate, the vertical semiconductor patterns 120 and the cap semiconductor patterns 127 Silicon include. The vertical semiconductor patterns 120 can use dopants with the same conductivity as the substrate 100 be doped. Alternatively, the vertical semiconductor patterns 120 be formed of an undoped semiconductor layer. A drain region may be formed in at least a part of each of the cap semiconductor patterns 127 be educated. The drain region may be doped with dopants of a second conductivity type (eg, a type different from the dopants of the first conductivity type that comprise the substrate 100 dope).

A dielectric multilayer 160 is between one of the vertical active patterns 130 and one of the corresponding gate patterns GSG, CG or SSG. The dielectric multilayer 160 may include a tunnel dielectric layer, a charge storage layer, and a dielectric blocking layer. The tunnel dielectric layer is adjacent (eg, directly adjacent) to a sidewall of the corresponding vertical active pattern 130 and the dielectric blocking layer may be adjacent (eg, directly adjacent) to the corresponding one of the gate patterns GSG, CG, and SSG. The charge storage layer is disposed between the tunnel dielectric layer and the dielectric blocking layer. The tunnel dielectric layer may include an oxide material and / or an oxynitride material. The dielectric blocking layer may include a high-k dielectric layer (eg, a metal oxide layer such as a hafnium oxide layer and / or an aluminum oxide layer) having a dielectric constant higher than that of the tunnel dielectric layer. In addition, the dielectric blocking layer may further include a dielectric barrier layer having an energy bandgap larger than that of the high-k dielectric layer. The dielectric barrier layer is disposed between the high-k dielectric layer and the charge storage layer. The charge storage layer includes a dielectric material having trapping sites capable of storing charges. For example, the charge storage layer may include an oxide layer and / or a metal oxide layer. When the dielectric multilayer 160 between the cell pattern CG and the vertical active patterns 130 can then be used as a dielectric select gate layer. At least part of the dielectric multilayer 160 may extend laterally to cover a bottom and a top of each of the gate patterns GSG, CG and SSG. In respective embodiments, each of the tunneling dielectric layer, the charge storage layer, and the dielectric blocking layer extends laterally in the dielectric multi-layer 160 to cover a bottom and a top of each of the gate patterns GSG, CG, and SSG, as through the dielectric multi-layer 160 in 1C shown.

Each of the vertical active patterns 130 can make a single vertical cell string. The vertical cell string may include a plurality of cell transistors sequentially stacked and electrically connected in series. In respective embodiments, the vertical cell string includes at least one ground select transistor, a plurality of cell transistors, and at least one string select transistor sequentially stacked. The mass selection transistor, the A plurality of cell transistors and the string selection transistor are electrically connected in series. In each of the vertical cell strings, the cell transistors may be at crossing points of the vertical active pattern 130 and the cell gate pattern CG be defined. Furthermore, the ground select transistors may be at intersections of the vertical active pattern 130 and the ground select gate pattern GSG, and the string select transistors may be at intersections of the vertical active pattern 130 and the string selection gate pattern SSG. Each of the ground select transistors, the cell transistors, and the string select transistors in the vertical cell string includes a vertical channel region disposed on a sidewall of the vertical active pattern 130 is defined. The ground selection transistor having the lowest ground select gate pattern GSG further includes a horizontal channel region formed in the substrate 100 is defined below the lowest mass selection gate pattern GSG.

Referring to 1C is a plurality of dielectric buffer patterns 103a between the stack structures 170 and the substrate 100 arranged the dielectric buffer pattern 103a borders on opposite sidewalls of the vertical active patterns 130 at. That way, the vertical active patterns 130 between adjacent ones of the dielectric buffer patterns 103a in the direction of the substrate 100 protrude or extend. In other words, the dielectric buffer patterns 103a Parts of the substrate 100 contact, and the vertical active pattern 130 may be other (eg adjacent) parts of the substrate 100 to contact. Each of the dielectric buffer patterns 103a may include an oxide material. Further referring to 1C is a dielectric cover pattern 135 on each of the stack structures 170 and on the vertical active pattern 130 arranged, which penetrates the same. Opposite side walls of the dielectric cover pattern 135 can be vertically self-aligned to opposite side walls of the stack structure 170 be under it. Each of the dielectric cover patterns 135 may include an oxide material, a nitride material and / or an oxynitride material.

Still referring to the 1A to 1C is a common source area 150 in the substrate 100 between adjacent ones of the stack structures 170 educated. Different common source areas 150 can in the substrate 100 adjacent to different sides of each of the stack structures 170 be arranged. The common source areas 150 extend in the first direction and are spaced apart in a second direction that is substantially perpendicular to the first direction. The second direction may be substantially parallel to the top of the substrate 100 and can be a direction of a y-axis of 1A correspond. The stack structures 170 and the common source areas 150 may be arranged alternately and repeatedly in the second direction. The common source areas 150 may be doped with dopants of the second conductivity type. In other words, the common source areas 150 doped with dopants, one from the substrate 100 have different conductivity type and the same conductivity type as the drain regions.

Referring to 1C are spaces between adjacent ones of the stack structures 170 with insulation patterns 177 filled. In other words, the isolation patterns 177 on each of the common source areas 150 arranged. Tops of the insulation patterns 177 can be substantially coplanar with tops of the dielectric cover patterns 135 be. The isolation pattern 177 may include an oxide material, a nitride material and / or an oxynitride material.

Still referring to the 1A to 1C penetrate connection contact pins ("strapping contact plugs") 180 the isolation patterns 177 to connect to the common source areas 150 to be electrically connected. At least one stack structure 170 from a pair of stack structures 170 adjacent to opposite side walls of the connection pins 180 may, when viewed in a plan view, a first area 168a and a second area 168b with a width W2 that is smaller than a width W1 of the first area. 1B represents a corresponding one of the stack structures 170 from 1A and the common source area 150 adjacent to the stack structure 170 represents.

Referring to the 1A and 1B the plurality of stack structures extends 170 parallel to the first direction. Furthermore, the plurality of stack structures 170 arranged in the second direction with a uniform pitch. Referring to 1B includes the stack structure 170 the first area 168a and the second area 168b , The first and the second area 168a and 168b are arranged in the first direction and have widths W1, W2 in the second direction. The second area 168b has a width W2 that is less than the width W1 of the first area 168a is. The first width W1 of the first area 168a may have a substantially uniform value over the entire area thereof. In contrast, the width of the second area varies 168b according to positions in the first direction. A minimum width of the second area 168b is defined as a second width W2. In corresponding embodiments, the second width corresponds to W2 of the second range 168b a width of a substantially central part of the second area 168b in the first direction.

As in 1B shown, the first area extends 168a the stack structure 170 in the first direction and has opposite first and second side walls 172a and 172b on. Similarly, the second area 168b the stack structure 170 opposite first and second side walls 173a and 173b on. The first and the second side wall 172a and 172b of the first area 168a are with the first sidewall 173a or the second side wall 173b of the second area 168b connected. When viewed in a plan view, the first side wall 173a of the second area 168b a substantially concave shape and a substantially rounded shape. In other words, the first sidewall 173a of the second area 168b towards the second side wall 173b of the second area 168b deepened. In corresponding embodiments, the second side wall 173b of the second area 168b and the second side wall 172b of the first area 168a together form a single flat sidewall extending in the first direction.

As in 1B further illustrated, the common source area includes 150 adjacent to the stack structure 170 with the first and the second area 168a and 168b a non-landing area 148a and a landing area 148b , The non-contact area 148a is located adjacent to the first area 168a the stack structure 170 , and the contact surface area 148b is located adjacent to the second area 168b the stack structure 170 , The connection pin 180 is with the contact surface area 148b electrically connected. The contact surface area 148b may have a width, that is, a distance along the y-axis greater than that of the non-contact area 148a is. Like the first and the second area 168a and 168b the stack structure 170 may be the non-contact area area 148a have a substantially uniform width S1 over the entire area thereof, and a width of the contact surface area 148b may vary according to a position in the first direction. The contact surface area 148b of the common source area 150 includes due to the second area 168b the stack structure 170 an area with a maximum width S2. A sum of the first width W1 of the first area 168a and the width S1 of the non-contact area 148a may be substantially equal to a sum of the second width W2 of the second area 168b and the maximum width S2 of the pad area 148b be. In corresponding embodiments, the connection pin contacts 180 directly the contact surface area 148b , Alternatively, patterns of metal semiconductor interconnect material are on top of the common source regions 150 formed, and the connection pins 180 Contact respective patterns of metal semiconductor interconnect material. The patterns of metal semiconductor interconnect material are under the insulation patterns 177 arranged. In respective embodiments, each of the patterns of metal semiconductor interconnect material is a metal silicide layer.

Referring again to the 1A and 1B has each of the plurality of stack structures 170 the first and the second area 168a and 168b on, and each of the common source areas 150 includes the non-contact area 148a and the contact area 148b , The connection pins 180 penetrate the insulation patterns 177 and are associated with respective ones of the common source regions 150 electrically connected. The second areas 168b the stack structures 170 and the connection pins 180 are alternately and repeatedly arranged in the second direction.

Referring to 1C is a dielectric interlayer 183 on the connection pins 180 , the insulation patterns 177 and the vertical active patterns 130 arranged. A plurality of bit lines 190a is on the dielectric interlayer 183 arranged. The bitlines 190a are at upper areas (eg, areas farther from the substrate 100 ) of the vertical active patterns 130 electrically connected. There is also a connection line 190b on the dielectric interlayer 183 arranged. The connection line 190b is with tops of the connection pins 180 electrically connected.

In corresponding embodiments, the bitlines are 190a and the connection line 190b at substantially the same level from an upper side of the substrate 100 positioned as in 1C shown. The bitlines 190a and the connection line 190b extend in the second direction so as to be substantially parallel to each other, as in FIG 1A shown.

Each of the bit lines 190a is with the vertical active patterns 130 located below, via first conductive pins 185a electrically connected. The first conductive pins 185a penetrate the regions of the dielectric interlayer 183 and the dielectric cover pattern 135 that is between the bitlines 190a and the vertical active patterns 130 are arranged. The connection line 190b is with the connection pins 180 via second conductive pins 185b electrically connected. The second conductive pins 185b penetrate the region of the dielectric interlayer 183 that is between the connection line 190b and the connection pins 180 is arranged. The first and second conductive pins 185a and 185b For example, at least one of a metal layer (eg, a tungsten layer, a copper layer, or an aluminum layer), a conductive metal nitride layer (eg, a titanium nitride layer or a tantalum nitride layer), and a transition metal layer (eg, a titanium layer or a tantalum layer). The bitlines 190a and the connection line 190b For example, at least one of a metal layer (eg, a tungsten layer, a copper layer, or an aluminum layer), a conductive metal nitride layer (eg, a titanium nitride layer or a tantalum nitride layer), and a transition metal layer (eg, a titanium layer or a tantalum layer).

In corresponding embodiments, the vertical active patterns correspond 130 under the connecting line 190b are arranged, vertical active dummy patterns. In addition, the vertical active patterns match 130 adjacent to both side walls of the connecting line 190b also the vertical active dummy patterns. The vertical active dummy patterns do not form the vertical cell strings. The first conductive pins 185a do not need to be formed on the vertical dummy active patterns. This serves to reduce / prevent the vertical active dummy patterns from acting as actual vertical active patterns of the vertical cell strings. The vertical dummy active patterns do not need the bitlines 190a be electrically connected. Some of the vertical active dummy patterns may be the second areas 168b the stack structures 170 penetrate.

According to corresponding embodiments of the 3D semiconductor memory device, the common source regions 150 with the connection line 190b over the respective connection pins 180 electrically connected. As a result, the electrical resistance of the common source regions decreases 150 to improve the reliability of the 3D semiconductor memory device. Furthermore, each of the stack structures includes 170 the first area 168a and the second area 168b which is narrower than the first area 168a is. Thus, each of the common source regions 150 enough of a (for example, enhanced or enlarged) planar area to the connecting pin 180 to contact. As a result, it is relatively easy to use the connection pin 180 with the common source area 150 at a reduction / minimization of distances between the stack structures 170 electrically connect. Although the stack structures 170 may be arranged to have a substantially uniform pitch P, as in FIG 1A can be, for example, the width S2 of the contact surface area 148b from one of the common source areas 150 enlarged / maximized. Accordingly, highly integrated 3D semiconductor memory devices having an improved / optimized layout scheme can be provided.

In corresponding embodiments of the 3D semiconductor memory device, all layers comprising the dielectric multilayer extend 160 form horizontally to cover the tops and bottoms of the respective gate patterns GSG, CG and SSG. Alternatively, the dielectric multilayer 160 have a different configuration.

Referring to the 2A and 2 B , which show an alternative embodiment of the invention, includes a dielectric multilayer 260 between vertical active patterns 230 and respective gate patterns GSG, CG and SSG, a tunnel dielectric layer, a charge storage layer and a dielectric blocking layer. The tunnel dielectric layer, the charge storage layer and the dielectric blocking layer of the dielectric multi-layer 260 can be made of the same material layers as the tunneling dielectric layer, the charge storage layer and the dielectric blocking layer of the in 1C shown dielectric multilayer 160 be formed.

The dielectric multilayer 260 includes a first sublayer 255 and a second sub-layer 257 , The first sub-layer 255 extends vertically to between the vertical active patterns 230 and the insulation patterns 110a to lie. The second sub-layer 257 extends horizontally to cover the tops and bottoms of the respective gate patterns GSG, CG and SSG. The first sub-layer 255 includes at least a portion of the tunnel dielectric layer, and the second sub-layer 257 includes at least a portion of the dielectric blocking layer. Each of the first and second sub-layers 255 and 257 may include the charge storage layer. In corresponding embodiments, the first sub-layer includes 255 the tunneling dielectric layer, the charge storage layer and the dielectric barrier layer (eg, a part of the dielectric blocking layer), and the second sub-layer 257 includes a high-k dielectric layer (eg, another part of the dielectric blocking layer). In alternative embodiments, the first and second sub-layers 255 and 257 different combinations (eg different combinations of the charge storage layer and the dielectric barrier layer).

Each of the vertical active patterns 230 includes a first vertical semiconductor pattern 227 and a second vertical semiconductor pattern 228 , The first vertical semiconductor pattern 227 is between the second vertical semiconductor pattern 228 and the first sub-layer 255 arranged. The first vertical semiconductor patterns 227 contact the substrate 100 due to the presence of horizontal extensions of the first sublayers 255 maybe not while the second vertical semiconductor pattern 228 the first vertical semiconductor pattern 227 and the substrate 100 can contact. An empty interior of each of the second vertical semiconductor patterns 228 is surrounded with the in 1C illustrated dielectric filling pattern 125 filled. Each of the vertical active patterns 230 furthermore, the in 1C illustrated semiconductor cover pattern 127 include. That is, the semiconductor cover pattern 127 can on the first and the second vertical active pattern 227 and 228 and the dielectric filling pattern 125 be arranged.

In corresponding embodiments form the second side wall 173b of the second area 168b and the second side wall 172b of the first area 168a in the respective stack structures 170 together a single flat sidewall extending in the first direction as in FIG 1B shown. Referring to the 3A and 3B can the second sidewall 173b of the second area 168b the respective stack structures 170 alternatively a different shape than those in 1B have shown.

Referring to the 3A and 3B , which show a further variant of the invention, has a plurality of stack structures 170a when viewed in a plan view, a different shape than that in 1A illustrated stack structures 170 on. For example, a pair of stacking structures 170a adjacent to opposite sides of the connection pin 180 is arranged, a symmetrical shape, through the connecting pin 180 is defined. Each of the stack structures 170a includes a first area 168a and a second area 168b ' , as in 3B shown. A first sidewall 173a of the second area 168b ' has a concave shape with respect to a first side wall 172a of the first area 168a on. Similarly, a second sidewall 173b ' of the second area 168b ' also a concave shape with respect to a second side wall 172b of the first area 168a on. In other words, both the first and the second sidewall are 173a and 173b ' of the second area 168b ' towards a center of the second area 168b ' the stack structure 170a deepened. As a result, both sidewalls show 173a and 173b ' the second areas 168b ' of the pair of stack structures 170a a concave shape. In other words, both have sidewalls 173a and 173b ' adjacent to the connection pins 180 a concave shape. In corresponding embodiments, the stack structures 170a Also arranged so that they have a substantially uniform pitch P in the second direction. Thus, a width of contact surface areas 148b ' of common source areas 150a between the stack structures 170a in a limited area larger, ie comparatively increased. In respective embodiments, a sum of a maximum width S2 'of the contact surface area 148b ' and a minimum width W2 'of the second area 168b ' the stack structure 170a substantially equal to a sum of a width S1 of the non-contact area 148a and a width W1 of the first area 168a the stack structure 170a ,

The vertical active patterns 230 and the dielectric multi-layer 260 referring to the 2A and 2 B can also be described in the 3A and 3B illustrated 3D semiconductor memory device can be applied.

According to respective embodiments, the connection pins are 180 on respective contact surface areas 148b ' the common source areas 150a arranged. Alternatively, the connection pins 180 on some of the common source areas 150a not arranged, as in the 4A and 4B shown.

Referring to the in the 4A and 4B Embodiments shown are connecting contact pins 180 with selected common source areas 150a electrically connected among the plurality of common source regions. On the other hand, on unselected common source areas 150 ' no connection pins among the plurality of common sources 180 arranged. The connection pins 180 are arranged in the second direction, and at least one of the unselected common source regions 150 ' is between the pair of adjacent connection pins 180 arranged. The connection pins 180 are with a connection line 190b electrically connected. In corresponding embodiments, the number of connection contact pins 180 under the connecting line 190b lower than those of the common source regions 150a and 150 ' under the connecting line 190b ,

Each of the selected common source areas 150a , that with the connection pins 180 electrically connected, includes the non-contact area area 148a and the contact surface area 148b ' as with reference to the 3A and 3B described. Accordingly, sidewalls of the second regions 168b ' the stack structures 170a ie areas along sides of the contact surface area 148b ' the common source areas 150a , a concave shape on, as in 3B shown.

Assuming a pair of stack structures 170 with the connection pin 180 alternatively, there is any pair of stack structures in between 170 the first area 168a and the second area 168b as with reference to the 1A and 1B described. In other words, in such embodiments, only one of the side walls of the respective second regions 168b a concave shape. This is the pair of stack structures 170 on both sides of the connection pin 180 arranged such that the concave side walls of the pair of stacking structures 170 the connection pin 180 in between are facing. In corresponding embodiments, the unselected common source regions 150 ' no contact surface area 148b or 148b ' on. That is, the unselected common source areas 150 ' may have a substantially uniform width, and a width of the unselected common source regions 150 ' may be substantially equal to a width of the non-contact area areas 148a the selected common source areas 150a be. As in 4A is shown in corresponding embodiments, at least one additional stack structure 170 ' with a uniform width between a pair of the connecting contact pins 180 arranged. In corresponding embodiments, the stack structures 170 and 170 ' arranged to have a substantially uniform pitch P in the second direction.

As in 4B is a doped connection region 200 in the substrate 100 arranged. The doped connection area 200 has the same conductivity as the common source regions 150a and 150 ' on. As in 4A shown, the doped connection region extends 200 in the second direction, around the unselected common source regions 150 ' and the selected common source regions 150a to contact. That is, the unselected common source areas 150 ' and the selected common source regions 150a are above the doped connection area 200 electrically connected to each other. In corresponding embodiments, the doped connection region is 200 under the connecting line 190b arranged. That is, the doped connection area 200 overlaps when viewed in the plan view of 4A with the connection line 190b , Thus, the doped connection region 200 with the contact surface areas 148b ' the selected common source areas 150a connected. The unselected common source areas 150 ' are through the doped connection area 200 with the connection pins 180 on the selected common source areas 150a electrically connected.

In the 5A to 5F a method for producing a 3D semiconductor memory device is shown. Referring to 5A becomes a dielectric buffer layer 103 on a substrate 100 formed doped with dopants of a first conductivity type. A sacrificial layer 105 and an insulation layer 110 are alternately and repeatedly on the dielectric buffer layer 103 stacked. The sacrificial layers 105 are formed of a material layer which has an etching selectivity with respect to the insulating layers 110 having. For example, the insulation layers 110 formed of an oxide layer, and the sacrificial layers 105 are formed from a nitride layer.

The insulation layers 110 , the sacrificial layers 105 and the dielectric buffer layer 103 are structured to channel openings 115 to build. The canal openings 115 put the substrate 100 free. A semiconductor layer becomes conformal to the substrate 100 with the channel openings 115 formed, and a dielectric filling layer, which the channel openings 115 fills is formed on the semiconductor layer. The dielectric filling layer may be formed of an oxide layer, a nitride layer and / or an oxynitride layer. The dielectric filling layer and the semiconductor layer are planarized until the uppermost, ie from the substrate 100 furthest away, the insulation layers 110 is exposed, creating a vertical semiconductor pattern 120 and a dielectric filling pattern 125 in the respective channel openings 115 be formed. The vertical semiconductor patterns 120 and the dielectric filling patterns 125 are deepened such that tops of the vertical semiconductor patterns 120 and the dielectric filling pattern 125 are at a level lower, ie closer to the substrate 100 as an upper surface of the uppermost insulating layer 110 is. Then, a semiconductor cover layer on the substrate 100 with the recessed vertical semiconductor patterns 120 and the recessed dielectric fill patterns 125 educated. The semiconductor cover layer fills the channel openings 115 on the vertical semiconductor patterns 120 and the dielectric fill patterns 125 , The semiconductor capping layer is planarized until the uppermost insulating layer 110 is exposed, creating a semiconductor cover pattern 127 in the respective channel openings 115 on the vertical semiconductor patterns 120 and the dielectric fill patterns 125 is formed. The semiconductor cover pattern 127 and the vertical semiconductor pattern 120 in each of the channel openings 115 are formed form a vertical active pattern 130 , There may be dopants of a second conductivity type in the semiconductor cover pattern 127 be injected to form drain areas.

Referring to 5B becomes a dielectric capping layer on the vertical active patterns 130 and the topmost insulating layer 110 educated. The dielectric covering layer, the insulating layers 110 , the sacrificial layers 105 and the dielectric buffer layer 103 are structured to ditches 145 forming a plurality of stack patterns. Each of the stack patterns includes a dielectric buffer pattern 103a , a preliminary mold structure 140 and a dielectric cover pattern 135 which are sequentially stacked. The trenches 145 are formed between the stack patterns. Each of the temporary casting structures 140 includes sacrificial patterns 105a and isolation patterns 110a which are stacked alternately and repeatedly. Thus the sacrificial patterns become 105a through the trenches 145 exposed. Each of the temporary casting structures 140 further includes the vertical active patterns 130 ,

The preliminary casting structures 140 when viewed in a plan view extend parallel to one another in a first direction, ie, the preliminary cast structures 140 extend like those in 1A illustrated stack structures 170 , The preliminary casting structures 140 are arranged in a second direction (eg, a y-axis direction) substantially perpendicular to the first direction so as to have a substantially uniform pitch when viewed in a plan view. In respective embodiments, each of the preliminary casting structures includes 140 a first area and a second area. The first areas of temporary casting structures 140 have a first width W1 in the second direction, and the second regions of the preliminary cast structures 140 have a width that is less than the first width W1 in the second direction. The second regions of the preliminary casting structures are shown in greater detail 140 a second width W2 corresponding to a minimum width of the second regions. The second width W2 is less than the first width W1. The preliminary casting structures 140 have substantially the same configuration as the stack structures when viewed in a plan view 170 from 1A on.

Dopants of the second conductivity type are below the trenches 145 in the substrate 100 implanted, creating common source areas 150 be formed. Accordingly, the preliminary casting structures 140 used as implantation masks. Thus, in respective embodiments, the common source regions 150 so formed that they due to the configuration of the preliminary casting structures 140 the same configuration as with reference to the 1A and 1b described, have.

Referring to 5C be the ones through the trenches 145 exposed sacrificial pattern 105a selectively removed to empty areas 155 to build. As a result, casting structures become 140a educated. Each of the casting structures 140a includes the stacked insulation patterns 110a and the empty areas 155 between the stacked insulation patterns 110a , In corresponding embodiments, the empty areas set 155 Parts of a sidewall of the corresponding vertical active pattern 130 free.

Referring to 5D becomes a dielectric multilayer 160 compliant on the substrate 100 with the empty areas 155 educated. The dielectric multilayer 160 becomes in a substantially uniform thickness on inner surfaces of the empty areas 155 educated. A conductive gate layer 165 which are the empty areas 155 fills, becomes on the substrate 100 with the dielectric multilayer 160 educated. In corresponding embodiments, the conductive gate layer fills 165 partly the trenches 145 , However, the invention is not limited to embodiments in which the gate conductive layer 165 the empty areas 155 fills and the trenches 145 partially filled.

Referring to 5E become areas of the conductive gate layer 165 outside the empty areas 155 removed to form gate patterns GSG, CG and SSG representing the empty areas 155 to fill. In addition, the gate patterns GSG, CG, and SSG are removed by removing the regions of the gate conductive layer 165 that are outside the empty areas 155 are located, separated from each other. The gate patterns GSG, CG and SSG as well as the isolation patterns 110a are alternating and repeated on a part of the substrate 100 stacked and form a stack structure 170 ,

In corresponding embodiments, portions of the dielectric multiple layer become 160 that are outside the empty areas 155 are formed, removed. Alternatively, at least a portion of the dielectric multilayer 160 that is outside the empty areas 155 is formed, remain.

One the trenches 145 filling insulation layer is on the substrate 100 formed with the gate patterns GSG, CG and SSG. The insulation layer is planarized to provide isolation patterns 177 in the trenches 145 to build.

Referring to 5F becomes a plurality of connection contact pins 180 formed to the isolation pattern 177 to penetrate. The connection pins 180 are with each of the common source areas 150 electrically connected.

A dielectric interlayer 183 becomes on substantially an entire surface of the substrate with the connecting pins 180 educated. The dielectric interlayer 183 and the dielectric cover patterns 135 are patterned to form openings which are tops of the vertical active patterns 130 in the first areas in the 1A and 1B with the reference symbol ' 168a are exposed, the stack structures exposing, and first conductive pins 185a are formed in respective ones of the openings. Thus, the first conductive pins 185a with respective vertical active patterns 130 electrically connected. In corresponding embodiments, the first conductive pins become 185a during the formation of the first conductive pins 185a not on the vertical active patterns 130 in the second areas, in the 1A and 1B with the reference symbol ' 168b are designated, the stack structures 170 educated. In other words, the vertical active patterns match 130 in the second areas 168b the stack structures 170 vertical active dummy patterns, as with reference to the 1A to 1C described. A plurality of second conductive pins 185b is formed to the dielectric interlayer 183 to penetrate. The second conductive pins 185b are formed to respective ones of the connection pins 180 to contact. The first and second conductive pins 185a and 185b can be formed at the same time.

bit 190a and a connection line 190b , z. B. as in the 1A to 1C are shown on the dielectric interlayer 183 educated. As a result, using in the 5A to 5F the processes illustrated with reference to the 1A to 1C described 3D semiconductor memory device provided.

The 6A and 6B illustrate another method of fabricating a 3D semiconductor memory device. Referring to FIG 6A becomes a dielectric buffer layer 103 on a substrate 100 formed, and sacrificial layers 105 as well as insulation layers 110 are alternately and repeatedly on the dielectric buffer layer 103 stacked. The insulation layers 110 , the sacrificial layers 105 and the dielectric buffer layer 103 are structured to channel openings 115 to build.

A first sub-layer 255 will conform to the substrate 100 with the channel openings 115 educated. A first semiconductor layer becomes conformal on the first sublayer 255 educated. The first semiconductor layer and the first sub-layer 255 are anisotropically etched until the substrate 100 under the canal openings 115 is exposed. As a result, first vertical semiconductor patterns become 227 on side walls of the channel openings 115 educated. The first sub-layer 255 is between the side walls of the channel openings 115 and the first vertical semiconductor patterns 227 arranged. The first sub-layer 255 becomes on the bottom surface of the channel openings during the anisotropic etching process 115 and on the top, ie of the substrate 100 furthest away, insulation layer 110 away.

Referring to 6B a second semiconductor layer conforms to the substrate 100 with the first vertical semiconductor patterns 227 formed, and a dielectric filling layer, which the channel openings 115 fills is formed on the second semiconductor layer. The dielectric filling layer and the second semiconductor layer are planarized until the uppermost insulating layer 110 is exposed. As a result, a second vertical semiconductor pattern 228 and a dielectric filling pattern 125 in each of the channel openings 115 educated. In at least one of the channel openings 115 contacts the second vertical semiconductor pattern 228 the first vertical semiconductor pattern 227 and the substrate 100 under the canal opening 115 , The first and second vertical semiconductor patterns 227 and 228 as well as the dielectric filling patterns 125 are deepened, and semiconductor cover patterns 127 be in the channel openings 115 on the recessed first and second vertical semiconductor patterns 227 and 228 and the recessed dielectric fill patterns 125 educated. The first and second vertical semiconductor patterns 227 and 228 and the semiconductor cover pattern 127 in each of the channel openings 115 form a vertical active pattern 230 , In at least a part of each of the semiconductor cover patterns 127 a drain region is formed.

According to respective embodiments, a dielectric capping layer is formed on the substrate with the drain regions. The dielectric covering layer, the insulating layers 110 , the sacrificial layers 105 and the dielectric buffer layer 103 are structured to ditches 145 forming a plurality of stack patterns. Each of the stack patterns includes a dielectric buffer pattern 103a , a preliminary cast structure and a dielectric cover pattern 135 which are sequentially stacked. The trenches 145 are formed between the stack patterns. Each of the preliminary cast structures includes sacrificial patterns and isolation patterns 110a which are stacked alternately and repeatedly. The sacrificial patterns are removed to empty areas 155 to build. The empty areas 155 put the first sub-layer 255 on sidewalls of the vertical semiconductor patterns 230 free.

A second sublayer 257 will conform to the substrate 100 with the empty areas 155 educated. The second sub-layer 257 can be up to one substantially uniform thickness on insides of the empty areas 155 be formed. The first and second sub-layers 255 and 257 form a dielectric multilayer 260 , Subsequent processes will be described using reference to FIGS 5D and 5F described method steps performed. As a result, with reference to FIGS 2A and 2 B described 3D semiconductor memory device using the in the 6A and 6B represented processes (and in corresponding embodiments further using the in the 5D and 5F represented processes).

In corresponding embodiments, with reference to FIGS 5A to 5F described manufacturing method of the 3D semiconductor memory device in 5B shown preliminary casting structures 140 formed so that they have the same planar configurations as those in the 3A and 3B illustrated stack structures 170a exhibit. Accordingly, with reference to FIGS 3A and 3B described 3D semiconductor memory device using the in the 5A to 5F provided processes.

A process for the preparation of in the 4A and 4B 3-D semiconductor memory device shown with reference to the 5A to 5F while it shows some differences. For example, referring to 7 becomes the doped connection area 200 of the 4A and 4B before the formation of the sacrificial layers 105 and the insulation layers 110 educated. The doped connection area 200 can be formed using a mask pattern comprising the doped connection region 200 Are defined. The dielectric buffer layer 103 may during an ion implantation process to form the doped junction region 200 be used as an ion implantation buffer layer. Alternatively, the dielectric buffer layer 103 after forming the doped connection region 200 be formed. In addition, the in 5B shown preliminary casting structures 140 be formed so that they have the same planar configurations as those in 4A illustrated stack structures 170 and 170 ' exhibit. Other manufacturing processes can be performed using the reference to the 5A to 5F described processes are performed. As a result, this will be in the 4A and 4B illustrated 3D semiconductor memory device using the in the 5A to 5F and 7 provided processes.

Referring to the 8A to 8C , which constitute another 3D semiconductor memory device according to the invention, is a well region 301 doped with dopants of a first conductivity type in a substrate 300 arranged. A plurality of stack structures 370a and 370b is on the trough area 301 arranged. As in 8A illustrated, the plurality of stack structures extends 370a and 370b are substantially parallel in a first direction, and are separated from each other in a second direction substantially perpendicular to the first direction. The first and second directions are parallel to an upper surface of the substrate 300 , Therefore, the first direction of an x-axis direction of 8A and the second direction may be a y-axis direction of 8A correspond.

Each of the stack structures 370a and 370b includes gate patterns GSG, CG and SSG and isolation patterns 310a which are stacked alternately and repeatedly, as in the 8B and 8C shown. The gate patterns GSG, CG and SSG of each of the stack structures 370a and 370b include at least one mass selection gate pattern GSG, a plurality of cell gate patterns CG stacked on the ground selection gate pattern GSG, and at least one string selection gate pattern SSG disposed on the top, ie, the substrate 300 farthest, cell-grid pattern CG is stacked. In respective embodiments, each of the stack structures includes 370a and 370b a plurality of mass selection gate patterns GSG, which are below the bottom, ie the substrate 300 Next, cell gate are stacked, and / or a plurality of string selection gate patterns SSG stacked on the top cell gate. The isolation pattern 310a the respective stack structures 370a and 370b are designed so that they have several different thicknesses, which are suitable for the properties of the device.

The isolation pattern 310a may include a layer of oxide material. The gate patterns GSG, CG and SSG include a layer of conductive material. For example, the gate patterns GSG, CG, and SSG may include at least one of a doped semiconductor (eg, a doped silicon layer or the like), a metal layer (eg, a tungsten layer, a copper layer, an aluminum layer, or the like), a conductive metal nitride layer (eg, a titanium nitride layer, a tantalum nitride layer, or the like) and a transition metal layer (eg, a titanium layer, a tantalum layer, or the like).

A plurality of vertical active patterns 330 penetrates a respective one of the stack structures 370a and 370b , The vertical active patterns 330 contact the trough area 301 , Each of the vertical active pattern 330 includes a vertical semiconductor pattern 320 with one of several forms, e.g. B. a tubular shape or a macaroni shape. An inner part of each of the vertical semiconductor patterns 320 is with a dielectric filling pattern 325 filled. Each of the vertical active patterns 330 further includes a semiconductor cover pattern 327 that on the dielectric filling pattern 325 and on the vertical semiconductor pattern 320 is arranged. The vertical semiconductor patterns 320 and the semiconductor cover patterns 327 may be the same semiconductor material layer as the substrate 300 include. If, for example, the substrate 300 is a silicon substrate, the vertical semiconductor patterns 320 and the semiconductor cover patterns 327 include a silicon layer. The vertical semiconductor patterns 320 and the semiconductor cover patterns 327 may have a polycrystalline structure or a monocrystalline structure. The vertical semiconductor patterns 320 may be doped with dopants of the first conductivity type or may consist of an undoped semiconductor layer. A drain region is in at least a part of each of the semiconductor cover patterns 327 arranged. The drain regions may be doped with dopants of a second conductivity type that is different from the first conductivity type. Bottoms of the drain regions may be at a level that is at tops of the top, ie, substrate 300 farthest, string selection gate pattern SSG adjacent.

A dielectric multilayer 360 , in the 8B is shown between the sidewalls of the vertical active pattern 330 and respective gate patterns GSG, CG and SSG are arranged. The dielectric multilayer 360 includes a tunnel dielectric layer, a charge storage layer and a dielectric blocking layer. The tunnel dielectric layer is adjacent to the sidewalls of the vertical active patterns 330 and the dielectric blocking layer adjoins the gate patterns GSG, CG and SSG. The charge storage layer is disposed between the tunnel dielectric layer and the dielectric blocking layer. The tunnel dielectric layer may include a layer of oxide material and / or a layer of oxynitride material. The dielectric blocking layer may comprise a high k dielectric layer, e.g. A metal oxide layer such as a hafnium oxide layer and / or an aluminum oxide layer having a dielectric constant higher than that of the tunneling dielectric layer. In addition, the dielectric blocking layer may further include a dielectric barrier layer having an energy bandgap larger than that of the high-k dielectric layer. The dielectric barrier layer is disposed between the high-k dielectric layer and the charge storage layer. The charge storage layer may include a dielectric layer with trapping sites capable of storing charges. For example, the charge storage layer includes a layer of oxide material and / or a metal oxide layer. When the dielectric multiple sends 360 between one of the cell gate patterns CG and the vertical active patterns 330 can be used as a data storage element to B. store logic data. In contrast, when the dielectric multilayer 360 between the selection gate patterns GSG or SSG and the respective vertical active patterns 330 can be used as a dielectric select transistor gate layer. At least part of the dielectric multilayer 360 may extend horizontally to cover tops and bottoms of the respective gate patterns GSG, CG and SSG. In respective embodiments, all of the layers, ie, the tunnel dielectric layer, the charge storage layer, and the dielectric blocking layer, extend to the dielectric multiple layer 360 horizontally to cover the tops and bottoms of the gate patterns GSG, CG and SSG, as in 8C shown.

Each of the vertical active patterns 330 provides a single vertical cell string. The vertical cell string includes a plurality of cell transistors that are sequentially stacked and electrically connected in series. The vertical cell string further includes at least one ground selection transistor located below the bottom, ie closest to the substrate 300 Cell transistor is stacked, and at least one string selection transistor on the top, ie from the substrate 300 farthest, cell transistor. In each of the vertical cell strings, the cell transistors are at crossing points of the vertical active pattern 330 and the cell gate pattern CG is defined. Furthermore, the ground selection transistors are at crossing points of the vertical active pattern 330 and the ground selection gate pattern GSG, and the string selection transistors are at crossing points of the vertical active pattern 330 and the string selection gate pattern SSG defined. Each of the ground select transistors, the cell transistors, and the string select transistors in the vertical cell string includes a vertical channel region disposed on a sidewall of the vertical active pattern 330 is defined. The ground selection transistor with the bottom, ie the substrate 300 Next, ground select gate pattern GSG may further include a horizontal channel region formed in the substrate 300 is defined below the lowest mass selection gate pattern GSG.

A plurality of dielectric buffer patterns 303a is between the stack structures 370a and 370b and the substrate 300 arranged. Accordingly, the vertical active patterns extend 330 in the direction of the substrate 300 , you can z. Between adjacent dielectric buffer patterns 303a in the direction of the substrate 300 protrude. In other words, the vertical active patterns 330 in contact with the trough area 301 even if the dielectric buffer pattern 303a are present, for. On opposite sidewalls of each of the vertical active patterns 330 , Each of the dielectric buffer patterns 303a may include an oxide material. A dielectric cover pattern 335 is on each of the stack structures 370a and 370b and on the vertical active pattern 330 arranged, which is the respective one of the stack structures 370a and 370b penetrates. Opposite side walls of the dielectric cover pattern 335 can be vertically self-aligned to opposite side walls of the stack structure 370a and 370b be under it. Each of the dielectric cover patterns 335 may include an oxide material, a nitride material and / or an oxynitride material.

Referring to the 8A to 8C The plurality of stack structures includes first stack structures 370a and second stack structures 370b , As in 8A is a first ditch 345a between a pair of adjacent first stack structures 370a Are defined. The first ditch 345a extends in the first direction. The first stacking structures 370a may be arranged to have a substantially uniform pitch in the second direction. A common source area 350 is in the substrate 300 under each of the first trenches 345a arranged. More detailed is the common source area 350 in the trough area 301 under each of the first trenches 345a trained as in 8B shown. The common source areas 350 may be doped with dopants of the second conductivity type. That is, the common source areas 350 may be doped with dopants of a conductivity type different from that of the well region 301 different. Subpages of the common source areas 350 may be at a higher level than a bottom of the trough area 301 are located. The common source areas 350 may be due to the first trenches 345a also extend in the first direction.

Each of the first trenches 345a includes a first area and a second area. The first and second regions of each of the first trenches 345a are arranged alternately in the first direction. The first and second areas of the first trenches 345a each have a width in the second direction. The first areas of the first trenches are more detailed 345a a first width D1, and the second regions of the first trenches 345a have a second width D2. In corresponding embodiments, the second width D2 is greater than the first width D1. The first width D1 of the first regions may be substantially uniform. In contrast, the second width D2 of the second regions may vary according to a position in the first direction. Each of the common source areas 350 includes due to a planar shape of the respective first trenches 345a a non-contact area and a pad area. Therefore, a width of the pad areas may be larger than that of the non-pad areas. The non-contact area areas of the common source areas 350 are among the first areas of the first trenches 345a arranged. Similarly, the contact surface regions are the common source regions 350 under the second areas of the first trenches 345a arranged.

A pair of first insulating spacers 378a is on opposite sidewalls within each of the first trenches 345a arranged. The opposite side walls of the first trenches 345a extend essentially in the first direction. In corresponding embodiments, the pair of first insulating spacers contacts 378a in the respective first areas of the first trenches 345a each other, contact each other z. B. directly, while the pair of first insulating spacers 378a in the respective second areas of the first trenches 345a is separated from each other. This may be because the second width D2 of the second regions is greater than the first width D1 of the first regions. As a result, one of the pair of first insulating spacers 378a surrounded opening 380a in each of the second areas of the first trenches 345a Are defined. The first insulating spacers 378a may have a substantially uniform width. The first insulating spacers 378a may include an oxide material, a nitride material and / or an oxynitride material.

Each of the pair of adjacent first stack structures 370a that the first ditch 345a defines, includes a first, to the first region of the first trench 345a adjacent area and a second, to the second area of the first trench 345a adjacent area. The first and second regions have a width in the second direction. The width Wb of the second regions is smaller than the width Wa of the first regions. This may be because the second width D2 of the second regions is greater than the first width D1 of the first regions. One of the opposite side walls of each of the first trenches 345a includes both a sidewall of the first regions of the first stack structures 370a as well as a sidewall of the second regions of the first stacked structures 370a , The side wall of the second region may have a concave shape.

Connecting pins 385a are in respective openings 380a arranged. The connection pins 385a are with the corresponding common source areas 350 electrically connected. The first stacking structures 370a and the connection pins 385a are alternately arranged in the second direction, such as. In 8A shown. Each of the connection pins 385a includes a conductive material. For example, each of the connection pins includes 385a at least one of a metal layer (eg, a tungsten layer, a copper layer, an aluminum layer, or the like), a conductive metal nitride layer (eg, a titanium nitride layer, a tantalum nitride layer, or the like) and a transition metal layer (eg, a titanium layer, a Tantalum layer or the like).

As in 8A is a second trench 345b between a pair of adjacent second stack structures 370b Are defined. The second ditch 345b also extends in the first direction. The second ditch 345b has a third width D3 in the second direction. The third width D3 of the second trench 345b can be substantially uniform. A tray receiving area 302 is in the trough area 301 under the second ditch 345b arranged. The tray receiving area 302 can with dopants of the same conductivity type, eg. B. of the first conductivity type, such as the trough area 301 be doped. In addition, the trough receiving area 302 a higher dopant concentration than the well region 301 exhibit.

A pair of second insulating spacers 378b is respectively on opposite side walls within the second trench 345b arranged. The opposite side walls of the second trench 345b extend substantially parallel in the first direction. The third width D3 of the second trench 345b may be greater than the first width D1 of the first regions of the first trench 345a be. The pair of second insulating spacers 378b is separated from each other. A deepening 380b is between the pair of second insulating spacers 378b Are defined. The depression 380b also extends in the first direction.

A conductive trough line 385b is in the depression 380b arranged and is with the trough receiving area 302 electrically connected. As a result, the conductive well conduit is 385b with the trough area 301 electrically connected. In an operating mode, a well bias, e.g. B. a given voltage, the trough area 301 through the conductive trough line 385b fed. The conductive trough line 385b extends in the first direction. An upper, ie from the substrate 300 farthest surface of the conductive trough line 385b can be at substantially the same level as tops of the connection pins 385a are located. That is, the top of the conductive well conduit 385b can be essentially coplanar with the tops of the connection pins 385 be. The conductive trough line 385b includes a conductive material. For example, the conductive well conduit includes 385b at least one of a metal layer (eg, a tungsten layer, a copper layer, an aluminum layer, or the like), a conductive metal nitride layer (eg, a titanium nitride layer, a tantalum nitride layer, or the like) and a transition metal layer (eg, a titanium layer, a Tantalum layer or the like). In embodiments, the conductive well conduit includes 385b the same conductive material as the connection pins 385a ,

As in 8B are shown, are first patterns 375a of a metal semiconductor interconnect material on tops of the common source regions, respectively 350 arranged. The first patterns 375a of the metal semiconductor interconnect material are among the first insulating spacers 378a arranged. The connection pins 385a Contact each of the first patterns 375a from the metal semiconductor compound material. Each of the connection pins 385a is with one of the common source areas 350 through one of the first patterns 375a electrically connected from the metal semiconductor interconnect material.

When viewed in a plan view, each of the first patterns 375a made of metal semiconductor compound material having a line shape extending in the first direction, the z. B. similar to the common source regions 350 extends. Thus, the electrical resistance of the common source regions 350 can be significantly reduced, ie can be relatively low. Each of the first patterns 375a The metal semiconductor interconnect material includes a first region disposed on the non-contact area of the respective common source regions 350 is arranged, and a second area, on the contact surface area of the respective common source regions 350 is arranged. From a planar viewpoint, a width of the second regions of the first pattern 375a metal semiconductor interconnect material greater than that of the first regions of the first patterns 375a be made of metal semiconductor compound material. The connection pins 385a Contact respective second areas of the first patterns 375a made of metal semiconductor compound material. Each of the first patterns 375a out Metal semiconductor compound material 375a may be a bonding material with a semiconductor element of the substrate 300 and a metal element. For example, each of the first patterns includes 375a metal compound interconnect material; a metal silicide layer such as a cobalt silicide layer, a titanium silicide layer, and / or a nickel silicide layer.

As in 8C is a second pattern 375b of metal semiconductor interconnect material on the well receiving area 302 arranged. The second pattern 375b of metal semiconductor interconnect material is under the second insulating spacers 378b arranged, z. Between the second insulating spacers 378b and the tray receiving area 302 , The conductive trough line 385b contacted, z. B. contacted directly, the second pattern 375b made of metal semiconductor compound material. Thus, the conductive well conduit is 385b through the second pattern 375b metal semiconductor interconnect material and the well receiving area 302 with the trough area 301 electrically connected. From a planar viewpoint, the second pattern extends 375b metal semiconductor interconnect material also in the first direction, e.g. B. as the trough receiving area 302 , As a result, the electrical resistance of the well receiving area 302 can be significantly reduced, ie can be relatively low. In corresponding embodiments, the second pattern includes 375b a metal silicide layer such as a cobalt chloride layer, a titanium silicide layer and / or a nickel silicide layer. The second pattern 375b The metal semiconductor compound material may be made of the same material layer as the first pattern 375a be formed of metal semiconductor compound material.

In corresponding embodiments, protective spacers 372 on inner walls of the first and second trenches 345a and 345b arranged. For example, each of the first patterns 375a of metal semiconductor interconnect material on the common source region 350 between a pair of adjacent protective spacers 372 in a corresponding one of the first trenches 345a arranged. Each of the protective spacers 372 in the first trenches 345a is between a sidewall of the first trench 345a and a side wall of the first insulating spacer 378a arranged. Similarly, the second pattern is 375b of metal semiconductor interconnect material on the well receiving area 302 between a pair of adjacent protective spacers 372 in the second trench 345b arranged. Each of the protective spacers 372 in the second trench 345b is between a side wall of the second trench 345b and a side wall of the second insulating spacer 378b arranged. Each of the protective spacers 372 may include an oxide material, a nitride material and / or an oxynitride material.

A dielectric interlayer 388 can on the substrate 300 with the connection pins 385a and the conductive well conduit 385b be arranged. The dielectric interlayer 388 may include an oxide material, a nitride material and / or an oxynitride material. The bitlines 395a can on the dielectric interlayer 388 be arranged. bit 395a are with upper areas, ie areas, of the substrate 300 farthest away, the vertical active pattern 330 electrically connected. In particular, the bitlines 395a with the drain regions in the vertical active patterns 330 electrically connected. The bitlines 395a can further by first conductive pins 390a with the upper areas of the vertical active pattern 330 be electrically connected. The first conductive pins 390a penetrate the dielectric interlayer 388 and the dielectric cover patterns 335 to the vertical active pattern 330 to contact.

In addition, a connection line 395b on the dielectric interlayer 388 be arranged. The connection line 395b is with the connection pins 385a electrically connected. The connection line 395b is through second conductive pins 390b with the connection pins 385a electrically connected. The second conductive pins 390b penetrate the dielectric interlayer 388 to the connection pins 385a to contact.

The bitlines 395a and the connection line 395b can be at essentially the same level from the top of the substrate 300 are located. In other words, the bitlines 395a and the connection line 395b to be essentially coplanar. In corresponding embodiments, an interconnect line may be on the dielectric interlayer 388 be arranged. The interconnection line is connected to the conductive well line 385b electrically connected. The interconnection line is at substantially the same level as the bit lines 395a and the connection line 395b arranged. The interconnection line may connect to one end or both ends of the conductive well conduit 385b be electrically connected.

Each of the first and second conductive pins 390a and 390b For example, at least one of a metal layer (eg, a tungsten layer, a copper layer, an aluminum layer, or the like), a conductive metal nitride layer (eg, a titanium nitride layer, a tantalum nitride layer, or the like) and a transition metal layer (e.g. Titanium layer, a tantalum layer or the like). Each of the bit lines 395a and the connection line 395b At least one of a metal layer (eg, a tungsten layer, a copper layer, an aluminum layer, or the like), a conductive metal nitride layer (eg, a titanium nitride layer, a tantalum nitride layer, or the like) and a transition metal layer (eg, a titanium layer, a tantalum layer or the like).

8D sets the bitlines 395a and the connection line 395b in the top view of 8A Referring to 8D the bitlines extend 395a and the connection line 395b essentially parallel. The bitlines 395a and the connection line 395b cross over the stack structures 370a and 370b , The connection line 395b overlaps with some of the vertical active patterns 330 which the stack structures 370a and 370b penetrate as in 8D shown. The vertical active patterns 330 , which with the connecting line 395b overlap, may correspond to vertical active dummy patterns. In addition, the vertical active patterns 330 , which partly with the connecting line 395b overlap, also corresponding to the vertical active dummy patterns. The vertical active dummy patterns are not with the bitlines 395a electrically connected.

Referring to the 8B and 8C can the second stack structures 370b Match dummy patterns. That is, the vertical active patterns 330 which the second stack structures 370b can also correspond to the vertical dummy active patterns. Thus, the vertical active patterns 330 which the second stack structures 370b penetrate, not with the bitlines 395a electrically connected. In corresponding embodiments, the first conductive pin is 390a not on the vertical active patterns 330 arranged, which the second stack structures 370b penetrate to act as the vertical active dummy patterns, as in 8C shown. Similarly, the first conductive pin needs 390a not on the vertical active dummy patterns of the vertical active patterns 330 be arranged, which are the first stack structures 370a penetrate. The vertical active dummy patterns showing the first stacking structures 370a can penetrate partially with the connecting line 395b overlap or may, when viewed in a plan view of the connecting line 395b adjoin.

According to corresponding embodiments of this 3D semiconductor memory device, the common source regions 350 through the connection pins 385a with the connection line 395b electrically connected. Thus, the electrical resistance of the common source regions 350 reduced. In addition, the trough area 301 with the conductive trough line 385b electrically connected. Thus, the electrical resistance of the well region 301 reduced. As a result, the reliability of the 3D semiconductor memory device can be improved and can be relatively high.

In addition, the connection pins are 385a in the respective openings 380a arranged through the first insulating spacers 378a are defined. Furthermore, the conductive well conduit is 385b in through the second insulating spacers 378b defined depression 380b arranged. That is, the connection pins 385a and the conductive well conduit 385b can through the first and second insulating spacers 378a and 378b be self-aligned. Thus, there is an adjusting clearance between the connecting contact pins 385a and the common source areas 350 not mandatory. Similarly, there is an adjustment margin between the conductive well conduit 385b and the tray receiving area 302 not mandatory. As a result, the 3D semiconductor memory device is improved / optimized to have a high reliability and a high integration density.

9 represents a further embodiment as a variant of the 3D semiconductor memory devices of 8A to 8D Referring to 9 is a dielectric multilayer 460 between vertical active patterns 430 and the gate patterns GSG, CG and SSG. The dielectric multilayer 460 may include a tunnel dielectric layer, a charge storage layer, and a dielectric blocking layer. The tunneling dielectric layer, the charge storage layer and the dielectric blocking layer may be formed of the same material layers as the tunneling dielectric layer, the charging layer and the dielectric blocking layer described with reference to FIGS 8A to 8C have been described.

The dielectric multilayer 460 includes a first sublayer 455 and a second sub-layer 457 , The first sub-layer 455 can extend vertically to between the vertical active patterns 430 and the insulation patterns 310a to lie. The second sub-layer 457 may extend horizontally to cover the bottoms and tops of the gate patterns GSG, CG and SSG. The first sub-layer 455 includes at least a portion of the tunnel dielectric layer, and the second sub-layer 457 includes at least a portion of the dielectric blocking layer. Each of the first and second sublayers 455 and 457 may include the charge storage layer. In corresponding embodiments, the first one includes sublayer 455 the tunnel dielectric layer, the charge storage layer and the dielectric barrier layer, e.g. B. a part of the dielectric blocking layer, and the second sub-layer 457 includes the high-k dielectric layer, e.g. B. another part of the dielectric blocking layer. However, the invention is not limited to such embodiments. That is, the first and second sublayers 455 and 457 can have a variety of other combinations.

Each of the vertical active patterns 430 includes a first vertical semiconductor pattern 427 and a second vertical semiconductor pattern 428 , The first vertical semiconductor patterns 427 are between the second vertical semiconductor patterns 428 and the first sublayers 455 arranged. The first vertical semiconductor patterns 427 contact the trough area 301 due to the presence of horizontal extensions of the first sublayers 455 not while the second vertical semiconductor pattern 428 the first vertical semiconductor pattern 427 and the trough area 301 contact, for. B. contact directly. The second vertical semiconductor pattern 428 can have different shapes, e.g. As a macaroni shape or a tubular shape. An empty interior of each of the second vertical semiconductor patterns 428 is surrounded with the dielectric filling pattern 325 , z. B. in the 8B and 8C illustrated dielectric filling pattern 325 , filled. Each of the vertical active patterns 430 further includes the semiconductor cover pattern 327 , z. B. in the 8B and 8C illustrated semiconductor cover pattern 327 , The first and second vertical semiconductor patterns 427 and 428 can be the same semiconductor layer as the substrate 300 include. The first and second vertical semiconductor patterns 427 and 428 may be doped with dopants of the first conductivity type. Alternatively, the first and second vertical semiconductor patterns 427 and 428 be undoped semiconductor patterns, z. B. intrinsic semiconductor patterns. A drain region doped with dopants of the second conductivity type may be present in at least a portion of each of the semiconductor cap patterns 327 be educated.

Referring to the 8A to 9 are the protective spacers 372 and the patterns 375a and 375b of metal semiconductor interconnect material in corresponding embodiments on the 3D semiconductor memory device such as those described with reference to FIGS 1A to 1C , referring to the 2A and 2 B , referring to the 3A and 3B and / or with reference to the 4A and 4B described, attached.

The 10A . 11A . 12A . 13A . 14A . 15A . 16A and 17A are composite cross-sectional views taken along lines II 'and II-II' of FIG 8A to illustrate method steps for fabricating a 3D semiconductor memory device according to respective embodiments, and FIGS 10B . 11B . 12B . 13B . 14B . 15B . 16B and 17B are cross-sectional views along lines II-II 'of 8A to continue the steps.

Referring to the 10A and 10B become dopants of a first conductivity type in a substrate 300 provided to a trough area 301 to build. A tray receiving area 302 is in a part of the trough area 301 formed as in 10B shown. The tray receiving area 302 can with dopants of the same conductivity type as the trough area 301 be doped. The dopant concentration of the well receiving area 302 can be higher than that of the trough area 301 be.

A dielectric buffer layer 303 will be on the substrate 300 with the trough area 301 educated. sacrificial layers 305 and insulation layers 310 are alternately and repeatedly on the dielectric buffer layer 303 stacked. The sacrificial layers 305 are made of a material layer having an etching selectivity with respect to the insulating layers 310 educated. For example, the insulation layers 310 are formed of an oxide layer, and the sacrificial layers 305 can be formed from a nitride layer. The dielectric buffer layer 303 can be formed from an oxide layer.

The insulation layers 310 , the sacrificial layers 305 and the dielectric buffer layer 303 are structured to a plurality of channel openings 315 to form which the trough areas 301 uncover. Then, a conformal semiconductor layer is formed on the substrate 300 with the channel openings 315 is formed, and a dielectric filling layer is formed on the semiconductor layer. The dielectric filling layer is formed around the channel openings 315 to fill. The dielectric filling layer and the semiconductor layer are planarized until the uppermost, ie from the substrate 300 furthest away, insulation layer 310 is exposed, creating a vertical semiconductor pattern 320 and a dielectric filling pattern 325 in each of the channel openings 315 be formed. The vertical semiconductor patterns 320 and the dielectric filling patterns 325 are deepened, so that topmost, ie from the substrate 300 farthest, vertical semiconductor pattern surfaces 320 and the dielectric filling pattern 325 at a lower level, ie closer to the substrate 300 as an upper surface of the uppermost insulating layer 310 are located. A semiconductor capping layer becomes on the substrate 300 with the recessed vertical semiconductor patterns 320 and the recessed dielectric fill patterns 325 educated. The semiconductor cover layer fills the channel openings 315 standing on the recessed vertical semiconductor patterns 320 and the recessed dielectric fill patterns 325 are provided. The semiconductor capping layer is planarized until the uppermost insulating layer 310 is exposed, whereby a plurality of semiconductor Abdeckmustern 327 is formed. Each of the vertical semiconductor patterns 320 and the semiconductor cover pattern 327 on it forms a vertical active pattern 330 , Dopants of a second conductivity type become in upper regions of the vertical active patterns 330 provided to form a plurality of drain regions.

Referring to the 11A and 11B becomes a dielectric capping layer on the substrate 300 formed with the drain regions. The dielectric covering layer, the insulating layers 310 and the sacrificial layers 305 are structured to ditches 345a and 345b to form a plurality of casting patterns 340a and 340b define. As a result, dielectric cover patterns become 335 on the casting patterns 340a respectively 340b educated. The respective dielectric cover patterns 335 are vertically self-aligned to the respective casting patterns 340a and 340b underneath. That is, side walls of each of the dielectric cover patterns 335 are vertically self-aligned to sidewalls of the corresponding casting pattern 340a and 340b ,

Each of the casting patterns 340a and 340b includes sacrificial patterns 305a and isolation patterns 310a which are stacked alternately and repeatedly. The plurality of casting patterns includes first casting patterns 340a and second casting patterns 340b , The trenches contain first trenches 345a and a second ditch 345b , The first trenches 345a are between a pair of adjacent first casting patterns 340a defined as in 11A shown. The second ditch 345b is between a pair of adjacent second casting patterns 340b defined as in 11B shown. The first and second casting patterns 340a and 340b can be the same planar shape as the one in 8A illustrated first and second stack structures 370a respectively 370b exhibit. That is, the planar shape of the first casting patterns 340a can be the same as the one in 8A illustrated first stack structures 370a and the planar shape of the second casting patterns 340b can be the same as the one in 8A illustrated second stack structures 370b be.

As in 11A illustrated, each includes the first trenches 345a a first region having a first width D1 and a second region having a second width D2. The second width D2 may be greater than the first width D1. Each of the first casting patterns 340a includes a first part adjacent to the first region of the respective first trenches 345a and a second part adjacent to the second area of the respective first trenches 345a , A width Wb of the second part of the respective first casting patterns 340a may be less than a width Wa of the first part of the respective first casting patterns 340a be. As in 11B shown, the second trench points 345b a third width D3. The second ditch 345b may have a substantially uniform width.

Referring to the 11A and 11B become dopants of a second conductivity type in the trough area 301 under the first ditches 345a injected to common source areas 350 to build. The substrate 300 under the second ditch 345b can be protected by a mask pattern, while the dopants of the second conductivity type in the well region 301 under the first ditches 345a be injected. The tray receiving area 302 is located under the second ditch 345b ,

In corresponding embodiments, the tray receiving area becomes 302 before forming the dielectric buffer layer 303 in the trough area 301 formed, and the second trench 345b is to the tray receiving area 302 adjusted. Alternatively, the tray receiving area 302 after the formation of the second trench 345b educated. For example, after the formation of a mask pattern, which becomes the substrate 300 under the first ditches 345a covered, dopants of the first conductivity type in the trough area 301 under the second ditch 345b injected to the trough receiving area 302 to build. Such is the tray receiving area 302 so formed that it self-adjusts to the second trench 345b is.

The dielectric buffer layer 303 under the first and second trenches 345a and 345b can after the formation of the common source areas 350 be removed. Alternatively, the dielectric buffer layer 303 under the first and second trenches 345a and 345b during the formation of the first and second trenches 345a and 345b be removed. When the dielectric buffer layer 303 under the first and second trenches 345a and 345b is removed, become dielectric buffer pattern 303a under the casting patterns 340a and 340b educated.

Referring to the 12A and 12B become the sacrificial patterns 305a removed to empty areas 355 to build. The empty areas 355 put some parts of sidewalls of the vertical active pattern 330 free. The isolation pattern 310a can be made of a material layer with an etching selectivity with respect to the sacrificial pattern 305a be formed. Thus, the isolation patterns 310a remain, even if the victim patterns 305a are removed. The isolation pattern 310a be of the vertical active patterns 330 carried. The empty areas 355 are between the stacked insulation patterns 310a arranged.

Referring to the 13A and 13B becomes a dielectric multilayer 360 compliant on the substrate 300 with the empty areas 355 formed, and one the empty areas 355 filling, conductive gate layer is on the dielectric multilayer 360 educated. Parts of the conductive gate layer outside the empty areas 355 are removed to form gate patterns GSG, CG and SSG containing the empty areas 355 to fill. As a result, a plurality of stack structures 370a and 370b on the substrate 300 educated. Each of the stack structures 370a and 370b includes the gate patterns GSG, CG and SSG as well as the isolation patterns 310a which are stacked alternately and repeatedly. Parts of the dielectric multilayer 360 that are outside the empty areas 355 are formed after the formation of the gate patterns GSG, CG and SSG are removed.

The plurality of stack structures include first stack structures 370a and second stack structures 370b , Each of the first trenches 345a is between a pair of adjacent first stack structures 370a defined, and the second trench 345b is between a pair of adjacent second stack structures 370b Are defined.

Referring to the 14A and 14B becomes a protective spacer layer conforming to the substrate 300 formed with the gate patterns GSG, CG and SSG. The protective spacer layer is anisotropically etched to protect spacers 372 on sidewalls of the first and second trenches 345a and 345b to build.

First metal semiconductor connection patterns 375a after the formation of the protective spacers 372 on the common source areas 350 educated. Similarly, a second metal semiconductor connection pattern becomes 375b on the tray receiving area 302 educated. The first and second metal semiconductor connection patterns 375a and 375b can be prepared using a self-aligned silicide technique, e.g. B. SALICIDE, are formed simultaneously. For example, a metal layer may be on the substrate 300 with the protective spacers 372 be formed. The metal layer may be the common source regions 350 and the tray receiving area 302 contact, for. B. contact directly. An annealing process may be performed such that metal atoms in the metal layer on semiconductor atoms in the common source regions 350 and the tray receiving area 302 react. As a result, the first metal semiconductor connection patterns become 375a on the common source areas 350 formed, and the second metal semiconductor connection pattern 375b is on the tray receiving area 302 educated. Then an unreacted metal layer is removed. The metal forming process and annealing process may be performed using an in situ technique. The metal layer may be formed on a cobalt layer, a nickel layer or a titanium layer.

An insulating spacer layer 378 will be on the substrate 300 with the metal semiconductor connection patterns 375a and 375b educated. In corresponding embodiments, the insulating spacer layer fills the first regions of the first trenches 345a while the insulating spacer layer 378 compliant in the second areas of the first trenches 345a is formed. This is because the second width D2 of the second regions is larger than the first width D1 of the first regions. In addition, the insulating spacer layer 378 also compliant in the second trench 345b be formed.

Referring to the 15A and 15B becomes the insulating spacer layer 378 anisotropically etched to first insulating spacers 378a and second insulating spacers 378b to build. The first insulating spacers 378a be on sidewalls, z. B. opposite side walls, the first trenches 345a formed, and the second insulating spacers 378b be on sidewalls, z. B. opposite side walls, the second trench 345b educated.

Each of the first trenches 345a includes the first region having the first width D1 and the second region having the second width D2. The pair of first insulating spacers 378a in each of the first areas is in contact with each other, for. B. in direct contact, as in 15A shown. In contrast, the pair of first insulating spacers 378a in each of the second areas separated as further in 15A shown. Thus, in each of the second regions of the first trenches 345a one of the first insulating spacers 378a surrounded opening 380a provided. The openings 380a in the second areas, the first metal semiconductor connection patterns lay 375a free under the second areas.

The pair of second insulating spacers 378b in the second trench 345b is separated from each other, as in 15B shown. Thus, between the pair of second insulating spacers 378b in the second trench 345b a depression 380b provided. The depression 380b puts the second one Metal semiconductor compound pattern 375b under the second ditch 345b free.

Referring to the 16A and 16B becomes a conductive layer 385 on the substrate 300 with the first and second insulating spacers 378a and 378b educated. The conductive layer 385 is formed so that it is essentially the openings 380a and the depression 380b crowded.

Referring to the 17A and 17B becomes the conductive layer 385 planarized until the insulating spacers 378a and 378b and / or the dielectric cover patterns 335 are exposed until z. B. are exposed surfaces of the substrate 300 farthest away. As a result, the openings become 380a filling connection pins 385a formed, and it becomes a depression 380b filling conductive trough line 385b educated. Some parts of the conductive layer 385 can after the planarization of the conductive layer 385 on the first insulating spacers 378a in the first areas of the first trenches 345a remain. The remnants of the conductive layer 385 can be removed using a cleaning process. Alternatively, the remainders of the conductive layer 385 remain without using the cleaning process. Even if the remains of the conductive layer 385 can remain, the remains of the conductive layer 385 electrically insulated by a subsequently formed insulating intermediate layer. Thus, the remains of the conductive layer influence 385 the operation of the 3D semiconductor memory device is not significant.

Then an insulating intermediate layer 388 on the substrate 300 with the connection pins 385a and the conductive well conduit 385b educated. The following are first and second conductive pins 390a and 390b formed, which is the insulating intermediate layer 388 penetrate, such. In 8B represented, and there are bitlines 395a and a connection line 395b on the insulating interlayer 388 formed, such. Tie 8B to 8D shown. Accordingly, with reference to FIGS 8A to 8D described 3D semiconductor memory device using the in the 10A to 17B provided method steps.

According to the manufacturing methods of respective embodiments, the openings 380a and the depression 380b so formed that they are self-aligned to the insulating spacers 378a respectively 378b are. Thus, the reliability of the 3D semiconductor memory device can be improved, and process margin can be increased in the fabrication of the 3D semiconductor memory device.

The 18A to 18C provide a method of manufacturing the 3D semiconductor memory device of 9 Referring to 18A becomes a first sublayer 455 after the formation of channel openings 315 compliant on a substrate 300 educated. A first semiconductor layer becomes conformal on the first sublayer 455 educated. The first semiconductor layer and the first sub-layer 455 are etched anisotropically until a well area 301 under the canal openings 315 is exposed. As a result, first vertical semiconductor patterns become 427 on side walls of the channel openings 315 educated. Due to the presence of the first sub-layer 455 in the channel openings 315 Contact the first vertical semiconductor pattern 427 the trough area 301 Not.

Referring to 18B a second semiconductor layer conforms to the substrate 300 with the first vertical semiconductor patterns 427 formed, and a dielectric filling layer, which the channel openings 315 is substantially filled, is formed on the second semiconductor layer. The dielectric filling layer and the second semiconductor layer are planarized until the uppermost, ie, from the substrate 300 furthest away, insulation layer 310 is exposed, creating a second vertical semiconductor pattern 428 and a dielectric filling pattern 325 formed by the second vertical semiconductor pattern 428 in each of the channel openings 315 is surrounded. Each of the second vertical semiconductor patterns 428 contacted, contacted z. B. directly, the first vertical semiconductor pattern 427 and the trough area 301 in the canal opening 315 , The first and second vertical semiconductor patterns 427 and 428 as well as the dielectric filling patterns 325 are deepened so that the top, ie from the substrate 300 farthest surfaces of the first and second vertical semiconductor patterns 427 and 428 and the dielectric filling pattern 325 at a lower level, ie closer to the substrate 300 as an upper surface of the uppermost insulating layer 310 are located. There will be semiconductor cover patterns 327 formed around the channel openings 315 on the recessed first and second vertical semiconductor patterns 427 and 428 and the recessed dielectric fill patterns 325 to fill. The first and second vertical semiconductor patterns 427 and 428 and the semiconductor cover pattern 327 in each of the channel openings 315 form a vertical active pattern 430 ,

A dielectric capping layer is placed on the substrate 300 with the semiconductor cover patterns 327 educated. The dielectric covering layer, the insulating layers 310 and the sacrificial layers 305 are structured to first trenches 345a to build. A second trench, z. B. the second trench 345b from 8C , is during the formation of the first trenches 345a educated. The first trenches 345a expose victim patterns, and the victim patterns are removed to empty areas 355 to build. The empty areas 355 put the first sublayers 455 on sidewalls of the vertical active patterns 430 free.

Referring to 18C becomes a second sublayer 457 compliant on the substrate 300 with the empty areas 355 formed, and a conductive gate layer is on the second sub-layer 457 educated. The conductive gate layer is formed to cover the empty areas 355 essentially fills. Parts of the conductive gate layer outside the empty areas 355 are removed to form gate patterns GSG, CG and SSG containing the empty areas 355 essentially fill. The first sub-layer 455 and the second sub-layer 457 form a dielectric multilayer 460 , Subsequent processes can be performed using the methods described in US Pat 14A to 17A and the 14B to 17B Process steps are performed.

Components of the 3D semiconductor memory devices according to respective embodiments of the invention may be combined / embodied in various forms. For example, the 3D semiconductor memory device may be encapsulated using various packaging techniques. For example, the 3D semiconductor memory device may be fabricated using any of a pack-on-pack (POP) technique, a ball grid array (BGAs) technique, a chip-scale packaging (CSPs) technique, a plastic Leaded chip carrier (PLCC) technology, a plastic dual in-line packaging (PDIP) technique, a die-in-waffle packaging technique, a die-in-wafer-forming technique, a chip on-board (COB) technology, a ceramic dual-in-line package (CERDIP) technique, a plastic quad flat pack (MQFP) technique, a thin quad flat pack (TQFP), Technology, a Small Outline Pack (SOIC) technique, a Shrink Small Outline Pack (SSOP) technique, a Thin Small Outline Pack (TSOP) technique, a system-in-pack (SIP ), A multi-chip packaging (MCP) technique, a wafer-level fabricated packing (WFP) technique, and a wafer-level processed stack packing (WSP) technique.

The package in which a 3D semiconductor memory device is mounted may further include at least one semiconductor device, e.g. For example, a control unit, a memory device, and / or a hybrid device having a function different from that of the 3D semiconductor memory device.

19 represents an example of an electronic system 1100 which includes one or more 3D semiconductor memory devices according to the invention. Referring to 19 includes the electronic system 1100 a control unit 1110 , an input / output (I / O) unit 1120 , a memory device 1130 , an interface unit 1140 and a data bus 1150 , At least two from the control unit 1110 , the I / O unit 1120 , of the memory device 1130 and the interface unit 1140 can over the data bus 1150 communicate with each other. The data bus 1150 corresponds to a path through which electrical signals are transmitted.

The control unit 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller or other logic device. Another logic device may have a similar function as any of the microprocessor, the digital signal processor, and the microcontroller. The I / O unit 1120 may include a keypad, a keyboard, or a display unit. The memory device 1130 can store data and / or commands. The memory device 1130 may include at least one 3D semiconductor memory device according to the invention described herein. The memory device 1130 may further include another type of semiconductor memory devices, that is, a type different from the 3D semiconductor memory device of the invention. For example, the memory device 1130 further includes a magnetic memory device, a phase change memory device, a dynamic random access memory (DRAM) device, and / or a static random access memory (SRAM) device. The interface unit 1140 transmits electrical data to a communication network or receives electrical data from a communication network. The interface unit 1140 can work wirelessly or with cable. For example, the interface unit includes 1140 an antenna for wireless communication or a transceiver for cable communication. The electronic system 1100 may further include a fast DRAM device and / or a fast SRAM device serving as a cache to improve operation of the controller 1110 acts.

The electronic system 1100 can be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card or other electronic product. The other electronic product can receive or transmit information data wirelessly.

20 represents an example of a memory card 1200 which includes one or more of the 3D semiconductor memory devices according to the invention. Referring to 20 includes the memory card 1200 a memory device 1210 , The memory device 1210 may include at least one 3D semiconductor memory device according to the invention described herein. The memory device 1210 may further include another type of semiconductor devices, that is, a type different from the three-dimensional semiconductor memory devices described herein. For example, the memory device 1210 further includes a magnetic memory device, a phase change memory device, a dynamic random access memory (DRAM) device, and / or a static random access memory device. The memory card 1200 includes a memory controller 1220 involving a data communication between a host and the memory device 1210 controls.

The memory controller 1220 includes a processing unit 1222 , z. A central processing unit (CPU), the overall operations of the memory card 1200 controls. In addition, the memory controller includes 1220 an SRAM device 1221 as the operating memory of the processing unit 1222 is used. In addition, the memory controller includes 1220 a host interface (I / F) unit 1223 and a memory interface (I / F) unit 1225 , The host interface unit 1223 may be configured to include a data communication protocol. The storage interface unit 1225 controls the communication between the memory controller 1220 and the memory device 1210 , The memory controller 1220 further includes an error checking and correction (ECC) block 1224 , The ECC block 1224 detects and corrects errors of data coming from the memory device 1210 be read out. The memory card 1200 may further include a read-only memory (ROM) device storing code data for interfacing with the haste. The memory card 1200 Can be used as a portable data storage card. Alternatively, the memory card 1200 Replace hard drives of computer systems with solid state drives of computer systems.

According to respective embodiments of the invention, connection pins may contact respective common source regions, e.g. B. contact directly. Thus, the electrical resistance of each of the common source regions can be reduced / minimized. Further, each of the connection contact pins may be disposed adjacent / adjacent to a second part of a stack structure, and the second part of the stack structure may have a relatively small width. Thus, a planar region of a portion of each of the common source regions electrically connected to the interconnect pins may be increased / maximized within a limited area due to the presence of the relatively narrow second portions of the stack structures, i. H. can be relatively large. Accordingly, the 3D semiconductor memory device according to the invention is improved / optimized to have a high reliability and a high integration density.

Claims (19)

3D semiconductor memory device having - a stack structure ( 170 ) extending in a first direction on a substrate ( 100 ) and gate patterns (GSG, CG, SSG) and isolation patterns ( 110a ), which are stacked alternately and repeatedly, the stack structure comprising a first region ( 168a ) and a second area ( 168b ) and the second region of the stack structure has a smaller width (W2) than a width (W1) of the first region in a second direction substantially perpendicular to the first direction, - a plurality of vertical active patterns ( 130 ), which penetrate the stack structure, - a dielectric multilayer ( 160 between a sidewall of one of the plurality of vertical active patterns and corresponding ones of the gate patterns, - a common source region ( 150 ) in the substrate adjacent to one side of the stack structure and - a connection pin ( 180 ) on the common source region, wherein the connection pin adjoins the second region of the stack structure. The 3D semiconductor memory device of claim 1, wherein - the first region of the stack structure has opposing first and second sidewalls ( 172a . 172b ), which extend substantially parallel to the first direction, - the second region of the stack structure opposite first and second side walls ( 173a . 173b ), the first side wall of the second region of the stack structure is recessed toward the second side wall of the second region of the stack structure so as to have a concave shape, and the connection contact pin is adjacent to the first side wall of the second region of the stack structure. The 3D semiconductor memory device according to claim 2, wherein the second sidewalls of the first and second regions of the stacked structure are one in Define substantially flat side wall extending substantially in the first direction. The 3D semiconductor memory device of claim 2, wherein the second sidewall of the second region of the stack structure is recessed toward the first sidewall of the second region of the stack structure so as to have a concave shape in a plan view. A 3D semiconductor memory device according to any one of claims 1 to 4, wherein - the common source region extends substantially in the first direction and a non-contact surface region ( 148a ) adjacent to the first region of the stack structure and a contact surface region ( 148b ) adjacent to the second region of the stack structure, and a width (S2) of the pad area is greater than a width (S1) of the non-pad area in the second direction. A 3D semiconductor memory device according to any one of claims 1 to 5, further comprising an isolation pattern (Fig. 177 ) on the common source region, wherein the connection pin penetrates the insulation pattern so as to be electrically connected to the common source region. A 3D semiconductor memory device according to any one of claims 1 to 6, further comprising an insulating spacer (10). 378a ) on a sidewall of the stacked structure, wherein a portion of the insulating spacer is located between the interconnect pin and the second portion of the stacked structure, and wherein the interconnect pin contacts the insulating spacer. A 3D semiconductor memory device according to any one of claims 1 to 7, further comprising: - a bit line ( 190a ) electrically connected to an upper end of one of the plurality of vertical active patterns, and - a connecting line ( 190b ) electrically connected to the connection pin. The 3D semiconductor memory device of claim 8, wherein the bitline and the interconnect line are substantially coplanar and extend substantially in the second direction. The 3D semiconductor memory device according to any one of claims 1 to 9, wherein the dielectric multi-layer covers upper and lower sides of respective ones of the gate patterns. A 3D semiconductor memory device according to any one of claims 1 to 10, comprising - a plurality of stack structures ( 170 ) extending in parallel in the first direction on the substrate, wherein the plurality of stack structures are separated from each other in the second direction and each of the plurality of stack structures includes gate patterns and isolation patterns alternately and repeatedly stacked - a plurality of vertical active ones Inspect ( 130 penetrating respective ones of the plurality of stack structures, - a plurality of dielectric multilayers ( 160 between respective sidewalls of the plurality of vertical active patterns and respective ones of the gate patterns, - a plurality of common source regions ( 150 ) formed in the substrate under trenches defined between the plurality of stack structures, and - a connection pin ( 180 ) electrically connected to one of the plurality of common source regions, wherein the connection pin is between a pair of the plurality of stack structures, and wherein at least one stack structure in the pair of the plurality of stack structures includes the first region and the second region Width of the second region is less than that of the first region and the connection pin is adjacent to a side of the second region. The 3D semiconductor memory device according to claim 11, wherein - the one of the plurality of common source regions electrically connected to the connection pin has a non-contact area (FIG. 148a ) and a contact surface area ( 148b ), the pad area has a larger width than the non-pad area in the second direction, and the pad area is one of a plurality of pad areas arranged in the second direction along with a plurality of second areas of the plurality of stack structures. A 3D semiconductor memory device according to claim 11 or 12, wherein A plurality of connection pins are provided that are electrically connected to respective ones of the plurality of common source regions, Each of the plurality of stack structures includes the first region and the second region, and - The plurality of connection contact pins and the second regions of the stack structures are arranged alternately and repeatedly in the second direction. A 3D semiconductor memory device according to any one of claims 11 to 13, further comprising: - a doped connection region ( 200 ) in the substrate to electrically connect the plurality of common source regions with the doped junction region extending in the second direction, and a junction line (FIG. 190b ) electrically connected to an upper surface of the connection contact pin, wherein the connection line extends substantially in the second direction and wherein a number of connection contact pins connected to the connection line is less than a number of the common source regions. A 3D semiconductor memory device according to any one of claims 11 to 14, further comprising a pair of insulating spacers (Fig. 378a ) on opposite sidewalls of each of the trenches, wherein one of the trenches is on the one of the plurality of common source regions electrically connected to the interconnect pin, and a first region adjacent to the first region of the at least one stacked structure and a second region The region adjacent to the second region of the at least one stacked structure, the pair of insulating spacers contacting each other in the first region and being separated from each other in the second region to define an opening surrounded by the pair of insulating spacers, and - The connecting pin extends into the opening. 3D semiconductor device with - first and second stack structures ( 370a . 370b ) each including gate patterns and an insulating pattern between the gate patterns, first and second active patterns ( 330 ), which penetrate the first and second stack structures, respectively - a common source region ( 350 ) between the first and second stack structures, - a connection pin ( 385a ) in an enlarged area ( 148b ) of the common source region extending between first and second smaller regions ( 148a ) of the common source region, and - a connecting line ( 395b ) on the first and second stack structures and on the connection pin. A 3D semiconductor device according to claim 16, wherein - the extended region of the common source region to a recessed region ( 168b ) adjoins the first stack structure or adjoins first and second recessed regions in the first and second stack structures, respectively, and a distance (D1, D2) between the first and second stack structures in the expanded region of the common source region greater than in the first and second smaller ones Is areas of the common source area. A 3D semiconductor device according to claim 16 or 17, further comprising a pattern ( 375a . 375b ) of metal semiconductor interconnect material between the interconnect pin and the common source region. A 3D semiconductor device according to any one of claims 16 to 18, further comprising first and second insulating spacers ( 378a . 378b ) on first and second side walls of the connection contact pin such that the first and second insulating spacers ( 378a ) are located between the connection pin and the first and second stack structures.

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