CN109742038B - 3D NAND memory and forming method thereof - Google Patents
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Abstract
A3D NAND memory and a forming method thereof are provided, wherein the forming method of the 3D NAND memory forms an intermediate isolation layer between a first stacked structure and a second stacked structure, the intermediate isolation layer and the first stacked structure are etched in sequence, and when a gate spacer is formed in the second stacked structure, the intermediate isolation layer and the first stacked structure, the intermediate isolation layer is utilized to enable the etching rate of etching the intermediate isolation layer to be consistent with the etching rate of etching the first stacked structure, and the etching rate of etching the second stacked structure to be consistent with the etching rate of etching the first stacked structure, so that the side wall of the gate spacer, which is caused by the fact that the etching rate of the intermediate isolation layer is different from the etching rate of etching the first stacked structure and the etching rate of the second stacked structure, is prevented from generating bending defects.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a 3D NAND memory and a forming method thereof.
Background
NAND flash memory is a better storage device than hard disk drives, and is widely used in electronic products as people seek nonvolatile storage products with low power consumption, light weight and good performance. At present, NAND flash memories with a planar structure are approaching the limit of practical expansion, and in order to further increase the storage capacity and reduce the storage cost per bit, 3D NAND memories with a 3D structure are proposed.
The existing manufacturing process of the 3D NAND memory comprises the following steps: providing a substrate, wherein a stacked structure in which isolation layers and sacrificial layers are alternately stacked is formed on the substrate; etching the stacked structure, and forming a channel hole exposing the surface of the substrate in the stacked structure; forming a storage structure in the channel hole; after the storage structure is formed, etching the stacked structure, and forming a grid separation groove in the stacked structure; removing the sacrificial layer, and forming a control gate at the position where the sacrificial layer is removed; and filling a conductive material in the grid isolation groove to form an array common source.
In order to further increase the storage capacity, in the prior art, when the stacked structure is formed, a multi-layer stacked structure is usually formed, each layer of stacked structure includes a plurality of alternately stacked isolation layers and sacrificial layers, a thick silicon oxide layer is formed between adjacent stacked structures, and a gate spacer exposed out of the surface of the substrate is formed by etching the thick silicon oxide layer between the multi-layer stacked structure and the stacked structure, but the sidewall morphology of the gate spacer is poor.
Disclosure of Invention
The invention aims to solve the technical problem of how to prevent the side wall of a grid spacer groove from generating bending defects.
The invention provides a method for forming a grid spacer groove of a 3D NAND memory, which comprises the following steps:
providing a substrate, wherein a first stacked structure in which isolation layers and sacrificial layers are alternately stacked, an intermediate isolation layer positioned on the first stacked structure, and a second stacked structure in which isolation layers and sacrificial layers are alternately stacked are formed on the intermediate isolation layer;
and etching the second stacked structure, the intermediate isolation layer and the first stacked structure in sequence to form a grid spacer groove in the second stacked structure, the intermediate isolation layer and the first stacked structure, and when etching, utilizing the intermediate isolation layer to ensure that the etching rate of etching the intermediate isolation layer is consistent with the etching rate of etching the first stacked structure, and the etching rate of etching the second stacked structure is consistent with the etching rate of etching the first stacked structure.
Optionally, the intermediate isolation layer includes: a first detection material layer on the first stacked structure; the insulating layer is positioned on the surface of the first detection material layer; a second detection material layer on the insulating layer; the second stacked structure is positioned on the second detection material layer; during the etching, the method for keeping the etching rate of the isolation layer in the etching consistent with the etching rate of the first stacked structure, and the method for keeping the etching rate of the second stacked structure consistent with the etching rate of the first stacked structure comprises the following steps: and when the first detection material layer is detected to be etched, changing the etching rate to etch the insulating layer so that the etching rate when the insulating layer is etched is consistent with the etching rate when the second stacking structure is etched, and when the first detection material layer is detected to be etched, changing the etching rate to etch the first stacking structure so that the etching rate when the first stacking structure is etched is consistent with the etching rate when the second stacking structure is etched.
Optionally, the materials of the first detection material layer and the second detection material layer are each independently SiON, Al2O3TiN or TaN.
Optionally, whether the second detection material layer is etched is judged by detecting a change in a spectrum of a byproduct generated when the second stack structure and the second detection material layer are etched, and whether the first detection material layer is etched is judged by detecting a change in a spectrum of a byproduct generated when the insulating layer and the first detection material layer are etched.
Optionally, when the second detection material layer is detected and etched, the etching rate is reduced to etch the insulating layer, so that the etching rate when the insulating layer is etched is kept consistent with the etching rate when the second stacked structure is etched, and when the first detection material layer is detected and etched, the etching rate is increased to etch the first stacked structure, so that the etching rate when the first stacked structure is etched is kept consistent with the etching rate when the second stacked structure is etched.
Optionally, when the sacrificial layer is made of silicon nitride, the insulating layer and the isolation layer are made of silicon oxide, and the first detection material layer and the second detection material layer are made of SiON, an etching gas used in etching the second stack structure is C4F6，C4F8，SF6，NF3，O2，CH2F2，CH3F，CHF3，CH4，Ar，Kr，N2The flow rate of the etching gas is 10-250sccm, the source power is 50-6000W, the bias power is 100-.
Optionally, the material of the isolation layer in the first stacked structure and the second stacked structure is the same as the material of the intermediate isolation layer, and when the intermediate isolation layer is formed, the density of the formed intermediate isolation layer is greater than the density of the isolation layer in the first stacked structure and the second stacked structure, so that the etching rate of the intermediate isolation layer is reduced; during the etching, the method for keeping the etching rate of the isolation layer in the etching consistent with the etching rate of the first stacked structure, and the method for keeping the etching rate of the second stacked structure consistent with the etching rate of the first stacked structure comprises the following steps: and sequentially etching the second stacked structure, the intermediate isolation layer and the first stacked structure by using the same etching parameter, and forming a grid separation groove in the second stacked structure, the intermediate isolation layer and the first stacked structure.
Optionally, the material of the isolation layer in the first stacked structure and the second stacked structure is the same as the material of the intermediate isolation layer, and when the intermediate isolation layer is formed, impurity ions are doped in the intermediate isolation layer, so that the etching rate of the intermediate isolation layer is reduced; during the etching, the method for keeping the etching rate of the isolation layer in the etching consistent with the etching rate of the first stacked structure, and the method for keeping the etching rate of the second stacked structure consistent with the etching rate of the first stacked structure comprises the following steps: and sequentially etching the second stacked structure, the intermediate isolation layer and the first stacked structure by using the same etching parameter, and forming a grid separation groove in the second stacked structure, the intermediate isolation layer and the first stacked structure.
Optionally, the method further includes: and removing the sacrificial layers in the first stacked structure and the second stacked structure through the gate isolation grooves, and filling a conductive material into a cavity left after the sacrificial layers are removed to form the control gate of the memory.
Optionally, the method further includes: etching back to remove the control gate materials on the side wall and the bottom surface of the gate isolation groove, so that the control gates of different layers are mutually disconnected; forming an isolation side wall on the side wall of the grid isolation groove; forming a source doped region in the substrate at the bottom of the grid isolation groove; and filling a conductive material into the grid isolation groove to form an array common source of the memory.
The present invention also provides a 3D NAND memory, comprising:
a substrate having thereon a first stacked structure in which isolation layers and control gates are alternately stacked; an intermediate isolation layer on the first stacked structure; a second stack structure in which the control gates and the isolation layers on the intermediate isolation layer are alternately stacked;
an array common source that penetrates the first stack structure, the intermediate isolation layer, and the second stack structure in a direction perpendicular to the substrate;
the middle isolation layer comprises a first detection material layer positioned on the first stacked structure, an insulating layer positioned on the surface of the first detection material layer and a second detection material layer positioned on the insulating layer; or the intermediate isolation layer and the isolation layer in the first stacked structure and the second stacked structure are made of the same material, and the material density of the intermediate isolation layer is greater than that of the isolation layer in the first stacked structure and the second stacked structure; or the intermediate isolation layer and the isolation layer in the first stacked structure and the second stacked structure are made of the same material, and the intermediate isolation layer is doped with impurity ions.
Optionally, the materials of the first detection material layer and the second detection material layer are each independently SiON, Al2O3TiN or TaN.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the forming method of the 3D NAND memory, the intermediate isolation layer is formed between the first stacking structure and the second stacking structure, the intermediate isolation layer and the first stacking structure are etched in sequence, and when the grid isolation groove is formed in the second stacking structure, the intermediate isolation layer and the first stacking structure, the intermediate isolation layer is utilized, so that the etching rate of etching the intermediate isolation layer is consistent with the etching rate of etching the first stacking structure, and the etching rate of etching the second stacking structure is consistent with the etching rate of etching the first stacking structure, and therefore the side wall of the grid isolation groove, which is caused by the fact that the etching rate of etching the intermediate isolation layer is different from the etching rate of etching the first stacking structure and the etching rate of etching the second stacking structure, is prevented from generating bending defects.
Further, the intermediate isolation layer includes: a first detection material layer on the first stacked structure; the insulating layer is positioned on the surface of the first detection material layer; and a second detection material layer on the insulating layer. By forming a first detection material layer and a second detection material layer: when etching is carried out, whether the second stacked structure is etched or not and whether the insulating layer is etched or not are judged by detecting the spectrums of the byproducts of the first detection material layer and the second detection material layer, so that the etching rate can be adjusted in the etching process, when the etching of the second detection material layer is detected, the etching rate is changed to etch the insulating layer, so that the etching rate when the insulating layer is etched is kept consistent with the etching rate when the second stacked structure is etched, when the etching of the first detection material layer is detected, the etching rate is changed to etch the first stacked structure, so that the etching rate when the first stacked structure is etched is kept consistent with the etching rate when the second stacked structure is etched, and therefore, the etching rate in the whole grid spacer forming process can be kept consistent (the etching rate of the etching intermediate isolation layer is kept consistent with the etching rates when the first stacked structure and the second stacked structure are etched), therefore, the bending defect of the formed side wall of the grid isolation groove is simply prevented.
In addition, through forming first detection material layer and second detection material layer, in the etching process, through the change that detects the spectrum, can be accurate the judgement whether etch insulating layer and whether etch through, thereby adjustment etching parameter that can be quick, in order to change the etching rate to the insulating layer and to the etching rate of first stacked structure, in order to be quick, simple and convenient and accurate realization keep unanimous with the etching rate that etches first stacked structure to the etching rate of isolation layer in the sculpture, the etching rate that etches the second stacked structure keeps unanimous with the rate that etches the first stacked structure, prevent that the lateral wall of the grid spacer groove that finally forms from producing crooked defect.
According to the 3D NAND memory, the middle isolation layer is arranged between the first stacking structure and the second stacking structure, the middle isolation layer and the first stacking structure are etched in sequence, when the grid isolation groove is formed in the second stacking structure, the middle isolation layer and the first stacking structure, the middle isolation layer is utilized, the etching rate of etching the middle isolation layer is consistent with the etching rate of etching the first stacking structure, the etching rate of etching the second stacking structure is consistent with the etching rate of etching the first stacking structure, and therefore the side wall of the grid isolation groove is prevented from generating bending defects due to the fact that the etching rate of etching the middle isolation layer is different from the etching rate of etching the first stacking structure and the second stacking structure, and the array common source performance formed in the grid isolation groove is improved.
Drawings
FIG. 1 is a flow chart of a method for forming a 3D NAND memory according to an embodiment of the invention;
FIGS. 2-10 are cross-sectional views illustrating the formation of a 3D NAND memory according to one embodiment of the present invention;
FIGS. 11-13 are cross-sectional views illustrating a process of forming a 3D NAND memory according to another embodiment of the present invention.
Detailed Description
As background art, the conventional etching of a thick silicon oxide layer between a multi-layer stack structure and a stack structure to form a gate spacer exposed on the surface of the substrate has poor sidewall morphology.
Research shows that the poor side wall morphology of the conventional grid spacer groove is mainly reflected by that the side wall bends towards one side, and the position of the poor side wall morphology corresponds to the position of the thick silicon oxide layer. Further research finds that when a thick silicon oxide layer between a multilayer stack structure and a stack structure is etched, the same etching parameter is adopted in the same etching cavity for etching, so that the etching rate when the stack structure is etched in the whole etching process is different from the etching rate when the thick silicon oxide layer is etched, and the etching rate when the stack structure is etched is specifically smaller than the etching rate when the thick silicon oxide layer is etched, so that the side wall of a grid spacer at the position corresponding to the thick oxide layer can be bent, and the performance of an array common source formed in the grid spacer is influenced.
The invention provides a 3D NAND memory and a forming method thereof, wherein the forming method of the 3D NAND memory comprises the steps of forming an intermediate isolation layer between a first stacked structure and a second stacked structure, etching the second stacked structure, the intermediate isolation layer and the first stacked structure in sequence, and using the intermediate isolation layer to enable the etching rate of the intermediate isolation layer to be consistent with the etching rate of etching the first stacked structure and enable the etching rate of the second stacked structure to be consistent with the etching rate of etching the first stacked structure when gate isolation grooves are formed in the second stacked structure, the intermediate isolation layer and the first stacked structure, so that the side wall of each gate isolation groove can be prevented from generating bending defects caused by the fact that the etching rate of the intermediate isolation layer is different from the etching rate of etching the first stacked structure and the second stacked structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Fig. 1 is a flow chart illustrating a method for forming gate spacers of a 3D NAND memory according to an embodiment of the invention.
Referring to fig. 1, the method for forming the gate spacer of the 3D NAND memory includes the steps of:
s101, providing a substrate, wherein a first stacked structure formed by alternately stacking an isolation layer and a sacrificial layer, a middle isolation layer positioned on the first stacked structure, and a second stacked structure formed by alternately stacking an isolation layer and a sacrificial layer positioned on the middle isolation layer are formed on the substrate;
s102, etching the second stacked structure, the intermediate isolation layer and the first stacked structure in sequence to form a grid separation groove in the second stacked structure, the intermediate isolation layer and the first stacked structure, and when etching, using the intermediate isolation layer to enable the etching rate of etching the intermediate isolation layer to be consistent with the etching rate of etching the first stacked structure, and enable the etching rate of etching the second stacked structure to be consistent with the etching rate of etching the first stacked structure.
The foregoing formation process is described in detail below with reference to the accompanying drawings.
FIGS. 2-10 are cross-sectional views illustrating a 3D NAND memory according to an embodiment of the present invention.
Referring to fig. 2, a substrate 100 is provided, and a first stacked structure 101 in which isolation layers 102 and sacrificial layers 103 are alternately stacked is formed on the substrate 100.
The material of the substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the substrate 100 is single crystal silicon (Si).
The first stacked structure 101 includes alternately stacked isolation layers 102 and sacrificial layers 103, and the sacrificial layers 103 are subsequently removed to form a cavity, and then a control gate is formed at a position where the sacrificial layers 103 are removed. The isolation layer 102 serves as electrical isolation between different layers of the control gate, and between the control gate and other devices (conductive contacts, trench holes, etc.).
The alternating lamination of the isolation layer 102 and the sacrificial layer 103 means that: after forming an isolation layer 102, a sacrificial layer 103 is formed on the surface of the isolation layer 102, and then the steps of forming the isolation layer 102 and the sacrificial layer 103 on the isolation layer 102 are sequentially performed in a loop. In this embodiment, the bottom layer of the first stacked structure 101 is an isolation layer 102, and the top layer is a sacrificial layer 103.
The number of layers of the first stacked structure 101 (the number of layers of the double-layer stacked structure including the isolation layer 102 and the sacrificial layer 103 in the first stacked structure 101) is determined according to the number of memory cells required to be formed in the vertical direction, the number of layers of the first stacked structure 101 may be 8, 32, 64, or the like, and the greater the number of layers of the first stacked structure 101, the greater the integration level can be. In this embodiment, only the number of layers in the stacked structure is 3 as an example.
The sacrificial layer 103 and the isolation layer 102 are made of different materials, and the sacrificial layer 103 has a high etching selectivity relative to the isolation layer 102, so that the etching amount of the isolation layer 102 is small or negligible when the sacrificial layer 103 is removed subsequently, and the integrity of the isolation layer 102 is ensured.
The isolation layer 102 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and the sacrificial layer 103 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, amorphous silicon, amorphous carbon, and polysilicon. In this embodiment, the isolation layer 102 is made of silicon oxide, the sacrificial layer 103 is made of silicon nitride, and the isolation layer 102 and the sacrificial layer 103 are formed by a chemical vapor deposition process.
In an embodiment, after forming the first stacked structure 101, the first stacked structure 101 is etched; forming a trench via in the first stacked structure 101; a memory structure is formed in the trench via.
The memory structure comprises at least a charge-trapping layer and a channel layer, wherein in one embodiment, the charge-trapping layer is an ONO layer, i.e., a stack of silicon oxide-silicon nitride-silicon oxide, and the channel layer is a polysilicon layer. In one embodiment, the memory structure may be formed by sequentially depositing an ONO layer, a polysilicon layer, and a silicon oxide layer in the trench via.
Referring to fig. 3, an intermediate isolation layer 104 is formed on the first stacked structure 101, and the intermediate isolation layer is used for sequentially etching the second stacked structure (specifically, refer to the subsequent description), the intermediate isolation layer 104, and the first stacked structure 101 in the following, so that when gate isolation grooves are formed in the second stacked structure, the intermediate isolation layer 104, and the first stacked structure 101, an etching rate for etching the intermediate isolation layer 104 is kept consistent with an etching rate for etching the first stacked structure 101, and an etching rate for etching the second stacked structure is kept consistent with an etching rate for etching the first stacked structure 101.
The intermediate isolation layer 104 is used for isolation between stacked structures of different layers and provides a flat surface for subsequent formation of a second stacked structure.
In this embodiment, the intermediate isolation layer 104 includes: a first detection material layer 105 on the first stacked structure 101; an insulating layer 106 on the surface of the first detection material layer 105; a second detection material layer 107 on the insulating layer 106.
The role of forming the first detection material layer 105 and the second detection material layer 107 is to: during etching, whether the second stacked structure is etched (the second pair of structures is subsequently formed on the intermediate isolation layer 104) and whether the insulating layer is etched are judged by detecting spectra of byproducts of the first detection material layer 105 and the second detection material layer 107, so that the etching rate can be adjusted during the etching process, when the second detection material layer 107 is detected to be etched, the etching rate is changed to etch the insulating layer, so that the etching rate during etching the insulating layer is consistent with the etching rate during etching the second stacked structure, and when the first detection material layer 105 is detected to be etched, the etching rate is changed to etch the first stacked structure 101, so that the etching rate during etching the first stacked structure 101 is consistent with the etching rate during etching the second stacked structure, so that the etching rate during forming the whole gate spacer groove can be consistent (the etching rate during etching the intermediate isolation layer is consistent with the etching rate during etching the first stacked structure and the etching rate during etching the second stacked structure are consistent with each other Uniform), thereby easily preventing the formed side wall of the gate spacer from generating bending defects.
The materials of the first detection material layer 105 and the second detection material layer 107 are different from the materials of the first stacked structure 101, the second stacked structure and the insulating layer 106, so that byproducts generated by etching the first detection material layer 105 and the second detection material layer 107 are different from byproducts generated by etching the first stacked structure 101, the second stacked structure and the insulating layer, therefore, when detection is performed, the spectral intensities generated by different byproducts are different, and whether the first detection material layer and the second detection material layer are etched is judged according to the change of the spectral intensities in the etching process.
The first detection material layer 105 and the second detection material layer 107 are made of SiON and Al2O3TiN or TaN, in this embodiment, the materials of the first detection material layer 105 and the second detection material layer 107 are the same, the materials of the first detection material layer 105 and the second detection material layer 107 are SiON, the material of the insulating layer 106 is the same as that of the isolation layer 102, and the material of the insulating layer 106 is silicon oxide.
Referring to fig. 4, a second stack structure 108 in which spacers 110 and sacrificial layers 109 are alternately stacked is formed on the intermediate spacers 104.
The second stacked structure 108 is formed on the surface of the second detection material layer 107.
The second stack structure 108 comprises alternately stacked isolation layers 110 and sacrificial layers 109, said sacrificial layers 109 being subsequently removed to form a cavity, and then a control gate is formed at the location where the sacrificial layers 109 are removed. The isolation layer 110 serves as electrical isolation between different layers of the control gate, and between the control gate and other devices (conductive contacts, trench holes, etc.).
In this embodiment, the bottom layer of the second stacked structure 108 is a sacrificial layer 109, and the top layer is an isolation layer 110. The alternating lamination of the isolation layer 110 and the sacrificial layer 109 means that: after forming a sacrificial layer 109, an isolation layer 110 is formed on the surface of the sacrificial layer 109, and then the steps of forming the sacrificial layer 109 and the isolation layer 110 on the isolation layer 110 are sequentially performed cyclically.
The number of layers of the second stacked structure 108 (the number of layers of the dual-layer stacked structure of the isolation layer 110 and the sacrificial layer 109 in the second stacked structure 108) is determined according to the number of memory cells required to be formed in the vertical direction, the number of layers of the second stacked structure 108 may be 8, 32, 64, and the like, and the greater the number of layers of the second stacked structure 108, the better the integration level can be. In this embodiment, only the number of layers in the stacked structure is 3 as an example.
The sacrificial layer 109 and the isolation layer 110 are made of different materials, and the sacrificial layer 109 has a high etching selectivity relative to the isolation layer 110, so that the etching amount of the isolation layer 110 is small or negligible when the sacrificial layer 109 is removed later, and the integrity of the isolation layer 110 is ensured.
The isolation layer 110 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and the sacrificial layer 109 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, amorphous silicon, amorphous carbon, and polysilicon. In this embodiment, the material of the first stacked structure 101 is the same as that of the second stacked structure, the material of the isolation layer 110 is silicon oxide, the material of the sacrificial layer 109 is silicon nitride, and the isolation layer 110 and the sacrificial layer 109 are formed by a chemical vapor deposition process.
In an embodiment, after forming the second stack structure 108, the second stack structure 108 is etched; forming a trench via in the second stack structure 108; a memory structure is formed in the trench via.
The memory structure comprises at least a charge-trapping layer and a channel layer, wherein in one embodiment, the charge-trapping layer is an ONO layer, i.e., a stack of silicon oxide-silicon nitride-silicon oxide, and the channel layer is a polysilicon layer. In one embodiment, the memory structure may be formed by sequentially depositing an ONO layer, a polysilicon layer, and a silicon oxide layer in the trench via.
Referring to fig. 5-7, the second stacked structure 108, the intermediate isolation layer 104, and the first stacked structure 101 are sequentially etched, the gate spacer 112 is formed in the second stacked structure 108, the intermediate isolation layer 104, and the first stacked structure 101, and when etching is performed, the etching rate of etching the intermediate isolation layer 104 is consistent with the etching rate of etching the first stacked structure 101, and the etching rate of etching the second stacked structure 108 is consistent with the etching rate of etching the first stacked structure 101.
The processes of sequentially etching the second stacked structure 108, the middle isolation layer 104 and the first stacked structure 101 are all performed in the same etching chamber
First, referring to fig. 5, the second stack structure 108 is etched, and an etched groove 111 is formed in the second stack structure 108.
The second stacked structure 108 is etched by anisotropic dry etching, which may be a plasma etching process. In one embodiment, when the sacrificial layer 109 is made of silicon nitride and the isolation layer 110 is made of silicon oxide, etching is performedThe etching gas adopted during etching the second stack structure 108 is C4F6，C4F8，SF6，NF3，O2，CH2F2，CH3F，CHF3，CH4，Ar，Kr，N2The flow rate of the etching gas is 10-250sccm, the source power is 50-6000W, the bias power is 100-.
During the etching of the second stack structure 108, a spectrum generated by a byproduct generated from the second stack structure 108 is detected. The specific spectrum detection means can adopt the spectrum detection means in the existing etching process.
After the second stacked structure 108 is etched through, the intermediate isolation layer 104 is etched, when the intermediate isolation layer is etched, the second detection material layer 107 is etched first, and when the second detection material layer 107 is etched, the spectrum generated by the byproduct is still detected, because the materials of the second detection material layer 107 and the second stacked structure 108 are different, the spectrum generated by the byproduct when the second detection material layer 107 is etched is different from the spectrum generated by the byproduct when the second stacked structure 108 is etched, that is, whether the second detection material layer 107 is etched is judged by detecting the change of the spectrum of the byproduct generated when the second stacked structure 108 and the second detection material layer 107 are etched. In one embodiment, the change in the spectrum is a change in the intensity or peak of the spectrum.
Referring to fig. 5 and 6 in combination, when the etching of the second detection material layer 107 is detected, the etching rate is changed to etch the insulating layer 106, so that the etching rate when the insulating layer 106 is etched is consistent with the etching rate when the second stack structure 108 is etched.
It should be noted that the etching rate for etching the second stacked structure 108, the etching rate for etching the insulating layer 106, and the etching rate for subsequently etching the first stacked structure 101 in this embodiment and the subsequent embodiments all refer to an average etching rate.
Specifically, when the etching of the second detection material layer 107 is detected, the changing of the etching rate includes increasing or decreasing the etching rate to etch the insulating layer 106, so that the etching rate when the insulating layer 106 is etched is consistent with the etching rate when the second stack structure 108 is etched.
During the etching process, the etching rate is changed by changing one or more of the type and/or flow of the gas used during etching, the magnitude of the bias power and the magnitude of the chamber pressure.
Specifically, the etch rate may be increased or decreased by changing the type of gas, increased or decreased by increasing or decreasing the flow of gas, increased or decreased by increasing or decreasing the bias power, and increased or decreased by decreasing or increasing the chamber pressure.
In this embodiment, since the material of the insulating layer 106 is the same as that of the isolation layer 110 or 102, and the material of the insulating layer 106 is silicon oxide, when the second detection material layer 107 is detected and etched, the etching rate is reduced to etch the insulating layer 106, so that the etching rate when the insulating layer 106 is etched is consistent with the etching rate when the second stack structure 108 is etched. Specifically, in this embodiment, the etching parameters used when etching the insulating layer 106 are obtained by reducing the gas flow rate when etching the second stack structure 108, reducing the bias power when etching the second stack structure 108, and increasing one or a combination of several of the chamber pressures when etching the second stack structure 108, on the basis of the etching parameters when etching the second stack structure 108, so as to reduce the etching rate to etch the insulating layer 106, so that the etching rate when etching the insulating layer 106 is consistent with the etching rate when etching the second stack structure 108.
In the process of etching the insulating layer 106, a spectrum generated by a byproduct when the insulating layer 106 is etched is detected, after the insulating layer 106 is etched through, the first detection material layer 105 is etched, and a spectrum generated by a byproduct of the first detection material layer 105 is detected when the first detection material layer 105 is etched, because the insulating layer 106 and the first detection material layer 105 are made of different materials, the spectrum generated by a byproduct when the insulating layer 106 is etched is different from the spectrum generated by a byproduct when the first detection material layer 105 is etched, that is, whether the second detection material layer 107 is etched is determined by detecting a change in the spectrum of a byproduct generated when the second stacked structure 108 and the second detection material layer 107 are etched, that is, whether the first detection material layer 105 is etched is determined by detecting a change in the spectrum of a byproduct generated when the insulating layer 106 and the first detection material layer 105 are etched.
Referring to fig. 6 and 7 in combination, when the etching to the first detection material layer 105 is detected, the etching rate is changed to etch the first stacked structure 101, so that the etching rate when the first stacked structure 101 is etched is consistent with the etching rate when the second stacked structure 108 is etched.
For a specific way of changing the etching rate, please refer to the above description related to the etching of the insulating layer with the changed etching rate, which is not repeated herein.
In this embodiment, when the etching of the first detection material layer 105 is detected, the etching rate is increased to etch the first stacked structure 101, so that the etching rate when the first stacked structure 101 is etched is kept consistent with the etching rate when the second stacked structure 108 is etched. In this embodiment, the isolation layer 102 is made of silicon oxide, the sacrificial layer 103 is made of silicon nitride, and an etching parameter when the first stacked structure 101 is etched is consistent with or slightly varies from an etching parameter when the second stacked structure 108 is etched, that is, when the first stacked structure 101 is etched, the etching parameter is changed to be consistent with or slightly varies from an etching parameter when the second stacked structure 108 is etched.
Therefore, in this embodiment, by forming the first detection material layer 105 and the second detection material layer 107, in the etching process, through detecting the change of the spectrum, whether the insulating layer 106 is etched or not and whether the insulating layer 106 is etched through or not can be accurately determined, so that the etching parameters can be quickly adjusted to change the etching rate of the insulating layer 106 and the etching rate of the first stacked structure 101, so that the etching rate of the isolation layer 104 in the etching process is kept consistent with the etching rate of the first stacked structure 101, the etching rate of the second stacked structure 108 is kept consistent with the etching rate of the first stacked structure 101, and the side wall of the finally formed gate spacer 112 is prevented from generating a bending defect.
Referring to fig. 8, after forming the gate spacer 112, the sacrificial layer 103 and the sacrificial layer 109 are removed (refer to fig. 7); control gate 114 and control gate 115 are formed at positions where sacrificial layer 103 and sacrificial layer 109 are removed.
Wet etching may be used to remove the sacrificial layer 103 and the sacrificial layer 109.
The material of control gate 114 and control gate 115 may be metal or other conductive material (e.g., polysilicon, etc.). In this embodiment, the conductive material is a metal, and the metal is one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.
In an embodiment, a high-K dielectric layer is further formed between the control gate 114 and the control gate 115 and the corresponding isolation layer 102 and 109, and the material of the high-K dielectric layer is HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO.
After forming control gate 114 and control gate 115, the control gate material on the sidewalls and bottom surface of gate spacer 112 is removed by etch back.
Referring to fig. 9 and 10, spacers 117 are formed on sidewalls of the gate spacers 112; the gate spacer 112 is filled with a conductive material to form the array common source 118.
The conductive material is polysilicon or metal.
In one embodiment, after forming the spacers 117 and before forming the array common source 118, the substrate at the bottom of the gate spacer 112 is doped to form a source dopant region therein.
FIGS. 11-13 are cross-sectional views illustrating a process of forming gate spacers of a 3D NAND memory according to another embodiment of the present invention. The present embodiment differs from the foregoing embodiments in the specific structure of the isolation layer and the manner in which the etching rate for etching the intermediate isolation layer is achieved to be consistent with the etching rate for etching the first stacked structure and the second stacked structure. It should be noted that, for the description or the limitation of the same or similar structure in this embodiment as in the foregoing embodiment, please refer to the description or the limitation of the corresponding part in the foregoing embodiment, which is not repeated in this embodiment.
In an embodiment, referring to fig. 11 and 12 in combination, when performing etching, a manner of keeping an etching rate of the isolation layer in etching consistent with an etching rate of the first stacked structure and the second stacked structure includes: the material of the isolation layer (102/110) in the first stacked structure 101 and the second stacked structure 108 is the same as the material of the intermediate isolation layer 104, when the intermediate isolation layer 104 is formed, the density of the formed intermediate isolation layer 104 is greater than the density of the isolation layer (102/110) in the first stacked structure 101 and the second stacked structure 108, so that the etching rate of the intermediate isolation layer 104 is reduced, then the second stacked structure 108, the intermediate isolation layer 104 and the first stacked structure 101 are etched in sequence by using the same etching parameters, and the gate isolation groove 112 is formed in the second stacked structure 108, the intermediate isolation layer 104 and the first stacked structure 101.
In an embodiment, the materials of the isolation layer (102/110) and the middle isolation layer 104 in the first and second stacked structures 101 and 108 are silicon oxide, and the density of the middle isolation layer 104 is greater than the density of the isolation layer (102/110) in the first and second stacked structures 101 and 108 by changing the process parameters of the silicon oxide.
In this embodiment, after the density of the formed intermediate isolation layer 104 is increased, the etching rate of the intermediate isolation layer 104 with the increased density is reduced compared to the etching rate of the isolation layer material without the increased density, so that when the same etching parameter is used for etching, the etching rate of the intermediate isolation layer 104 can be kept consistent with the etching rates of the first stacked structure 101 and the second stacked structure 108, and in an embodiment, the density of the intermediate isolation layer 104 is such that the ratio of the densities of the isolation layers (102/110) in the first stacked structure 101 and the second stacked structure 108 is (1.5-2.0): 1.
In another embodiment, referring to fig. 11 and 12 in combination, when performing etching, a manner of keeping an etching rate of the isolation layer in etching consistent with an etching rate of the first stacked structure and the second stacked structure includes: the material of the isolation layer (102/110) in the first stacked structure 101 and the second stacked structure 108 is the same as the material of the intermediate isolation layer 104, when the intermediate isolation layer 104 is formed, impurity ions are doped in the intermediate isolation layer 104 to reduce the etching rate of the intermediate isolation layer 104, then the second stacked structure 108, the intermediate isolation layer 104 and the first stacked structure 101 are sequentially etched by using the same etching parameters, and the gate isolation groove 112 is formed in the second stacked structure 108, the intermediate isolation layer 104 and the first stacked structure 101.
In this embodiment, the intermediate isolation layer 104 doped with impurity ions has a lower etching rate than an isolation layer material not doped with impurity ions, so that the etching rate of the intermediate isolation layer 104 can be kept consistent with the etching rates of the first stacked structure 101 and the second stacked structure 108 when the same etching parameter is used for etching.
In one embodiment, the doped impurity ions are boron ions.
Referring to fig. 13, after forming the gate spacer 112, the sacrificial layer 103 and the sacrificial layer 109 are removed (refer to fig. 12); correspondingly forming a control gate 114 and a control gate 115 at the positions where the sacrificial layer 103 and the sacrificial layer 109 are removed; after forming the control gate 114 and the control gate 115, etching back to remove the control gate material on the sidewall and bottom surface of the gate spacer 112; forming sidewalls 117 on sidewalls of the gate spacers 112 (see fig. 12); the gate spacer 112 is filled with a conductive material to form the array common source 118.
In one embodiment, after forming the spacers 117 and before forming the array common source 118, the substrate at the bottom of the gate spacer 112 is doped to form a source dopant region therein.
The present invention also provides a 3D NAND memory, please refer to fig. 10 or fig. 13, including:
a substrate 100, wherein the substrate 100 is provided with a first stacked structure 101 formed by alternately stacking isolation layers 102 and control gates 114; an intermediate isolation layer 104 on the first stacked structure 101; a second stack structure 108 in which isolation layers 110 and control gates 115 are alternately stacked on the intermediate isolation layer 104;
an array common source 118 penetrating the first stack structure 101, the intermediate isolation layer 104, and the second stack structure 108 in a direction perpendicular to the substrate 100;
the intermediate isolation layer 104 includes (refer to fig. 10) a first detection material layer 105 on the first stacked structure 101, an insulating layer 106 on a surface of the first detection material layer 105, and a second detection material layer 107 on the insulating layer 106; or (refer to fig. 13) the intermediate isolation layer 104 and the isolation layer (102/110) in the first stacked structure 101 and the second stacked structure 108 are composed of the same material, and the material density of the intermediate isolation layer 104 is greater than the material density of the isolation layer (102/110) in the first stacked structure 101 and the second stacked structure 108; alternatively (refer to fig. 13), the intermediate isolation layer 104 and the isolation layer (102/110) in the first stacked structure 101 and the second stacked structure 108 are made of the same material, and the intermediate isolation layer 104 is doped with impurity ions.
In one embodiment, the materials of the first and second detection material layers 105 and 107 are each independently SiON, Al2O3TiN or TaN.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (12)
1. A method for forming a 3D NAND memory, comprising:
providing a substrate, wherein a first stacked structure in which isolation layers and sacrificial layers are alternately stacked, an intermediate isolation layer positioned on the first stacked structure, and a second stacked structure in which isolation layers and sacrificial layers are alternately stacked are formed on the substrate, wherein the intermediate isolation layer comprises a first detection material layer positioned on the first stacked structure, an insulation layer positioned on the surface of the first detection material layer, and a second detection material layer positioned on the insulation layer; or the intermediate isolation layer and the isolation layer in the first stacked structure and the second stacked structure are made of the same material, and the material density of the intermediate isolation layer is greater than that of the isolation layer in the first stacked structure and the second stacked structure; or the intermediate isolation layer and the isolation layer in the first stacked structure and the second stacked structure are made of the same material, and the intermediate isolation layer is doped with impurity ions;
and etching the second stacked structure, the intermediate isolation layer and the first stacked structure in sequence to form a grid spacer groove in the second stacked structure, the intermediate isolation layer and the first stacked structure, and when etching, utilizing the intermediate isolation layer to ensure that the etching rate of etching the intermediate isolation layer is consistent with the etching rate of etching the first stacked structure, and the etching rate of etching the second stacked structure is consistent with the etching rate of etching the first stacked structure.
2. The method of forming a 3D NAND memory of claim 1, wherein when the middle isolation layer comprises: when the first detection material layer is positioned on the first stacking structure, the insulating layer is positioned on the surface of the first detection material layer, and the second detection material layer is positioned on the insulating layer, the second stacking structure is positioned on the second detection material layer; during the etching, the method for keeping the etching rate of the isolation layer in the etching consistent with the etching rate of the first stacked structure, and the method for keeping the etching rate of the second stacked structure consistent with the etching rate of the first stacked structure comprises the following steps: and when the first detection material layer is detected to be etched, changing the etching rate to etch the insulating layer so that the etching rate when the insulating layer is etched is consistent with the etching rate when the second stacking structure is etched, and when the first detection material layer is detected to be etched, changing the etching rate to etch the first stacking structure so that the etching rate when the first stacking structure is etched is consistent with the etching rate when the second stacking structure is etched.
3. The method of forming a 3D NAND memory of claim 2 wherein the materials of the first and second sensing material layers are each independentlyGround is SiON, Al2O3TiN or TaN.
4. The method of claim 3, wherein whether the second detection material layer is etched is determined by detecting a change in a spectrum of a byproduct generated when the second stack structure and the second detection material layer are etched, and whether the first detection material layer is etched is determined by detecting a change in a spectrum of a byproduct generated when the insulating layer and the first detection material layer are etched.
5. The method of claim 4, wherein when the second detection material layer is detected to be etched, the etching rate is decreased to etch the insulating layer such that the etching rate when the insulating layer is etched is consistent with the etching rate when the second stacked structure is etched, and when the first detection material layer is detected to be etched, the etching rate is increased to etch the first stacked structure such that the etching rate when the first stacked structure is etched is consistent with the etching rate when the second stacked structure is etched.
6. The method of claim 5, wherein when the sacrificial layer is made of silicon nitride, the insulating layer and the isolation layer are made of silicon oxide, and the first and second sensing material layers are made of SiON, an etching gas used in etching the second stack structure is C4F6，C4F8，SF6，NF3，O2，CH2F2，CH3F，CHF3，CH4，Ar，Kr，N2The flow rate of the etching gas is 10-250sccm, the source power is 50-6000W, the bias power is 100-.
7. The method of forming a 3D NAND memory as claimed in claim 1, wherein when the intermediate isolation layer is formed when a material of the isolation layer is the same as a material of the intermediate isolation layer in the first and second stack structures, the intermediate isolation layer is formed so that a density of the intermediate isolation layer is greater than a density of the isolation layer in the first and second stack structures, so that an etching rate of the intermediate isolation layer is reduced; during the etching, the method for keeping the etching rate of the isolation layer in the etching consistent with the etching rate of the first stacked structure, and the method for keeping the etching rate of the second stacked structure consistent with the etching rate of the first stacked structure comprises the following steps: and sequentially etching the second stacked structure, the intermediate isolation layer and the first stacked structure by using the same etching parameter, and forming a grid separation groove in the second stacked structure, the intermediate isolation layer and the first stacked structure.
8. The method of forming a 3D NAND memory as claimed in claim 1, wherein when the intermediate isolation layer is formed when a material of the isolation layer is the same as a material of the intermediate isolation layer in the first and second stacked structures, impurity ions are doped in the intermediate isolation layer so that an etch rate of the intermediate isolation layer is reduced; during the etching, the method for keeping the etching rate of the isolation layer in the etching consistent with the etching rate of the first stacked structure, and the method for keeping the etching rate of the second stacked structure consistent with the etching rate of the first stacked structure comprises the following steps: and sequentially etching the second stacked structure, the intermediate isolation layer and the first stacked structure by using the same etching parameter, and forming a grid separation groove in the second stacked structure, the intermediate isolation layer and the first stacked structure.
9. The method of forming a 3D NAND memory as claimed in any one of claims 1 to 8, further comprising: and removing the sacrificial layers in the first stacked structure and the second stacked structure through the gate isolation grooves, and filling a conductive material into a cavity left after the sacrificial layers are removed to form the control gate of the memory.
10. The method of forming a 3D NAND memory of claim 9, further comprising: etching back to remove the control gate materials on the side wall and the bottom surface of the gate isolation groove, so that the control gates of different layers are mutually disconnected; forming an isolation side wall on the side wall of the grid isolation groove; forming a source doped region in the substrate at the bottom of the grid isolation groove; and filling a conductive material into the grid isolation groove to form an array common source of the memory.
11. A3D NAND memory, comprising:
a substrate having thereon a first stacked structure in which isolation layers and control gates are alternately stacked; an intermediate isolation layer on the first stacked structure; a second stack structure in which the control gates and the isolation layers on the intermediate isolation layer are alternately stacked;
an array common source that penetrates the first stack structure, the intermediate isolation layer, and the second stack structure in a direction perpendicular to the substrate;
the middle isolation layer comprises a first detection material layer positioned on the first stacked structure, an insulating layer positioned on the surface of the first detection material layer and a second detection material layer positioned on the insulating layer; or the intermediate isolation layer and the isolation layer in the first stacked structure and the second stacked structure are made of the same material, and the material density of the intermediate isolation layer is greater than that of the isolation layer in the first stacked structure and the second stacked structure; or the intermediate isolation layer and the isolation layer in the first stacked structure and the second stacked structure are made of the same material, and the intermediate isolation layer is doped with impurity ions.
12. The 3D NAND memory of claim 11 wherein the material of the first and second sensing material layers are each independently SiON, Al2O3TiN or TaN.
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