CN112802854B - 3D NAND memory and forming method thereof - Google Patents
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
A3D NAND memory and a forming method thereof, wherein the 3D NAND memory comprises a semiconductor substrate, a control gate and an isolation layer are alternately stacked on the semiconductor substrate, and the end part of the stack structure is provided with a step structure; a dielectric layer covering the step structure and positioned on the semiconductor substrate; a dummy through hole penetrating through the stacked structure, wherein a dummy through hole material layer is filled in the dummy through hole, and the hardness of the dummy through hole material layer is greater than that of the dielectric layer; a gate spacer penetrating the stacked structure; and the conductive semiconductor layer is positioned between the metal layer and the semiconductor substrate. The memory can prevent the metal layer from remaining.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a 3D NAND memory and a forming method thereof.
Background
NAND flash memory is a better storage device than hard disk drives, and is widely used in electronic products as people seek nonvolatile storage products with low power consumption, light weight and good performance. At present, NAND flash memories with a planar structure are approaching the limit of practical expansion, and in order to further improve the storage capacity and reduce the storage cost per bit, NAND memories with a 3D structure are proposed.
At present, the main components of the 3D NAND memory may include array memory cells and peripheral circuits, and the access operation to the data in each memory cell is realized through the control of the peripheral circuits, so that the conductivity of each part is an important factor in the manufacturing process of the 3D NAND memory.
Among them, Array Common Source (ACS) is an important structure with high conductivity requirement, and there are various schemes for forming the Array Common Source at present, where the ACS is usually formed by filling tungsten (W), and although tungsten has good conductivity, during the formation process, large stress is generated, which may cause various process problems, such as wafer warpage and sliding, lithography deformation, stack dislocation, and the like, and further cause performance degradation of the device. For this reason, in the second scheme, polysilicon is used instead of tungsten, but polysilicon has a conductivity much lower than tungsten, and even if doped polysilicon is used, its conductivity is much lower than tungsten, and the manufacturing cost is relatively high.
The third scheme considers the problems of stress and resistance, the array common source is formed by forming a polysilicon layer and a metal layer on the polysilicon layer, but the metal layer is easy to remain when the array common source is formed.
Disclosure of Invention
The invention aims to solve the technical problem of how to prevent the metal layer from remaining in the process of forming the 3D NAND memory.
The invention provides a method for forming a 3D NAND memory, which comprises the following steps:
providing a semiconductor substrate, wherein a stacked structure formed by alternately stacking a sacrificial layer and an isolation layer is formed on the semiconductor substrate, and the end part of the stacked structure is provided with a step structure;
forming a dielectric layer covering the step structure on the semiconductor substrate;
forming a plurality of dummy through holes in the dielectric layer and the step structure, wherein a dummy through hole material layer is filled in the dummy through holes, and the hardness of the dummy through hole material layer is greater than that of the dielectric layer;
after the pseudo through hole material layer is formed, forming a plurality of grid isolation grooves in the dielectric layer and the step structure; forming a conductive semiconductor layer in the grid separation groove, wherein the surface of the conductive semiconductor layer is lower than that of the dielectric layer;
and forming a metal layer on the conductive semiconductor layer, wherein the metal layer is filled in the grid isolation groove.
Optionally, the high-temperature deformation of the dummy through-hole material layer is smaller than the high-temperature deformation of the dielectric layer.
Optionally, the thermal stress of the dummy via material layer is smaller than the thermal stress of the dielectric layer.
Optionally, the dielectric layer is made of silicon oxide, and the dummy through hole material layer is made of polysilicon.
Optionally, the forming process of the metal layer is as follows: forming a metal material layer on the stacked structure, in the grid separation groove and on the dielectric layer; and flattening and removing the metal material layer on the stacked structure and the dielectric layer, and forming a metal layer on the conductive semiconductor layer, wherein the metal layer is filled in the grid isolation groove.
Optionally, the forming process of the conductive semiconductor layer is as follows: forming a semiconductor material layer on the stacked structure and the dielectric layer and in the grid separation groove; and removing the semiconductor material layer on the stacked structure and the dielectric layer by adopting a chemical mechanical polishing process in a planarization manner, and removing the planarized semiconductor material layer with a part of thickness by back etching, so as to form a conductive semiconductor layer in the grid separation groove, wherein the surface of the conductive semiconductor layer is lower than that of the dielectric layer.
Optionally, before the dummy via material layer of the dummy via, a barrier layer is formed on the bottom and sidewall surfaces of the dummy via.
Optionally, the method further includes: forming a first hard mask layer on the stacked structure and the dielectric layer, wherein the first hard mask layer is provided with a first opening exposing the surface of the dielectric layer above the step structure; etching the dielectric layer and the step structure along the first opening by taking the first mask layer as a mask, and forming a pseudo through hole in the dielectric layer and the step structure; after the planarization.
Optionally, the method further includes: after filling a dummy through hole material layer in the dummy through hole, forming a second hard mask layer on the dummy through hole material layer and the surface of the first hard mask layer, wherein the second hard mask layer is provided with a second opening exposing the surface of the first hard mask layer on the surface of the step structure; and etching the first hard mask layer, the dielectric layer and the step structure along the second opening by taking the second hard mask layer as a mask, and forming a grid isolation groove in the dielectric layer and the step structure.
Optionally, a channel via is formed in the stacked structure on one side of the step structure, and the channel via has a storage structure therein.
Optionally, the memory structure includes a charge storage layer on a sidewall surface of the channel via and a channel layer on a sidewall surface of the charge storage layer.
Optionally, the charge storage layer includes a blocking oxide layer on a sidewall surface of the trench hole, a charge trapping layer on a sidewall surface of the blocking oxide layer, and a tunneling oxide layer on a sidewall surface of the charge trapping layer.
Optionally, while forming a plurality of dummy through holes in the dielectric layer and the step structure, a plurality of channel holes are also formed in the stacked structure on one side of the step structure; and forming a plurality of grid isolation grooves in the dielectric layer and the step structure, and simultaneously forming a plurality of grid isolation grooves in the stacking structure at one side of the step structure.
Optionally, the dummy through hole material layer is filled in the dummy through hole in the dielectric layer and the step structure, and the dummy through hole material layer is also filled in the channel hole in the stacked structure on one side of the step structure; and when the conductive semiconductor layer and the metal layer positioned on the conductive semiconductor layer are formed in the dielectric layer and the grid separating groove in the step structure, the conductive semiconductor layer and the metal layer positioned on the conductive semiconductor layer are also formed in the grid separating groove in the stacked structure on one side of the step structure.
Optionally, the method further includes: the sacrificial layer is replaced with a control gate.
The present invention also provides a 3D NAND memory, comprising:
the semiconductor device comprises a semiconductor substrate, wherein a stacked structure formed by alternately stacking control gates and isolation layers is arranged on the semiconductor substrate, and a step structure is arranged at the end part of the stacked structure;
a dielectric layer covering the step structure and positioned on the semiconductor substrate;
the dummy through holes are filled with dummy through hole material layers of the dummy through holes, and the hardness of each dummy through hole material layer is greater than that of the dielectric layer;
a plurality of grid isolation grooves positioned in the dielectric layer and the step structure;
the conductive semiconductor layer is positioned in the grid separation groove, and the surface of the conductive semiconductor layer is lower than that of the dielectric layer;
and the metal layer is positioned on the conductive semiconductor layer and is filled in the grid isolation groove.
Optionally, the high-temperature deformation of the dummy through-hole material layer is smaller than the high-temperature deformation of the dielectric layer.
Optionally, the thermal stress of the dummy via material layer is smaller than the thermal stress of the dielectric layer.
Optionally, the dielectric layer is made of silicon oxide, and the dummy through hole material layer is made of polysilicon.
Optionally, the bottom and sidewall surfaces of the dummy via further have a barrier layer.
Optionally, the method further includes: and the dummy through hole part is positioned in the first hard mask layer, and the dummy through hole material layer is filled in the dummy through hole.
Optionally, the method further includes: and the grid isolation groove is partially positioned in the first hard mask layer and the second hard mask layer, and the grid isolation groove is filled with the metal layer.
Optionally, a channel through hole is formed in the stacked structure on one side of the step structure, and a storage structure is arranged in the channel through hole.
Optionally, the memory structure includes a charge storage layer on a sidewall surface of the channel via and a channel layer on a sidewall surface of the charge storage layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the forming method of the 3D NAND memory, the plurality of pseudo through holes are formed in the dielectric layer and the step structure, the pseudo through hole material layer filling the pseudo through holes is formed, and the hardness of the pseudo through hole material layer is greater than that of the dielectric layer; after the pseudo through hole material layer is formed, forming a plurality of grid isolation grooves in the dielectric layer and the step structure; forming a semiconductor material layer on the stacked structure and the dielectric layer and in the grid separation groove; removing the semiconductor material layer on the stacked structure and the dielectric layer in a planarization mode by adopting a chemical mechanical polishing process, removing the planarized semiconductor material layer with a part of thickness in a back etching mode, and forming a conductive semiconductor layer in the grid separation groove, wherein the surface of the conductive semiconductor layer is lower than that of the dielectric layer; and forming a metal layer on the conductive semiconductor layer, wherein the metal layer is filled in the grid isolation groove. According to the invention, the pseudo through holes are formed in the dielectric layer and the step structure, on one hand, in the 3D NAND manufacturing process, as the sacrificial layer in the stack structure is removed, and the control gate is correspondingly formed at the position where the sacrificial layer is removed, the pseudo through holes are formed, and then the pseudo through hole material layers are filled in the pseudo through holes, and the pseudo through hole material layers cannot be removed when the sacrificial layer is removed, so that the step structure can be supported by the pseudo through hole material layers, and the step structure is not easy to collapse; on the other hand, the whole dielectric layer is divided into a plurality of blocks by the dummy through holes, so that the shrinkage of the dielectric layer in the subsequent high-temperature process or heating can be reduced, and when the dummy through holes in the dielectric layer and the step structure are filled with the dummy through hole material layer, because the hardness of the dummy through hole material layer is greater than that of the dielectric layer, the hardness of the whole material (the dielectric layer and the dummy through hole material layer) on the step structure can be increased by the dummy through hole material layer, and the high-temperature deformation and the thermal stress are both reduced, so that the difference between the shrinkage rate of the whole material (the dielectric layer and the dummy through hole material layer) on the step structure and the shrinkage rate of the stacked structure is smaller, and then a conductive semiconductor layer is formed in the grid separation groove (specifically, the semiconductor material layers are formed on the stacked structure and the dielectric layer and in the grid separation groove; and the semiconductor material layers on the stacked structure and the dielectric layer are removed by planarization), a concave defect cannot be formed on the surface of the dielectric layer above the step structure; when the metal layer is formed on the conductive semiconductor layer through deposition and chemical mechanical polishing processes, the metal material on the surface of the dielectric layer is prevented from remaining, so that the subsequent etching of the dielectric layer is not influenced to form a plurality of through holes exposing the surfaces of the corresponding step structures.
Furthermore, the pseudo through hole material layer is made of polycrystalline silicon, the hardness of the polycrystalline silicon material layer is higher than that of the silicon oxide material layer, high-temperature deformation and thermal stress are relatively small, and when the polycrystalline silicon is used as the pseudo through hole material layer, the surface of the dielectric layer can be better prevented from generating a concave defect.
According to the 3D NAND memory, metal residue does not exist on the surface of the dielectric layer on the step structure.
Drawings
FIGS. 1-9 are cross-sectional views illustrating a process of forming a 3D NAND memory according to an embodiment of the present invention.
Detailed Description
As mentioned in the background, when a polysilicon layer and a metal layer on the polysilicon layer are formed to form a common source of an array, the metal layer is prone to remain.
Research finds that the 3D NAND memory formation process is: firstly, forming a stacked structure with alternately stacked sacrificial layers and isolation layers on a semiconductor substrate, wherein the end part of the stacked structure is provided with a step structure; forming a dielectric layer covering the step structure; forming a plurality of grid isolation grooves in the stacked structure on one side of the step structure; forming a polysilicon material layer on the stacked structure and the dielectric layer and in the grid isolation groove; removing the polysilicon material layer on the stacked structure and the dielectric layer by a chemical mechanical polishing process, then etching back to remove the polysilicon material layer with partial thickness, and forming a polysilicon layer in the gate isolation groove, wherein the surface of the polysilicon layer is lower than the surface of the dielectric layer; forming a metal material layer on the stacked structure, the polycrystalline silicon layer and the dielectric layer; and removing the metal material layer on the surface of the stacked structure and the dielectric layer by a chemical mechanical polishing process, and forming a metal layer in the grid separation groove, wherein the metal layer is positioned on the polycrystalline silicon layer.
Further research shows that the dielectric layer formed on the step structure is usually a silicon oxide material, the silicon oxide material may shrink in a subsequent high temperature process or heating, and the shrinkage rate of the silicon oxide layer on the step structure is higher than the shrinkage rates of the isolation layer and the sacrificial layer in the stacked structure, which may cause the dielectric layer on the step structure to be recessed. In addition, after the grid separating groove is opened, when the sacrificial layer is replaced by tungsten (control grid) with higher tensile stress, each thin film structure can be pressed downwards, because the hardness of a medium layer material and a pseudo channel hole material on the step structure is lower than that of a stacked structure, the supporting force is insufficient, the depression on the step structure can be aggravated, a metal material layer can be deposited in the depression of the medium layer in the subsequent process, because the high grinding selection ratio of the medium layer material and the metal layer, the metal material in the depression is difficult to remove by CMP, metal residues are caused, when a contact structure connected with the step structure is formed in the subsequent process, the formation of a through hole exposing the step structure in the medium layer is influenced, and short circuit between adjacent contact structures is easily caused.
Therefore, the invention provides a 3D NAND memory and a forming method thereof, wherein the forming method comprises the steps of forming a pseudo through hole in a dielectric layer and a step structure, on one hand, in the manufacturing process of the 3D NAND, as a sacrificial layer in a stack structure is removed later, and a control gate is correspondingly formed at the position where the sacrificial layer is removed, the pseudo through hole is formed, and then a pseudo through hole material layer is filled in the pseudo through hole, the pseudo through hole material layer cannot be removed when the sacrificial layer is removed, so that the step structure can be supported by the pseudo through hole material layer, and the step structure is not easy to collapse; on the other hand, when the pseudo through hole material layers are filled in the dielectric layer and the pseudo through holes in the step structure, the hardness of the pseudo through hole material layers is higher than that of the dielectric layer, even if the hardness of the dielectric layer is reduced due to stress release, the overall hardness of the dielectric layer on the step structure is increased due to the pseudo through hole material layers, and when a conductive semiconductor layer is formed in the grid separation groove subsequently (specifically, a semiconductor material layer is formed on the stacked structure and the dielectric layer and in the grid separation groove; and the semiconductor material layers on the stacked structure and the dielectric layer are removed in a planarization mode), a concave defect cannot be formed on the surface of the dielectric layer above the step structure; when the metal layer is formed on the conductive semiconductor layer through deposition and chemical mechanical polishing processes, the metal material on the surface of the dielectric layer is prevented from remaining, so that the subsequent etching of the dielectric layer is not influenced to form a plurality of through holes exposing the surfaces of the corresponding step structures.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
FIGS. 1-9 are cross-sectional views illustrating a process of forming a 3D NAND memory according to an embodiment of the present invention.
Referring to fig. 1, a semiconductor substrate 100 is provided, a stacked structure 111 in which a sacrificial layer 103 and an isolation layer 104 are alternately stacked is formed on the semiconductor substrate 100, and an end of the stacked structure 111 has a step structure 11; a dielectric layer 105 covering the step structure 11 is formed on the semiconductor substrate 100.
The material of the semiconductor substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon (Si).
The stacked structure 111 comprises several sacrificial layers 103 and isolation layers 104 stacked alternately, the sacrificial layers 103 are subsequently removed to form a cavity, and then a control gate is formed at the position where the sacrificial layers 103 are removed. The isolation layer 104 serves as electrical isolation between different layers of the control gate, and between the control gate and other devices (conductive contacts, trench holes, etc.).
The sacrificial layer 103 and the isolation layer 104 are alternately stacked, that is: after forming a layer of sacrificial layer 103, a layer of isolation layer 104 is formed on the surface of sacrificial layer 103, and then the steps of forming sacrificial layer 103 and isolation layer 104 on sacrificial layer 103 are sequentially performed cyclically. In this embodiment, the bottom layer of the stacked structure 111 is a sacrificial layer 103, and the top layer is an isolation layer 104.
The number of layers of the stacked structure 111 (the number of layers of the dual-layer stacked structure of the sacrificial layer 103 and the isolation layer 104 in the stacked structure 111) is determined according to the number of memory cells required to be formed in the vertical direction, the number of layers of the stacked structure 111 may be 8, 32, 64, or the like, and the greater the number of layers of the stacked structure 111, the higher the integration level is. In the present embodiment, only the number of layers of the stacked structure 111 is 5 as an example.
The sacrificial layer 103 and the isolation layer 104 are made of different materials, and when the sacrificial layer 103 is removed subsequently, the sacrificial layer 103 has a high etching selection ratio relative to the isolation layer 104, so that when the sacrificial layer 103 is removed, the etching amount of the isolation layer 104 is small or negligible, and the flatness of the isolation layer 104 is ensured.
The isolation layer 104 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and the sacrificial layer 103 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, amorphous silicon, amorphous carbon, and polysilicon. In this embodiment, the isolation layer 104 is made of silicon oxide, the sacrificial layer 103 is made of silicon nitride, and the isolation layer 104 and the sacrificial layer 103 are formed by a chemical vapor deposition process.
The top surface of the dielectric layer 105 is flush with the top surface of the stacked structure 111, the dielectric layer 105 is made of silicon oxide, and the forming process for forming the dielectric layer 105 may be a plasma enhanced chemical vapor deposition process, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a high density plasma chemical vapor deposition process, or an atomic layer chemical vapor deposition process. In this embodiment, the dielectric layer 105 may shrink after being heated or in a subsequent high temperature process or during being heated, and since the shrinkage rate of the dielectric layer 105 is higher than the shrinkage rates of the isolation layer and the sacrificial layer in the stacked structure, the dielectric layer on the step structure may be recessed.
In this embodiment, a plurality of channel holes are further formed in the stacked structure 111 on one side of the step structure 11, and the storage structure 108 is formed in the plurality of channel holes.
The memory structure 108 includes a charge storage layer 107 on a sidewall surface of the channel via and a channel layer 106 on the charge storage layer surface 107.
In one embodiment, the charge storage layer 107 includes a blocking oxide layer, a charge trapping layer on the blocking oxide layer, and a tunneling oxide layer on the charge trapping layer. The charge trapping layer is made of silicon nitride, and the channel layer 106 is made of polysilicon.
In an embodiment, a buffer oxide layer 101 and an interlayer dielectric layer 102 on the buffer oxide layer 101 are further formed between the stacked structure 111 and the semiconductor substrate 100. In an embodiment, the interlayer dielectric layer 102 is a double-layer stacked structure including a silicon nitride layer on the buffer oxide layer 101 and a silicon oxide layer on the silicon nitride layer.
In an embodiment, after a plurality of trench holes are formed in the stacked structure 111 on one side of the step structure 11, the buffer oxide layer 101 and the interlayer dielectric layer 102 at the bottom of the trench holes and a portion of the semiconductor substrate 100 are continuously etched to form a groove; forming a semiconductor epitaxial layer in the groove by a selective epitaxial process, wherein the surface of the semiconductor epitaxial layer is lower than the surface of the interlayer dielectric layer 102 and higher than the surface of the semiconductor substrate 100, the semiconductor epitaxial layer is made of silicon, germanium or silicon germanium, and in this embodiment, the semiconductor epitaxial layer is made of silicon; a memory structure 108 is formed on the semiconductor epitaxial layer.
Referring to fig. 2 and 3, a plurality of dummy vias 110 are formed in the dielectric layer 105 and the step structure 11.
In this embodiment, the purpose of forming the dummy via 110 in the dielectric layer 105 and the step structure 11 is as follows: on one hand, in the 3D NAND manufacturing process, since the sacrificial layer in the stack structure is removed later, and the control gate is correspondingly formed at the position where the sacrificial layer is removed, the dummy via hole 110 is formed, and then the dummy via hole 110 is filled with the dummy via hole material layer, the dummy via hole material layer cannot be removed when the sacrificial layer is removed, so that the dummy via hole material layer can support the step structure 11, and the step structure is not easy to collapse; on the other hand, when the whole dielectric layer 105 is divided into a plurality of blocks by the dummy via 110, the shrinkage of the dielectric layer 105 in the subsequent high-temperature process or heating can be reduced, and when the dummy via material layers are filled in the dielectric layer 105 and the dummy via 110 in the step structure 11, because the hardness of the dummy via material layer is greater than that of the dielectric layer 105, the hardness of the whole material (the dielectric layer and the dummy via material layer) on the step structure 11 can be increased by the dummy via material layer, and the high-temperature deformation and the thermal stress are both reduced, so that the difference between the shrinkage rate of the whole material (the dielectric layer and the dummy via material layer) on the step structure 11 and the shrinkage rate of the stacked structure is smaller, and then a conductive semiconductor layer is formed in the gate spacer (specifically, a semiconductor material layer is formed on the stacked structure and the dielectric layer and in the gate spacer; and the semiconductor material layer on the stacked structure and the dielectric layer is removed by planarization), a concave defect cannot be formed on the surface of the dielectric layer above the step structure; when the metal layer is formed on the conductive semiconductor layer through deposition and chemical mechanical polishing processes, the metal material on the surface of the dielectric layer is prevented from remaining, so that the subsequent etching of the dielectric layer is not influenced to form a plurality of through holes exposing the surfaces of the corresponding step structures.
In this embodiment, before forming the dummy channel via, a first hard mask layer 109 is formed on the stacked structure 111 and the dielectric layer 105, and the first hard mask layer 109 has a first opening exposing the surface of the dielectric layer 105 above the step structure 11; and etching the dielectric layer 105 and the step structure 11 along the first opening by using the first mask layer 109 as a mask, and forming a dummy through hole 110 in the dielectric layer 105 and the step structure 11. In one embodiment, the material of the first hard mask layer 109 is silicon oxide.
In an embodiment, while the plurality of dummy vias are formed in the dielectric layer 105 and the step structure 11, the plurality of dummy vias are also formed in the stacked structure 11 on one side of the step structure 11.
Referring to fig. 4, a dummy via material layer 113 filling the dummy via 110 (refer to fig. 3) is formed, the dummy via material layer 113 having a hardness greater than that of the dielectric layer 105.
In one embodiment, the forming process of the dummy via material layer 113 is as follows: forming a dummy through hole material layer in the dummy through hole and on the surface of the first hard mask layer 105; the dummy via material layer 113 is formed in the dummy via 110 (see fig. 3) by removing the dummy via material layer on the surface of the first mask layer 105 by a chemical mechanical polishing process.
In other embodiments, when the first mask layer is not formed, the dummy via material layer on the surface of the dielectric layer is removed by planarization, and the dummy via material layer is formed in the dummy via.
In an embodiment, the hardness of the dummy via material layer 113 is greater than the hardness of the dielectric layer 105, the high temperature deformation of the dummy via material layer 110 is less than the high temperature deformation of the dielectric layer 105, and the thermal stress of the dummy via material layer 110 is less than the thermal stress of the dielectric layer 105, so that the shrinkage rate of the whole material (the dielectric layer and the dummy via material layer) on the step structure 11 is closer to or less different from that of the stacked structure, and when a conductive semiconductor layer is subsequently formed in the gate spacer (specifically, a semiconductor material layer is formed on the stacked structure and the dielectric layer and in the gate spacer, and the semiconductor material layer on the stacked structure and the dielectric layer is removed by planarization), a recess defect is not formed on the surface of the dielectric layer above the step structure.
In the embodiment, the pseudo through hole material layer is made of polycrystalline silicon, the hardness of the polycrystalline silicon material layer is higher than that of the silicon oxide material layer, high-temperature deformation and thermal stress are relatively small, when the polycrystalline silicon is used as the pseudo through hole material layer, the surface of the dielectric layer can be better prevented from generating a concave defect, the forming process is simple, and the cost is low.
In other embodiments, the dummy via material layer 113 may be made of other suitable materials, so long as the hardness of the dummy via material layer 113 is greater than that of the dielectric layer 105.
In one embodiment, the dummy via in the dielectric layer 105 and the step structure 11 is filled with a dummy via material layer, and the dummy via in the stacked structure 111 on one side of the step structure 11 is also filled with a dummy via material layer.
In an embodiment, before forming the dummy via material layer 113, a barrier layer 112 is formed on the bottom and sidewall surfaces of the dummy via 111, and the formation of the barrier layer 112 is used to prevent damage to the dummy via material layer 113 during the subsequent formation of the control gate, so as to further ensure the performance of the dummy via material layer 113 in preventing the dielectric layer 105 from generating the recess defect. The barrier layer 112 may be a single layer or a multi-layer stack structure. In one embodiment, the forming process of the barrier layer is as follows: and forming a layer of silicon nitride on the bottom and the side wall surface of the dummy through hole 111, and then performing wet oxidation to form a barrier layer structure.
Referring to fig. 5 and 6, after forming the dummy via material layer 113, a plurality of gate spacers 115 are formed in the dielectric layer 105 and the step structure 11.
The purpose of forming the gate spacer 115 is to form an Array Common Source (ACS). In this embodiment, the gate spacer 115 is formed in the dielectric layer 105 and the step structure 11. In other embodiments, a plurality of gate spacers 115 are formed in the dielectric layer 105 and the step structure 11, and a plurality of gate spacers 115 are formed in the stacked structure on one side of the step structure.
In an embodiment, after filling the dummy via material layer in the dummy via and before forming the gate spacer, a second hard mask layer 114 is formed on the surfaces of the dummy via material layer 113 and the first hard mask layer 105, and the second hard mask layer 114 has a second opening exposing the surface of the first hard mask layer on the surface of the step structure 11; and etching the first hard mask layer 109, the dielectric layer 105 and the step structure 11 along the second opening by using the second hard mask layer 114 as a mask, and forming a gate separation groove 115 in the dielectric layer 105 and the step structure 11.
In an embodiment, after forming the gate spacer 115 and before forming the conductive semiconductor layer 116, further comprising: the sacrificial layer is replaced with a control gate 123.
The sacrificial layer 103 may be removed by wet etching.
The material of the control gate 123 may be metal or other conductive material (such as polysilicon). In this embodiment, the conductive material is a metal, and the metal is one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.
In an embodiment, a high-K dielectric layer is further formed between the control gate 123 and the corresponding isolation layer 104, and the material HfO of the high-K dielectric layer2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO.
In an embodiment, when the sacrificial layer 103 is removed, the silicon nitride layer in the interlayer dielectric layer 102 is removed at the same time, and the selection gate 132 is formed at the position where the silicon nitride layer is removed, and the formation process of the selection gate 132 is the same as the formation steps of the control gate 123 and the control gate 129.
Referring to fig. 7, a semiconductor material layer is formed on the stacked structure 111 and the dielectric layer 105 and in the gate spacer 115; and removing the semiconductor material layer on the stacked structure 111 and the dielectric layer 105 by planarization, and removing a part of the planarized semiconductor material layer by back etching, so as to form a conductive semiconductor layer 116 in the gate separation groove 115, wherein the surface of the conductive semiconductor layer 116 is lower than the surface of the dielectric layer 105.
The conductive semiconductor layer 116 is made of silicon, germanium, silicon germanium, or silicon carbide.
In this embodiment, a second hard mask layer 114 is formed on the dielectric layer 105, and the semiconductor material layer on the second hard mask layer 114 is planarized.
In other embodiments, the semiconductor material layer on the surface of the dielectric layer 105 is planarized and removed when the first hard polishing layer 109 and the second hard mask layer 114 are not formed on the dielectric layer 105.
In the present application, because the dummy through hole material layer 113 is formed in the step structure 11 and the dielectric layer 105, the hardness of the structure formed by the dielectric layer on the step structure or the dielectric layer, the first hard mask layer and the second hard mask layer is increased, and when the semiconductor material layer on the dielectric layer is removed by planarization, the surface of the dielectric layer or the surface of the second hard mask layer does not form a recessed defect, or even if the recessed defect is formed, the size of the recessed defect is small, and the depth is also shallow.
In an embodiment, when the conductive semiconductor layer 116 is formed in the dielectric layer 105 and the gate spacer in the step structure 11, the conductive semiconductor layer 116 is also formed in the gate spacer in the stacked structure 111 on one side of the step structure 11.
Referring to fig. 8 and 9, a metal layer 117 is formed on the conductive semiconductor layer 116, and the metal layer 117 fills the gate spacer.
In an embodiment, the forming process of the metal layer 117 is: forming a metal material layer 125 on the conductive semiconductor layer 116, in the gate spacer and on the second hard mask layer 114; removing the metal material layer 125 on the surface of the second hard mask layer 114 by planarization (chemical mechanical polishing); a metal layer 117 is formed on the conductive semiconductor layer 116, and the metal layer 117 fills the gate isolation trench.
In another embodiment, the metal layer is formed by the following process: forming a metal material layer on the surface of the stacked structure 111, in the gate isolation groove and on the surface of the dielectric layer 105; removing the metal material layer on the surface of the stacked structure 111 and on the surface of the dielectric layer 105 by planarization (chemical mechanical polishing); a metal layer is formed on the conductive semiconductor layer 116, and the metal layer fills the gate spacer.
In the present application, since there is no recess defect on the surface of the dielectric layer 105 or the surface of the second hard mask layer 114, when the metal material layer is removed by planarization, no metal residue is generated on the surface of the dielectric layer on the step structure 11.
The conductive semiconductor layer 116 and the metal layer 117 constitute an Array Common Source (ACS). In one embodiment, the material of the metal layer 117 is tungsten.
An embodiment of the present invention further provides a 3D NAND memory, referring to fig. 9, including:
a semiconductor substrate 100, wherein the semiconductor substrate 100 has a stacked structure in which control gates 103 and isolation layers 104 are alternately stacked, and the end of the stacked structure has a step structure 11;
a dielectric layer 105 located on the semiconductor substrate 100 and covering the step structure 11;
a plurality of dummy through holes in the dielectric layer 105 and the step structure 11, wherein a dummy through hole material layer 113 is filled in the dummy through holes, and the hardness of the dummy through hole material layer 113 is greater than that of the dielectric layer 105;
a plurality of gate isolation grooves positioned in the dielectric layer 105 and the step structure 11;
the conductive semiconductor layer 116 is positioned in the grid separation groove, and the surface of the conductive semiconductor layer 116 is lower than the surface of the dielectric layer 405;
and a metal layer 117 located on the conductive semiconductor layer 116, wherein the metal layer 117 fills the gate isolation trench.
Specifically, the dielectric layer 105 is made of silicon oxide, the dummy via material layer 113 is made of polysilicon, and the metal layer 117 is made of tungsten.
In one embodiment, the bottom and sidewall surfaces of the dummy vias also have a barrier layer 12.
In one embodiment, the method further comprises: and a first hard mask layer 109 on the stacked structure 111 and the dielectric layer 105, wherein the dummy via is partially located in the first hard mask layer, and the dummy via is filled with the dummy via material layer. And the second hard mask layer 114 is positioned on the surfaces of the dummy through hole material layer 113 and the first hard mask layer 109, the gate separation groove is partially positioned in the first hard mask layer 109 and the second hard mask layer 114, and the metal layer is filled in the gate separation groove.
In one embodiment, the stacked structure on one side of the step structure 11 has a channel via therein, and the channel via has a storage structure therein. The memory structure includes a charge storage layer on a sidewall surface of the channel via and a channel layer on a sidewall surface of the charge storage layer.
The definition or description of the same or similar structure in this embodiment as that in the foregoing embodiment is omitted, and for details, refer to the definition or description of the corresponding parts in the foregoing embodiment.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (15)
1. A3D NAND memory, comprising:
the semiconductor device comprises a semiconductor substrate, wherein a stacked structure formed by alternately stacking control gates and isolation layers is arranged on the semiconductor substrate, and a step structure is arranged at the end part of the stacked structure;
the dielectric layer is positioned on the semiconductor substrate and covers the step structure;
a dummy through hole penetrating through the stacked structure, wherein a dummy through hole material layer is filled in the dummy through hole, and the hardness of the dummy through hole material layer is greater than that of the dielectric layer;
a gate spacer penetrating the stacked structure;
and the conductive semiconductor layer is positioned between the metal layer and the semiconductor substrate.
2. The 3D NAND memory of claim 1 wherein the dummy via material layer has a lower high temperature deformation than the dielectric layer.
3. The 3D NAND memory of claim 1 wherein the dummy via material layer has a thermal stress less than the thermal stress of the dielectric layer.
4. The 3D NAND memory of claim 1 wherein the dielectric layer is silicon oxide and the dummy via material layer is polysilicon.
5. The 3D NAND memory of claim 1 wherein the bottom and sidewall surfaces of the dummy via further have a barrier layer.
6. The 3D NAND memory of claim 1 wherein the stacked structure on one side of the step structure has a channel via therein with a storage structure therein.
7. The 3D NAND memory of claim 6 wherein the storage structure comprises a charge storage layer on a surface of a sidewall of the channel via and a channel layer on a surface of a sidewall of the charge storage layer.
8. The 3D NAND memory of claim 1 wherein the dummy vias include a first dummy via that extends through the stepped structure and a second dummy via that extends through the stacked structure outside of the stepped structure.
9. The 3D NAND memory of claim 1 wherein the gate spacer includes a first gate spacer and a second gate spacer, the first gate spacer penetrating the stepped structure, the second gate spacer penetrating the stacked structure outside of the stepped structure.
10. The 3D NAND memory of claim 1 wherein the material of the conductive semiconductor layer is silicon, germanium, silicon germanium, or silicon carbide.
11. The 3D NAND memory of claim 1 or 10 wherein the material of the metal layer is tungsten.
12. A method for forming a 3D NAND memory, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a stacked structure formed by alternately stacking a control gate and an isolation layer, and the end part of the stacked structure is provided with a step structure;
forming a dielectric layer covering the step structure on the semiconductor substrate;
forming a pseudo through hole penetrating through the stacked structure, wherein a pseudo through hole material layer is filled in the pseudo through hole, and the hardness of the pseudo through hole material layer is greater than that of the dielectric layer;
forming gate spacers penetrating the stacked structure;
and forming a conductive semiconductor layer and a metal layer in the grid separation groove, wherein the conductive semiconductor layer is positioned between the metal layer and the semiconductor substrate.
13. The method of forming a 3D NAND memory of claim 12, wherein the dummy vias include a first dummy via that penetrates through the stepped structure and a second dummy via that penetrates through the stacked structure except the stepped structure.
14. The method of forming a 3D NAND memory of claim 12, wherein the gate spacer includes a first gate spacer and a second gate spacer, the first gate spacer penetrating the stepped structure, the second gate spacer penetrating the stacked structure outside the stepped structure.
15. The method of forming a 3D NAND memory as claimed in claim 12, wherein the conductive semiconductor layer is made of silicon, germanium, silicon germanium, or silicon carbide, and the metal layer is made of tungsten.
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| CN110289265B (en) * | 2019-06-28 | 2020-04-10 | 长江存储科技有限责任公司 | Method for forming 3D NAND memory |
| US11239181B2 (en) * | 2019-10-24 | 2022-02-01 | Micron Technology, Inc. | Integrated assemblies |
| CN111279479B (en) * | 2020-01-20 | 2021-07-09 | 长江存储科技有限责任公司 | Local contact for three-dimensional memory device and method for forming the same |
| CN111477632B (en) * | 2020-04-23 | 2021-04-23 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device |
| WO2022048244A1 (en) * | 2020-09-07 | 2022-03-10 | 长鑫存储技术有限公司 | Semiconductor device, preparation method therefor and storage apparatus |
| CN112038349A (en) * | 2020-09-08 | 2020-12-04 | 长江存储科技有限责任公司 | Method for forming channel hole of three-dimensional memory device and three-dimensional memory device |
| CN112018122B (en) * | 2020-09-08 | 2024-06-11 | 长江存储科技有限责任公司 | Method for forming channel hole of three-dimensional memory device and three-dimensional memory device |
| CN112331671B (en) * | 2020-10-19 | 2021-11-05 | 长江存储科技有限责任公司 | Method for forming 3D NAND memory |
| CN112310105B (en) * | 2020-10-30 | 2022-05-13 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN112420724B (en) * | 2020-11-18 | 2021-09-28 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| CN113629059B (en) * | 2021-05-21 | 2024-05-10 | 长江存储科技有限责任公司 | Manufacturing method of 3D memory device and 3D memory device |
| CN113838858B (en) * | 2021-09-24 | 2024-04-05 | 长江存储科技有限责任公司 | Method for preparing three-dimensional memory |
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