CN112864167B - 3D NAND memory and forming method thereof - Google Patents
3D NAND memory and forming method thereof Download PDFInfo
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
The invention relates to a 3D NAND memory and a forming method thereof. The forming method of the 3D NAND memory includes: providing a semiconductor substrate, wherein a first stacking structure is formed on the semiconductor substrate, a first channel hole is formed in the first stacking structure, and a groove is formed in the semiconductor substrate at the bottom of the first channel hole; forming a semiconductor epitaxial layer in the groove; forming a metal silicide layer on the surface of the semiconductor epitaxial layer; forming a charge storage layer on the first channel hole side wall and the bottom; etching the charge storage layer and part of the metal silicide layer on the bottom of the first channel hole to form an opening exposing the surface of the semiconductor epitaxial layer; and forming a second channel layer in the opening, wherein the second channel layer is contacted with the semiconductor epitaxial layer. The invention ensures that the characteristic dimension of the first channel hole is kept unchanged or changed little, thereby ensuring the stability of the process.
Description
Technical Field
The present invention relates to the field of semiconductor fabrication, and in particular, to a 3D NAND memory and a method of forming the same.
Background
NAND flash memory is a better storage device than hard disk drives, and is widely used in electronic products as people seek nonvolatile memory products with low power consumption, light weight and good performance. Currently, a NAND flash memory of a planar structure has come close to the limit of practical expansion, and in order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory of a 3D structure has been proposed.
The existing 3D NAND memory formation process generally includes: forming a stacked layer in which silicon nitride layers and silicon oxide layers are alternately stacked on a substrate; etching the stacked layer, forming a channel hole in the stacked layer, etching a substrate at the bottom of the channel hole after forming the channel hole, and forming a groove in the substrate; forming an epitaxial silicon layer, commonly also referred to as SEG, in a recess at the bottom of the channel hole by selective epitaxial growth (Selective Epitaxial Growth); forming a charge storage layer and a channel layer in the channel hole, the channel layer being connected to an epitaxial silicon layer (SEG); and removing the silicon nitride layer, and forming gate metal at the position where the silicon nitride layer is removed.
In the existing 3D NAND memory forming process, the characteristic size of a channel hole is easy to change, and the stability of the process is affected.
Disclosure of Invention
The invention aims to solve the technical problem of how to keep the characteristic dimension of a channel hole stable in the forming process of a 3D NAND memory, thereby keeping the stability of the process.
The invention provides a method for forming a 3D NAND memory, which comprises the following steps:
providing a semiconductor substrate, wherein a first stacking structure with alternately stacked sacrificial layers and isolation layers is formed on the semiconductor substrate, a first channel hole penetrating through the thickness of the first stacking structure is formed in the first stacking structure, and a groove is formed in the semiconductor substrate at the bottom of the first channel hole;
forming a semiconductor epitaxial layer in the groove;
forming a metal silicide layer on the surface of the semiconductor epitaxial layer;
forming a charge storage layer on the first channel hole side wall and the bottom;
etching the charge storage layer and part of the metal silicide layer on the bottom of the first channel hole to form an opening exposing the surface of the semiconductor epitaxial layer;
and forming a second channel layer in the opening, wherein the second channel layer is contacted with the semiconductor epitaxial layer.
Optionally, the forming process of the metal silicide layer comprises the following steps: forming a metal layer on the surface of the semiconductor epitaxial layer, the surface of the side wall of the first channel hole and the surface of the first stacking structure; annealing is carried out, so that the metal layer reacts with the semiconductor epitaxial layer to form a metal silicide layer; unreacted metal is removed.
Optionally, the annealing atmosphere is inert gas, and the annealing temperature is lower than 600 ℃.
Optionally, the etching selectivity ratio of the metal silicide layer relative to the charge storage layer and the semiconductor epitaxial layer is at least more than 2:1.
Optionally, the method further comprises: forming a first channel layer on the charge storage layer; and etching the first channel layer, the charge storage layer and part of the metal silicide layer on the bottom of the first channel hole to form an opening exposing the surface of the semiconductor epitaxial layer.
Optionally, the specific step of forming the second channel layer in the opening includes:
removing the first channel layer;
a second channel layer is formed on the charge storage layer surface and the bottom and sidewall surfaces of the opening.
Optionally, the specific step of forming the second channel layer in the opening includes:
and reserving the first channel layer, and forming a second channel layer on the surface of the first channel layer and the bottom and side wall surfaces of the opening.
Optionally, the method further comprises:
filling a channel hole sacrificial layer in the first channel hole;
a second stacked structure in which a sacrificial layer and an isolation layer formed on the first stacked structure are alternately stacked;
forming a second channel hole penetrating through the thickness of the second stacking structure in the second stacking structure, wherein the second channel hole is communicated with the first channel hole;
removing the channel hole sacrificial layer;
and forming a charge storage layer on the side walls and the bottoms of the first channel hole and the second channel hole.
Alternatively, the sacrificial layer is replaced with a control gate.
In order to solve the above problems, the present invention also provides a 3D NAND memory including:
a semiconductor substrate, a first stacked structure formed by alternately stacking control gates and isolation layers on the semiconductor substrate, wherein the first stacked structure is provided with a first channel hole penetrating through the thickness of the first stacked structure, the semiconductor substrate at the bottom of the first channel hole is provided with a groove, and a semiconductor epitaxial layer is formed in the groove;
the metal silicide layer is positioned on the surface of the semiconductor epitaxial layer;
a charge storage layer on the first channel hole sidewall and bottom;
and a second channel layer on the charge storage layer, the second channel layer being in contact with the semiconductor epitaxial layer.
Optionally, the etching selectivity ratio of the metal silicide layer relative to the charge storage layer and the semiconductor epitaxial layer is at least more than 2:1.
Optionally, the material of the metal silicide layer is nickel silicide, tungsten silicide, cobalt silicide, tantalum silicide or titanium silicide.
Optionally, the charge storage layer includes a blocking oxide layer, a charge trapping layer on the blocking oxide layer, and a tunneling oxide layer on the charge trapping layer.
Optionally, the method further comprises:
a first channel layer located on the charge storage layer;
an opening in the first channel layer and the charge storage layer on the bottom of the first channel hole exposing the metal silicide layer.
Optionally, the method further comprises:
a second stacked structure in which a sacrificial layer and an isolation layer are alternately stacked on the first stacked structure, the second stacked structure having a second channel hole penetrating through a thickness of the second stacked structure, the second channel hole communicating with the first channel hole; a charge storage layer is located on the first and second channel hole sidewalls and bottom.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the forming method of the 3D NAND memory, the metal silicide layer is formed on the surface of the semiconductor epitaxial layer, and oxidation is not caused to the sacrificial layer on the side wall of the first channel hole when the metal silicide layer is formed, so that the characteristic size of the first channel hole is kept unchanged or changed very little, and the process stability is ensured; in addition, by forming the metal silicide layer on the surface of the semiconductor epitaxial layer, when the first channel layer and the charge storage layer on the bottom of the first channel hole are removed by etching to form an opening, the metal silicide layer can be used as an etching stop layer to well protect the surface of the semiconductor epitaxial layer, so that the flatness of the surface of the semiconductor epitaxial layer is ensured, and the performance of the semiconductor epitaxial layer at the bottom of the metal silicide layer in contact with the second channel layer is improved; and when the metal silicide layer is removed, the metal silicide layer has high etching selectivity relative to the first channel layer, the charge storage layer and the semiconductor epitaxial layer, so that the etched amount of the first channel layer and the charge storage layer in the channel hole and the first channel layer and the charge storage layer exposed at two sides of the opening is small, the stability of the characteristic dimension of the first channel hole is further ensured, and meanwhile, the etched amount of the semiconductor epitaxial layer at the bottom is small when the metal silicide layer is removed, and the flatness of the semiconductor epitaxial layer is further ensured.
Further, the forming process of the metal silicide layer comprises the following steps: forming a metal layer on the surface of the semiconductor epitaxial layer, the surface of the side wall of the first channel hole and the surface of the first stacking structure; annealing is carried out, so that the metal layer reacts with the semiconductor epitaxial layer to form a metal silicide layer; and removing unreacted metal, wherein the thickness of the formed metal silicide layer is not limited by the influences of the depth, the size and the side wall morphology of the first channel hole because the metal layer is in direct contact with the surface of the semiconductor epitaxial layer when the metal silicide layer is formed, so that the thickness of the formed metal silicide layer is kept uniform, the surface energy of the semiconductor epitaxial layer remained at the bottom of the metal silicide layer is further kept flat, and the performance of the semiconductor epitaxial layer at the bottom of the metal silicide layer in subsequent contact with the second channel layer is further improved.
According to the 3D NAND memory, the metal silicide layer is arranged on the surface of the semiconductor epitaxial layer, and oxidation is not caused to the sacrificial layer on the side wall of the first channel hole when the metal silicide layer is formed, so that the characteristic size of the first channel hole is kept unchanged or is kept small; and when the first channel layer and the charge storage layer on the bottom of the first channel hole are removed by etching to form an opening, the metal silicide layer is used as an etching stop layer to well protect the surface of the semiconductor epitaxial layer, so that the flatness of the surface of the semiconductor epitaxial layer is ensured, and the performance of the semiconductor epitaxial layer at the bottom of the metal silicide layer in subsequent contact with the second channel layer is improved.
Drawings
Fig. 1 to 16 are schematic cross-sectional views illustrating a process of forming a 3D NAND memory according to an embodiment of the present invention.
Detailed Description
As to the background art, in the existing 3D NAND memory forming process, the feature size of the channel hole is easy to change, which affects the stability of the process.
It has been found that the prior art process of forming the charge storage layer and the channel layer generally includes: forming a charge storage layer on the side wall and the bottom of the channel hole; forming a first channel layer on the charge storage layer; etching to remove the first channel layer and the charge storage layer on the bottom of the channel hole to form a surface opening exposing the epitaxial silicon layer (SEG); and forming a second channel layer in the opening and on the surface of the first channel layer, wherein the second channel layer and the first channel layer form a channel layer. In order to prevent the surface of the epitaxial silicon layer (SEG) from being damaged when the opening is formed, a layer of silicon oxide is generally formed on the surface of the epitaxial silicon layer (SEG) by a thermal oxidation process after the epitaxial silicon layer (SEG) is formed as an etching stop layer when the opening is formed, and the silicon nitride layer on the side wall of the channel hole is oxidized by the thermal oxidation process, so that the characteristic size of the channel hole is changed.
In addition, when silicon oxide is formed on the surface of the epitaxial silicon layer (SEG) through a thermal oxidation process, due to the effects of the deeper depth, smaller size and side wall morphology of the channel hole, oxidizing gas is easily unevenly distributed on the surface of the epitaxial silicon layer (SEG) at the bottom of the channel hole, and the surface of the epitaxial silicon layer (SEG) is unevenly or insufficiently oxidized, so that the thickness of the formed silicon oxide is uneven, the surface of the rest of the epitaxial silicon layer (SEG) is uneven, when the silicon oxide is etched after the opening is formed to expose the surface of the epitaxial silicon layer (SEG), the exposed surface of the epitaxial silicon layer (SEG) is uneven, and when a second channel layer is formed on the uneven surface of the epitaxial silicon layer (SEG), the second channel layer is easily in poor contact with the surface of the epitaxial silicon layer (SEG). And, the silicon oxide has relatively low material etch selectivity as an etch stop layer relative to the epitaxial silicon layer (SEG), channel layer and charge storage layer, which is detrimental to control of channel hole feature size and epitaxial silicon layer (SEG) surface flatness.
Therefore, the invention provides a 3D NAND memory and a forming method thereof, wherein the forming method is characterized in that a metal silicide layer is formed on the surface of a semiconductor epitaxial layer, oxidation is not caused to a sacrificial layer on the side wall of a first channel hole when the metal silicide layer is formed, so that the characteristic size of the first channel hole is kept unchanged or changed very little, the stability of a process is ensured, and the metal silicide layer is formed on the surface of the semiconductor epitaxial layer, and when an opening is formed by removing the first channel layer and a charge storage layer on the bottom of the first channel hole in a subsequent etching manner, the metal silicide layer can be used as an etching stop layer to well protect the surface of the semiconductor epitaxial layer, so that the flatness of the surface of the semiconductor epitaxial layer is ensured, and the performance of the semiconductor epitaxial layer at the bottom of the metal silicide layer when the semiconductor epitaxial layer is subsequently contacted with a second channel layer is improved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In describing embodiments of the present invention in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Fig. 1 to 16 are schematic cross-sectional views illustrating a process of forming a 3D NAND memory according to an embodiment of the present invention.
Referring to fig. 1 and 2, a semiconductor substrate 100 is provided, a first stack structure 111 is formed on the semiconductor substrate 100, in which a sacrificial layer 103 and an isolation layer 104 are alternately stacked, the first stack structure 111 has a first channel hole 105 penetrating through the thickness of the first stack structure 111, the semiconductor substrate 100 at the bottom of the first channel hole 105 has a recess 106, and a semiconductor epitaxial layer 107 is formed in the recess 106.
The material of the semiconductor substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon (Si).
The first stacked structure 111 includes a plurality of sacrificial layers 103 and isolation layers 104 alternately stacked, the sacrificial layers 103 being subsequently removed to form a cavity, and then a control gate being formed at a position where the sacrificial layers 103 are removed. The spacer layer 104 serves as an electrical isolation between the control gates of the different layers, and between the control gates and other devices (conductive contacts, channel holes, etc.).
The alternate lamination of the sacrificial layer 103 and the spacer layer 104 means that: after forming a sacrificial layer 103, a spacer 104 is formed on the surface of the sacrificial layer 103, and then the steps of forming the sacrificial layer 103 and the spacer 104 on the sacrificial layer 103 are sequentially repeated. In this embodiment, the bottom layer of the first stacked structure 111 is a sacrificial layer 103, and the top layer is an isolation layer 104.
The number of layers of the first stacked structure 111 (the number of layers of the double-layer stacked structure of the sacrificial layer 103 and the isolation layer 104 in the first stacked structure 111) is determined according to the number of memory cells to be formed in the vertical direction, and the number of layers of the first stacked structure 111 may be 8 layers, 32 layers, 64 layers, etc., so that the higher the number of layers of the first stacked structure 111, the higher the integration level can be. In this embodiment, the description will be given taking, as an example, only 4 layers of the first stacked structure 111.
The materials of the sacrificial layer 103 and the isolation layer 104 are different, and when the sacrificial layer 103 is removed later, the sacrificial layer 103 has a high etching selectivity ratio relative to the isolation layer 104, so that when the sacrificial layer 103 is removed, the etching amount of the isolation layer 104 is small or negligible, and the flatness of the isolation layer 104 is ensured.
The material of the isolation layer 104 may be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride, and the material of the sacrificial layer 103 may be one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, and polysilicon. In this embodiment, the material of the isolation layer 104 is silicon oxide, the material of the sacrificial layer 103 is silicon nitride, and the isolation layer 104 and the sacrificial layer 103 are formed by chemical vapor deposition.
The first channel hole 105 is formed by an anisotropic dry etching process, which may be a plasma etching process, before the etching process, a patterned mask layer is formed on the first stacked structure 111, the patterned mask layer has an opening exposing the surface of the first stacked structure 111, and during the etching, the patterned mask layer is used as a mask to etch the first stacked structure 111, and the first channel hole 105 is formed in the first stacked structure 111.
In an embodiment, a buffer oxide layer 101 and a dielectric layer 102 on the buffer oxide layer 101 are further formed between the first stacked structure 111 and the semiconductor substrate 100, and after the first channel hole 105 is formed, the buffer oxide layer 101 and the dielectric layer 102 at the bottom of the first channel hole 105 and a part of the semiconductor substrate 100 are continuously etched to form a groove 106; a semiconductor epitaxial layer 107 (refer to fig. 4) is formed in the recess 106 through a selective epitaxial process, where the surface of the semiconductor epitaxial layer 107 is lower than the surface of the dielectric layer 102 and higher than the surface of the semiconductor substrate 100, and the material of the semiconductor epitaxial layer 107 is silicon, germanium or silicon germanium, and in this embodiment, the material of the semiconductor epitaxial layer 107 is silicon.
In an embodiment, the dielectric layer 102 is a dual-layer stack structure, and includes a silicon nitride layer on the buffer oxide layer 101 and a silicon oxide layer on the silicon nitride layer.
Referring to fig. 3, a metal silicide layer 137 is formed on the surface of the semiconductor epitaxial layer 107.
The material of the metal silicide layer 137 is nickel silicide, tungsten silicide, cobalt silicide, tantalum silicide or titanium silicide.
The metal layer is a nickel layer, a tungsten layer, a cobalt layer, a tantalum layer or a titanium layer. The annealing atmosphere is inert gas, the annealing comprises a first annealing and a second annealing, and the temperature of the first annealing and the temperature of the second annealing are lower than 600 ℃.
In the present application, when the metal silicide layer 137 is formed, oxidation is not brought to the sacrificial layer 103 on the sidewall of the first channel hole 105, so that the feature size of the first channel hole 105 is ensured to be unchanged or changed very little, and thus the stability of the process is ensured; in addition, by forming the metal silicide layer 137 on the surface of the semiconductor epitaxial layer 107, when the first channel layer and the charge storage layer on the bottom of the first channel hole 105 are etched and removed to form an opening, the metal silicide layer 137 can be used as a stop layer for etching to well protect the surface of the semiconductor epitaxial layer 137, so that the flatness of the surface of the semiconductor epitaxial layer 137 is ensured, and the performance of the semiconductor epitaxial layer 107 on the bottom of the metal silicide layer 137 in contact with the second channel layer is improved; in addition, when the metal silicide layer 137 is removed, the metal silicide layer 137 has a high etching selectivity ratio with respect to the first channel layer, the charge storage layer and the semiconductor epitaxial layer 107, so that the amount of etching of the first channel layer and the charge storage layer in the channel hole and the first channel layer and the charge storage layer exposed at both sides of the opening is small, thereby further ensuring the stability of the characteristic dimension of the channel hole, and simultaneously, the etching amount of the semiconductor epitaxial layer 137 at the bottom is small when the metal silicide layer 137 is removed, and further ensuring the flatness of the semiconductor epitaxial layer 137.
In one embodiment, the forming process of the metal silicide layer 137 includes: forming a metal layer (not shown) on the surface of the semiconductor epitaxial layer 107, the surface of the sidewall of the first channel hole 105, and the surface of the first stacked structure 111; annealing is performed so that the metal layer reacts with the semiconductor epitaxial layer 107 to form a metal silicide layer 137; when the metal silicide layer 137 is formed, the thickness of the formed metal silicide layer 137 is not limited by the depth, the size and the sidewall morphology of the first channel hole 105, so that the thickness of the formed metal silicide layer 137 is kept uniform, the surface of the semiconductor epitaxial layer 107 remained at the bottom of the metal silicide layer 137 can be kept flat, and the performance of the semiconductor epitaxial layer 107 at the bottom of the metal silicide layer 137 in contact with the second channel layer is further improved.
Referring to fig. 4, the first channel hole 105 (refer to fig. 3) is filled with a channel hole sacrificial layer 108.
By forming the channel hole sacrificial layer 108 so that the first stack structure 111 has a flat surface, the subsequent formation of the second stack structure on the first stack structure 111 is facilitated.
In one embodiment, the formation process of the channel hole sacrificial layer 108 is: forming a sacrificial material layer in the first channel hole 105 and on the surface of the first stacked structure 111, the sacrificial material layer filling the first channel hole 105; the sacrificial material layer on the surface of the first stack structure 111 is removed by planarization, and the channel hole sacrificial layer 108 is in the first channel hole 105, wherein the planarization may be performed by using a chemical mechanical polishing process.
The material of the channel hole sacrificial layer 108 may be polysilicon, amorphous silicon, or amorphous carbon. In this embodiment, the material of the channel hole sacrificial layer 108 is polysilicon.
In other embodiments, after forming the metal silicide layer 137, the channel hole sacrificial layer 108 and the second stack structure are not formed, and the charge storage layer is directly formed on the first channel hole sidewall and the bottom; forming a first channel layer on the charge storage layer; etching the first channel layer and the charge storage layer on the bottom of the first channel hole until reaching the metal silicide layer to form an opening exposing the metal silicide layer; and removing part or all of the metal silicide layer to expose the surface of the semiconductor epitaxial layer.
Referring to fig. 5, a second stack structure 112 in which a sacrificial layer 109 and an isolation layer 110 formed on the first stack structure 101 are alternately stacked; a second channel hole 115 penetrating the thickness of the second stack structure 112 is formed in the second stack structure 112, and the second channel hole 115 communicates with the first channel hole 105.
The sacrificial layer 109 is subsequently removed to form a cavity, and then a control gate is formed at the location where the sacrificial layer 109 is removed. The isolation layer 110 serves as an electrical isolation between the control gates of the different layers, and between the control gates and other devices (conductive contacts, channel holes, etc.).
The alternate lamination of the sacrificial layer 109 and the spacer layer 110 means that: after forming a sacrificial layer 109, a spacer 110 is formed on the surface of the sacrificial layer 109, and then the steps of forming the sacrificial layer 109 and the spacer 110 on the sacrificial layer 109 are sequentially repeated. In this embodiment, the bottom layer of the second stacked structure 112 is a sacrificial layer 109, and the top layer is an isolation layer 110.
The number of layers of the second stacked structure 112 (the number of layers of the double-layer stacked structure of the sacrificial layer 109 and the isolation layer 110 in the second stacked structure 112) is determined according to the number of memory cells to be formed in the vertical direction, and the number of layers of the second stacked structure 112 may be 8 layers, 32 layers, 64 layers, etc., so that the higher the number of layers of the second stacked structure 112, the higher the integration level can be. In this embodiment, only 4 layers of the second stacked structure 112 are described as an example.
The materials of the sacrificial layer 109 and the isolation layer 110 are different, and when the sacrificial layer 109 is removed later, the sacrificial layer 109 has a high etching selectivity ratio relative to the isolation layer 110, so that when the sacrificial layer 109 is removed, the etching amount of the isolation layer 110 is small or negligible, and the flatness of the isolation layer 110 is ensured.
The material of the isolation layer 110 may be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride, and the material of the sacrificial layer 109 may be one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, and polysilicon. In this embodiment, the material of the isolation layer 110 is silicon oxide, the material of the sacrificial layer 109 is silicon nitride, and the isolation layer 110 and the sacrificial layer 109 are formed by chemical vapor deposition.
In this embodiment, the second stacked structure 112 is etched to form the second channel hole 115 by using an anisotropic dry etching process, and in a specific embodiment, the anisotropic dry etching process is a plasma etching process.
In one embodiment, a portion of the via sacrificial layer 108 may be over-etched to remove when the second channel hole 115 is etched.
In an embodiment, before etching the second stack structure 112, a buffer oxide layer 113 and a dielectric layer 114 on the buffer oxide layer 113 are formed on the second stack structure 112, and before etching the second stack structure 112, an opening corresponding to the second channel hole 115 is formed in the dielectric layer 114 and the buffer oxide layer 113.
In an embodiment, the dielectric layer 114 may be a dual-layer stack structure, including a silicon nitride layer on the buffer oxide layer 113 and a silicon oxide layer on the surface of the silicon nitride layer.
In the present embodiment, only one first stack structure and one second stack structure are described as an example, and in other embodiments, the first stack structure and the second stack structure may be plural, and the plural first stack structures and the plural second stack structures may be alternately stacked.
Referring to fig. 5 and 6 in combination, the channel hole sacrificial layer 108 is removed.
And removing the channel hole sacrificial layer 108 by wet etching. In this embodiment, TMAH (tetramethylammonium hydroxide) solution is used to remove the channel hole sacrificial layer 108.
Referring to fig. 7 and 8, a charge storage layer 116 is formed on sidewalls and bottoms of the first and second channel holes 105 and 115.
The charge storage layer 116 is for storing charge. The sacrificial material layer 108 is removed prior to forming the charge storage layer 116. In one embodiment, the removal of the sacrificial material layer 108 uses a wet etch process.
Referring to fig. 8, fig. 8 is an enlarged schematic view of the charge storage layer 116 formed in fig. 7, the charge storage layer 116 including a blocking oxide layer 116a, a charge trapping layer 116b on the blocking oxide layer 116a, and a tunneling oxide layer 116c on the charge trapping layer 116 b.
The material of the blocking oxide layer 116a and the tunneling oxide layer 116c is silicon oxide, and the material of the charge trapping layer 116b is silicon nitride. The charge trapping layer 116b, the tunnel oxide layer 116c, and the blocking oxide layer 116a are formed using a chemical vapor deposition process.
Referring to fig. 9, a first channel layer 117 is formed on the charge storage layer 116.
The first channel layer 117 may be a part of the channel layer, and the first channel layer 117 may also protect the charge storage layer 116 from being etched when the charge storage layer 116 and the metal silicide layer 137 at the bottom of the first channel hole 105 are subsequently etched.
In this embodiment, the material of the first channel layer 117 is polysilicon.
Referring to fig. 10, the first channel layer 117 and the charge storage layer 116 on the first channel hole bottom 105 are etched, and the opening 125 exposing the metal silicide layer 137 is formed with the metal silicide layer 137 as a stop layer.
The first channel layer 117 and the charge storage layer 116 on the first channel hole bottom 105 are etched using an anisotropic dry etching process. In one embodiment, the anisotropic dry etching process is a plasma etching process, and the gas used in the plasma etching process includes a fluorocarbon-containing gas.
When the first channel layer 117 and the charge storage layer 116 on the bottom 105 of the first channel hole are etched, the amount of the metal silicide layer 137 removed by etching is small, so that the stopping process of etching can be well controlled, and the metal silicide layer 137 serving as a stopping layer of etching can well protect the surface of the semiconductor epitaxial layer 137, so that the surface of the semiconductor epitaxial layer 137 is prevented from being over-etched.
Referring to fig. 11, the metal silicide layer 137 is removed, so that the opening 125 exposes the surface of the semiconductor epitaxial layer 107.
The metal silicide layer 137 is removed by dry etching or wet etching.
In this embodiment, the metal silicide layer 137 is removed by dry etching, and in one embodiment, the dry etching is anisotropic plasma etching. When the metal silicide layer 137 is removed, the metal silicide layer 137 has a high etching selectivity (at least greater than 2:1) with respect to the first channel layer 117, the charge storage layer and the semiconductor epitaxial layer 107, so that the amount of etching of the first channel layer and the charge storage layer in the channel hole and the first channel layer and the charge storage layer exposed at both sides of the opening is small, thereby further ensuring the stability of the characteristic dimension of the channel hole, and simultaneously, the etching amount of the semiconductor epitaxial layer 137 at the bottom is small when the metal silicide layer 137 is removed, and further ensuring the flatness of the semiconductor epitaxial layer 137.
When the metal silicide layer 137 is removed by anisotropic plasma etching, a portion of the metal silicide layer 137 under the charge storage layer 116 is retained.
When the first channel layer 117 and the charge storage layer 116 at the bottom of the first channel hole 105 are etched away, the first channel layer 117 and the charge storage layer 116 on the surface of the dielectric layer 114 may be removed at the same time.
In other embodiments, referring to fig. 12, a wet etching is used to remove the metal silicide layer 137.
When the metal silicide layer 137 is removed, the metal silicide layer 137 has a high etching selectivity (at least greater than 2:1) with respect to the first channel layer, the charge storage layer and the semiconductor epitaxial layer 107, so that the amount of etching of the first channel layer and the charge storage layer in the channel hole and the first channel layer and the charge storage layer exposed at both sides of the opening is small, thereby further ensuring the stability of the characteristic dimension of the channel hole, and simultaneously, the etching amount of the semiconductor epitaxial layer 137 at the bottom is small when the metal silicide layer 137 is removed, and further ensuring the flatness of the semiconductor epitaxial layer 137.
The metal silicide layer 137 is removed entirely when wet etching is used.
Referring to fig. 13, fig. 13 proceeds on the basis of fig. 11, and a second channel layer 120 is formed on the bottom and sidewall surfaces of the first channel layer 117 and the opening 125.
The material of the second channel layer 120 is polysilicon, and the forming process is chemical vapor deposition. The second channel layer 120 and the first channel layer 117 together constitute a first channel layer of the NAND memory.
In another embodiment, the first channel layer 117 is removed prior to forming the second channel layer 120.
In other embodiments, referring to fig. 14, fig. 14 is a view of fig. 12, where the first channel layer 117 (referring to fig. 12) is removed, and a second channel layer 120 is formed on the surface of the charge storage layer 116 and the bottom and sidewall surfaces of the opening 125.
Referring to fig. 15 or 16, fig. 15 is performed on the basis of fig. 13, and fig. 16 is performed on the basis of fig. 14, a filling layer 121 is formed on the channel layer 120, and the filling layer 121 fills the first and second channel holes.
The material of the filling layer 121 is silicon oxide or other suitable material.
Referring to fig. 15 or 16, after forming the channel layer 120 or the filling layer 121, the sacrificial layer 103 and the sacrificial layer 109 in the first stacked structure 111 and the second stacked structure 112 are removed (refer to fig. 13 or 14); the control gate 123 and the control gate 129 are formed correspondingly at positions where the sacrifice layer 103 and the sacrifice layer 109 are removed.
Wet etching may be used to remove the sacrificial layer 103 and the sacrificial layer 109.
The material of the control gate 123 and the control gate 129 may be metal or other conductive material (such as polysilicon). In this embodiment, the conductive material is a metal, and the metal is one or more of W, al, cu, ti, ag, au, pt, ni.
In an embodiment, a high-K dielectric layer is further formed between the control gate 123 and the control gate 129 and the corresponding isolation layer 104 and isolation layer 110, and the material HfO of the high-K dielectric layer 2 、TiO 2 、HfZrO、HfSiNO、Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 Or BaSrTiO.
In an embodiment, when the sacrificial layer 103 and the sacrificial layer 109 are removed, the silicon nitride layer in the dielectric layer 102 is removed at the same time, and the selection gate 132 is correspondingly formed at the position where the silicon nitride layer is removed, and the forming process of the selection gate 132 is the same as the forming steps of the control gate 123 and the control gate 129.
In another embodiment of the present invention, a 3D NAND memory is provided, please refer to fig. 10, which includes:
a semiconductor substrate 100, a first stacked structure 111 in which a sacrificial layer 103 and an isolation layer 104 are alternately stacked on the semiconductor substrate 100, the first stacked structure 111 having a first channel hole 105 penetrating through the thickness of the first stacked structure 111, the semiconductor substrate 100 at the bottom of the first channel hole 105 having a recess in which a semiconductor epitaxial layer 107 is formed;
a metal silicide layer 137 on the surface of the semiconductor epitaxial layer 107;
a charge storage layer 116 on the sidewalls and bottom of the first channel hole 105;
an opening 125 of the metal silicide 137 is exposed in the charge storage layer 116 at the bottom of the first channel hole 105.
In an embodiment, the charge storage layer 116 further has a first channel layer 117, and the opening 125 is located in the first channel layer 117 and the charge storage layer 116 on the bottom of the first channel hole 105, exposing the metal silicide layer 137.
The metal silicide layer is formed by the following process: forming a metal layer on the surface of the semiconductor epitaxial layer, the surface of the side wall of the first channel hole and the surface of the first stacking structure; annealing is carried out, so that the metal layer reacts with the semiconductor epitaxial layer to form a metal silicide layer; unreacted metal is removed.
The metal silicide layer 137 has a high etching selectivity with respect to the first channel layer 117, the charge storage layer 116, and the semiconductor epitaxial layer 107.
The charge storage layer 116 includes a blocking oxide layer, a charge trapping layer on the blocking oxide layer, and a tunneling oxide layer on the charge trapping layer.
In an embodiment, further comprising:
a second stack structure 112 in which the sacrificial layer 109 and the isolation layer 110 are alternately stacked on the first stack structure 111, the second stack structure 112 having a second channel hole 115 penetrating through a thickness of the second stack structure, the second channel hole 115 communicating with the first channel hole 105; a charge storage layer 116 is located on the sidewalls and bottom of the first and second channel holes 105, 115.
The same or similar structures as those of the foregoing embodiments are defined or described in this embodiment, and will not be described in detail herein, reference is made to the definition or description of the corresponding parts in the foregoing embodiments.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (13)
1. A method of forming a 3D NAND memory, comprising:
providing a semiconductor substrate, wherein a first stacking structure with alternately stacked sacrificial layers and isolation layers is formed on the semiconductor substrate, a first channel hole penetrating through the thickness of the first stacking structure is formed in the first stacking structure, and a groove is formed in the semiconductor substrate at the bottom of the first channel hole;
forming a semiconductor epitaxial layer in the groove;
forming a metal silicide layer on the surface of the semiconductor epitaxial layer, wherein the sacrificial layer on the side wall of the first channel hole is not oxidized when the metal silicide layer is formed;
forming a charge storage layer on the side wall and the bottom of the first channel hole, wherein the etching selectivity ratio of the metal silicide layer relative to the charge storage layer and the semiconductor epitaxial layer is at least more than 2:1;
etching the charge storage layer on the bottom of the first channel hole by taking the metal silicide layer as a stop layer to form an opening exposing the metal silicide layer;
removing the metal silicide layer to expose the surface of the semiconductor epitaxial layer through the opening;
and forming a second channel layer in the opening, wherein the second channel layer is contacted with the semiconductor epitaxial layer.
2. The method of forming a 3D NAND memory of claim 1 wherein the metal silicide layer forming process is: forming a metal layer on the surface of the semiconductor epitaxial layer, the surface of the side wall of the first channel hole and the surface of the first stacking structure; annealing is carried out, so that the metal layer reacts with the semiconductor epitaxial layer to form a metal silicide layer; unreacted metal is removed.
3. The method of forming a 3D NAND memory of claim 2 wherein the annealed atmosphere is an inert gas and the annealed temperature is less than 600 degrees celsius.
4. The method of forming a 3D NAND memory of claim 1, further comprising:
forming a first channel layer on the charge storage layer; and etching the first channel layer, the charge storage layer and part of the metal silicide layer on the bottom of the first channel hole to form an opening exposing the surface of the semiconductor epitaxial layer.
5. The method of forming a 3D NAND memory of claim 4 wherein the forming a second channel layer in the opening comprises:
removing the first channel layer;
a second channel layer is formed on the charge storage layer surface and the bottom and sidewall surfaces of the opening.
6. The method of forming a 3D NAND memory of claim 4 wherein the forming a second channel layer in the opening comprises:
and reserving the first channel layer, and forming a second channel layer on the surface of the first channel layer and the bottom and side wall surfaces of the opening.
7. The method of forming a 3D NAND memory of claim 1, further comprising:
filling a channel hole sacrificial layer in the first channel hole;
a second stacked structure in which a sacrificial layer and an isolation layer formed on the first stacked structure are alternately stacked;
forming a second channel hole penetrating through the thickness of the second stacking structure in the second stacking structure, wherein the second channel hole is communicated with the first channel hole;
removing the channel hole sacrificial layer;
and forming a charge storage layer on the side walls and the bottoms of the first channel hole and the second channel hole.
8. The method of forming a 3D NAND memory of claim 1 or 7 wherein the sacrificial layer is replaced with a control gate.
9. A 3D NAND memory, comprising:
a semiconductor substrate, a first stacked structure formed by alternately stacking control gates and isolation layers on the semiconductor substrate, wherein the first stacked structure is provided with a first channel hole penetrating through the thickness of the first stacked structure, the semiconductor substrate at the bottom of the first channel hole is provided with a groove, and a semiconductor epitaxial layer is formed in the groove;
the metal silicide layer is positioned on the surface of the semiconductor epitaxial layer;
the metal silicide layer is positioned between the charge storage layer and the semiconductor epitaxial layer, and the etching selection ratio of the metal silicide layer relative to the charge storage layer and the semiconductor epitaxial layer is at least more than 2:1;
and a second channel layer on the charge storage layer, the second channel layer being in contact with the semiconductor epitaxial layer.
10. The 3D NAND memory of claim 9 wherein the metal silicide layer material is nickel silicide, tungsten silicide, cobalt silicide, tantalum silicide or titanium silicide.
11. The 3D NAND memory of claim 9 wherein the charge storage layer comprises a blocking oxide layer, a charge trapping layer on the blocking oxide layer, and a tunneling oxide layer on the charge trapping layer.
12. The 3D NAND memory of claim 9 further comprising:
a first channel layer located on the charge storage layer;
an opening in the first channel layer and the charge storage layer on the bottom of the first channel hole exposing the metal silicide layer.
13. The 3D NAND memory of claim 9 further comprising:
a second stacked structure in which a sacrificial layer and an isolation layer are alternately stacked on the first stacked structure, the second stacked structure having a second channel hole penetrating through a thickness of the second stacked structure, the second channel hole communicating with the first channel hole; a charge storage layer is located on the first and second channel hole sidewalls and bottom.
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| CN110176461B (en) * | 2019-06-17 | 2020-04-10 | 长江存储科技有限责任公司 | 3D NAND memory and forming method thereof |
| KR20210027986A (en) * | 2019-09-03 | 2021-03-11 | 에스케이하이닉스 주식회사 | Semiconductor memory device and manufacturing method thereof |
| CN111106116B (en) * | 2020-01-02 | 2022-09-09 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
| CN111403403B (en) * | 2020-03-31 | 2023-05-26 | 长江存储科技有限责任公司 | Three-dimensional memory and method for manufacturing the same |
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| CN112259549A (en) * | 2020-10-19 | 2021-01-22 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor device and semiconductor device |
| WO2022083299A1 (en) * | 2020-10-19 | 2022-04-28 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device and method for forming the same |
| CN113924647B (en) * | 2020-10-19 | 2023-08-18 | 长江存储科技有限责任公司 | Three-dimensional memory device and method for forming the same |
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