CN113838858B - Method for preparing three-dimensional memory - Google Patents

Method for preparing three-dimensional memory Download PDF

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Publication number
CN113838858B
CN113838858B CN202111121719.7A CN202111121719A CN113838858B CN 113838858 B CN113838858 B CN 113838858B CN 202111121719 A CN202111121719 A CN 202111121719A CN 113838858 B CN113838858 B CN 113838858B
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compensation layer
stress compensation
wafer
stress
layer
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CN113838858A (en
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谢炜
张坤
王迪
周文犀
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application relates to a method for preparing a three-dimensional memory and the three-dimensional memory. The method comprises the following steps: forming a gate stack structure and an insulating material layer covering the gate stack structure on a first surface of the wafer, wherein the gate stack structure comprises interlayer insulating layers and gate layers which are alternately stacked and is divided into a step region and a core region, and a channel structure penetrates through the core region of the gate stack structure; forming a first stress compensation layer on the insulating material layer; and forming a plurality of connection pillars electrically connected to the channel structure or the gate layer through the first stress compensation layer and the insulating material layer. The first stress compensation layer is formed of a material having a high compressive stress. By forming the stress compensation layer with high compressive stress on the front surface of the wafer, the thickness of the stress compensation layer on the back of the wafer can be effectively prevented from being excessively large, the risk of peeling or falling off can be reduced, and the internal stress of the semiconductor device on the wafer can be improved.

Description

Method for preparing three-dimensional memory
Technical Field
The present application relates to the field of semiconductors, and more particularly, to a method of improving wafer warpage in a semiconductor manufacturing process and a three-dimensional memory.
Background
In the production of semiconductor devices, it is often necessary to provide wafers (wafer) and then to manufacture the semiconductor devices on the wafers. However, as the number of layers of a semiconductor device increases, the stress between the layers becomes unbalanced. The stress created by these layers acts on the wafer, causing the wafer to warp (bow) under the influence of various stress factors. Continuing to manufacture semiconductor devices using such warped wafers can affect layer-to-layer alignment, cause pattern structural distortion, and even wafer bonding failure, thereby reducing product yield.
In particular, after forming the channel structure of the memory string, the sacrificial layer in the stacked structure needs to be replaced with the gate layer through the slit structure (GL). Such material replacement during the GL process may result in severe stress variation, and a significant increase in wafer warpage, directly affecting the alignment of the subsequent channel contact (C1 CH) to the channel structure, the alignment of the gate contact (SSCT) to the gate layer, and the bonding alignment to the CMOS wafer.
Currently, wafer bulk stress is typically balanced by depositing a specific film (e.g., silicon nitride film, silicon oxide film, etc.) on the back of the wafer to adjust the wafer warpage.
However, as the fabrication process proceeds, the structure/material composition of the semiconductor device changes, so does the overall wafer stress and warpage. Therefore, it is necessary to repeatedly laminate a stress balance film on the back surface of the wafer to improve the warpage value. The multiple deposition of the back-of-the-crystal film is complicated in process and high in cost, and the excessively thick film is easy to peel or fall off.
Meanwhile, the warpage optimization mode of the wafer back deposition film does not substantially improve the internal stress distribution of the semiconductor device. For example, in a process of interconnecting from the bottom of a channel structure to an external circuit, it is necessary to remove a semiconductor device formed on a wafer and a part of the structure of the bottom of the channel structure and a stress balance film formed on the wafer back thereof after bonding the wafer with another wafer (for example, a wafer on which peripheral circuits such as CMOS are formed) to expose the bottom of the channel structure. The internal stress of the semiconductor device changes with the removal of the corresponding structure, and the warp value of another wafer bonded with the semiconductor device also increases.
Disclosure of Invention
The present application provides a method for improving warpage of a wafer on which a semiconductor device is located by improving internal stress distribution of the semiconductor device.
The present application also provides a three-dimensional memory with improved internal stress.
According to an aspect of the present application, there is provided a method of preparing a three-dimensional memory, wherein the method comprises: forming a gate stack structure and an insulating material layer covering the gate stack structure on a first surface of the wafer, wherein the gate stack structure comprises interlayer insulating layers and gate layers which are alternately stacked and is divided into a step region and a core region, and a channel structure penetrates through the core region of the gate stack structure; forming a first stress compensation layer on the insulating material layer; and forming a plurality of connection pillars electrically connected to the channel structure or the gate layer through the first stress compensation layer and the insulating material layer. The first stress compensation layer is formed of a material having a high compressive stress.
In an embodiment, the first stress compensation layer is formed of silicon nitride.
In an embodiment, forming the plurality of connection posts includes: forming a gate contact hole exposing at least a portion of the gate layer; forming a channel contact hole exposing at least a portion of the channel structure; and filling the gate contact hole and the channel contact hole with a conductive material.
In an embodiment, forming the gate contact hole includes: patterning the first stress compensation layer to open at a position of the first stress compensation layer corresponding to a position where the gate contact hole is to be formed; and patterning the insulating material layer using the patterned first stress compensation layer as a hard mask layer.
In an embodiment, forming the channel contact hole includes: patterning the first stress compensation layer to open at a position of the first stress compensation layer corresponding to a position where a channel contact hole is to be formed; and patterning the insulating material layer using the patterned first stress compensation layer as a hard mask layer.
In an embodiment, the method further comprises: a second stress compensation layer is formed on a second surface of the wafer opposite the first surface, wherein the second stress compensation layer is formed of a material having a high tensile stress.
In an embodiment, the first stress compensation layer has a thickness ofTo->Is within the range of (2); and the thickness of the second stress compensation layer is +.>To->Within a range of (2).
In an embodiment, the method further comprises: bonding a peripheral circuit wafer on one side of the first stress compensation layer; and removing the wafer to expose the channel structure.
According to another aspect of the present application, there is also provided a three-dimensional memory including: a gate stack structure including gate layers and interlayer insulating layers alternately stacked and divided into a core region and a step region; a channel structure penetrating the gate stack structure in the core region; a first stress compensation layer disposed on the gate stack and having a plurality of openings; and a plurality of connection pillars electrically connected to portions of each of the gate layers in the step region or the channel structure via the plurality of openings. The first stress compensation layer comprises a material having a high compressive stress.
The three-dimensional memory further includes: and peripheral circuits bonded on the first stress compensation layer.
The first stress compensation layer comprises silicon nitride.
The first stress compensation layer may have a thickness ofTo->Within a range of (2).
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:
FIG. 1 is a flow diagram illustrating a method of fabricating a three-dimensional memory according to an embodiment of the present application;
fig. 2a to 2i are cross-sectional views illustrating a method of manufacturing a three-dimensional memory according to an embodiment of the present application; and
fig. 3a to 3i are cross-sectional views illustrating a method of manufacturing a three-dimensional memory according to a comparative embodiment.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed description are merely illustrative of exemplary embodiments of the application and are not intended to limit the scope of the application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.
It should be noted that in the present specification, the expressions of first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the feature. Thus, the first stress compensation layer discussed below may also be referred to as a second stress compensation layer, and vice versa, without departing from the teachings of the present application.
In the drawings, the thickness, size, and shape of the components have been slightly adjusted for convenience of description. The figures are merely examples and are not drawn to scale. As used herein, the terms "about," "approximately," and the like are used as terms of a table approximation, not as terms of a table degree, and are intended to account for inherent deviations in measured or calculated values that will be recognized by one of ordinary skill in the art.
It will be further understood that the terms "comprises," "comprising," "includes," "including," "having," "containing," and/or "including," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of the following" appears after a list of features that are listed, the entire listed feature is modified instead of modifying a separate element in the list. Furthermore, when describing embodiments of the present application, use of "may" means "one or more embodiments of the present application. The term "exemplary" is intended to mean exemplary or illustrative.
Unless otherwise defined, all terms (including engineering and technical terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. In addition, unless explicitly defined or contradicted by context, the particular steps included in the methods described herein are not necessarily limited to the order described, but may be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
The present application may be presented in various forms, some examples of which are described below.
The present application provides a method for improving warpage of a wafer on which a semiconductor device is located by improving internal stress distribution of the semiconductor device.
Fig. 1 is a flow chart illustrating a method of manufacturing a three-dimensional memory according to an embodiment of the present application. As shown in fig. 1, a method 1000 of manufacturing a three-dimensional memory according to an embodiment of the present application includes:
s110: forming a gate stack structure and an insulating material layer covering the gate stack structure on a first surface of the wafer, wherein the gate stack structure is divided into a step region and a core region and includes alternately stacked interlayer insulating layers and gate layers, and a channel structure penetrates through the core region of the gate stack structure;
s120: forming a first stress compensation layer on the insulating material layer; and
s130: a plurality of connection pillars are formed through the first stress compensation layer and the insulating material layer, the plurality of connection pillars being electrically connected to the channel structure or to the gate layer in the step region.
Wherein the first stress compensation layer may be formed of a material having a high compressive stress.
Fig. 2a to 2i are cross-sectional views illustrating a method of manufacturing a three-dimensional memory according to an embodiment of the present application. The method 1000 will be described in detail below with reference to fig. 2a to 2 i.
Fig. 2a shows a cross-sectional view of the semiconductor structure formed after performing step S110. The method of step S110 may be performed using a GL pre-process known in the art. The embodiment of the present application is not particularly limited as long as it can form a semiconductor intermediate structure having the gate stack structure 500 and the insulating material layer 600 as shown in fig. 2 a. This is not repeated here in order not to obscure the focus of the present application.
As shown in fig. 2a, the wafer 100 includes opposing first and second surfaces 101, 102. In fig. 2, the first surface 101 and the second surface 102 are opposite in the "z" direction. During the fabrication of the semiconductor device, new layers of film are continually deposited on the first surface 101. An example of a semiconductor device formed on the wafer 100 after step S110 is shown in fig. 2a, but is not limited thereto, which may include: a semiconductor substrate 200 (e.g., polysilicon) formed on the first surface 101 of the wafer 100, and an insulating layer 201 (e.g., silicon oxide) may be interposed between the semiconductor substrate 200 and the first surface 101; a gate stack structure 500 formed on the semiconductor substrate 200, which may be divided into a core region GB and a step region SS (see fig. 2 b), and may include an interlayer insulating layer 501 (e.g., including an insulating material such as silicon oxide) and a gate layer 502 (e.g., including a conductive material such as tungsten) alternately stacked in the z-direction; a channel structure 400 that may extend through the gate stack 500 and into the semiconductor substrate 200; and an insulating material layer 600 covering the gate stack 500.
Optionally, the semiconductor device after step S110 may further include a source sacrificial layer 300. The source sacrificial layer 300 is formed between the semiconductor substrate 200 and the gate stack 500, and may include a plurality of suitable sacrificial layers, such as an oxide layer, a polysilicon layer, and an oxide layer, which are sequentially stacked as shown in fig. 2 a.
Optionally, the channel structure 400 may further include: ONO structures (e.g., blocking layer 401, charge storage layer 402, tunneling layer 403); and a polysilicon channel layer 404 and a channel plug 405, both of which may be electrically connected to the peripheral circuit wafer 800 (see fig. 2 h) via a connection post CT (see fig. 2 g), which will be described in detail below.
Optionally, the insulating material layer 600 may further include a CAP layer (CT CAP OX) covering the channel plug 405 of the channel structure 400 to protect the channel plug 405 in a subsequent process. The cap layer may be formed by depositing an oxide by a chemical vapor deposition process.
Illustratively, the material of the wafer 100 may be single crystal silicon, germanium (Ge), silicon germanium (SiGe), or the like. In the embodiments of the present application, a single crystal silicon wafer will be described as an example.
Because of the difference of the thermal expansion coefficients of the wafer and the film layers on the wafer, the stress generated by the film layers or the wafer is different, so that the wafer is warped. In general, the warp state of a wafer can be generally divided into two types: one is that the edge of the wafer is bent upwards and the middle is protruded downwards, which is similar to a bowl shape which is put forward; the other is that the edge of the wafer is bent downwards and the middle is recessed upwards, which is similar to a reverse bowl shape.
The warp state of the wafer can also be characterized by adopting warp, wherein the warp generally refers to the distance between the highest point and the lowest point of the wafer when the wafer is horizontally placed, and the two warp states can be distinguished by the positive and negative values of the warp. And when the warpage is 0, the wafer is relatively flat. Herein, when the value of the warp is positive, the wafer is limited to be in a warp state of a bowl shape in which the wafer is placed; when the value of the warpage is negative, the wafer is limited to be in a warpage state of a reversed bowl shape. The larger the absolute value of warpage, the greater the degree of warpage of the wafer. When the absolute value of warpage exceeds 200 micrometers (μm), it is considered unsuitable for further processing on the wafer, requiring a planarization process.
As previously described, in the related art, the wafer may be planarized by depositing a specific stress compensation layer on the back side of the wafer (which corresponds to the surface on which the semiconductor device is not fabricated, such as the second surface 102 in fig. 2 a). In an exemplary embodiment, the stress compensation layer may be a silicide film having a specific stress property, in other words, different silicide films may be correspondingly selected for stress balancing according to a wafer warp state. Specifically, if the warpage state of the wafer is in a forward bowl shape, a silicide film with tensile stress can be grown on the back surface of the wafer, and the warpage degree of the wafer is reduced through the tensile stress of the silicide film; if the wafer is in a reverse bowl shape, a silicide film with compressive stress is grown on the back surface of the wafer, and the degree of the wafer warpage is reduced by the compressive stress of the silicide film.
In the embodiment of the present application, after the semiconductor device structure shown in fig. 2a is formed through the GL process, the semiconductor device structure has a tensile stress and exhibits a shrinkage potential, so that the wafer 100 generally has a "bowl" shape, i.e. the middle of the wafer is protruded downward, the edge of the wafer is tilted, more specifically, the first surface 101 of the wafer 100 is warped to be concave, and the second surface 102 is warped to be convex. At this time, the wafer 100 has a warp of approximately 300 μm.
In step S120, as shown in fig. 2c, a first stress compensation layer 700 may be formed on the insulating material layer 600.
In an exemplary embodiment, the first stress compensation layer 700 may be formed of a material having a high compressive stress, for example, it may be formed of a silicide having a high compressive stress. In an exemplary embodiment, the silicide may be silicon nitride, silicon oxide, silicon oxynitride, or a silicide formed by doping the above materials. Among them, silicon nitride has good stability, and the type and magnitude of stress generated are relatively easy to control through a growth process. In this application, silicon nitride will be described as an example of a material forming the first stress compensation layer.
By forming the first stress compensation layer having a high compressive stress, a strong tensile stress of the semiconductor structure formed on the wafer 100 can be neutralized as a whole, improving the internal stress distribution state thereof. Thus, the warp of the wafer can be improved. After the first stress compensation layer 700 is formed, the absolute value of the warp of the wafer may be reduced to less than or equal to 100 μm, for example, -100 μm. In this case, the wafer 100 may be in a "bowl" shaped warp state with upside down. At this time, the overall internal stress of the semiconductor device of the wafer 100 may be expressed as compressive stress. Since the tensile stress of the semiconductor structure is raised during the subsequent step S130, in particular, the process of filling the conductive material, the overall internal stress of the semiconductor device is excessively adjusted to the compressive stress, which may be balanced with the tensile stress that may be raised later. In this step, a certain margin is reserved for stress balance in the subsequent process, so that the number of times of performing the stress balance process in the subsequent process can be effectively reduced.
In addition, as shown in fig. 2b, step S120 may further include: a second stress compensation layer 710 having a high tensile stress may be formed on the second surface 102 of the wafer 100 before the first stress compensation layer 700 is formed. For example, the second stress compensation layer 710 may be formed of silicon nitride having a high tensile stress.
As described above, in the case where the wafer 100 exhibits a bow-like state of being placed in a normal position, the wafer warp degree can be improved by forming the stress compensation layer with high tensile stress on the back surface thereof, so that the wafer tends to be flat. In this embodiment, the absolute value of the warp of the wafer can be reduced to less than or equal to 100 μm, for example, +100 μm, by a process of back-of-wafer silicon nitride deposition (BS SiN DEP) as shown in fig. 2 b. In this case, the wafer 100 is still in the "bowl" shaped warp state being placed.
Although an example in which the second stress compensation layer 710 is formed before the first stress compensation layer 700 is formed is shown herein, it should be understood that this is only exemplary, and the second stress compensation layer 710 may be formed after the first stress compensation layer 700.
In this case, since the first stress compensating layer 700 above the wafer 100 has a high compressive stress and the second stress compensating layer 710 below it has a high tensile stress, both tend to planarize the wafer 100 as if the downwardly convex middle portion of the wafer were subjected to an upward force and the upwardly turned edge was subjected to a downward force, thereby tending to planarize the entire wafer.
In the exemplary embodiment, the stress compensation layers 700 and 710 may be formed by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, however, other thin film growth methods may also be employed in other embodiments of the present invention.
In the embodiments of the present application, the stress compensation layers 700 and 710 are each formed as a silicon nitride film, but exhibit different stress characteristics, which can be achieved by changing process conditions (such as temperature, intake air amount, etc.) of PECVD. Meanwhile, the compression stress/tensile stress can be controlled by controlling the PECVD process conditions, so that the warpage of the wafer 100 can be controlled.
The process of forming the stress compensation layers 700 and 710 will be described in detail below.
In forming the first stress compensation layer 700, a silicon hydride (SiH 4 ) And ammonia (NH) 3 ) A silicon nitride (SiN) film having a compressive stress is grown over the wafer 100 (specifically, on the insulating material layer 600) using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a nitrogen atmosphere using a combination of a high frequency power source and a low frequency power source as a reactant.
Specifically, the compressive stress of SiN films is mainly due to the bombardment effect of energetic particles. At NH 3 、SiH 4 、N 2 In the ambient, siN may have some intrinsic compressive stress when deposited. If a low-frequency power source is introduced in the deposition process, a method of combining high frequency with low frequency is adopted, and the high-energy particle bombardment effect can be generated due to long particle acceleration time and high speed when reaching the reaction surface under the action of a low-frequency electric field. Under the bombardment of particlesCan lead to the combination or rearrangement of atoms and ions, further expand and deform the film structure, generate compressive stress and form the silicon nitride film with compressive stress. The SiN film after recombination of atoms and ions becomes more dense.
In forming the second stress compensation layer 710, silane (SiH 4 ) And ammonia (NH) 3 ) A SiN film having a tensile stress is grown on the second surface 102 of the wafer 100 using a PECVD process with a high frequency power source for the reactants.
Specifically, in NH 3 And SiH 4 In depositing SiN films by PECVD techniques for reactants, hydrogen (H) will bond with nitrogen (N), silicon (Si) and remain in the film. During the reaction disilane and amino groups are formed in the gas phase, the plasma products react at the substrate surface and subsequently pass H 2 And NH 3 The rejection reaction of (2) again carries out the release process of the redundant H2 on the surface of the film. During this process, the film densifies, the si—n bonds are stretched and limited by the surrounding network structure, and are effectively frozen into a tensile stress state, thereby forming a silicon nitride film having tensile stress. In the deposition of a silicon nitride film with tensile stress, the treatment of H becomes a critical factor, and the content of H directly influences the stress of the film.
When the first stress compensation layer 700 is formed, the temperature is lower, the flow rate of ammonia gas is larger, and the formed silicon nitride film has more defects (more impurities) and lower compactness than the second stress compensation layer 710.
In an exemplary embodiment, the thickness of the first stress compensation layer 700 may be atTo->Within (2), for example, can be +.>Second stress compensation layer710 may be +.>To->Within (2), for example, can be +.>It should be appreciated that the above thickness ranges are exemplary only, as long as the stress levels of the two stress compensation layers may result in improved wafer warpage.
In another embodiment of the present application, the second stress compensation layer 710 may be omitted. In this case, the magnitude of the compressive stress of the first stress compensation layer 700 may be appropriately controlled to effectively balance the wafer warpage without affecting the stress distribution balance of the final semiconductor device finished product.
Step S130 will be described in detail with reference to fig. 2d to 2 g.
In step S130, a plurality of connection posts are formed through the first stress compensation layer 700 and the insulating material layer 600.
In an exemplary embodiment, step S130 includes: step S131, forming a gate contact hole SSCT exposing at least a portion of the gate stack structure 500; step S132, forming a channel contact hole C1CH exposing at least a portion of the channel structure 400; and step S133, filling the gate contact hole SSCT and the channel contact hole C1CH with a conductive material.
In the step S131 of forming the gate contact hole SSCT, it may include: (1) transferring a mask pattern for forming the gate contact hole SSCT onto the hard mask for the gate contact hole SSCT; and (2) transferring the mask pattern onto the semiconductor device structure.
Specifically, as shown in fig. 2d, step (1) may first form a first hard mask HM1 for the gate contact hole SSCT etching on the first stress compensation layer 700; next, a first photoresist layer PH1 may be formed on the first hard mask HM1; subsequently, the first hard mask HM1 and the first stress compensation layer 700 may be patterned by a photolithography process so that both may be opened in the step region SS at a position corresponding to a position where the gate contact hole SSCT is to be formed.
Step (2) may form gate contact holes SSCT through the insulating material layer 600 and extending to the respective gate layers 502 using the first hard mask HM1 and the first stress compensation layer 700 as masks by an etching process, as shown in fig. 2 e. In this step, any suitable etching process in the art may be used, which is not limited herein.
Illustratively, although not shown in the drawings, the first hard mask HM1 and the first photoresist layer PH1 may be removed after the gate contact hole SSCT is formed.
Illustratively, the first hard mask HM1 is, for example, an asheable hard mask (Ashable Hard Mask, AHM); specifically, amorphous carbon film is possible. The excessive thickness of the hard mask may result in increased overlay alignment difficulty. However, in the present application, the main component of the first stress compensation layer 700 is silicon nitride, and the region to be etched in the step (2) is the insulating material layer 600, and the main component thereof is silicon oxide, so that the first stress compensation layer 700 may be used as a part of the hard mask to perform the gate contact hole SSCT etching, so that the thickness of the first hard mask HM1 may be reduced.
In another embodiment of the present application, the first hard mask HM1 may be omitted in case that the thickness of the first stress compensation layer 700 is appropriately increased to ensure the SSCT etching of the gate contact hole. In this case, the thickness of the first stress compensation layer 700 may be properly controlled in consideration of the etching depth of the gate contact hole SSCT, so that the requirement of balancing the wafer warpage can be satisfied without affecting the stress distribution balance of the final semiconductor device product under the condition of ensuring the gate contact hole SSCT etching requirement.
In the step S132 of forming the channel contact hole C1CH, it may include: step (3), transferring the mask pattern for forming the channel contact hole C1CH onto the hard mask for the channel contact hole C1CH; and (4) transferring the mask pattern to the semiconductor device structure.
In the embodiment of the present application, unlike the gate contact hole SSCT, since the etching depth of the channel contact hole C1CH is often small, the first stress compensation layer 700 may be directly used as a hard mask for the channel contact hole C1CH without additionally disposing a layer of hard mask. Thus, not only the process can be simplified, but also the process cost can be reduced.
Specifically, as shown in fig. 2f, first, a second photoresist layer PH2 may be formed on the first stress compensation layer 700; subsequently, the first stress compensation layer 700 may be patterned through a photolithography process so that it may be opened in the core region GB at a position corresponding to a position where the channel contact hole C1CH is to be formed; next, using the first stress compensation layer 700 as a hard mask, a channel contact hole C1CH penetrating the insulating material layer 600 and extending to the channel plug 405 of the channel structure 400 is formed by an etching process. In this step, any suitable etching process in the art may be used, which is not limited herein.
Illustratively, although not shown in the drawings, the second photoresist layer PH2 may be removed after the channel contact hole C1CH is formed.
Referring to fig. 2g, in step S133 of filling the gate contact hole SSCT and the channel contact hole C1CH with a conductive material, a conductive material such as tungsten may be deposited to the gate contact hole SSCT and the channel contact hole C1CH by a deposition process or the like to form a plurality of connection pillars CT. Thus, the plurality of connection pillars CT may be electrically connected to the channel plug 405 of the channel structure 400 or a portion of the gate layer 502 in the step region SS.
It should be appreciated that the above is merely an example, and that any suitable process may be used herein to fill the gate contact hole SSCT and the channel contact hole C1CH.
In addition, step S130 may further include: after filling the conductive material, a Chemical Mechanical Polishing (CMP) process is used to polish the top surface of the semiconductor device to remove excess conductive material.
In an exemplary embodiment, in step S131 of filling the conductive material, since the conductive material such as tungsten has a tensile stress, the tensile stress of the whole of the semiconductor device may be increased. Under the influence of this, the wafer warp changes from-100 μm in the aforementioned step S120 to an absolute value of less than 10 μm, for example, approximately 0.
According to an embodiment of the present application, as shown in fig. 2h, the method 1000 may further include: a peripheral circuit wafer 800 is bonded on one side of the first stress compensation layer 700. Specifically, peripheral circuit wafer 800 includes CMOS circuit layer 810 and wafer substrate 820. The peripheral circuit wafer 800 may be bonded to the semiconductor device manufactured through step S130 through various suitable bonding processes, which are not particularly limited herein.
In addition, as shown in fig. 2i, the method 1000 may further include: with the source sacrificial layer 300, and the barrier layer 401 of the channel structure 400 (see fig. 2 a) as stop layers, the second stress compensation layer 710, the wafer 100, the semiconductor substrate 200, etc. are removed by a CMP process to expose the bottom structure 400B of the channel structure 400 for interconnection with external circuitry.
Fig. 3a to 3i show cross-sectional views of a method of manufacturing a three-dimensional memory according to a comparative example. In the comparative example, the wafer warp problem is ameliorated by merely forming a stress compensation layer on the backside of the wafer.
The wafer warp values at various process stages of the comparative example method and the method of the present application are given in table 1 below. Where x-bow represents the wafer warp value in the x-axis direction and y-bow represents the wafer warp value in the y-axis direction. GL loop represents a stage after the GL process is completed, and corresponds to FIG. 2a and FIG. 3a. BS SiN DEP1 represents a stage after deposition of a second stress compensation layer on the back side of the wafer, which corresponds to fig. 2b and 3b. FS SiN DEP represents a stage after deposition of a first stress compensation layer on the front side of the wafer (i.e. on the layer of insulating material), which corresponds to fig. 2c. CT W DEP represents a stage after formation of a connection post by filling metal tungsten, which corresponds to fig. 2g and 3f. BS SiN DEP2 represents a stage after deposition of a third stress compensation layer on the second stress compensation layer, which corresponds to fig. 3g. Bonding represents a stage after wafer Bonding with peripheral circuitry, which corresponds to fig. 2h and 3h. Si CMP represents a stage of exposing the bottom 400B of the channel structure, which corresponds to fig. 2i and 3i.
TABLE 1
The comparative example method will be briefly described below in conjunction with fig. 3 a-3 i, while wafer warpage values for the comparative example method and the various process stages of the method of the present application are compared in conjunction with table 1. For clarity, the same or similar repetitive description as the method previously described with reference to fig. 2a to 2i will be omitted, and like reference numerals denote like parts.
First, referring to fig. 3a, a gate stack 500 and a layer of insulating material 600 may be formed on a first surface 101 of a wafer 100 as described with reference to fig. 2 a. At this time, the warp value of the wafer 100 may be about 300 μm.
Next, referring to fig. 3b, a second stress compensation layer 710 is formed on the second surface 102 of the wafer 100. Similar to fig. 2b, the second stress compensation layer 710 may be formed of silicon nitride having a high tensile stress, and may be about the thicknessThe warpage value of the wafer 100 may be reduced from 300 μm to 100 μm due to the second stress-compensating layer 710.
Subsequently, referring to fig. 3c to 3d, the gate contact hole SSCT is etched. In this process, a first hard mask HM1 and a first photoresist layer PH1 for the gate contact hole SSCT etching are formed directly on the insulating material layer 600; the first hard mask HM1 may then be patterned by a photolithography process; the pattern of the first hard mask HM1 is then transferred to the insulating material layer 600, thereby forming the gate contact hole SSCT.
In the comparative embodiment, the thickness of the first hard mask HM1 may be aboutHowever, in embodiments of the present application, as described above, since the first stress compensation layer 700 may also act as a portion of the hard mask for the gate contact hole SSCT etch, the first hard mask HM1 may be thinned, for example, may be less than about +.>Even if appropriate, the first hard mask HM1 can be removed, whereby the process cost can be effectively reduced.
Then, referring to fig. 3e, the channel contact hole C1CH is etched. In this process, a second hard mask HM2 and a second photoresist layer PH2 for etching the channel contact hole C1CH are newly formed on the insulating material layer 600; the second hard mask HM2 may then be patterned; the pattern of the second hard mask HM2 is then transferred to the insulating material layer 600, thereby forming the channel contact hole C1CH.
In a comparative embodiment, the thickness of the second hard mask HM2 may be aboutHowever, in the embodiment of the present application, as described above, the first stress compensation layer 700 may also serve as a hard mask for the channel contact hole C1CH etching without additionally depositing a new hard mask as in the comparative embodiment, so that the process cost may be reduced and the process steps may be simplified.
Next, referring to fig. 3f, as in the method described with reference to fig. 2g, a conductive material such as metal tungsten may be filled in the gate contact hole SSCT and the channel contact hole C1CH to form a plurality of connection pillars CT. At this time, the internal stress of the semiconductor structure varies drastically due to the filling of the metal material, so that the warp value of the wafer 100 increases from 100 μm to 200 μm.
In order to balance the warpage of the wafer to meet bonding requirements with the peripheral circuit wafer, in a comparative embodiment, the wafer warpage value may be reduced by continuing the process of depositing silicon nitride on the back of the wafer.
For example, as shown in fig. 3g, a third stress compensation layer 720 may be formed below the second stress compensation layer 710 such that the warp value of the wafer 100 is reduced from 200 μm to approximately 0 μm. In a comparative example, the third stress compensation layer 720 may be a thin silicon nitride with high tensile stressA film, and may be aboutAccording to a comparative example, the third stress compensation layer 720 may be formed in a similar manner to the second stress compensation layer 710, and will not be described here.
According to a comparative embodiment, the silicon nitride deposition thickness under the wafer (the sum of the thicknesses of the second stress compensation layer 710 and the third stress compensation layer 720) is already up to this pointHowever, the bottom film of the wafer is too thick, which may risk easy peeling or falling off, interfering with the subsequent process. However, according to the embodiment of the present application, unlike the comparative embodiment, the film thickness of the back surface of the wafer can be thinned, or even omitted, by forming silicon nitride on the front surface of the wafer to compensate for the internal stress of the semiconductor device, thereby enabling the film thickness of the back surface of the wafer to be, for example, 0 to +.>Within a range of (2).
In a comparative embodiment, the peripheral circuit wafer 800 may then be bonded to the surface on which the plurality of bond posts CT are located, as shown in fig. 3 h-3 i; and removing the third stress compensation layer 720, the second stress compensation layer 710, the wafer 100, and the semiconductor substrate 200 to expose the channel structure 400 for interconnection with external circuitry.
Since the third stress compensating layer 720, the second stress compensating layer 710, the wafer 100, the semiconductor substrate 200, etc. are removed, the stress of the current semiconductor device also varies due to the above structural changes. Specifically, the current semiconductor devices exhibit tensile stress and cause an increase in the warp of the wafer substrate 820 of the peripheral circuit wafer 800.
In a comparative embodiment, at this time, the warp of the wafer substrate 820 is increased to 300 μm or more. However, according to the embodiment of the present application, the variation in the warp of the wafer substrate 820 of the peripheral circuit wafer 800 is not significant due to the presence of the first stress compensation layer 700 having a compressive stress, and may be, for example, less than or equal to 100 μm. Therefore, the present application optimizes the internal stress distribution of the semiconductor device through the first stress compensation layer 700 having a high compressive stress, and can effectively suppress the warp rebound after the Si CMP stage.
According to the method for manufacturing the three-dimensional memory, the stress compensation layer with high compressive stress is formed on the front surface (for example, on the insulating material layer) of the wafer, and the margin balanced with the tensile stress possibly increased in the subsequent process can be reserved by controlling the magnitude of the compressive stress, so that the stress compensation layer does not need to be repeatedly formed on the wafer back for a plurality of times, the thickness of the stress compensation layer on the wafer back is effectively prevented from being too large, and the risk of being stripped or falling is reduced.
In addition, by forming a stress compensation layer having a high compressive stress on the front surface of the wafer (e.g., on the insulating material layer), internal stress of semiconductor devices on the wafer can be improved, and wafer warpage can be ensured within a range in which processing can be continued even when the wafer/semiconductor substrate is removed in the Si CMP process.
In addition, a stress compensation layer formed on the front side of the wafer (e.g., on the insulating material layer) may act as at least part of the hard mask for the gate contact etch, so that the hard mask thickness may be reduced, or even omitted. Similarly, the stress compensation layer can also serve as a hard mask for etching the channel contact hole, at least one hard mask deposition process can be omitted, the process cost is reduced, and the process steps are simplified.
There is also provided, in accordance with an embodiment of the present application, a three-dimensional memory that may include: a gate stack structure including gate layers and interlayer insulating layers alternately stacked and divided into a core region and a step region; a channel structure penetrating the gate stack structure in the core region; a first stress compensation layer disposed on the gate stack and having a plurality of openings; and a plurality of connection pillars electrically connected to a portion of each of the gate layers in the step region or the channel structure via the plurality of openings, wherein the first stress compensation layer comprises a material having a high compressive stress.
In an embodiment, the three-dimensional memory may further include peripheral circuitry, and the peripheral circuitry may be bonded on the first stress compensation layer.
In an embodiment, the first stress compensation layer may include silicon nitride.
In an embodiment, the first stress compensation layer may have a thickness that isTo->Within a range of (2).
The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It should be understood by those skilled in the art that the scope of protection referred to in this application is not limited to the specific combination of the above technical features, but also encompasses other technical solutions formed by any combination of the above technical features or their equivalents without departing from the technical concept. Such as the above-mentioned features and the technical features having similar functions (but not limited to) in the application are replaced with each other.

Claims (9)

1. A method of making a three-dimensional memory, wherein the method comprises:
forming a gate stack structure on a first surface of a wafer, and an insulating material layer covering the gate stack structure, wherein the gate stack structure comprises alternately stacked interlayer insulating layers and gate layers and is divided into a step region and a core region, and a channel structure penetrates through the core region of the gate stack structure;
forming a first stress compensation layer on the insulating material layer; and
a plurality of connection pillars electrically connected to the channel structure or the gate layer are formed through the first stress compensation layer and the insulating material layer,
wherein the first stress compensation layer is formed of silicon nitride having a high compressive stress;
a second stress compensation layer is formed on a second surface of the wafer opposite the first surface, wherein the second stress compensation layer is formed of a material having a high tensile stress.
2. The method of claim 1, wherein forming the plurality of connection posts comprises:
forming a gate contact hole exposing at least a portion of the gate layer;
forming a channel contact hole exposing at least a portion of the channel structure; and
the gate contact hole and the channel contact hole are filled with a conductive material.
3. The method of claim 2, wherein forming the gate contact hole comprises:
patterning the first stress compensation layer to be opened at a position of the first stress compensation layer corresponding to a position where the gate contact hole is to be formed; and
the insulating material layer is patterned using the patterned first stress compensation layer as a hard mask layer.
4. The method of claim 2, wherein forming the channel contact hole comprises:
patterning the first stress compensation layer to be opened at a position of the first stress compensation layer corresponding to a position where the channel contact hole is to be formed; and
the insulating material layer is patterned using the patterned first stress compensation layer as a hard mask layer.
5. The method of claim 1, wherein the first stress compensation layer has a thickness that is atTo->Is within the range of (2); and
the thickness of the second stress compensation layer is equal toTo->Within a range of (2).
6. The method of claim 1, further comprising:
bonding a peripheral circuit wafer on one side of the first stress compensation layer; and
the wafer is removed to expose the channel structure.
7. A three-dimensional memory formed according to the method of claim 1, comprising:
a gate stack structure including gate layers and interlayer insulating layers alternately stacked and divided into a core region and a step region;
a channel structure penetrating the gate stack structure in the core region;
a first stress compensation layer disposed on the gate stack and having a plurality of openings; and
a plurality of connection pillars electrically connected to portions of each of the gate layers in the step region or the channel structure via the plurality of openings,
the material of the first stress compensation layer is silicon nitride with high compressive stress.
8. The three-dimensional memory of claim 7, further comprising: and peripheral circuits bonded on the first stress compensation layer.
9. The three-dimensional memory of claim 7, wherein the first stress compensation layer has a thickness that is atTo the point ofWithin a range of (2).
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