CN110459462B - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- CN110459462B CN110459462B CN201910730351.0A CN201910730351A CN110459462B CN 110459462 B CN110459462 B CN 110459462B CN 201910730351 A CN201910730351 A CN 201910730351A CN 110459462 B CN110459462 B CN 110459462B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
The invention provides a method for forming a semiconductor device, which comprises the steps of placing a substrate in a reaction cavity; introducing reaction gas into the reaction cavity to generate a silicon oxynitride layer on the substrate; and after the silicon oxynitride layer meets the control requirement, immediately stopping introducing the reaction gas, and not performing a step of reaction chamber purification so as to enable the charge density on the surface of the silicon oxynitride layer to be larger than a set value, thereby neutralizing high-density and high-energy plasma generated when a dielectric layer is formed by adopting a high-density plasma chemical vapor deposition process as much as possible, enhancing the plasma resisting capability of the silicon oxynitride layer and weakening the plasma damage.
Description
Technical Field
The invention relates to the technical field of semiconductor preparation, in particular to a forming method of a semiconductor device.
Background
In recent years, progress in process technology and market demand have led to more and more high-density various types of memory devices, in which a Non-volatile memory (NVM) can retain data information when a system is turned off or no power is supplied, and a floating gate type memory device is a nonvolatile memory in which charges are stored in a floating gate and which can retain data information when no power is supplied, and thus is widely used in various commercial and military electronic devices and apparatuses.
The steps of forming a floating gate type memory device generally include: providing a substrate, wherein a source electrode/a drain electrode is formed in the substrate, and a gate structure is formed on the substrate, and generally comprises a stacked body formed by a gate oxide layer, a floating gate layer and a control gate layer, and a gate dielectric layer surrounding the stacked body. After forming a gate structure on the substrate, a silicon oxynitride layer (SiON) covering the gate structure and the substrate is also required to be formed, the silicon oxynitride layer is used as a Dielectric Anti-Reflection Coating (DARC) to improve the exposure resolution of the subsequent process, and then a Dielectric layer is formed on the silicon oxynitride layer.
With the shrinking of the size of a semiconductor device, the distance between two adjacent gate structures of a floating gate type memory device is very small, which results in a large aspect ratio of an opening formed between the two adjacent gate structures, in order to ensure that a dielectric layer can better fill the opening formed between the two adjacent gate structures, a high-density plasma chemical vapor deposition process is generally required to form the dielectric layer, and in order to meet the filling requirement of a larger aspect ratio (for example, greater than 3), the power of the high-density plasma chemical vapor deposition process is gradually increased, which results in that the high-density plasma chemical vapor deposition process generates high-density and high-energy charged plasma to bombard the surface of the silicon oxynitride layer during the filling process, and the charged plasma can pass through the silicon oxynitride layer and the control gate layer and the floating gate layer of the gate structures, irreversible damage is caused to the gate oxide layer, which causes a problem in the reliability of the device. However, if the power of the high-density plasma chemical vapor deposition process is reduced, the filling capability of the high-density plasma chemical vapor deposition process is affected, so that holes are generated in the dielectric layer, and when a contact hole is formed to connect a source/drain/gate, the holes in the dielectric layer are easy to generate dielectric breakdown, so that the contact holes are connected, a short circuit of a circuit is formed, and the yield of the device is reduced.
Disclosure of Invention
The invention aims to provide a method for forming a semiconductor device, which can give consideration to both the reliability and the yield of the semiconductor device.
In order to achieve the above object, the present invention provides a method of forming a semiconductor device, comprising:
placing a substrate in a reaction chamber;
introducing reaction gas into the reaction cavity to generate a silicon oxynitride layer on the substrate;
and stopping introducing the reaction gas after the silicon oxynitride layer meets the control requirement, so that the charge density of the surface of the silicon oxynitride layer is greater than a set value.
Optionally, the reaction gas includes a first reaction gas containing silicon and a second reaction gas containing nitrogen and oxygen; alternatively, the reaction gas includes a first reaction gas containing silicon, a third reaction gas containing nitrogen, and a fourth reaction gas containing oxygen.
Optionally, the first reactive gas comprises monosilane, the second reactive gas comprises nitrous oxide, and a volume ratio of monosilane in the first reactive gas to nitrous oxide in the second reactive gas is greater than or equal to 0.53.
Optionally, before introducing the reaction gas into the reaction chamber, introducing the second reaction gas into the reaction chamber in advance to clean the reaction chamber; or, before the reaction gas is introduced into the reaction cavity, introducing the third reaction gas into the reaction cavity in advance to clean the reaction cavity; wherein the flow rate of the second reactive gas or the third reactive gas is greater than or equal to 720 ml/min.
Optionally, when the thickness of the silicon oxynitride layer is between 140 angstroms and 160 angstroms, the silicon oxynitride layer meets the control requirement.
Optionally, the set value is greater than or equal to 1.0 milli-base/square centimeter.
Optionally, a plurality of gate structures are further formed on the substrate, and the silicon oxynitride layer is located on the substrate and extends to cover the gate structures.
Optionally, an opening is formed between two adjacent gate structures, and after the introduction of the reaction gas is stopped, the method for forming the semiconductor device further includes:
and forming a dielectric layer by adopting a high-density plasma chemical vapor deposition process, wherein the dielectric layer covers the silicon oxynitride layer and fills the opening.
Optionally, the electrical property of the plasma used in the high-density plasma chemical vapor deposition process is opposite to the electrical property of the charges on the surface of the silicon oxynitride layer.
Optionally, the aspect ratio of the opening is greater than 3, and the power of the high density plasma chemical vapor deposition process is greater than 1000 w.
It is common in the art to utilize a silicon-containing reactant gas (e.g., monosilane SiH)4) And a nitrogen-oxygen containing reaction gas (e.g. nitrous oxide N)2O) to form a silicon oxynitride layer, and, after the silicon oxynitride layer has been formed to meet control requirements, continuing to pass a nitrogen-oxygen containing reactant gas in the reaction chamber for about 20 seconds to purge the reaction chamber. The inventors have experimentally found that the utilization of N as shown in FIG. 12Time to purge the reaction chamber versus charge density of the silicon oxynitride surface, as can be seen in FIG. 1, using N2The time for purifying the reaction cavity and the charge density of the surface of the silicon oxynitride layer are in a monotonically decreasing relation, namely N is used2The longer the time for cleaning the reaction chamber, the smaller the charge density of the surface of the silicon oxynitride layer, and the charges of the surface of the silicon oxynitride layer are all positively charged. Through further analysis, it is found that the high density, high energy plasma generated during the process of forming the dielectric layer using the high density plasma cvd process is generally negatively charged.
Based on this, in the method for forming the semiconductor device provided by the invention, a substrate is arranged in the reaction cavity; introducing reaction gas into the reaction cavity to generate a silicon oxynitride layer on the substrate; and after the silicon oxynitride layer meets the control requirement, immediately stopping introducing the reaction gas, and not performing a step of reaction chamber purification so as to enable the charge density on the surface of the silicon oxynitride layer to be larger than a set value, thereby neutralizing high-density and high-energy plasma generated when a dielectric layer is formed by adopting a high-density plasma chemical vapor deposition process as much as possible, enhancing the plasma resisting capability of the silicon oxynitride layer and weakening the plasma damage.
Drawings
FIG. 1 is a graph of time for purging the reaction chamber with N2O as a function of charge density at the surface of the silicon oxynitride layer;
fig. 2 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a substrate and a gate structure according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of forming a silicon oxynitride layer on a substrate according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram illustrating a dielectric layer formed on a silicon oxynitride layer according to an embodiment of the invention;
wherein the reference numerals are:
10-a substrate; 20-a gate structure; 21-a gate oxide layer; 22-a floating gate layer; 23-a control gate layer; 24-a gate dielectric layer; 30-opening; a 40-silicon oxynitride layer; 50-dielectric layer.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
As shown in fig. 2, the present invention provides a method for forming a semiconductor device, comprising:
step S1: placing a substrate in a reaction chamber;
step S2: introducing reaction gas into the reaction cavity to generate a silicon oxynitride layer on the substrate;
step S3: and stopping introducing the reaction gas after the silicon oxynitride layer meets the control requirement, so that the charge density of the surface of the silicon oxynitride layer is greater than a set value.
Specifically, please refer to fig. 3-5, which are schematic cross-sectional views of a plurality of semiconductor structures formed by the method for forming a semiconductor device according to the present embodiment, and the method for forming a semiconductor device according to the present embodiment will be described in detail with reference to fig. 3-5.
Referring to fig. 3, step S1 is executed to provide a substrate 10, where a plurality of active regions (not shown) are defined in the substrate 10, each of the active regions extends from the top of the substrate 10 to a certain depth toward the inside of the substrate 10, and source regions and drain regions (at the circular arcs in the substrate 10 in fig. 3) are formed alternately in the active regions by ion implantation, and further, the doping types of the source regions and the drain regions may be determined according to the types of specific devices to be formed. The gate structure 20 is formed on the substrate 10 between the source region and the drain region, the gate structure 20 includes a stacked body and a gate dielectric layer 24 covering the side wall of the stacked body, the stacked body includes a gate oxide layer 21, a floating gate layer 22 and a control gate layer 23 which are sequentially overlapped, the gate oxide layer 21 covers part of the substrate 10, an ONO structure (a composite structure layer of silicon oxide-silicon nitride-silicon oxide) is further arranged between the floating gate layer 22 and the control gate layer 23 to isolate the floating gate layer 22 and the control gate layer 23, and the gate dielectric layer 24 is used for protecting the floating gate layer 22 and the control gate layer 23 from being invaded and damaged by the outside.
Further, as the size of the semiconductor device is reduced, the distance between two adjacent gate structures 20 is smaller, so that the aspect ratio of the opening 30 between two adjacent gate structures 20 is gradually increased, and the filling difficulty is higher.
Next, as shown in fig. 4, step S2 is performed to introduce a reaction gas into the reaction chamber to generate a silicon oxynitride layer 40 on the substrate 10, wherein the silicon oxynitride layer 40 further extends to cover the gate structure 20. Specifically, the reaction gas may include a first reaction gas containing silicon and a second reaction gas containing nitrogen and oxygen, so that the first reaction gas and the second reaction gas containing nitrogen and oxygen react in the reaction chamber to generate silicon oxynitride. In this embodiment, the first reaction gas is monosilane (SiH)4) The second reaction gas is nitrous oxide (N)2O), and the volume ratio of monosilane in the first reaction gas to nitrous oxide in the second reaction gas is greater than or equal to 0.53. Optionally, in order to prevent other impurity gases from affecting the formation of the silicon oxynitride 40, before the reaction gas is introduced into the reaction chamber, nitrous oxide may be introduced into the reaction chamber in advance to clean the reaction chamber, wherein the flow rate of the nitrous oxide is greater than or equal to 720 ml/min.
Further, the reaction gases may also include a first reaction gas containing silicon, a third reaction gas containing nitrogen, and a fourth reaction gas containing oxygen, but when the reaction chamber is cleaned, the third reaction gas may be used to clean the reaction chamber, and the flow rate of the third reaction gas may also be greater than or equal to 720 ml/min. And after cleaning, introducing the fourth reaction gas to enable the third reaction gas and the fourth reaction gas to react to generate a gas containing nitrogen and oxygen, and finally introducing the first reaction gas to enable the first reaction gas and the gas containing nitrogen and oxygen to react to generate the silicon oxynitride layer 40.
It is understood that while the present embodiment uses monosilane to react with nitrous oxide to form the silicon oxynitride layer 40, other embodiments may use other first and second reactive gases, for example, the first reactive gas may also be chlorosilane (SiCl)4) And the second reactive gas may be Nitric Oxide (NO), and the third reactive gas may be ammonia (NH)3) Or nitrogen (N)2) The fourth reaction gas may be oxygen (O)2) And the like, as long as the silicon oxynitride can be generated by reaction in the reaction chamber.
Next, step S3 is executed, after the silicon oxynitride layer 40 meets the control requirement, the introduction of the reaction gas is stopped, so that the charge density on the surface of the silicon oxynitride layer 40 is greater than a predetermined value. Specifically, in this embodiment, when the thickness of the silicon oxynitride layer 40 is between 140 angstroms and 160 angstroms, the silicon oxynitride layer 40 is considered to meet the control requirement, and of course, the control requirement of the formed silicon oxynitride layer 40 may be different for different semiconductor devices, and the control requirement of the silicon oxynitride layer 40 may be set according to the specifically prepared semiconductor device, which is not illustrated herein. As shown in fig. 1, since the time for purging the reaction chamber with the second reactive gas and the charge density on the surface of the silicon oxynitride layer 40 are monotonically decreased, that is, the longer the time for purging the reaction chamber with the second reactive gas, the lower the charge density on the surface of the silicon oxynitride layer 40, in the present embodiment, the introduction of the reactive gas is stopped immediately after the silicon oxynitride layer 40 meets the control requirement, and the step of purging the reaction chamber is not performed, so that the charge density on the surface of the silicon oxynitride layer 40 is maximized. Optionally, the set value is greater than or equal to 1.0 millibank per square centimeter, that is, stopping the introduction of the reaction gas can ensure that the charge density of the surface of the silicon oxynitride layer 40 is greater than 1.0 millibank per square centimeter, and the charges of the surface of the silicon oxynitride layer 40 are all positively charged (the electric field strength is a positive value).
Next, as shown in fig. 4 and 5, a dielectric layer 50 is formed by using a high density plasma chemical vapor deposition process (HDPCVD), and the dielectric layer 50 covers the silicon oxynitride layer 40 and fills the opening 30. Due to the large aspect ratio of the opening 30 (e.g., greater than 3), in order to prevent the dielectric layer 50 filling the opening 30 from generating voids, the power of the high density plasma cvd process is high (greater than 1000W), so that the high density plasma cvd process generates high density, high energy plasma. However, since the high-density and high-energy plasma is negatively charged and the charges on the surface of the silicon oxynitride layer 40 are positively charged, when the high-density and high-energy plasma bombards the silicon oxynitride layer 40, the charges on the surface of the silicon oxynitride layer 40 can neutralize part of the high-density and high-energy plasma, so that the plasma damage caused by the high-density plasma chemical vapor deposition process can be reduced, and the high-density and high-energy plasma cannot easily pass through the control gate layer 23 and the floating gate layer 22 to irreversibly damage the gate oxide layer 21, thereby taking into account the reliability and yield of the semiconductor device.
In summary, the method for forming a semiconductor device according to the embodiment of the invention includes disposing a substrate in a reaction chamber; introducing reaction gas into the reaction cavity to generate a silicon oxynitride layer on the substrate; and after the silicon oxynitride layer meets the control requirement, immediately stopping introducing the reaction gas, and not performing a step of reaction chamber purification so as to enable the charge density on the surface of the silicon oxynitride layer to be larger than a set value, thereby neutralizing high-density and high-energy plasma generated when a dielectric layer is formed by adopting a high-density plasma chemical vapor deposition process as much as possible, enhancing the plasma resisting capability of the silicon oxynitride layer and weakening the plasma damage.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of forming a semiconductor device, comprising:
placing a substrate in a reaction chamber;
introducing reaction gas into the reaction cavity to generate a silicon oxynitride layer on the substrate;
and stopping introducing the reaction gas after the silicon oxynitride layer meets the control requirement, and not performing the purification step of the reaction cavity so as to enable the charge density on the surface of the silicon oxynitride layer to be larger than a set value.
2. The method according to claim 1, wherein the reaction gas comprises a first reaction gas containing silicon and a second reaction gas containing nitrogen and oxygen; alternatively, the reaction gas includes a first reaction gas containing silicon, a third reaction gas containing nitrogen, and a fourth reaction gas containing oxygen.
3. The method of forming a semiconductor device according to claim 2, wherein the first reactive gas comprises monosilane, the second reactive gas comprises nitrous oxide, and a volume ratio of monosilane in the first reactive gas to nitrous oxide in the second reactive gas is greater than or equal to 0.53.
4. The method for forming a semiconductor device according to claim 2, wherein the second reactive gas is previously introduced into the reaction chamber to clean the reaction chamber before the reactive gas is introduced into the reaction chamber; or, before the reaction gas is introduced into the reaction cavity, introducing the third reaction gas into the reaction cavity in advance to clean the reaction cavity; wherein the flow rate of the second reactive gas or the third reactive gas is greater than or equal to 720 ml/min.
5. The method of claim 1, wherein the silicon oxynitride layer meets control requirements when the silicon oxynitride layer has a thickness of between 140 a and 160 a.
6. The method of forming a semiconductor device according to any one of claims 1 to 5, wherein the set value is greater than or equal to 1.0 milli-base/square centimeter.
7. The method of claim 1, wherein a plurality of gate structures are further formed on the substrate, and wherein the silicon oxynitride layer is on the substrate and extends over the gate structures.
8. The method of claim 7, wherein an opening is formed between two adjacent gate structures, and after the introduction of the reaction gas is stopped, the method further comprises:
and forming a dielectric layer by adopting a high-density plasma chemical vapor deposition process, wherein the dielectric layer covers the silicon oxynitride layer and fills the opening.
9. The method of claim 8, wherein a plasma used in the HDP CVD process has a charge opposite to a charge on the surface of the SiON layer.
10. The method of claim 8, wherein an aspect ratio of the opening is greater than 3 and a power of the HDP CVD process is greater than 1000W.
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