CN109461740A - A kind of three-dimensional storage part and preparation method thereof - Google Patents
A kind of three-dimensional storage part and preparation method thereof Download PDFInfo
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- CN109461740A CN109461740A CN201811260872.6A CN201811260872A CN109461740A CN 109461740 A CN109461740 A CN 109461740A CN 201811260872 A CN201811260872 A CN 201811260872A CN 109461740 A CN109461740 A CN 109461740A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 17
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- 239000002184 metal Substances 0.000 claims abstract description 212
- 239000011241 protective layer Substances 0.000 claims abstract description 112
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- 238000000034 method Methods 0.000 claims abstract description 48
- 239000004065 semiconductor Substances 0.000 claims description 39
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- 238000005530 etching Methods 0.000 claims description 29
- 239000000377 silicon dioxide Substances 0.000 claims description 18
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention discloses a kind of preparation methods of three-dimensional storage part, the described method comprises the following steps: providing underlying structure, the underlying structure includes the metal gates being alternately stacked and first material layer；The first material layer between the metal gates is removed, groove between metal gate layers is formed；Protective layer is formed, the protective layer at least fills the end of groove between the metal gate layers, and the protective layer makes trench interiors between the metal gate layers remain with air gap.
Description
Technical field
The present invention relates to memory device technical fields more particularly to a kind of three-dimensional storage part and preparation method thereof.
Background technique
Memory (Memory) is in modern information technologies for protecting stored memory device.With each class of electronic devices
The continuous improvement of demand to integrated level and the density of data storage, common two-dimensional storage device are increasingly difficult to meet the requirements,
In this case, three-dimensional (3D) memory device comes into being.
Three-dimensional storage part wipes speed and guarantor due to storage density with higher, controllable production cost, suitable compile
Characteristic is held, the main product in non-volatile memory market is had become.In general, three-dimensional storage part structure may include vertical
The multiple layer metal grid arranged on direction passes through SiO between the metal gates2Dielectric layer separates.However, in order to improve storage
Density, the metal gate stack number in three-dimensional storage part is more and more, arranges more and more intensive, following, gold
Belong to the SiO between grid2Thickness of dielectric layers needs appropriate be thinned to reduce stress influence.In this way, since metal gates spacing subtracts
SiO small, between metal gates2Dielectric layer is thinning, and the parasitic capacitance value between metal gates inevitably enlarges, this will result directly in
RC retardation ratio effect is obvious, declines memory device response speed.
It can be seen that how to improve the RC retardation ratio effect in three-dimensional storage part between metal gates, the entirety of device is improved
Performance, become this field at this stage urgent need to resolve the technical issues of.
Summary of the invention
In view of this, the main purpose of the present invention is to provide a kind of three-dimensional storage parts and preparation method thereof.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
The embodiment of the invention provides a kind of preparation methods of three-dimensional storage part, the described method comprises the following steps:
Underlying structure is provided, the underlying structure includes the metal gates being alternately stacked and first material layer；
The first material layer between the metal gates is removed, groove between metal gate layers is formed；
Protective layer is formed, the protective layer at least fills the end of groove between the metal gate layers, and the protective layer
So that trench interiors remain with air gap between the metal gate layers.
In above scheme, the protective layer covers the region between the metal gate layers except the end of groove, the guarantor
The unfilled region of sheath thus forms the air gap in the region.
In above scheme, metal gates described in the protective layer covering top.
In above scheme, the step of offer underlying structure, is specifically included:
Semiconductor substrate is provided, is formed be alternately stacked by first material layer and second material layer on the semiconductor substrate
Laminated construction；
The laminated construction is etched, grid line separate slot, the upper surface of the grid line separate slot exposure semiconductor substrate are formed；
The second material layer is removed, gate trench is formed；
Metal gates filling is executed in the gate trench, being formed includes the metal gates and the first material being alternately stacked
The underlying structure of layer.
In above scheme, the first material layer between the removal metal gates is specifically included:
The first material layer described in second bottom more than metal gates is removed, described in metal gates described in the bottom and second bottom
First material layer between metal gates is retained.
In above scheme, the method for forming the protective layer includes:
Along the side wall deposition protective layer of the grid line separate slot, the protective layer at least covers the surface of the underlying structure,
And the protective layer be at least covered on the metal gates side-walls towards the grid line separate slot and the metal gates
The end towards the grid line separate slot of interlayer groove.
In above scheme, the protective layer material includes silica.
In above scheme, the protective layer is deposited using chemical vapor deposition process；
After depositing protective layer, the method also includes:
Mask layer is formed on the surface of the underlying structure, the mask layer has opening, and the opening exposes the grid
Line separate slot and the part protective layer；
Along the opening, on the grid line separate slot side wall protective layer side wall and grid line separate slot bottom
Protective layer performs etching, so that the side-walls towards the grid line separate slot of the metal gates and the metal gates interlayer
The end towards the grid line separate slot of groove, which is formed, has certain thickness protective layer.
It in above scheme, is deposited, is had along the side wall deposition of the grid line separate slot certain thick using atom layer deposition process
The protective layer of degree, so that groove between the side-walls and the metal gate layers towards the grid line separate slot of the metal gates
Towards the grid line separate slot end formed have certain thickness protective layer.
In above scheme, after being formed with the certain thickness protective layer, the method also includes: in the grid
Conductive material is filled in line separate slot, forms array common source.
In above scheme, the underlying structure further includes several channel structures, and the channel structure passes through the metal gate
Pole is simultaneously alternatively arranged；
Definition is edge channels structure near the channel structure of the grid line separate slot；The protective layer is at least filled in institute
State the end of groove between the metal gate layers of the side towards the grid line separate slot of edge channels structure；The edge channels knot
The air gap is remained in groove between the metal gate layers of the side far from the grid line separate slot of structure.
In above scheme, the protective layer fills up the gold of the side towards the grid line separate slot of the edge channels structure
Groove between category grid layer.
The embodiment of the invention also provides a kind of three-dimensional storage part, the device includes:
Metal gate stack, including the spaced metal gates of several layers；
Groove between metal gate layers, between adjacent two layers metal gates；
Protective layer at least covers the end of groove between the metal gate layers and surrounds air gap.
In above scheme, the device further include:
Semiconductor substrate is located at the bottom device；
The metal gates are layered in the semiconductor substrate；The metal gate layers inter-drain slot position is described in the second bottom
Between metal gates more than metal gates.
In above scheme, there is first material layer between metal gates described in metal gates and second bottom described in the bottom.
In above scheme, the device further include:
Grid line separate slot, in the metal gates in the semiconductor substrate；
The protective layer, side-walls and the metal gates positioned at the metal gates towards the grid line separate slot
The end towards the grid line separate slot of interlayer groove.
In above scheme, the protective layer material includes silica.
In above scheme, the device further include: array common source is located in the grid line separate slot.
The embodiment of the invention also provides a kind of three-dimensional storage part, the device includes:
Metal gate stack, including the spaced metal gates of several layers；
Groove between metal gate layers, between adjacent two layers metal gates；
Across several grid line separate slots of the metal gate stack, the metal gate layers interval trough is at least close to described
Matcoveredn is filled in the end of grid line separate slot, and region of the groove except the end forms air gap between the metal gate layers.
In above scheme, region overlay of the groove except the end has the protective layer between the metal gate layers,
The unfilled region of protective layer thus forms the air gap in the region.
In above scheme, metal gates described in top are covered with the protective layer.
In above scheme, the side wall of the grid line separate slot is covered with the protective layer.
In above scheme, further includes: the array common source in the grid line separate slot.
In above scheme, the protective layer is the silica that atom layer deposition process is formed.
In above scheme, the protective layer is the silica that chemical vapor deposition process is formed.
In above scheme, further includes: between metal gates described in metal gates and second bottom described in the bottom
One material layer.
In above scheme, the three-dimensional storage part further include:
Across several spaced channel structures of the metal gate stack；
Definition is edge channels structure near the channel structure of the grid line separate slot；The direction of the edge channels structure
The end of groove is filled with the protective layer between the metal gate layers of the side of the grid line separate slot；The edge channels structure
The air gap is formed in groove between the metal gate layers of side far from the grid line separate slot.
In above scheme, groove between the metal gate layers of the side towards the grid line separate slot of the edge channels structure
It is filled up by the protective layer.
The preparation method of three-dimensional storage part provided by the embodiment of the present invention, comprising the following steps: underlying structure is provided,
The underlying structure includes the metal gates being alternately stacked and first material layer；Remove the first material between the metal gates
Layer forms groove between metal gate layers；Protective layer is formed, the protective layer at least fills the end of groove between the metal gate layers
Portion, and the protective layer makes trench interiors between the metal gate layers remain with air gap.In this way, due in metal gates interlayer
Trench interiors remain with air gap, i.e., are separated between metal gates using air gap, and the dielectric constant of air gap levels off to 1, is much smaller than
The dielectric constant of other media material is, for example, less than SiO2Dielectric constant (~3.9), so as to be effectively reduced metal gate
Interelectrode capacity value reduces the RC retardation ratio effect in memory device between metal gates, improves the response speed of device, improve device
Overall performance.
Detailed description of the invention
Fig. 1 is using SiO2The three-dimensional storage part structural profile illustration of dielectric layer isolating metal grid layer；
Fig. 2 is the diagrammatic cross-section of three-dimensional storage part during the preparation process；
Fig. 3 is the flow diagram of the preparation method of three-dimensional storage part provided in an embodiment of the present invention；
Fig. 4 to Figure 11 is that the device architecture section in the preparation process of three-dimensional storage part provided in an embodiment of the present invention shows
It is intended to；
Figure 12 is that the arrangement architecture of grid line separate slot and through-hole structure is bowed in three-dimensional storage part provided in an embodiment of the present invention
View.
Description of symbols:
100,200- three-dimensional storage part；
10,20- semiconductor substrate；
11,21- laminated construction；111,211- first material layer；112- second material layer；The first insulation material layer of 214-；
22- stacks film layer；The barrier layer 221-；222- accumulation layer；223- tunnel layer；
23- channel layer；
24- insulative core layer；
25- doped region；
26- gate structure；261- high-k dielectric layer；262- metal barrier；163,263- metal gates；
27- etching barrier layer；28- protective layer；29- array common source.
Specific embodiment
Disclosed illustrative embodiments that the present invention will be described in more detail below with reference to accompanying drawings.Although being shown in attached drawing
Exemplary embodiments of the present invention, it being understood, however, that may be realized in various forms the present invention, without that should be illustrated here
Specific embodiment limited.It is to be able to thoroughly understand the present invention, and energy on the contrary, providing these embodiments
It is enough to be fully disclosed to those skilled in the art range disclosed by the invention.
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description；That is, not describing whole features of practical embodiments here, it is not described in detail well known function and structure.
In the accompanying drawings, for clarity, floor, area, the size of element and its relative size may be exaggerated.Phase from beginning to end
Identical element is indicated with appended drawing reference.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " its
When its element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer,
Or there may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ",
When " being directly connected to " or " being directly coupled to " other elements or layer, then there is no elements or layer between two parties.Although should be understood that
Can be used term first, second, third, etc. various component, assembly units, area, floor and/or part are described, these component, assembly units, area,
Layer and/or part should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part
With another component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below,
Component, area, floor or part are represented by second element, component, area, floor or part.And when discuss second element, component, area,
When layer or part, do not indicate that the present invention certainly exists first element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ...
On ", " above " etc., herein can for convenience description and be used to describe an elements or features shown in figure
With the relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relation term intention further includes
The different orientation of device in using and operating.For example, then, being described as " in other elements if the device in attached drawing is overturn
Below " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary
Term " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated and (be rotated by 90 °
Or other orientations) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
Fig. 1 is shown using SiO2The three-dimensional storage part structure of dielectric layer isolating metal grid layer.
As shown, three-dimensional storage part 100 includes: semiconductor substrate 10, and it is arranged in described half along the vertical direction
The metal gates 163 of 10 top of conductor substrate；Pass through 111 (SiO of first material layer between the metal gates 1632Dielectric layer)
It separates.
In the preparation process of above-mentioned three-dimensional storage part, the metal gates 163 can be by removing first material layer
Second material layer between 111 is filled metal material in the groove formed after removal and is formed.And the first material layer
111 are retained, and form metal gates zone isolation structure.
In order to make it easy to understand, can specifically refer to Fig. 2.In the preparation process of three-dimensional storage part, it is necessary first in institute
State the laminated construction 11 that formation is alternately stacked by first material layer 111 and second material layer 112 in semiconductor substrate 10；Wherein,
First material layer 111 can be SiO2Dielectric layer, second material layer 112 can be SiN material layer.163 shape of metal gates
At in the position where the second material layer 112.
From Fig. 1 and Fig. 2 can be seen that in three-dimensional storage part on vertical direction metal gates number demand increasing
More, the laminated construction 11 formed on a semiconductor substrate is also required to the more crypto set of arrangement, this just not can avoid first material layer
111 and the thickness in monolayer of second material layer 112 be suitably thinned；When being subsequently formed metal gates, correspondingly, metal gates
Spacing between each layer of thickness and adjacent two layers all becomes smaller, and the dielectric layer between adjacent two layers metal gates is thinner.
In metal gates interlamellar spacing from becoming smaller, and the parasitism in the still immovable situation of inter-level dielectric layer material, between metal gates
Capacitance certainly will will increase.
In one embodiment of this invention, a kind of preparation method of three-dimensional storage part is provided.
Fig. 3 shows the flow diagram of the preparation method of the three-dimensional storage part.
As shown, the described method comprises the following steps:
Step 101 provides underlying structure, and the underlying structure includes the metal gates being alternately stacked and first material layer；
First material layer between step 102, the removal metal gates, forms groove between metal gate layers；
Step 103 forms protective layer, and the protective layer at least fills the end of groove between the metal gate layers, and institute
Stating protective layer makes trench interiors between the metal gate layers remain with air gap.
Referring to FIG. 4, in an embodiment of the present invention, the step of offer underlying structure, is specifically included:
Firstly, providing semiconductor substrate 20, formed in the semiconductor substrate 20 by first material layer 211 and the second material
The laminated construction 21 that bed of material (not shown) is alternately stacked；
Here, the semiconductor substrate 20 may include that (for example, silicon (Si) serves as a contrast at least one element semiconductor material
Bottom, germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor materials, extremely
Few organic semiconducting materials or other semiconductor materials being known in the art.
First material layer 211 can be dielectric layer, and material includes but is not limited to Si oxide, silicon-nitride layer, silicon nitrogen
Oxide and other high dielectric constants (high k) dielectric layer；Second material layer can be sacrificial layer, such as can be by oxide
The formation of one of layer, nitride layer, silicon carbide layer, silicon layer and germanium-silicon layer.In the present embodiment, first material layer 211 can be by
SiO2It is formed, second material layer can be formed by SiN, so that the laminated construction 21 formed is NO lamination.First material layer and
Two material layers can use chemical vapor deposition (CVD) technique, plasma enhanced chemical vapor deposition (PECVD) technique or original
Sublayer deposition (ALD) technique is formed；Wherein, first material layer and second material layer can have mutually the same thickness, can also
With thickness different from each other.In one embodiment, the first material layer of the bottom can compare lamination in laminated construction 21
The first material layer of other layers is thin in structure 21；The first material layer of bottom layer second from the bottom can be compared to folded in laminated construction 21
The first material layer of other layers is thick in layer structure 21；Each second material layer can have essentially identical thickness.
Then, with continued reference to Fig. 4, the laminated construction 21 is etched, forms grid line (Gate Line) separate slot GH, the grid
The upper surface of the line separate slot GH exposure semiconductor substrate；
In one embodiment of this invention, before forming grid line separate slot GH, the method can also include completing channel
The step of structure.Specifically, the laminated construction 21 is etched, channel through-hole CH, the channel through-hole CH exposure described half are formed
Conductor substrate 20.The channel through-hole CH can be formed by dry etch process.Optionally, at the bottom of the channel through-hole CH
In portion, the semiconductor substrate 20, formed epitaxial layer (SEG).Film layer is stacked next, being formed in the channel through-hole CH
22.In one embodiment, the stacking film layer 22 may include barrier layer-accumulation layer-tunnel layer structure；The stacking film layer 22
It is specifically as follows ONO lamination, AONO lamination, ONOP lamination or other suitable stacking film layer structures.In the present embodiment, institute
State to be formed it is described stack film layer process can specifically include: in the channel through-hole CH deposit one layer of high-k dielectric layer (such as
Al2O3Layer), the high-k dielectric layer can have relatively thin thickness；Deposited oxide layer is (such as in the high-k dielectric layer
SiO2Layer)；The high-k dielectric layer and the oxide skin(coating) collectively constitute compound barrier layer 221；Continue in the oxide skin(coating)
Upper deposition accumulation layer 222；In one embodiment, the accumulation layer 222 is specifically as follows electric charge capture layer, the electric charge capture layer
Material can be nitride (such as SiN layer)；Tunnel layer 223, the material of the tunnel layer 223 are deposited in the accumulation layer 222
Material can be oxide (such as SiO2Layer)；The barrier layer 221, accumulation layer 222, tunnel layer 223 play control memory jointly
The effect of part electric charge store function, i.e., collectively as memory layer.It is heavy that CVD or ALD method can be used in the stacking film layer 22
Product is formed.It may include that etching stacks film layer bottom after the stacking film layer 22 formation, the exposure epitaxial layer SEG's
Step.Next, depositing trench layer 23, the channel layer 23 provides carrier mobile channel for the memory device；Institute
It states and forms (such as the SiO of insulative core layer 24 on channel layer 232), which fills up the rest of channel through-hole CH.
The step of executing and etch the laminated construction 21, forming grid line separate slot GH.Specifically, such as photoresist can be used
Form mask layer on the laminated construction 21, after exposure-development, grid line separate slot GH to be formed in the exposure laminated construction
Part；The laminated construction material in the part of the grid line separate slot GH to be formed is removed using etching technics, to be formed
Grid line separate slot GH；The etching technics terminates at the upper surface of the semiconductor substrate.
In one embodiment of this invention, the method also includes the semiconductors in the bottom grid line separate slot GH
In substrate, it is formed with semiconductor doping region 25.The doped region 25 can be by passing through the grid line for atoms of dopant
Separate slot GH is injected into the semiconductor substrate 20 and is formed；Alternatively, selective epitaxial growth ion doping half can also be passed through
Conductor material is formed.The doped region 25 can be used as the source region of device.In the present embodiment, the semiconductor is mixed
Miscellaneous region 25 is, for example, N-type semiconductor doped region；The semiconductor substrate 20 is, for example, p type semiconductor layer.
Referring again to FIGS. 4, the method also includes: the second material layer is removed, gate trench T is formed.Here, described
Second material layer can have different etching selection ratios from first material layer, so that the more conducively described second material layer is gone
It removes.
In one embodiment of this invention, after the second material layer is removed, semiconductor substrate 20 and epitaxial layer SEG
Exposed surface through peroxidating, form the first insulation material layer 214.
Next, please referring to Fig. 5-6, metal gates 263 being executed in the gate trench T and are filled, being formed includes alternating
The metal gates 263 of stacking and the underlying structure of first material layer 211.
In one embodiment, it can specifically include: first depositing one layer of high-k dielectric layer 261 in the gate trench T；So
Afterwards, the deposited metal barrier layer 262 in the high-k dielectric layer 261；Finally, the metal barrier described in the gate trench T
Fill the metal gate layers 263 in 262 inside.Wherein, the height that the material of the high-k dielectric layer can be common selected from this field
Dielectric constant material, such as Al2O3；The metal barrier can be by transition metal material or the metal nitride shape of conduction
At for example including at least one of titanium, tantalum, titanium nitride, tantalum nitride；The metal gate layers can be formed by electrode material,
For example, tungsten, nickel or tungsten nickel etc..The high-k dielectric layer 261, the metal barrier 262, the metal gate layers
263 collectively constitute the gate structure 26 of the memory device.Also, the high-k dielectric layer 261, the metal barrier 262,
The metal gate layers 263 can be by being formed in grid line separate slot GH using CVD or ALD process deposits.
With reference to Fig. 6, the gate structure material in the grid line separate slot GH is removed, exposes first insulation material layer 214
Upper surface and first material layer 211 side wall, formed metal gates 263 side wall.In one embodiment, the grid are removed
Gate structure material in line separate slot GH, can be executed by wet-etching technology.
Next, please referring to Fig. 7 a and Fig. 7 b, etching barrier layer 27 is formed in the grid line separate slot GH.The etching
The upper surface on barrier layer 27 is located at the side-walls of metal gates described in second bottom (i.e. bottom device layer metal gates second from the bottom)；
So that between metal gates described in the etching barrier layer 27 at least metal gates described in the device bottom and second bottom
The side wall of first material layer 211 and the device architecture of 211 bottom of first material layer on form enough protective effects.Institute
The material for stating etching barrier layer 27 can choose the material for having higher etching selection ratio with first material layer, such as can be
SiN, a-Si etc..
It as shown in Figure 7a, in an embodiment of the present invention, can be by high depth than chemical vapor deposition (HARP CVD)
Technique or gas ions enhancing chemical vapor deposition (PECVD) technique form the etching barrier layer 27.In this embodiment, institute
State the grid line three-way hole grid line separate slot GH that etching barrier layer 27 is also covered on metal gates described in device second bottom or more
On side wall.
As shown in Figure 7b, in an alternative embodiment of the invention, the etching barrier layer 27 can fill up the grid line first
Separate slot GH；By chemically mechanical polishing (CMP) technique, the top section of the etching barrier layer 27 is planarized；Etching
Etching barrier layer 27 in the grid line separate slot GH finally makes the upper surface of the etching barrier layer 27 be located at the second bottom
The side-walls of the metal gates are located between metal gates described in metal gates described in the device bottom and second bottom
First material layer 211 upper surface on.It the step of etching barrier layer 27 in the etching grid line separate slot GH, can be with
It is executed using dry etch process.
Next, referring to FIG. 8, first material layer described in removal second bottom more than metal gates, gold described in the bottom
The first material layer belonged between metal gates described in grid and second bottom is retained.In this way, between the metal gates, shape
At groove LT between the metal gate layers.
In an embodiment of the present invention, a small amount of quarter removed on the side wall of the grid line separate slot GH can first be etched
Lose barrier layer；Then first material layer more than metal gates described in the secondarily etched removal second bottom.It is another in the present invention
In embodiment, the first material layer of metal gates described in the second bottom or more can be directly removed.The removal step can be with
It is realized using wet-etching technology.It, can be with the high K medium in the gate structure 26 when removing the first material layer
Layer 261 is used as etch stop layer；The gate structure 26 will not be destroyed；The device bottom metal gates and second bottom
First material layer 211 between metal gates is retained due to the presence of etching barrier layer 27.
Next, referring to FIG. 9, removing remaining etching barrier layer 27.In the present embodiment, wet etching can be used
Technique removes remaining etching barrier layer materials.
Next, please referring to Figure 10 a and Figure 10 b, protective layer 28 is formed.Specifically, the method may include: along institute
The side wall deposition protective layer of grid line separate slot GH is stated, the protective layer at least covers the surface of the underlying structure, and the protection
Layer is at least covered on groove between the side-walls and the metal gate layers towards the grid line separate slot of the metal gates 263
The end towards the grid line separate slot GH of LT.In one embodiment, the protective layer material includes SiO2.Implement in the present invention
In example, due to depositing operation feature, step coverage rate is poor during the deposition process for the protective layer, therefore the protective layer can be only
It is deposited between the Metal gate layer in groove LT, and is first sealed on the top of grid line separate slot GH on a small quantity；So that the metal
The end towards the grid line separate slot GH of groove LT is capped between grid layer, and between the metal gate layers groove LT inside
Remain with air gap.
As shown in Figure 10 a, in an embodiment of the present invention, it is protected using described in chemical vapor deposition (CVD) process deposits
Layer 28；After depositing protective layer 28, mask layer is formed on the surface of the underlying structure, the mask layer has opening, described
Opening exposes the grid line separate slot GH and the part protective layer 28；Along the opening, to the grid line separate slot GH side wall
On 28 side wall of protective layer and the protective layer 28 of the bottom grid line separate slot GH perform etching so that the metal gates 263
The side-walls and the metal gate layers towards the grid line separate slot GH between groove LT towards the grid line separate slot GH's
End, which is formed, has certain thickness protective layer 28.In one embodiment, it is also removed in the etching technics in the residue
First insulation material layer 214 in heart district domain.
As shown in fig. lob, in an alternative embodiment of the invention, using atomic layer deposition (ALD) process deposits, along the grid
The side wall Direct precipitation of line separate slot GH has certain thickness protective layer so that the metal gates 263 towards the grid line
The end towards the grid line separate slot GH of groove LT forms and has centainly between the side-walls of separate slot and the metal gate layers
The protective layer 28 of thickness.It in one embodiment, further include not formed in the grid line separate slot GH after depositing protective layer 28
The remaining central area of the protective layer 28 executes the step of etching technics, and the etching technics eliminates the remaining center
The first insulation material layer 214 in domain.In the present embodiment, since atom layer deposition process can accurately control the thin of deposition
Film thickness, and there is excellent deposition uniformity and consistency；Therefore Direct precipitation may be implemented with certain thickness protection
Layer.In addition, the protective layer 28 can be suitably thinned in etching removal part first insulation material layer 214.
In the above-described embodiments, first insulation material layer 214 in the central area grid line separate slot GH is removed,
The upper surface of doped region 25 described in the semiconductor substrate 20 can be made to be exposed.
As shown in Figure 10 a-10b, in embodiments of the present invention, groove LT is except the end between the metal gate layers
Region can also be covered with the protective layer 28, the unfilled region of protective layer 28 thus forms institute in the region
State air gap.The protective layer 28 is for example covered at the upper and lower surfaces of the gate structure 26.In addition, metal described in top
Grid can be covered with the protective layer 28.
In an embodiment of the present invention, definition is edge channels structure near the channel structure of the grid line separate slot GH；
The end of groove LT is filled between the metal gate layers of the side towards the grid line separate slot GH of the edge channels structure
State protective layer 28；Shape in groove LT between the metal gate layers of the side far from the grid line separate slot GH of the edge channels structure
At there is the air gap.Further, the metal gate layers of the side towards the grid line separate slot GH of the edge channels structure
Between groove LT filled up by the protective layer 28.
Specifically, Fig. 4 of the present invention to Figure 11 illustrates only each one of a grid line separate slot GH and its two sides in device
A channel structure；However, three-dimensional storage part can also include: several spaced ditches across the metal gate stack
Road structure.Figure 12 is please referred to, includes several spaced channel through-hole CH in the two sides of grid line separate slot GH, it is logical in the channel
Channel structure is formed in the CH of hole；It will be near the channel structure (channel structure in figure in dotted line frame) of the grid line separate slot GH
It is defined as edge channels structure；Further combined with Figure 10 a-10b, the edge channels structure towards the grid line separate slot GH's
The end of groove LT is filled with the protective layer between the metal gate layers of side, and can be filled up by the protective layer 28；And
The gas is formed in groove LT between the metal gate layers of the side far from the grid line separate slot GH of the edge channels structure
Gap.
Next, Figure 11 is please referred to, after being formed with the certain thickness protective layer 28, in the grid line separate slot
Conductive material is filled in the remaining central area of GH, forms array common source (ACS) 29.
Specifically, the conductive material can be formed by electrode material commonly used in the art, for example, tungsten, nickel or tungsten
Nickel alloy etc..In one embodiment, can by PVD, CVD, plating, without one of modes such as electric-type plating or combinations thereof come
Form the conductive material.The ACS is contacted with the source region of memory device, thus by the source region and external circuit
Between formed be conductively connected.
In this way, completing the preparation method of three-dimensional storage part provided in an embodiment of the present invention.In the present embodiment, described
Three-dimensional storage part is specifically as follows three dimensional NAND memory.
Based on the above method, and Figure 11 is combined, the embodiment of the invention also provides a kind of three-dimensional storage parts 200.
The three-dimensional storage part 200 includes:
Semiconductor substrate 20 is located at the bottom device；
Metal gate stack, including the spaced metal gates 263 of several layers；The metal gates 263 are layered in institute
It states in semiconductor substrate 20；
Groove LT between metal gate layers, between adjacent two layers metal gates 263；In one embodiment, the metal
Groove LT is located between the metal gates 263 of metal gates described in second bottom or more between grid layer.
Protective layer 28 at least covers the end of groove LT between the metal gate layers and surrounds air gap.In one embodiment,
The protective layer is the silica that atom layer deposition process is formed.In another embodiment, the protective layer is chemical vapor deposition
The silica that product technique is formed.Further, 28 material of protective layer may include silica.
In an embodiment of the present invention, the device 200 further include: grid line separate slot GH is located at the semiconductor substrate 20
On the metal gates 263 in；As shown in figure 11, the grid line separate slot GH passes through the metal gate stack；Figure 11 only shows
A grid line separate slot GH is gone out, but in embodiments of the present invention, the grid line separate slot GH may include several.
In an embodiment of the present invention, the protective layer 28, positioned at the metal gates 263 towards the grid line separate slot
The end towards the grid line separate slot GH of groove LT between the side-walls of GH and the metal gate layers.The grid line separate slot GH
Side wall can be covered with the protective layer 28；Side-walls of the protective layer 28 in the grid line separate slot GH can have centainly
Thickness, such as the protective layer 28 the side towards the center grid line separate slot GH have flat side surface.Such as Figure 11 institute
Show, the metal gate layers interval trough LT is at least filled with the protective layer 28, institute in the end close to the grid line separate slot GH
Region of the groove LT except the end forms air gap between stating metal gate layers.In addition, groove LT between the metal gate layers
Region except the end can also be covered with the protective layer 28, and the unfilled region of protective layer 28 thus exists
The region forms the air gap.The protective layer 28 is for example covered at the upper and lower surfaces of the gate structure 26.
In an embodiment of the present invention, metal gates 263 described in top can be covered with the protective layer 28.
As shown in figure 12, in an embodiment of the present invention, definition is side near the channel structure of the grid line separate slot GH
Edge channel structure (channel structure in figure in dotted line frame)；The side towards the grid line separate slot GH of the edge channels structure
Metal gate layers between groove LT end be filled with the protective layer 28；The edge channels structure far from the grid line every
The air gap is formed between the metal gate layers of the side of slot GH in groove LT.Further, the court of the edge channels structure
It is filled up to groove LT between the metal gate layers of the side of the grid line separate slot GH by the protective layer 28.
In an embodiment of the present invention, have first between metal gates described in metal gates and second bottom described in the bottom
Material layer 211.In an embodiment of the present invention, the device 200 further include: array common source 29 is located at the grid line separate slot
In GH.
In addition, it is necessary to explanation, structure and the three-dimensional storage part of three-dimensional storage part provided by the above embodiment
Preparation method embodiment belongs to same design, and specific implementation process and other detailed constructions are detailed in embodiment of the method, here
It repeats no more.It, in the absence of conflict, can be in any combination between technical solution documented by the embodiment of the present invention.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention, it is all
Made any modifications, equivalent replacements, and improvements etc. within the spirit and principles in the present invention, should be included in protection of the invention
Within the scope of.
Claims (28)
1. a kind of preparation method of three-dimensional storage part, which is characterized in that the described method comprises the following steps:
Underlying structure is provided, the underlying structure includes the metal gates being alternately stacked and first material layer；
The first material layer between the metal gates is removed, groove between metal gate layers is formed；
Protective layer is formed, the protective layer at least fills the end of groove between the metal gate layers, and the protective layer makes
Trench interiors remain with air gap between the metal gate layers.
2. the method according to claim 1, wherein the protective layer covers groove between the metal gate layers
Region except end, the unfilled region of protective layer thus form the air gap in the region.
3. the method according to claim 1, wherein metal gates described in protective layer covering top.
4. the method according to claim 1, wherein the step of offer underlying structure, specifically includes:
Semiconductor substrate is provided, is formed folded by what first material layer and second material layer were alternately stacked on the semiconductor substrate
Layer structure；
The laminated construction is etched, grid line separate slot, the upper surface of the grid line separate slot exposure semiconductor substrate are formed；
The second material layer is removed, gate trench is formed；
Metal gates filling is executed in the gate trench, being formed includes the metal gates being alternately stacked and first material layer
The underlying structure.
5. the method according to claim 1, wherein the first material layer between the removal metal gates is specific
Include:
Remove the first material layer of metal gates described in second bottom or more, metal described in metal gates described in the bottom and second bottom
First material layer between grid is retained.
6. according to the method described in claim 4, it is characterized in that, the method for forming the protective layer includes:
Along the side wall deposition protective layer of the grid line separate slot, the protective layer at least covers the surface of the underlying structure, and institute
State protective layer be at least covered on the metal gates side-walls towards the grid line separate slot and the metal gates interlayer
The end towards the grid line separate slot of groove.
7. the method according to claim 1, wherein the protective layer material includes silica.
8. according to the method described in claim 6, it is characterized in that, depositing the protective layer using chemical vapor deposition process；
After depositing protective layer, the method also includes:
Form mask layer on the surface of the underlying structure, the mask layer has an opening, the opening exposing grid line every
Slot and the part protective layer；
Protection along the opening, to protective layer side wall and grid line separate slot bottom on the grid line separate slot side wall
Layer performs etching, so that groove between the side-walls and the metal gate layers towards the grid line separate slot of the metal gates
Towards the grid line separate slot end formed have certain thickness protective layer.
9. according to the method described in claim 6, it is characterized in that, deposited using atom layer deposition process, along the grid line every
The side wall deposition of slot have certain thickness protective layer so that the side-walls towards the grid line separate slot of the metal gates with
And the end towards the grid line separate slot of groove is formed with certain thickness protective layer between the metal gate layers.
10. method according to claim 8 or claim 9, which is characterized in that formed have the certain thickness protective layer it
Afterwards, the method also includes: fill conductive material in the grid line separate slot, form array common source.
11. described according to the method described in claim 6, it is characterized in that, the underlying structure further includes several channel structures
Channel structure passes through the metal gates and is alternatively arranged；
Definition is edge channels structure near the channel structure of the grid line separate slot；The protective layer is at least filled in the side
The end of groove between the metal gate layers of the side towards the grid line separate slot of edge channel structure；The edge channels structure
The air gap is remained in groove between the metal gate layers of side far from the grid line separate slot.
12. according to the method for claim 11, which is characterized in that the protective layer fills up the court of the edge channels structure
To groove between the metal gate layers of the side of the grid line separate slot.
13. a kind of three-dimensional storage part, which is characterized in that the device includes:
Metal gate stack, including the spaced metal gates of several layers；
Groove between metal gate layers, between adjacent two layers metal gates；
Protective layer at least covers the end of groove between the metal gate layers and surrounds air gap.
14. device according to claim 13, which is characterized in that the device further include:
Semiconductor substrate is located at the bottom device；
The metal gates are layered in the semiconductor substrate；Metal gate layers inter-drain slot position metal described in second bottom
Between metal gates more than grid.
15. device described in 3 or 14 according to claim 1, which is characterized in that described in metal gates described in the bottom and second bottom
There is first material layer between metal gates.
16. device according to claim 14, which is characterized in that the device further include:
Grid line separate slot, in the metal gates in the semiconductor substrate；
The protective layer, side-walls and the metal gates interlayer positioned at the metal gates towards the grid line separate slot
The end towards the grid line separate slot of groove.
17. device according to claim 13, which is characterized in that the protective layer material includes silica.
18. device according to claim 16, which is characterized in that the device further include:
Array common source is located in the grid line separate slot.
19. a kind of three-dimensional storage part, which is characterized in that the device includes:
Metal gate stack, including the spaced metal gates of several layers；
Groove between metal gate layers, between adjacent two layers metal gates；
Across several grid line separate slots of the metal gate stack, the metal gate layers interval trough is at least close to the grid line
Matcoveredn is filled in the end of separate slot, and region of the groove except the end forms air gap between the metal gate layers.
20. device according to claim 19, which is characterized in that groove is except the end between the metal gate layers
Region overlay have a protective layer, the unfilled region of protective layer thus forms the air gap in the region.
21. device according to claim 19, which is characterized in that metal gates described in top are covered with the protection
Layer.
22. device according to claim 19, which is characterized in that the side wall of the grid line separate slot is covered with the protection
Layer.
23. device according to claim 22, which is characterized in that further include: the array in the grid line separate slot is total
Source electrode.
24. device according to claim 19, which is characterized in that the protective layer is the oxygen that atom layer deposition process is formed
SiClx.
25. device according to claim 19, which is characterized in that the protective layer is what chemical vapor deposition process was formed
Silica.
26. device according to claim 19, which is characterized in that further include: be located at the bottom described in metal gates and time
First material layer between metal gates described in bottom.
27. 9 to 26 described in any item devices according to claim 1, which is characterized in that the three-dimensional storage part further include:
Across several spaced channel structures of the metal gate stack；
Definition is edge channels structure near the channel structure of the grid line separate slot；Described in the direction of the edge channels structure
The end of groove is filled with the protective layer between the metal gate layers of the side of grid line separate slot；The edge channels structure it is separate
The air gap is formed in groove between the metal gate layers of the side of the grid line separate slot.
28. device according to claim 27, which is characterized in that the edge channels structure towards the grid line separate slot
Side metal gate layers between groove filled up by the protective layer.
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| CN113161359A (en) * | 2021-01-04 | 2021-07-23 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing process thereof |
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