KR20160094827A - Semiconductor memory device and method of fabricating the same - Google Patents

Abstract

Provided is a stacking structure having gate electrode and insulation layers alternately stacked on a substrate. On the substrate, provided is a cell channel structure including a first semiconductor pattern connected to the substrate by penetrating the stacked structure and a first channel pattern arranged on the first semiconductor pattern and connected to the first semiconductor pattern. On the substrate, provided is a dummy vertical channel structure spaced apart from the stacked structure and including a second semiconductor pattern connected to the substrate and a second channel pattern arranged on the second semiconductor pattern and connected to the second semiconductor pattern. A first height from a surface of the substrate to an upper surface of the first semiconductor pattern is higher than a second height from the surface of the substrate to an upper surface of the second semiconductor pattern.

Description

TECHNICAL FIELD The present invention relates to a semiconductor memory device and a fabrication method thereof,

TECHNICAL FIELD The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a three-dimensional semiconductor memory device with improved reliability and integration, and a method of manufacturing the same.

It is required to increase the degree of integration of semiconductor devices in order to meet the excellent performance and low price required by consumers. Since the degree of integration of semiconductor devices is an important factor in determining the price of a product, an increased degree of integration is required in particular. Since the degree of integration of the conventional two-dimensional or planar semiconductor device is mainly determined by the area occupied by the unit memory cell, it is greatly influenced by the level of the fine pattern formation technique. However, the integration of the two-dimensional semiconductor device is increasing, but is still limited, because of the high-cost equipment required to miniaturize the pattern.

In order to overcome these limitations, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device with improved reliability and integration.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device with improved reliability and integration.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor memory device comprising: a laminated structure disposed on a substrate and having gate electrodes and insulating layers alternately repeatedly laminated; A cell channel structure including a first semiconductor pattern connected to the substrate and a first channel pattern disposed on the first semiconductor pattern and connected to the first semiconductor pattern and a second channel pattern formed on the substrate, And a first dummy channel structure including a second semiconductor pattern connected to the substrate and a second channel pattern disposed on the second semiconductor pattern and connected to the second semiconductor pattern. The first height from the surface of the substrate to the upper surface of the first semiconductor pattern may be greater than the second height from the surface of the substrate to the upper surface of the second semiconductor pattern.

According to some embodiments, the memory device may further include a bit line electrically connected to the cell channel structure.

According to some embodiments, the cell channel structure may further include a first information storage pattern disposed between the first channel pattern and the laminate structure. The first dummy channel structure may further include a second information storage pattern contacting the sidewalls of the second channel pattern. The first channel pattern and the second channel pattern may include the same material, and the first information storage pattern and the second information storage pattern may include the same material.

According to some embodiments, the substrate includes a cell region including a cell array region and a connection region adjacent to the cell array region, a peripheral region spaced apart from the cell region, and a boundary region between the cell region and the peripheral region can do. The laminated structure may be disposed in the cell region and extend in a first direction, and may have an end of a step structure in the connection region.

According to some embodiments, the device may further include a mold insulation layer covering the end portion of the laminate structure and disposed on the substrate in the connection region, the boundary region, and the peripheral region. The first dummy channel structure may penetrate the mold insulating layer and connect to the substrate.

According to some embodiments, a third semiconductor pattern penetrating the mold insulating layer and the end portion of the laminated structure in the connection region and connected to the substrate, and a third semiconductor pattern connected to the third semiconductor pattern, The second dummy channel structure may include a third channel pattern disposed on the second dummy channel structure.

According to some embodiments, the first dummy channel structure may have a circular shape, an elliptical shape, or a bar shape in a plan view.

According to some embodiments, the memory device may further include peripheral circuitry disposed on the substrate of the peripheral region. The peripheral circuit device may include a gate insulating film, a gate electrode, and a source / drain region.

According to some embodiments, the memory device may further include a gate oxide film disposed on a sidewall of the first semiconductor pattern. The gate oxide film may not be disposed on the sidewall of the second semiconductor pattern.

A semiconductor memory device according to embodiments of the present invention includes a cell area including a cell array area and a connection area, a peripheral area spaced apart from the cell area, and a boundary area between the connection area and the peripheral area Stacked structures disposed on the substrate in the cell region in a first direction and spaced apart from each other in the first direction, the stacked structures each including gate electrodes and insulating films alternately stacked at an end of a step structure in the connection region, Each of said first channel patterns being connected to said first semiconductor pattern, said first channel pattern being disposed on said first semiconductor pattern and being connected to said substrate, , A second semiconductor layer (10), which penetrates each end of the stacked structures in the connection region And a second semiconductor pattern disposed on the second semiconductor pattern and including a second channel pattern connected to the second semiconductor pattern, a third semiconductor pattern connected to the substrate in the boundary region, And a second dummy channel structure disposed on the semiconductor pattern and including a third channel pattern connected to the third semiconductor pattern.

According to some embodiments, each of the first semiconductor patterns has a first height from a surface of the substrate to an upper surface of each of the first semiconductor patterns, and the second semiconductor patterns have a first height Wherein the second semiconductor pattern has a second height from the surface of the substrate to an upper surface of the first sub semiconductor pattern, The third height may be less than the first height and the second height may be less than the first height.

According to some embodiments, the second semiconductor patterns include a second sub-semiconductor pattern that is closest to the first semiconductor patterns, and the second sub-semiconductor pattern includes a portion of the second sub- And the fourth height may be substantially the same as the first height.

According to some embodiments, the memory device may further include a peripheral circuit element disposed on the substrate of the peripheral region, and a peripheral protective layer covering the peripheral circuit element. The peripheral circuit device may include a gate insulating film, a gate electrode, and a source / drain region.

According to some embodiments, the memory device may further include a mold insulation layer covering the peripheral protective layer, the substrate in the boundary region, and the end of the laminate structure. The first and second dummy channel structures may pass through the mold insulation layer.

According to some embodiments, each of the cell channel structures may further include a first information storage pattern in contact with a sidewall of the first channel pattern. Each of the first dummy channel structures may further include a second information storage pattern in contact with a side wall of the second channel pattern. The second dummy channel structure may further include a third information storage pattern contacting the sidewalls of the third channel pattern. Wherein the first channel pattern, the second channel pattern, and the third channel pattern include the same material, and the first information storage pattern, the second information storage pattern, and the third information storage pattern include the same material .

According to some embodiments, the second dummy channel structure may be provided in plurality. Each of the second dummy channel structures may have a circular or elliptical shape in a plan view and may be arranged along the first direction.

According to some embodiments, the second dummy channel structure may have a bar shape in plan view and may extend along the first direction.

A semiconductor memory device according to embodiments of the present invention includes a laminated structure disposed on a substrate and having gate electrodes and insulating layers alternately repeatedly laminated, a first semiconductor pattern extending through the laminated structure and connected to the substrate, And a first channel pattern disposed on the first semiconductor pattern and connected to the first semiconductor pattern, a second semiconductor pattern disposed on the substrate and spaced apart from the stacked structure and connected to the substrate, And a second channel pattern disposed on the second semiconductor pattern and connected to the second semiconductor pattern, and a gate oxide film disposed on a sidewall of the first semiconductor pattern. The gate oxide film may not be disposed on the sidewall of the second semiconductor pattern.

According to some embodiments, a part of the side wall of the first semiconductor pattern may be concave, and the side wall of the second semiconductor pattern may not be concave.

According to some embodiments, the first height from the surface of the substrate to the top surface of the first semiconductor pattern may be greater than the second height from the surface of the substrate to the top surface of the second semiconductor pattern.

A method of manufacturing a semiconductor memory device according to embodiments of the present invention includes providing a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, A first semiconductor pattern which forms a laminated structure in which gate electrodes and insulating layers are alternately repeatedly laminated, penetrates the laminated structure, and is connected to the substrate, and a second semiconductor pattern which is disposed on the first semiconductor pattern, Forming a cell channel structure including a first channel pattern connected to a semiconductor pattern, forming a mold insulating layer on the substrate in the peripheral region and the boundary region, and separating the mold insulating layer A second semiconductor pattern which penetrates through the first semiconductor pattern and connects to the substrate, and a second semiconductor pattern which is disposed on the second semiconductor pattern, Board may form a first dummy channel structure including the pattern. The first height from the surface of the substrate to the upper surface of the first semiconductor pattern may be greater than the second height from the surface of the substrate to the upper surface of the second semiconductor pattern.

 A manufacturing method of a semiconductor memory device according to embodiments of the present invention includes a cell region including a cell array region and a connection region, a peripheral region separated from the cell region, a boundary region between the connection region and the peripheral region, Forming a mold structure including alternately stacked insulating films and sacrificial films on a substrate of the cell region, covering a part of the mold structure, and forming the connection region, the boundary region, And forming a mold insulating layer on the substrate in the peripheral region, a first semiconductor pattern penetrating the mold structure on the cell array region and connected to the substrate, and a second semiconductor pattern disposed on the first semiconductor pattern, Forming a cell channel structure including a first channel pattern to be connected to a pattern, Forming first dummy channel structures each including a second semiconductor pattern connected to the substrate and a second channel pattern disposed on the second semiconductor pattern and connected to the second semiconductor pattern, A third semiconductor pattern penetrating the mold insulating layer in the boundary region and connected to the substrate, and a third channel pattern disposed on the third semiconductor pattern and connected to the third semiconductor pattern, . ≪ / RTI >

A semiconductor memory device according to embodiments of the present invention includes a substrate including a cell region including a cell array region and a connection region and a peripheral region separated from the cell region, A first semiconductor pattern having an end of a stepped structure in the connection region and passing through the stacked structure in which gate electrodes and insulating layers are alternately repeatedly stacked, a first semiconductor pattern connected to the substrate, And a first channel pattern connected to the first semiconductor pattern, and a second semiconductor pattern penetrating an end portion of the laminated structure in the connection region and connected to the substrate, And a second channel pattern disposed on the first semiconductor pattern and connected to the second semiconductor pattern. Wherein the first semiconductor pattern has a first height from the substrate to an upper surface of the first semiconductor pattern and the second semiconductor patterns include a sub semiconductor pattern disposed furthest from the first semiconductor pattern, The pattern may have a second height from the substrate to an upper surface of the sub-semiconductor pattern, and the second height may be less than the first height.

According to embodiments of the present invention, the semiconductor memory device may include a cell region including a cell array region and a connection region, a peripheral region, and a boundary region between the cell region and the peripheral region. The first semiconductor patterns of the cell channel structures disposed in the cell array region, the second semiconductor patterns of the first dummy channel structure disposed in the connection region, and the third semiconductor pattern of the second dummy vertical channel structure disposed in the boundary region, Epitaxial growth method. The influence of the outgassing of the impurities from the mold insulating layer on the epitaxial growth of the second semiconductor pattern close to the third semiconductor pattern can be weakened. Thus, the upper surface of the second semiconductor pattern close to the boundary region is formed to be higher than the upper surface of the lowermost gate electrode, and the gate oxide film can be uniformly formed on the side surface of the second semiconductor pattern. As a result, since insulation between the second semiconductor pattern and the gate electrode is ensured, leakage current phenomenon through the second semiconductor pattern is prevented, and a highly reliable memory semiconductor device can be realized.

1 is a schematic plan view of a semiconductor memory device according to embodiments of the present invention.
FIGS. 2A to 2C are top views of a semiconductor memory device according to embodiments of the present invention, and are enlarged views of the AR portion of FIG. 1. FIG.
3 to 5 are sectional views showing a semiconductor memory device according to embodiments of the technical idea of the present invention, wherein FIG. 3 is a sectional view taken along the line I-I 'of FIG. 2, Sectional views taken along line II-II 'of FIG.
Figs. 6A to 6C are enlarged views of portions A1, A2, and A3 in Fig. 3, respectively.
7A to 7D are schematic plan views of a semiconductor memory device according to embodiments of the technical idea of the present invention.
FIGS. 8A to 18A and FIGS. 8B to 18B are views for explaining a method of manufacturing a semiconductor memory device according to an embodiment of the technical idea of the present invention. FIGS. 8A to 18A correspond to line I-I ' And Figs. 8B to 18B are cross-sectional views corresponding to the line II-II 'in Fig.
Figs. 19A to 19C are enlarged views of B1 in Fig. 12A, B2 in Fig. 12B, and B3 in Fig. 12B.
20 is a schematic block diagram illustrating a memory system including a semiconductor memory device according to embodiments of the present invention;
21 is a schematic block diagram illustrating an electronic system including a semiconductor memory device according to embodiments of the present invention;

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. Also, in this specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate, or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations according to the technical idea of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a schematic plan view of a semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 1, a cell region CR may be disposed at the center of the semiconductor memory device. The cell region CR may include a cell array region CAA and a connection region CTA at the edge of the cell array region CAA. The cell array region CAA may comprise memory cells arranged in an array.

In the connection region (CTA), gate contacts connecting with the gate electrodes (or word lines) of the memory cells may be arranged. In the periphery of the semiconductor memory device, a peripheral region PR may be disposed to surround the cell region CR. Peripheral circuits (e.g., row decoders, sense amplifiers, etc.) for controlling the memory cells may be disposed in the peripheral region PR. A boundary region BR may be provided between the cell region CR and the peripheral region PR.

FIGS. 2A to 2C are top views of a semiconductor memory device according to embodiments of the present invention, and are enlarged views of the AR portion of FIG. 1. FIG. FIGS. 3 to 5 are cross-sectional views illustrating a semiconductor memory device according to embodiments of the present invention. FIG. 3 is a cross-sectional view taken along the line I-I 'of FIG. 2A, Sectional views taken along line II-II 'of FIG. Figs. 6A to 6C are enlarged views of A1 in Fig. 3, A2 in Fig. 4, and A3 in Fig. 4, respectively. 7A to 7D are schematic plan views of a semiconductor memory device according to embodiments of the technical idea of the present invention.

Referring to FIGS. 2A, 3, and 5, a semiconductor memory device according to embodiments of the present invention includes stacked structures 30 disposed on a substrate 100, stacked structures 30 A common source region 152 disposed in the substrate 100 between the stacked structures 30 and a first source region 152 disposed between the cell channel structures 200a and the first and second dummy channels 200a, Structures 200b and 200c, and at least one peripheral circuit element PT.

The substrate 100 includes a cell region CR including a cell array region CAA and a connecting region CTA adjacent to the cell array region CAA, a peripheral region PR spaced apart from the cell region PR, And a boundary region BR between the region CR and the peripheral region PR.

The substrate 100 may comprise a semiconductor material. For example, the substrate 100 may be a silicon (Si) monocrystalline substrate, a germanium (Ge) monocrystalline substrate, or a silicon-germanium (SiGe) monocrystalline substrate. According to some embodiments, the substrate 100 may be a Semiconductor on Insulator (SOI) substrate. For example, the substrate 100 may include a semiconductor active layer (e.g., a silicon layer, a silicon-germanium layer, or a germanium layer) disposed on an insulating layer that protects the transistors provided on the semiconductor substrate. The substrate 100 may be, for example, a P-type semiconductor substrate, but is not limited thereto. The substrate 100 may include a well region (not shown).

At least one peripheral circuit element PT may be disposed in the peripheral region PR. The peripheral circuit element PT includes a peripheral gate insulating film 101, a peripheral gate electrode 103 on the peripheral gate insulating film 101, and a source / drain region 107 adjacent to the sidewalls of the peripheral gate electrode 103 . The peripheral gate insulating film 101 is disposed on the substrate 100, and may include an oxide film, a high-k film, and / or a combination thereof. The peripheral gate electrode 103 may be formed of a material such as silicon (e.g., polysilicon), metal silicide (e.g., tungsten silicide (WSi), nickel silicide (NiSi), cobalt silicide (CoSi) (TiSi), tantalum silicide (TaSi)), or a metal (e.g., tungsten or aluminum), and / or combinations thereof. A peripheral gate spacer 105 may be disposed on the sidewalls of the peripheral gate electrode 103. The source / drain region 107 is disposed in the substrate 100 and may include an N-type impurity (for example, phosphorus (P)) or a P-type impurity (for example, boron (B) . The peripheral protection layer 109 covering the peripheral circuit element PT may be disposed on the substrate 100. [ The peripheral protection layer 109 may include a silicon oxide film or a silicon nitride film. The peripheral circuit element PT may comprise, for example, a high voltage or a low voltage transistor.

The stacked structures 30 may be disposed in the cell region CR. For example, each of the stacked structures 30 may extend from the cell region CAA to the connection region CTA. Each of the stacked structures 30 may extend along a first direction D1 parallel to the surface of the substrate 100. [ The stacked structures 30 may be arranged separately from each other in a second direction D2 parallel to the surface of the substrate 100 and perpendicular to the first direction D1. For example, the stacked structures 30 may be separated from each other in the second direction D2 by the trenches 150 extending in the first direction D1.

Each of the stacked structures 30 may include gate electrodes GE and insulating films 110 alternately and repeatedly stacked on the substrate 100. [ Some of the insulating films 110 may be thicker or thinner than the other insulating films 110. For example, the thickness of the lowermost insulating film 110-1 may be thinner than that of the other insulating films 110. [ For example, the second insulating film 110-2 and the uppermost insulating film 110-3 from the substrate 100 may be thicker than the other insulating films 110. [ Each of the insulating films 110 may include, for example, silicon oxide.

Each of the gate electrodes GE may include a conductive film. For example, each of the gate electrodes GE may be a semiconductor film (for example, a silicon film doped with an impurity), a metal silicide film (For example, a titanium nitride film, a tungsten nitride film, or a tantalum nitride film), a metal film (for example, tungsten silicide film, tungsten silicide film, tungsten silicide film or tantalum silicide film) A nickel film, a cobalt film, a titanium film, or a tantalum film) and / or a combination film thereof.

The semiconductor memory device may be a three-dimensional memory device. For example, the semiconductor memory device may be a 3D NAND flash memory device. Accordingly, the gate electrodes GE can be used as the control gate electrodes of the memory cells. For example, gate electrodes GE2 between the uppermost gate electrode GE3 and the lowermost gate electrode GE1 may be used as control gate electrodes (e.g., word lines). Gate electrodes GE2 may be combined with the cell channel structures 200a to form memory cells. Thus, in the cell array region CAA of the substrate 100, vertical memory cell strings including memory cells arranged vertically can be provided. The bottom and top gate electrodes GE1 and GE3 may be used as the gate electrodes of the select transistors SST and GST. For example, the gate electrode GE3 of the uppermost layer is used as the gate electrode of the string selection transistor SST which controls the electrical connection between the bit line BL and the cell channel structures 200a, and the gate electrode GE1 of the lowermost layer May be used as the gate electrode of the ground selection transistor GST which controls the electrical connection between the common source region 152 and the cell channel structures 200a.

Each of the laminate structures 30 may have an end 30e of a stepwise structure in the connection area CTA. For example, in the connection region CTA, each of the gate electrodes GE may have a pad portion (GEP) extending from the cell array region CAA in the first direction D1. For example, in the connection area CTA, the vertical height of each of the laminated structures 30 can be made smaller stepwise as it approaches the boundary area BR. A mold insulating layer 118 covering the laminate structures 30 may be disposed in the connection region CTA, the boundary region BR, and the peripheral circuit region PR. For example, the mold insulating layer 118 may cover the end portions 30e (e.g., pad portions (GEP) of the gate electrodes GE) of the laminated structures 30. [ The mold insulating layer 118 can be in contact with the substrate 100 in the boundary region BR. The mold insulating layer 118 may be disposed on the peripheral protective layer 109. The mold insulating layer 118 may cover the peripheral circuit element PT. The mold insulating layer 118 may include an oxide film or a low-K dielctric film.

The cell channel structures 200a may be connected to the substrate 100 through each of the stacked structures 30. That is, the cell channel structures 200a are connected to the substrate 100 and extend in a third direction D3 perpendicular to the surface of the substrate 100, and may be surrounded by each of the stacked structures 30 have. For example, the cell channel structures 200a may be surrounded by respective gate electrodes GE of the stacked structures 30. For example, In plan view, the cell channel structures 200a may be arranged along a first direction D1 and a second direction D2. For example, as shown in FIG. 2A, the cell channel structures 200a are arranged in a zigzag fashion along the first direction D1 adjacent to each other in the second direction D2. The rows of columns 200a may be repeatedly arranged along the second direction D2. That is, the rows of the pair of cell channel structures 200a may pass through each of the stacked structures 30. According to some embodiments, the rows of one cell channel structures 200a arranged in a staggered fashion in the first direction D1 are repeatedly arranged along the second direction D2, or the rows of the cell channel structures 200a arranged in the second direction D2 The rows of three or more cell channel structures 200a adjacent to each other in the first direction D1 and arranged in a zigzag manner in the first direction D1 may be repeatedly arranged along the second direction D2.

Each of the cell channel structures 200a may include a first semiconductor pattern 126a, a first channel pattern 140a, and a first information storage pattern 130a. Each of the cell structures 200a may further include a first buried insulation pattern 144a. The first information storage pattern 130a, the first channel pattern 140a and the first buried insulation pattern 144a may be disposed on the first semiconductor pattern 126a.

The first semiconductor pattern 126a may be directly connected to the substrate 100 and may extend into the substrate 100. For example, a portion of the first semiconductor pattern 126a may be embedded within the substrate 100, and another portion of the first semiconductor pattern 126a may have a pillar shape protruding vertically on the substrate 100. The first semiconductor pattern 126a may have a first height T1 which is the maximum height from the surface of the substrate 100 to the top surface of the first semiconductor pattern 126a. That is, the first height T1 may be larger than the thickness of the lowermost gate electrode GE1. For example, the upper surface of the first semiconductor pattern 126a may be located at a higher level than the upper surface of the lowermost gate electrode GE1. The upper surface of the first semiconductor pattern 126a may be located at a lower level than the upper surface of the second insulating film 110-2 from the substrate 100. [ The first semiconductor pattern 126a may comprise silicon (Si). For example, the first semiconductor pattern 126a may be an epitaxial pattern comprising monocrystalline silicon or polysilicon. According to some embodiments, the first semiconductor pattern 126a may comprise at least one of germanium (Ge), silicon germanium (SiGe), III-V semiconductor compound, Or a Group II-VI semiconductor compound. The first semiconductor pattern 126a may be an undoped pattern or may be a pattern doped with the same impurity as the conductivity type of the substrate 100. [

A gate oxide film 156 may be disposed on the sidewalls of the first semiconductor pattern 126a. The gate oxide film 156 may be disposed between the lowermost gate electrode GE1 and the first semiconductor pattern 126a. The gate oxide film 156 may include a silicon oxide film (for example, a thermal oxide film). The gate oxide film 156 may have a bulging shape. The first semiconductor pattern 126a may have a concave side wall 126as. For example, a part of the side wall 126as of the first semiconductor pattern 126a may be recessed by the gate oxide film 156. [

The first channel pattern 140a may be disposed on the first semiconductor pattern 126a and extend in the third direction D3. The first channel pattern 140a may be connected to the first semiconductor pattern 126a. The first channel pattern 140a may be disposed between the first information storage pattern 130a and the first buried insulation pattern 144a. The top of the first channel pattern 140a may be in an opened form. According to some embodiments, the first channel pattern 140a may have a top open and a bottom open, a hollow cylinder, or a macaroni form. According to some embodiments, the first channel pattern 140a may be in the form of a cylinder. In this case, the cell channel structure 200a may not include the first buried insulation pattern 144a. The first channel pattern 140a may include a polycrystalline semiconductor material, an amorphous semiconductor material, or a single crystal semiconductor material. The first channel pattern 140a may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide One can be included. The first channel pattern 140a may be an impurity-doped semiconductor material or may comprise a semiconductor material doped with the same impurity as the conductivity type of the substrate 100. [

The first information storage pattern 130a may be disposed between the laminate structure 30 and the first channel pattern 140a. The first information storage pattern 130a may be disposed on the first semiconductor substrate 126a and extend in the third direction D3. The first information storage pattern 130a may have an open top shape and a bottom shape. The first information storage pattern 130a may include a thin film for storing data. For example, the first data storage pattern 130a may be configured such that data stored therein has a voltage difference between the cell channel structure 200a and the gate electrodes GE or a Fowler-Nordheim tunneling effect But the present invention is not limited thereto. According to some embodiments, the first information storage pattern 130a is a thin film (e.g., a thin film for a phase change memory device or a thin film for a variable resistance memory device) capable of storing data based on another operating principle, .

6A, the first data storage pattern 130 includes a first blocking insulating layer 132 adjacent to the gate electrodes GE, a tunnel insulating layer 136 in contact with the first channel pattern 140a, And a charge storage layer 134 between the charge storage layer 134 and the charge storage layer 134. The tunnel insulating film 136 may be, for example, a silicon oxide film. The charge storage film 134 may be an insulating film including a trap insulating film or conductive nano dots. The trap insulating film may include, for example, silicon nitride. The first blocking insulating film 132 may include a silicon oxide film and / or a high-k film (for example, an aluminum oxide film or a hafnium oxide film). The first blocking insulating film 132 may be composed of a single film or a plurality of thin films. According to some embodiments, the first blocking insulating film 132 may be a single film including a silicon oxide film. According to other embodiments, the first blocking insulating film 132 may include a plurality of thin films including an aluminum oxide film and / or a hafnium oxide film.

A second blocking insulating film 158 may be further disposed between the gate electrodes GE and the cell channel structure 200a and between the insulating films 110 and the gate electrodes GE. For example, the second blocking insulating film 158 may include a portion interposed between the gate electrodes GE and the cell channel structure 200a, and a portion covering the top and bottom surfaces of the gate electrodes GE . The second blocking insulating film 158 may be composed of a single film or a plurality of thin films. The second blocking insulating film 158 may include a high-k film (for example, an aluminum oxide film and / or a hafnium oxide film). According to some embodiments, the second blocking insulating film 158 may not be formed.

The first buried insulating pattern 144a may be disposed on the first semiconductor pattern 126a and extend in the third direction D3. The first buried insulation pattern 144a may be arranged to fill the space provided by the first channel pattern 140a. The first buried insulating pattern 144a may include a silicon oxide film or a silicon nitride film.

The first dummy channel structures 200b may be disposed in the connection area CAA and the second dummy channel structures 200c may be disposed in the boundary area BR. The first and second dummy channel structures 200b and 200c are inactive channel structures 200b and 200c.

The first dummy channel structures 200b may be disposed on the substrate 100 through each of the mold insulating layer 118 and the laminated structures 30. [ Each of the first dummy channel structures 200b may pass through each stepped end 30e of the stacked structures 30. [ For example, each of the first dummy channel structures 200b may include at least one gate electrode GE disposed below the end of the pad portion (GEP) of the corresponding gate electrodes GE, One insulating film 110, and the mold insulating layer 118 disposed thereon.

According to some embodiments, the first dummy channel structure 200b closest to the cell array region CAA includes a mold insulating layer 118, an end of the pad portion (GEP) of the top layer gate electrode GE3, And may be connected to the substrate 100 through the gate electrodes GE and the insulating films 110 of the substrate 100. [ The first dummy channel structure 200b disposed furthest from the cell array region CAA (or closest to the boundary region BR) includes a mold insulating layer 118, a second gate electrode GE2 The lowest layer gate electrode GE1, the second insulating film 110-2 from the substrate 100 and the lowermost insulating film 110-1 can be connected to the substrate 100 . According to other embodiments, the first dummy channel structure 200b closest to the boundary region BR includes the mold insulating layer 118, the end of the pad portion GEP of the lowermost gate electrode GE1, 110 - 1 and the substrate 100. The first dummy channel structures 200b may be arranged in two rows parallel to the first direction D1 as shown in FIG. 2A, but the first dummy channel structures 200b may be arranged in one row or three or more rows.

Each of the first dummy channel structures 200b may include a second semiconductor pattern 126b, a second channel pattern 140b, a second information storage pattern 130b, and a second buried insulation pattern 144b. have. The second information storage pattern 130b, the second channel pattern 140b and the second buried insulation pattern 144b may be disposed on the second semiconductor pattern 126b and extend in the third direction D3.

The second semiconductor pattern 126b is directly connected to the substrate 100 and may extend into the substrate 100. [ For example, a part of the second semiconductor pattern 126b may be embedded in the substrate 100, and another part of the second semiconductor pattern 126b may have a pillar shape protruding vertically on the substrate 100. [ According to some embodiments, a part of the second semiconductor patterns 126b (for example, the second semiconductor pattern 126b-1 closest to the boundary region BR) (100). ≪ / RTI > The second semiconductor pattern 126b may be disposed under the corresponding laminated structure 30. [

The upper surface of the second semiconductor pattern 126b may be located at a higher level than the upper surface of the lowermost gate electrode GE1. The upper surface of the second semiconductor pattern 126b may be located at a lower level than the upper surface of the second insulating film 110-2 from the substrate 100. [ The second semiconductor patterns 126b may include a first sub semiconductor pattern 126b-1 and a second sub semiconductor pattern 126b-2. The first sub semiconductor pattern 126b-1 is located closest to the boundary region BR (for example, the third semiconductor pattern 126c), and the cell array region CAA (for example, 126a). ≪ / RTI > The second sub semiconductor pattern 126b-2 may be closest to the cell array area CAA (for example, the first semiconductor pattern 126a). The first sub semiconductor pattern 126b-1 may have a second height T2 which is the maximum height from the surface of the substrate 100 to the top surface of the first sub semiconductor pattern 126b-1. The second sub semiconductor pattern 126b-2 may have a third height T3 which is the maximum height from the surface of the substrate 100 to the upper surface of the second sub semiconductor pattern 126b-2. The second and third heights T2 and T3 may be greater than the thickness of the bottom layer gate electrode GE1. The third height T3 may be substantially the same as the first height T1 of the first semiconductor pattern 126a. The second height T2 may be smaller than the first and third heights T1 and T3. The second semiconductor pattern 126b may include the same material as the first semiconductor pattern 126a.

The gate oxide film 156 may be disposed on the sidewall of the second semiconductor pattern 126b. The gate oxide film 156 may be disposed between the lowermost gate electrode GE1 and the second semiconductor pattern 126b. The gate oxide film 156 may include an oxide film (for example, a thermal oxide film). The gate oxide film 156 may have a bulging shape. The second semiconductor pattern 126b may have a partially recessed side wall 126bs. For example, a part of the side wall 126bs of the second semiconductor pattern 126b may be recessed by the gate oxide film 156. [

As a result, the upper surface of the first sub semiconductor pattern 126b-1 of the second semiconductor pattern 126b may be located at a higher level than the upper surface of the lowermost gate electrode GE1. The gate oxide film 156 may be uniformly formed on the sidewall of the first sub semiconductor pattern 126b-1 so that the insulation characteristics between the bottom gate electrode GE1 and the first sub semiconductor pattern 126b can be secured. Accordingly, a leak current phenomenon through the second semiconductor pattern 126b is prevented, and a highly reliable memory semiconductor device can be realized.

And the second channel pattern 140b may be connected to the second semiconductor pattern 126b. The second channel pattern 140b may be disposed between the second information storage pattern 130b and the second buried insulation pattern 144b. The second panel pattern 140b has substantially the same shape as the first channel pattern 140a and may include substantially the same material. The second information storage pattern 130b may be disposed between the laminated structure 30 and the second channel pattern 140b.

The second information storage pattern 130b may include substantially the same material as the first information storage pattern 130a and may have substantially the same structure. 6B, the second information storage pattern 130b may include a first blocking insulating layer 132 adjacent to the gate electrodes GE, a tunnel insulating layer 136 contacting the second channel pattern 140b, ), And a charge storage layer 134 therebetween. One side of the first blocking insulating film 132 is adjacent to the gate electrode GE and the other side of the first blocking insulating film 132 is in contact with the mold insulating layer 118.

The second blocking insulating film 138 may be further disposed between the gate electrodes GE and the first dummy channel structure 200b and between the insulating films 110 and the gate electrodes GE. According to some embodiments, the second blocking insulating film 138 may not be formed.

The second buried insulating pattern 144b may be disposed on the second semiconductor pattern 126b and extend in the third direction D3. The second buried insulation pattern 144b may be arranged to fill the space provided by the second channel pattern 140b. The second buried insulating pattern 144b may include a silicon oxide film or a silicon nitride film.

The second dummy channel structures 200c may penetrate the mold insulation layer 118 in the boundary region BR. Each of the second dummy channel structures 200c may be connected to the substrate 100. [ Each of the second dummy channel structures 200c may have a circular or elliptical shape as shown in FIG. 2A in a plan view, or may have a bar shape as shown in FIG. 2B. Referring to FIGS. 2A and 2B, the second dummy channel structures 200c may be arranged in rows along a second direction D2 in plan view. For example, the second dummy channel structures 200c may be spaced apart from the stacked structures 30, and at least one adjacent to each of the stacked structures 30 may be disposed and heat in a second direction D2 Lt; / RTI > According to some embodiments, each of the second dummy channel structures 200c, as shown in FIG. 2C, has a circular or elliptical shape in plan view, and two rows parallel to the second direction D2 But may be arranged in three or more rows parallel to the second direction D2 without being limited thereto. 7A, each of the second dummy channel structures 200c has a bar shape and has a second direction D2 between the connection region CTA and the peripheral region PR As shown in FIG. For example, each of the second dummy channel structures 200c may be spaced apart from the stacking structures 30 in the first direction D1 and extend along the second direction D2. According to some embodiments, the second dummy channel structures 200c may surround the cell region CR, as shown in Figures 7B and 7C. For example, the second dummy channel structures 200c are arranged between the connection region CTA and the peripheral region PR along the second direction D2, and extend along the first direction D1 along the cell region CR ) And the peripheral region PR. According to some embodiments, as shown in FIG. 7D, the second dummy channel structure 200c may surround the cell region CR in a loop shape.

Each of the second dummy channel structures 200c may include a third semiconductor pattern 126c, a third channel pattern 140c, a third information storage pattern 130c, and a third buried insulation pattern 144c. have. The third information storage pattern 130c, the third channel pattern 140c and the third buried insulation pattern 144c may be disposed on the third semiconductor pattern 126c and extend in the third direction D3.

The third semiconductor pattern 126c is directly connected to the substrate 100 and may extend into the substrate 100. [ For example, a portion of the third semiconductor pattern 126c may be embedded in the substrate 100, and another portion of the third semiconductor pattern 126c may have a pillar shape protruding vertically on the substrate 100. According to some embodiments, the third semiconductor pattern 126c may extend deeper into the substrate 100 than the first semiconductor pattern 126a. The third semiconductor pattern 126c may have a fourth height T4 which is the maximum height from the surface of the substrate 100 to the top surface of the third semiconductor pattern 126c. The fourth height T4 may be smaller than the first height T1 of the first semiconductor pattern 126a and the second and third heights T2 and T3 of the second semiconductor pattern 126b. According to some embodiments, the fourth height T4 may be greater than the second height T2 and less than the first and third heights T1, T3, as shown in FIG. The third semiconductor pattern 126c may include the same material as the first semiconductor pattern 126a.

The gate oxide film 156 may not be formed on the sidewalls of the third semiconductor pattern 126c. Therefore, the third semiconductor pattern 126c may have a side wall 126cs having no concave portion. The side wall 126cs of the third semiconductor pattern 126c can directly contact the mold insulating layer 118. [

The upper surfaces of the first to third semiconductor patterns 126a, 126b, and 126c may have various shapes. For example, the upper surfaces of the first to third semiconductor patterns 126a, 126b, 126c may have a flat shape, an inclined shape with respect to the substrate 100, or a spiral shape.

And the third vertical channel pattern 140c may be connected to the third semiconductor pattern 126c. The third vertical channel pattern 140c may be disposed between the third information storage pattern 130c and the third buried insulation pattern 144c. The third channel pattern 140c has substantially the same shape as the first channel pattern 140a and may include substantially the same material.

The third information storage pattern 130c may be disposed between the mold insulating layer 118 and the third channel pattern 140c. The third information storage pattern 130c includes substantially the same material as the first information storage pattern 130a and may have substantially the same structure. 6C, the third information storage pattern 130c includes a first blocking insulating layer 132 contacting the mold insulating layer 118, a tunnel insulating layer 136 contacting the third vertical channel pattern 140c, ), And a charge storage layer 134 therebetween.

The third buried insulation pattern 144c may be disposed on the third semiconductor pattern 126c and extend in the third direction D3. The third buried insulation pattern 144c may be arranged to fill the space provided by the third channel pattern 140c. The third buried insulation pattern 144c may include a silicon oxide film or a silicon nitride film.

Each of the conductive pads 128 may be disposed on each of the first and second dummy channel structures 200b and 200c of the cell channel structures 200a. Each of the conductive pads 128 may comprise a conductive material. Each of the conductive pads 128 may include an impurity region doped with an impurity. According to some embodiments, one end of the cell channel structure 200a contacting the conductive pad 128 may include a drain region.

A common source region 152 may be formed in the substrate 100 exposed to the trenches 150 separating the stacked structures 30 from one another. For example, a common source region 152 may be disposed within the substrate 100 between the stacked structures 30 and extend along the first direction D1. The common source region 152 may include, for example, an N-type impurity (for example, arsenic (As) or phosphorus (P)).

A common source plug 166 may be formed in the trench 150 and electrically connected to the common source region 152. The common source plug 166 may extend in the first direction D1. A separate isolation spacer 162 may be disposed between the stacked structures 30 and the common source plug 166. The isolation insulating spacers 162 may cover the side walls of the laminated structures 30. [ According to some embodiments, the isolation spacer 162 may fill between adjacent lamination structures 30, and a common source plug 166 having a hole shape may pass through the isolation spacer 162 to form a common And can contact the source region 152. The isolation spacer 162 may comprise silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. The common source plug 166 may comprise a conductive material (e.g., tungsten, copper, silicon, or aluminum). Additionally, the common source plug 166 may comprise a barrier metal layer. For example, the barrier metal layer may comprise at least one of a transition metal (e.g., titanium or tantalum) or a conductive metal nitride (e.g., titanium nitride or tantalum nitride).

The capping insulating layer 148 and the first interlayer insulating layer 170 may be disposed on the laminating structures 30 and the mold insulating layer 118. The first interlayer insulating layer 170 may cover the common source plug 166. Sub bit line contacts 168 that are connected to each of the conductive pads 128 through the first interlayer insulating layer 170 and the capping insulating layer 148 and sub bit line contacts 168 connected to the sub bit line contacts 168. [ The bit lines SBL may be disposed in the cell array region CAA. Each of the sub bit lines SBL is disposed on the first interlayer insulating layer 170 and includes a pair of cell vertical channel structures 200a adjacent to each other in the second direction D2 with the trench 150 therebetween. Can be electrically connected.

A second interlayer insulating layer 174 may be disposed on the first interlayer insulating layer 170 to cover the sub bit lines SBL. The capping insulating layer 148 and the first and second interlayer insulating layers 170 and 174 may include a nitride layer or an oxide layer.

Gate contacts 180 connecting the pad portions GEP of the gate electrodes GE to the connection region CTA may be disposed. Each of the gate contacts 180 may be formed to be capable of penetrating through the first and second interlayer insulating layers 170 and 174, the capping insulating layer 148, the mold insulating layer 118 and the second blocking insulating layer 158 have. Each of the gate contacts 180 can be connected to the pad portion (GEP) of the corresponding gate electrode GE. The height of each of the gate contacts 180 may increase in the first direction D1 toward the boundary region BR.

The peripheral contacts 182 may be disposed in the peripheral region PR. The peripheral contacts 182 are formed to extend through the first and second interlayer insulating layers 170 and 174, the capping insulating layer 148, the mold insulating layer 118, and the peripheral passivation layer 109, PT) of the source / drain region 107 of the semiconductor device.

The bit lines BL, the first and second wirings M 1 and M 2 may be disposed on the second interlayer insulating layer 174. The bit line BL may extend in the second direction D2. Each of the bit lines BL may be connected to corresponding sub bit lines SBL through corresponding bit line contacts 176. [ As a result, the bit lines BL can be electrically connected to the cell vertical channel structures 200a. The first wires M1 may be electrically connected to the gate contacts 180. [ Each of the first wirings M1 can electrically connect each gate electrode GE of the stacked structures 30 located at the same level. According to some embodiments, the first wires M1 connected to the bottom gate electrodes GE1 may not be electrically connected to each other. And the second wires M2 may be electrically connected to the peripheral contacts 182. [ The second wirings M2 may be electrically connected to the first wirings M1 and / or the bit lines BL.

Sub bit line contact 168, sub bit line SBL, bit line contact 176, gate contact 180 and peripheral contact 182 include conductive material (e.g., tungsten, silicon, or copper) can do. In addition, sub-bit line contact 168, sub bit line SBL, bit line contact 176, gate contact 180 and peripheral contact 182 may comprise a barrier metal layer. The barrier metal layer may comprise at least one of, for example, a transition metal (e.g., titanium or tantalum) and / or a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The bit line BL and the first and second wirings M1 and M2 may comprise a metal (for example, aluminum or copper).

The first and second dummy channel structures 200b and 200c may not be electrically connected to the bit line BL, the first wiring M1, and the second wiring M2. Accordingly, the first and second dummy channel structures 200b and 200c can be electrically isolated.

8A to 18A and FIGS. 8B to 18B are diagrams for explaining a method of manufacturing a semiconductor memory device according to embodiments of the technical idea of the present invention, wherein FIGS. 8A to 18A correspond to line I-I ' And Figs. 8B to 18B are cross-sectional views corresponding to the line II-II 'in Fig. 2A. Figs. 19A to 19C are enlarged views of B1 in Fig. 12A, B2 in Fig. 12B, and B3 in Fig. 12B.

Referring to FIGS. 8A and 8B, a peripheral circuit element PT and a laminated mold structure 10 may be formed on a substrate 100. The substrate 100 includes a cell region CR including a cell array region CAA and a connecting region CTA, a peripheral region PR spaced apart from the cell region CR, CTA) and a peripheral region (PR).

The substrate 100 may comprise a semiconductor material. For example, the substrate 100 may be a silicon (Si) monocrystalline substrate, a germanium (Ge) monocrystalline substrate, or a silicon-germanium (SiGe) monocrystalline substrate. According to some embodiments, the substrate 100 may be a Semiconductor on Insulator (SOI) substrate. For example, the substrate 100 may include a semiconductor active layer (e.g., a silicon layer, a silicon-germanium layer, or a germanium layer) disposed on an insulating layer that protects the transistors provided on the semiconductor substrate. The substrate 100 may be a semiconductor substrate of a first conductivity type (e.g., P-type). A well region (not shown) may be formed on the substrate 100.

The peripheral circuit element PT may be formed on the substrate 100 in the peripheral region PR. The peripheral circuit element PT may include a source / drain region 107 adjacent to both the peripheral gate insulating film 101, the peripheral gate electrode 103, and the peripheral gate electrode 103. For example, the peripheral circuit element PT is formed by sequentially forming the peripheral gate insulating film 101 and the peripheral gate electrode 103 on the substrate 100 and forming the peripheral circuit element PT on the substrate 100 To form a source / drain region 107. The source / A peripheral gate spacer 107 may be formed on the sidewall of the peripheral gate electrode 103. [ The peripheral circuit element PT may comprise, for example, a low voltage or high voltage transistor. The peripheral protection layer 109 may be formed on the substrate 100 so as to cover the peripheral circuit element PT. The peripheral protective layer 109 can expose the substrate 100 in the cell region CR and the boundary region BR.

The peripheral gate insulating film 101 may include an oxide film (for example, a silicon oxide film) or a high-k dielectic film. The peripheral gate electrode 103 may be formed of silicon (e.g., polysilicon), a metal silicide (e.g., tungsten silicide (WSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicide Silicide (TaSi)), metal (e.g., tungsten or aluminum), and / or combinations thereof. The peripheral protective layer 109 may include an oxide film or a nitride film.

The mold structure 10 may be formed on the peripheral protective layer 109 of the substrate 100 of the cell region CR, the substrate 100 of the boundary region BR and the peripheral region PR. The mold structure 10 may be formed by alternately repeating the insulating films 110 and the sacrificial films 112. [ The mold structure 10 may include a plurality of insulating films 110 and a plurality of sacrificial films 112. The sacrificial films 112 may be formed of a material having etch selectivity with respect to the insulating films 110. For example, the sacrificial films 112 may have a higher etch selectivity in a wet etch process using a chemical solution than the insulating films 110. For example, each of the insulating films 110 is a silicon oxide film, and each of the sacrificial films 112 may be a silicon nitride film. According to some embodiments, each of the sacrificial films 112 may be any one of a silicon carbide film, a silicon film, and a silicon germanium film. According to other embodiments, each of the insulating films 110 is a silicon nitride film, and each of the sacrificial films 112 may be any one of a silicon oxide film, a silicon carbide film, a silicon film, and a silicon germanium film.

The insulating films 110 and the sacrificial films 112 may be formed using a thermal CVD process, a plasma enhanced chemical vapor deposition process, or an atomic layer deposition (ALD) process .

The sacrificial films 112 may have the same thickness. According to some embodiments, the insulating film 110-1 in contact with the substrate 100 may be a silicon oxide film formed by a thermal oxidation process or a deposition process, and may be formed thinner than the other insulating films 110. [ The insulating layer 110-2 of the second layer from the substrate 100 and the insulating layer 110-3 of the uppermost layer may be formed thicker than the other insulating layers 110 or the sacrificial layers 112. [

Referring to FIGS. 9A and 9B, the mold structure 10 may be patterned to have a stepwise structure in the connection area CTA. That is, the mold structure 10 may have an end portion 10e of a stepped structure. For example, the sacrificial films 112 may have pad portions 112a forming a stepped structure. A portion of each pad portion 112a of the sacrificial films 112 may be exposed. The vertical height of the mold structure 10 in the connection area CTA can be increased stepwise as it approaches the cell array area CAA.

A mold insulating layer 118 may be formed on the substrate 100 in the connection region CTA and the peripheral region PR. The mold insulating layer 118 may cover the end portion 10e of the mold structure 10. For example, the mold insulating layer 118 may cover the pad portions 112a of the sacrificial films 112. The mold insulating layer 118 may cover the substrate 100 and the peripheral protective layer 109 in the boundary region BR. The mold insulating layer 118 may contact the substrate 100 in the boundary region BR. The mold insulating layer 118 may comprise, for example, an oxide film or a low-k dielectic film.

10A and 10B, first channel holes 120a, second channel holes 120b, and third channel openings 120a, 120b are formed in the cell array region CAA, the connection region CTA, and the border region BR. And 120c, respectively.

In the cell array area (CAA), the first channel holes 120a can penetrate the mold structure 10 and expose the substrate 100. For example, the first channel holes 120a may be formed by anisotropically etching the mold structure 10. The substrate 100 can be over-deflected when the mold structure 10 is etched. In the plan view, the first channel holes 120a may be formed to be arranged in the same manner as the cell channel structures 200a shown in FIG. 2A.

The second channel holes 120b can expose the substrate 100 through the mold insulating layer 118 and the end portion 10e of the stepped mold structure 10 in the connection region CTA. The second channel holes 120b may be formed by anisotropically etching the mold insulating layer 118 and the mold structure 10. [ For example, the second channel holes 120b may be formed by the mold insulating layer 118 and the end of the pad portion 112a of the stepped sacrificial films 112, at least one insulating film 110 beneath the pad portion 112a, And may be formed by etching the film 112. When the second channel holes 120b are formed, the substrate 100 may overfed and be recessed. The second channel holes 120b may be arranged in the same manner as the first dummy vertical channel structures 200b shown in FIG. 2A.

In the boundary region BR, the third channel opening 120c can be formed by etching the mold insulating layer 118, and the substrate 100 can be over-deflected and recessed. The third channel opening 120c may have a hole shape as shown in FIG. 2A. And a plurality of third channel openings 120c may be formed in rows in the second direction D2. According to some embodiments, the third channel openings 120c have a hole shape and may be arranged in a plurality of rows parallel to the second direction D2 as shown in Fig. 2C. According to some embodiments, the third channel openings 200c are each in the form of a hole, as shown in FIG. 7B, and are disposed along the first direction D1 and the second direction D2, ). According to some embodiments, the third channel opening 120c may have a trench shape (or a slit shape) as shown in FIG. 2B. As shown in FIG. 7A, the third channel opening 120c may have a trench shape (or a slit shape) and may extend along the second direction D2. According to some embodiments, the third channel opening 120c has a trench shape and extends in first and second directions D1 and D2 as shown in Figures 7C and 7D, (CR).

11A to 11B, a first semiconductor pattern 126a, a second semiconductor pattern 126b, and a second semiconductor pattern 126b are formed in the first channel holes 120a, the second channel holes 120b, and the third channel opening 120c, And a third semiconductor pattern 126c, respectively. Each of the first to third semiconductor patterns 126a, 126b, and 126c may be connected to the substrate 100. [ A portion of each of the first to third semiconductor patterns 126a, 126b, and 126c may be embedded in the substrate 100, and each of the other portions may protrude onto the substrate 100 to have a pillar shape. The first and second semiconductor patterns 126a and 126b are higher than the upper surface of the bottommost sacrificial film 112 of the sacrificial films 112 and are twice higher than the upper surface of the sacrificial films 112, And upper surfaces located at a level lower than the upper surface of the insulating film 110-2. The upper surfaces of the first to third semiconductor patterns 126a, 126b, and 126c may have various shapes. For example, the upper surfaces of the first to third semiconductor patterns 126a, 126b, 126c may have a flat shape, an inclined shape with respect to the substrate 100, or a spiral shape.

Each of the first semiconductor patterns 126a may have a first height T1. The first height T1 may be the maximum height from the surface of the substrate 100 to the top surface of the first semiconductor pattern 126a. The second semiconductor patterns 126b may include a first sub semiconductor pattern 126b-1 and a second sub semiconductor pattern 126b-2. The first sub semiconductor pattern 126b-1 is located closest to the boundary region BR (for example, the third semiconductor pattern 126c), or closest to the cell array region CAA (for example, Lt; RTI ID = 0.0 > 126a). ≪ / RTI > The second sub semiconductor pattern 126b-2 may be closest to the cell array area CAA, for example, the first semiconductor patterns 120a. The first sub semiconductor pattern 126b-1 may have a second height T2 and the second sub semiconductor pattern 126b-2 may have a third height T3. The second height T2 is the maximum height from the surface of the substrate 100 to the top surface of the first sub semiconductor pattern 126b-1, the third height T3 is the maximum height from the surface of the substrate 100, May be the maximum height to the upper surface of the pattern 126b-2. The third semiconductor pattern 126c may have a fourth height T4 and the fourth height T4 may be the maximum height from the surface of the substrate 100 to the top surface of the third semiconductor pattern 126c. The fourth height T4 may be smaller than the first to third heights T1, T2, and T3. The first height T1 may be substantially equal to the third height T3. The second height T2 may be smaller than the first and third heights T1 and T3. According to some embodiments, the fourth height T4 may be higher than the second height T2 and less than the first and third heights T1, T3, as shown in FIG.

The first to third semiconductor patterns 126a, 126b, and 126c may be formed using the same process by a selective epitaxial growth method. The first to third semiconductor patterns 126a, 126b, and 126c may be an epitaxial pattern including silicon (Si). For example, the first to third semiconductor patterns 126a, 126b, and 126c may be monocrystalline silicon, or an epitaxial pattern including polysilicon.

Selective epitaxial growth can be performed at a high temperature in the range of 700 ° C to 1000 ° C, for example, using Dichlorosilane (SiH 2 Cl 2). Accordingly, impurities (e.g., hydrogen, carbon, or nitrogen) generated from the mold insulating layer 118 can be outgas through the third channel opening 120c. The first sub semiconductor pattern 126b-1 formed in the second channel hole 120b closest to the boundary region BR due to the third channel opening 120c can grow smoothly, And may have an upper surface higher than the upper surface.

According to a general technique without the third channel opening 120c, the amount of outgassing of impurities through the second channel hole 120b adjacent to the boundary region BR in the second channel holes 120b can be increased. Thus, the growth of the second semiconductor patterns 126b adjacent to the boundary region BR can be suppressed. As a result, the upper surface of the first sub semiconductor pattern 126b-1 may be lower than the upper surface of the lowermost sacrificial film 112. Therefore, the leakage of current through the first sub semiconductor pattern 126b-1 can lower the reliability of the memory semiconductor device.

According to the embodiments of the present invention described above, since the third channel opening 120c is utilized as a passage through which the impurities generated from the mold insulating layer 118 are emitted, the second semiconductor patterns 126b (for example, Suppression of the epitaxial growth of one sub semiconductor pattern 126b-1 can be prevented.

According to some embodiments, the first to third semiconductor patterns 126a, 126b, and 126c may be formed of germanium (Ge), silicon germanium (SiGe), III-V semiconductor compound, And / or a Group II-VI semiconductor compound. Each of the first to third semiconductor patterns 126a, 126b, 126c may be doped with the same impurity as the conductivity type of the substrate 100, or the impurity may be undoped.

Referring to FIGS. 12A, 12B, 19A, 19B and 19C, the cell channel structures 200a, the first dummy channel structures 200b and the second dummy channel structures 200c are arranged in a cell array region CAA Each of the cell channel structures 200a may be formed in the first channel holes 120a and the first dummy channel structures 200b may be formed in the first channel holes 120a. May be formed in the second channel holes 120b and the second dummy channel structure 200c may be formed in the third channel opening 120c. The cell channel structures 200a may be arranged in the first and second directions D1 and D2 as shown in FIG. 2A.

Each of the cell channel structures 200a may include a first semiconductor pattern 126a, a first channel pattern 140a, a first information storage pattern 130a, and a first buried insulation pattern 144a. The first channel pattern 140a, the first information storage pattern 130a, and the first buried insulation pattern 144a may be formed on the first semiconductor pattern 126a.

The first data storage pattern 130a may cover the inner wall of each of the first channel holes 120a. For example, the first information storage pattern 130a may be formed as a spacer on the inner wall of each of the first channel holes 120a. For example, the first information storage pattern 130a may have an opened top shape and a bottom shape. The first information storage pattern 130a may be in contact with the insulating films 110 and the sacrificial films 112 of the molding structure 10. [ The first information storage pattern 130 may include a thin film capable of storing data. For example, the information storage pattern 130 may include a thin film that can store data using Fowler-Nordheim tunneling. According to some embodiments, the first information storage pattern 130a is a thin film (e.g., a thin film for a phase change memory device or a thin film for a variable resistance memory device) capable of storing data based on another operating principle, . ≪ / RTI >

19A, the first information storage pattern 130a may include a first blocking insulating layer 132, a charge storage layer 134, and a tunnel insulating layer 136. Referring to FIG. For example, the first blocking insulating film 132, the charge storage film 134, and the tunnel insulating film 136 may be sequentially formed on the inner wall of the first channel hole 120a. The first blocking insulating film 132 may include a silicon oxide film and / or a high-k film (for example, an aluminum oxide film or a hafnium oxide film). The first blocking insulating film 132 may be composed of a single film or a plurality of thin films. For example, the first blocking insulating film 132 may be a single film including a silicon oxide film. For example, the first blocking insulating film 132 may include a plurality of thin films including an aluminum oxide film and / or a hafnium oxide film.

The charge storage film 134 may be an insulating film including a trap insulating film or conductive nano dots. The trap insulating film may include, for example, a silicon nitride film. The tunnel insulating film 136 may be, for example, a silicon oxide film. The first blocking insulating layer 132 and the charge storage layer 134 may be formed using plasma enhanced chemical vapor deposition (CVD) or atomic layer deposition (ALD). The tunnel insulating layer 136 may be formed using a plasma enhanced chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a thermal oxidation process. The tunnel insulating layer 136 may be in contact with the first channel pattern 140a.

The first channel pattern 140a is in contact with the first information storage pattern 130a and the first channel pattern 140a may be conformally formed in the liner shape within the first channel holes 120a. The first channel pattern 140a may be connected to the first semiconductor pattern 126a. The first channel pattern 140a may have a top opened form. According to some embodiments, the first channel pattern 140a may be in an open top, bottom open, hollow cylinder, or macaroni form. According to some embodiments, the first channel pattern 140a may be in the shape of a cylinder filled with the first channel holes 120a. The first channel pattern 140a may comprise a semiconductor material. The first channel pattern 140a may be a pattern comprising any one of a polycrystalline semiconductor material, an amorphous semiconductor material, or a single crystal semiconductor material. The first channel pattern 140a may be formed of one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs) And may include at least any one of them. The first channel pattern 140a may be an un-doped semiconductor material or a semiconductor material including impurities the same as the conductivity type of the substrate 100. [ The first channel pattern 140a may be formed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or epitaxial growth.

The first buried insulation pattern 144a may be formed to fill the first channel holes 120a in which the first channel pattern 140a is formed. The first buried insulating pattern 144a may include a silicon oxide film or a silicon nitride film.

Each of the first dummy channel structures 200b may include a second semiconductor pattern 126b, a second channel pattern 140b, a second information storage pattern 130b, and a second buried insulation pattern 144b. have. The second channel pattern 140b, the second information storage pattern 130b, and the second buried insulating pattern 144b may be formed on the second semiconductor pattern 126b.

The second information storage pattern 130b may cover the inner wall of the second channel holes 120b. For example, the second information storage pattern 130b may be formed as a spacer on the inner walls of the second channel holes 120b. The second information storage pattern 130b has substantially the same structure as the first information storage pattern 130a of the cell channel structure 200a and may include the same material. For example, the second information storage pattern 130b may include a first blocking insulating layer 132, a charge storage layer 134, and a tunnel insulating layer 132 which are sequentially formed on the inner walls of the second channel holes 120b, And may include an insulating film 136.

The second channel pattern 140b contacts the second data storage pattern 130b and may be conformally formed in the liner shape in the second channel holes 120b. And the second channel pattern 140b may be connected to the second semiconductor pattern 126b. The second channel pattern 140b has substantially the same shape as the first channel pattern 140a and may include the same material. The second buried insulation pattern 144b may be formed to fill the second channel holes 120b formed with the second channel pattern 140b. The second buried insulating pattern 144b has substantially the same shape as the first buried insulating pattern 144a and may include the same material.

 The second dummy channel structure 200c may include a third semiconductor pattern 126c, a third information storage pattern 130c, and a third buried insulation pattern 144c. The third channel pattern 140c, the third information storage pattern 130c, and the third buried insulation pattern 144c may be formed on the third semiconductor pattern 126c. The second dummy channel structure 200c can be in contact with the mold insulating layer 118. [

The third data storage pattern 130c may cover the inner wall of the third channel opening 120c. For example, the third information storage pattern 130c may be formed as a spacer on the inner wall of the third channel opening 120c. The third information storage pattern 130c may be in contact with the mold insulating layer 118. [ The third information storage pattern 130c has substantially the same structure as the first information storage pattern 130a of the cell channel structures 200a and may include the same material. For example, as shown in FIG. 19C, the third information storage pattern 130c includes a first blocking insulating film 132, a charge storage film 134, and a tunnel insulating film 132 which are sequentially formed on the inner wall of the third channel opening 120c. (136). The first to third information storage patterns 130a, 130b and 130c may be formed by the same process.

The third channel pattern 140c contacts the third information storage pattern 130c and may be formed on the third semiconductor pattern 126c. The third channel pattern 140c may be formed conformally in the form of a liner within the third channel opening 120c and connected to the third semiconductor pattern 126c. The third channel pattern 140c has the same shape as the first channel pattern 140a and may include the same material. The first to third channel patterns 140a, 140b and 140c may be formed by the same process.

The third buried insulation pattern 144c may be formed to fill the third channel opening 120c in which the third channel pattern 140c is formed. The third buried insulation pattern 144c has substantially the same shape as the first buried insulation pattern 144a and may include the same material. The first to third channel patterns 140a, 140b and 140c may be formed by the same process. The first through third buried insulating patterns 144a, 144b, and 144c may be formed in the same process.

The first, second, and third information storage patterns 130a, 130b, and 130c may be formed by the same process using the same material. The first to third channel patterns 140a, 140b, and 140c may be formed in the same process using the same material. The first through third buried insulating patterns 144a, 144b, and 144c may be formed in the same process using the same material.

The second dummy channel structure 200c is a plan view. It may have the circular or elliptical shape shown in Fig. 2A, or it may have the bar shape shown in Fig. 2B. Referring to FIGS. 2A and 2B, the second dummy channel structures 200c may be arranged in rows along a second direction D2 in plan view. For example, the second dummy channel structures 200c may be spaced apart from the stacked structures 30, and at least one adjacent to each of the stacked structures 30 may be disposed and heat in a second direction D2 Lt; / RTI > 2C, each of the second dummy channel structures 200c has a circular or elliptical shape when viewed in a plan view, and is arranged in two rows parallel to the second direction D2 But may be arranged in three or more rows parallel to the second direction D2 without being limited thereto. 7A, each of the second dummy channel structures 200c has a bar shape, and a second direction D2 is formed between the connection region CTA and the peripheral region PR As shown in FIG. For example, each of the second dummy channel structures 200c may be spaced apart from the stacking structures 30 in the first direction D1 and extend along the second direction D2. According to some embodiments, the second dummy channel structures 200c may surround the cell region CR, as shown in Figures 7B and 7C. For example, the second dummy channel structures 200c are arranged between the connection region CTA and the peripheral region PR along the second direction D2, and extend along the first direction D1 along the cell region CR ) And the peripheral region PR. According to some embodiments, as shown in FIG. 7D, the second dummy channel structure 200c may surround the cell region CR in a loop shape.

Conductive pads 128 may be formed on the cell channel structures 200a, the first and second dummy channel structures 200b and 200c, respectively. Each of the conductive pads 126 may comprise a conductive material. Each of the conductive pads 128 may include an impurity region doped with an impurity. According to some embodiments, one end of the cell channel structures 200 in contact with the conductive pads 128 may include a drain region. A capping insulating layer 148 may be formed on the mold structure 10 and the mold insulating layer 118 so as to cover the conductive pads 128. [ The capping insulating layer 148 may include an oxide layer or a nitride layer.

13A and 13B, a trench 150 may be formed in the mold structure 10 in the cell region CR. The trench 150 may be formed by patterning the capping insulating layer 148 and the mold structure 10 to expose the substrate 100. 2A, the trenches 150 may be formed to extend in the first direction D1 from the cell array region CAA to the connection region CTA. As shown in FIG. 2A, Likewise, the trenches 150 may allow the cell channel structures 200a to be arranged in two rows in a zigzag fashion in a first direction D1. Accordingly, the cell channel structures 200a arranged in two rows in a zigzag manner in the first direction D1 can be repeatedly arranged in the second direction D2. According to some embodiments, the trenches 150 may allow the cell channel structures 200a to be arranged in one or more rows in a jig regrowth in a first direction D2.

The common source region 152 can be formed in the substrate 100 exposed to the trench 150. [ For example, impurities (for example, phosphorus (P) or arsenic (As)) of N-type conductivity can be ion-implanted into the substrate 100 to form the common source region 152.

14A and 14B, openings 154 may be formed in the mold structure 10 in the cell array area CAA and the connection area CTA. For example, the openings 154 may be formed by removing the sacrificial films 112 of the mold structure 10 exposed to the trenches 150. The openings 154 may be formed by removing the sacrificial films 112 by isotropic etching. The openings 150 may be formed to expose the sidewalls of the cell channel structures 200a and the first dummy channel structures 200b.

The gate oxide film 156 may be formed on the sidewalls 126as of the first semiconductor patterns 126a and the sidewalls 126bs of the second semiconductor patterns 126a. The gate oxide film 156 may be formed by thermally oxidizing the sidewalls 126as and 126bs of the first and second semiconductor patterns 126a and 126b exposed by the openings 154. [ In the cell region CR, the gate oxide film 156 has a bulged shape and can be formed uniformly. For example, the gate oxide film 156 may be uniformly formed on the sidewalls 126bs of the first sub semiconductor pattern 126b-1 of the second semiconductor patterns 126b. The gate oxide film 156 may be formed by a thermal oxidation process so that the sidewalls 126as and 126bs of the first and second semiconductor patterns 126a and 126b may have a concave shape. The third semiconductor patterns 126c are not exposed by the openings 154 and thus the gate oxide film 156 is not formed on the side walls 126cs of the third semiconductor pattern 126c in contact with the mold insulating layer 118 . Accordingly, at least a part of the side wall 126cs of the third semiconductor pattern 126c may have a profile of a flat cross-section in the third direction D3.

15A and 15B, a gate conductive film 159 filling the openings 154 can be formed. The gate conductive film 159 may include a semiconductor film, a metal silicide film, a metal film, a metal nitride film, or a combination film thereof. For example, the semiconductor film may be a silicon film doped with an impurity. As another example, the metal silicide film may include cobalt silicide, titanium silicide, tungsten silicide, or tantalum silicide. The metal film may include, for example, tungsten, nickel, cobalt, titanium, or tantalum. The metal nitride film may include, for example, titanium nitride, tungsten nitride, or tantalum nitride.

The second blocking insulating film 158 may be formed in the opening 154 before the gate conductive film 159 is formed. Thus, the second blocking insulating film 158 surrounds the upper surface, the lower surface, and the side surfaces of the gate conductive film 159, and can contact the first blocking insulating film 132. The second blocking insulating film 158 may be composed of a single film or a plurality of thin films. The second blocking insulating film 158 may include a high-k film (for example, an aluminum oxide film or a hafnium oxide film). According to some embodiments, the second blocking insulating film 158 may not be formed.

16A and 16B, the gate conductive film 159 may be patterned to form the gate electrodes GE. For example, an isotropic etching process may be performed so that the gate conductive film 159 formed in the trench 150 and on the capping insulating layer 148 is completely removed. Accordingly, the gate electrodes GE separated by the insulating films 110 in the third direction D3 can be formed.

The gate electrodes GE extend from the cell array region CAA to the connection region CTA and may have pad portions GEP forming a stepwise structure in the connection region CTA. The horizontal length of the gate electrodes GE may decrease as the distance from the substrate 100 in the third direction D2 increases.

As a result, the stacked structures 30 including the insulating film 110 and the electrodes GE repeatedly alternately stacked in the third direction D3 on the substrate 100 of the cell region CR can be formed have. As shown in FIG. 2A, the stacked structures 30 may extend in a first direction D1 and be separated from each other by trenches 150 in a second direction D2. The cell channel structures 200a may pass through the stacked structures 30 and the gate electrodes GE may cover the cell channel structures 200a. The first dummy channel structures 200b may penetrate a part of the laminated structures 30. [ For example, the gate electrodes GE may cover a part of the first dummy channel structures 200b. The stacked structures 30 may have an end 30e of a stepwise structure in the connection region CTA.

The gate electrodes GE may be combined with the cell channel structures 200a to form memory cells. Thus, the cell array region CAA may be provided with vertical memory cell strings including vertically arranged memory cells. The bottom and top gate electrodes GE1 and GE3 may be used as the gate electrodes of the select transistors SST and GST. Gate electrodes GE between the bottom and top gate electrodes GE1, GE3 can be used as the control gate electrodes of the memory cells.

A common source plug 166 and a separate isolation spacer 162 may be formed to fill the trench 150 over the common source region 152. The isolation insulating spacer 162 protects the side surfaces of the gate electrodes GE and can isolate the gate electrodes GE and the common source plug 166 from each other. The isolation insulating spacers 162 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. The common source plug 166 may be formed in the trench 150 formed with the insulating spacer 162 to be electrically connected to the common source region 152. The common source plug may be formed to extend in the first direction D1. According to some embodiments, a common source plug 166 having a hole shape can penetrate the isolation spacer 162 and contact the common source region 152. The common source plug 166 may comprise a metal (e.g., tungsten, copper, or aluminum). Additionally, the common source plug 166 may comprise a barrier metal layer. For example, the barrier metal layer may comprise at least one of a transition metal (e.g., titanium or tantalum) and / or a conductive metal nitride (e.g., titanium nitride or tantalum nitride). According to some embodiments, a high concentration of impurities may be implanted into the common source region 152 prior to formation of the common source plug 166.

Referring to FIGS. 17A and 17B, sub-bit line contacts 168 and sub-bit line contacts 168 electrically connected to the cell channel structures 200a in the cell array area CAA are electrically connected The sub bit lines SBL may be formed.

The first interlayer insulating layer 170 may be formed on the capping insulating layer 148. The first interlayer insulating layer 170 may include an oxide film, a low dielectric film, or a nitride film. The sub bit line contacts 168 may be formed to penetrate the first interlayer insulating layer 170 and the camping insulating layer 148 to connect to the conductive pads 128 on the cell channel structures 200a.

 The formation of the sub bit line contacts 168 forms contact holes that expose the conductive pads 128 on the cell vertical channel structures 200a in the first interlayer insulating layer 170 and the capping insulating layer 148 , Depositing a conductive film in the contact holes, and planarizing the conductive film.

Sub bit lines SBL electrically connected to the sub bit line contacts 168 may be formed on the first interlayer insulating layer 170. 2A, each of the sub bit lines SBL includes a pair of sub bit line contacts 168 connected to neighboring cell channel structures 200a via the trench 150 Can be electrically connected. Each of the sub bit lines SBL may be a pattern extending in the second direction D2. Each of the sub bit line contacts 168 and sub bit lines SBL may comprise a conductive material (e.g., silicon, tungsten, or copper). In addition, each of the sub bit line contacts 178 and sub bit lines SBL may comprise a barrier metal layer. For example, the barrier metal layer may comprise at least one of a transition metal (e.g., titanium or tantalum) and / or a conductive metal nitride (e.g., titanium nitride or tantalum nitride).

18A and 18B, bit lines BL are formed in a cell array region CAA, gate contacts 180 and first wirings M 1 are formed in a connection region CTA The peripheral contacts 182 and the second wiring M2 may be formed in the peripheral region PR.

A second interlayer insulating layer 174 covering the sub bit lines SBL may be formed on the first interlayer insulating layer 170. [ The second interlayer insulating layer 170 may include an oxide film, a low dielectric film, or a nitride film. The gate contact 180 passing through the second interlayer insulating layer 174, the first interlayer insulating layer 170, the capping insulating layer 148, the mold insulating layer 118, and the second blocking insulating layer 158 is connected Region (CTA). Each of the gate contacts 180 can be connected to the pad portion (GEP) of the corresponding gate electrode GE. The height of each of the gate contacts 180 may increase in the first direction D1 toward the boundary region BR.

The peripheral contacts 182 passing through the second interlayer insulating layer 174, the first interlayer insulating layer 170, the capping insulating layer 148, the mold insulating layer 118, and the peripheral protective layer 109 are surrounded May be formed in the region PR. The peripheral contacts 182 can be connected to the source / drain regions 107 of the peripheral circuit elements PT.

Gate contacts 180 and peripheral contacts 182 may comprise a conductive material (e.g., silicon, tungsten, or copper). Additionally, the gate contacts 180 and the peripheral contacts 182 may comprise a barrier metal layer. For example, the barrier metal layer may comprise at least one of a transition metal (e.g., titanium or tantalum) and / or a conductive metal nitride (e.g., titanium nitride or tantalum nitride).

The bit lines BL may be formed on the second interlayer insulating layer 174. [ The bit line BL is connected to the bit line contacts 176 through the second interlayer insulating layer 174 and connected to the sub bit lines SBL. The bit lines BL may extend in the second direction D2. The bit lines BL may be electrically connected to the cell channel structures 200a.

 The first wirings Ml electrically connecting the gate contacts 180 to each other may be formed in the connection region CTA. Each of the first wirings M1 can electrically connect the gate electrodes GE located at the same level. According to some embodiments, the first wires M1 that are electrically connected to the bottom gate electrodes GE1 may not be connected to each other.

The second wirings M2 are formed in the peripheral region PR and may be electrically connected to the peripheral contacts 182. [ The second wirings M2 may be electrically connected to the first wirings M1 and / or the bit lines BL. The bit lines BL and the first and second interconnects M1 and M2 may comprise a metal (e.g., aluminum or copper).

The first and second dummy channel structures 200b and 200c may not be electrically connected to the bit line BL, the first wiring M1, and the second wiring M2. Accordingly, the first and second dummy channel structures 200b and 200c can be electrically isolated.

20 is a schematic block diagram illustrating a memory system including a semiconductor memory device according to embodiments of the present invention;

Referring to FIG. 20, the memory system 1000 may be a semiconductor storage device. For example, the memory system 1000 may be a memory card or a solid state drive (SSD). The memory system 1000 may include a controller 1200 and a memory 1300 in a housing 1100. Controller 1200 and memory 1300 may exchange electrical signals. For example, according to a command of the controller 1200, the memory 1300 and the controller 1200 can exchange data. Accordingly, the memory system 1000 can store data in the memory 1300, or output data from the memory 1300 to the outside. The memory 1300 may include a semiconductor memory device according to embodiments of the present invention.

21 is a schematic block diagram illustrating an electronic system including a semiconductor memory device according to embodiments of the present invention;

21, the electronic system 2000 may include a controller 2200, a storage device 2300, and an input / output device 230. [ Controller 2200, storage device 2300, and input / output device 230 may be coupled through a bus 2100, bus. The bus 2100 may be a path through which data is moved. For example, the controller 2200 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing the same functions. The input / output device 230 may include at least one selected from a keypad, a keyboard, and a display device. The storage device 2300 is a device for storing data. The storage device 2300 may store data and / or instructions executed by the controller 2200, and the like. The storage device 2300 may include a volatile storage element and / or a non-volatile storage element. The storage device 2300 may be formed of a flash memory. These flash memories can be configured as SSDs. In this case, the electronic system 2000 can stably store a large amount of data in the storage device 2300. The memory device 2300 may include a semiconductor memory device according to embodiments of the present invention. The electronic system 2000 may further include an interface 2500 for transferring data to or receiving data from the communication network. The interface 2500 may be in wired or wireless form. For example, the interface 2500 may include an antenna or a wired or wireless transceiver.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the above-described embodiments are illustrative and non-restrictive in every respect.

Claims (18)

A laminated structure disposed on the substrate and alternately repeating the gate electrodes and the insulating layers;
A cell channel structure including a first semiconductor pattern penetrating the stacked structure and connected to the substrate, and a first channel pattern disposed on the first semiconductor pattern and connected to the first semiconductor pattern; And
And a second channel pattern disposed on the substrate and spaced apart from the laminated structure, the second channel pattern being disposed on the second semiconductor pattern and connected to the second semiconductor pattern, Channel structure,
Wherein a first height from a surface of the substrate to an upper surface of the first semiconductor pattern is greater than a second height from a surface of the substrate to an upper surface of the second semiconductor pattern. The method according to claim 1,
Wherein the cell channel structure further comprises a first information storage pattern disposed between the first channel pattern and the laminate structure. 3. The method of claim 2,
Wherein the first dummy channel structure further comprises a second information storage pattern in contact with a side wall of the second channel pattern, wherein the first channel pattern and the second channel pattern include the same material, And the second information storage pattern comprise the same material. The method according to claim 1,
Wherein the substrate includes a cell region including a cell array region and a connection region adjacent to the cell array region, a peripheral region spaced apart from the cell region, and a boundary region between the cell region and the peripheral region,
Wherein said stacked structure is disposed in said cell region and extends in a first direction and has an end of a step structure in said connection region. 5. The method of claim 4,
And peripheral circuit elements disposed on the substrate in the peripheral region
Wherein the peripheral circuit element includes a gate insulating film, a gate electrode, and a source / drain region. 5. The method of claim 4,
Further comprising a mold insulation layer covering the end portion of the laminate structure and disposed on the substrate in the connection region, the boundary region and the peripheral region, the first dummy channel structure passing through the mold insulation layer, To the semiconductor memory device. The method according to claim 6,
A third semiconductor pattern penetrating the mold insulating layer and the end portion of the laminated structure in the connection region and connected to the substrate, and a third channel pattern connected to the third semiconductor pattern and disposed on the third semiconductor pattern, And a second dummy channel structure including the second dummy channel structure. 8. The method of claim 7,
Wherein the first dummy channel structure has a circular shape, an elliptical shape, or a bar shape in a plan view. The method according to claim 1,
Further comprising a gate oxide film disposed on a sidewall of the first semiconductor pattern, wherein the gate oxide film is not disposed on a sidewall of the second semiconductor pattern. A cell region including a cell array region and a connection region, a peripheral region spaced apart from the cell region, and a boundary region between the connection region and the peripheral region;
Forming a mold structure including alternately stacked insulating films and sacrificial films on a substrate of the cell region;
Covering a part of the mold structure, forming a mold insulation layer on the substrate in the connection region, the boundary region, and the peripheral region;
A first channel pattern passing through the mold structure on the cell array region and including a first semiconductor pattern connected to the substrate and a first channel pattern disposed on the first semiconductor pattern and connected to the first semiconductor pattern, Forming;
A second semiconductor pattern penetrating the mold insulating layer and the mold structure on the connection region and connected to the substrate and a second channel pattern disposed on the second semiconductor pattern and connected to the second semiconductor pattern, To form first dummy channel structures; And
And a third channel pattern formed on the third semiconductor pattern and connected to the third semiconductor pattern, the third semiconductor pattern passing through the mold insulating layer of the boundary region and connected to the substrate, And forming a gate electrode on the semiconductor substrate. 11. The method of claim 10,
Wherein the first semiconductor pattern has a first height from a surface of the substrate to an upper surface of the first semiconductor pattern and the second semiconductor patterns include a first sub semiconductor pattern closest to the third semiconductor pattern, The first semiconductor pattern has a second height from a surface of the substrate to an upper surface of the first sub semiconductor pattern, and the third semiconductor pattern has a third height from a surface of the substrate to an upper surface of the third semiconductor pattern Wherein the third height is smaller than the first height and the second height is smaller than the first height. 12. The method of claim 11,
Wherein the second semiconductor patterns further include a second sub semiconductor pattern closest to the first semiconductor pattern and the second sub semiconductor pattern has a fourth height from a surface of the substrate to an upper surface of the second sub semiconductor pattern And the fourth height is substantially the same as the first height. 12. The method of claim 11,
Forming peripheral circuit elements on the substrate in the peripheral region; And
Further comprising forming a peripheral protective layer to protect the peripheral circuit elements,
Wherein the peripheral circuit element includes a gate insulating layer and a gate electrode stacked on the substrate, and a source / drain region formed in the substrate adjacent to the gate electrode, wherein the mold insulating layer covers the peripheral protection layer Gt; 12. The method of claim 11,
Wherein the cell channel structure further comprises a first information storage pattern in contact with a sidewall of the first channel pattern,
Wherein each of the first dummy channel structures further comprises a second information storage pattern in contact with a side wall of the second channel pattern,
Wherein the second dummy channel structure further comprises a third information storage pattern in contact with a sidewall of the third channel pattern,
Wherein the first channel pattern, the second channel pattern, and the third channel pattern include the same material, and the first information storage pattern, the second information storage pattern, and the third information storage pattern include the same material Wherein the semiconductor memory device is a semiconductor memory device. 12. The method of claim 11,
Wherein the second dummy channel structures are formed in a plurality of shapes and each of the second dummy channel structures has a circular shape or an elliptical shape in a plan view and is arranged along one direction. 12. The method of claim 11,
Wherein the second dummy vertical channel structure has a bar shape in a plan view and extends along one direction. 12. The method of claim 11,
Further comprising forming a gate oxide film on the sidewalls of the first and second semiconductor patterns,
And the gate oxide film is not formed on the sidewall of the third semiconductor pattern. 12. The method of claim 11,
Removing the sacrificial layers to form openings;
Forming a gate conductive film in the openings; And
And patterning the gate conductive film to form gate electrodes.

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