KR102300728B1 - Semiconductor Memory Device And Method of Fabricating The Same - Google Patents

Abstract

A semiconductor memory device includes a stacked structure including gate electrodes and insulating layers arranged in a first direction and alternately stacked on a substrate, and vertical channel structures passing through the stacking structure. Each of the vertical channel structures includes a semiconductor pattern connected to the substrate and a vertical channel pattern connected to the semiconductor pattern. Each of the semiconductor patterns included in the vertical channel structures has recessed sidewalls. The semiconductor patterns have different minimum widths.

Description

TECHNICAL FIELD [0002] Semiconductor memory device and method of manufacturing the same

The present invention relates to a semiconductor memory device and a method for manufacturing the same.

It is required to increase the degree of integration of semiconductor devices in order to meet the excellent performance and low price demanded by consumers. In the case of a semiconductor memory device, since the degree of integration is an important factor in determining the price of a product, an increased degree of integration is particularly required. In the case of a conventional two-dimensional or planar semiconductor memory device, since the degree of integration is mainly determined by an area occupied by a unit memory cell, it is greatly affected by the level of a fine pattern forming technique. However, very expensive equipment is required for pattern miniaturization, and an increase in the degree of integration of a two-dimensional semiconductor memory device is still limited. Accordingly, there is an increasing demand for a semiconductor memory device in which memory cells are vertically arranged.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having high integration and high reliability.

Another object of the present invention is to provide a method of manufacturing a semiconductor device having high integration and high reliability.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to exemplary embodiments of the present invention for achieving the above object, a semiconductor memory device includes insulating layers and gate electrodes that are alternately and repeatedly stacked on a substrate, stacked structures arranged in a first direction, and the stacked structure first and second semiconductor patterns passing through each of the layers, connected to the substrate and arranged side by side in the first direction, passing through each of the stacked structures, and disposed on each of the first and second semiconductor patterns first and second vertical channel patterns, a trench between the stacked structures; and a common source plug disposed in the trench. The first semiconductor pattern may be disposed adjacent to the trench, and the second semiconductor pattern may be disposed far from the trench. A minimum width of the first semiconductor pattern may be smaller than a minimum width of the second semiconductor pattern.

In some embodiments, each of the stack structures horizontally surrounds the first gate electrode penetrated by the semiconductor patterns and the vertical channel patterns, and a second gate electrode vertically stacked on the first gate electrode may include

In some embodiments, an information storage pattern may be disposed between the second gate electrodes and the first vertical channel pattern, and between the second gate electrodes and the second vertical channel pattern.

In some embodiments, the first gate electrode surrounds sidewalls of the first and second semiconductor patterns, has ends spaced apart from each other in the first direction, and is disposed between the first semiconductor pattern and the second semiconductor pattern. may have a first thickness and a second thickness greater than the first thickness adjacent to the end portions.

In some embodiments, each of the first and second semiconductor patterns may have recessed sidewalls.

In some embodiments, each of the first and second semiconductor patterns may have the minimum width between the recessed sidewalls.

In some embodiments, the recessed sidewalls of the second semiconductor pattern have a first recess sidewall and a second recess sidewall opposite to each other in the first direction, and a maximum recess of the first recess sidewall The recess depth may be different from a maximum recess depth of the sidewall of the second recess.

In some embodiments, a difference between the maximum recess depth in the first recess sidewall and the maximum recess depth in the second recess sidewall may be about 10 Å to about 60 Å.

In some embodiments, maximum recess depths of the recessed sidewalls of the first semiconductor pattern may be substantially the same.

According to exemplary embodiments of the present invention for achieving the above object, a semiconductor memory device includes insulating layers and gate electrodes that are alternately and repeatedly stacked on a substrate, stacked structures arranged in a first direction, and the stacked structure semiconductor patterns passing through each of the substrates and connected to the substrate and arranged side by side in the first direction, vertical channel patterns penetrating each of the stacked structures and disposed on each of the semiconductor patterns, the stacked structures a trench disposed therebetween, and a common source plug disposed within the trench. At least one of the semiconductor patterns may have recess sidewalls opposite to each other in the first direction, and maximum recess depths of the recess sidewalls may be different from each other.

In some embodiments, the recessed sidewalls of the at least one semiconductor pattern include a first recess sidewall proximate to the trench and a second recess sidewall distal from the trench in the first direction, a maximum recess depth of the first recess sidewall may be greater than a maximum recess depth of the second recess sidewall;

In some embodiments, a difference between the maximum recess depth of the first recess sidewall and the maximum recess depth of the second recess sidewall may be about 10 Å to about 60 Å.

In some embodiments, a height of the first recess sidewall may be higher than a height of the second recess sidewall.

In some embodiments, each of the stack structures includes a first gate electrode penetrated by semiconductor patterns, wherein the first gate electrode is in the first recess than in a region adjacent to a sidewall of the second recess. It may be thicker in areas adjacent to the sidewalls.

In some embodiments, the semiconductor device may further include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer disposed between each of the vertical channel patterns and each of the stacked structures.

A semiconductor memory device according to exemplary embodiments of the present invention for achieving the above object includes a first semiconductor pattern and a second semiconductor pattern, the first and second semiconductor patterns arranged side by side in a first direction and connected to a substrate The first and second vertical channel patterns respectively disposed thereon, and a gate electrode that horizontally surrounds the first and second semiconductor patterns and has ends in the first direction. Each of the first and second semiconductor patterns has a minimum width in a region adjacent to the gate electrode, a minimum width of the first semiconductor pattern is smaller than a minimum width of the second semiconductor pattern, and the gate electrode has a minimum width of the first semiconductor pattern. and a first thickness in a region between the second semiconductor patterns and a second thickness different from the first thickness in a region adjacent to the ends of the gate electrode. and each of the second semiconductor patterns may have a first recess sidewall and a second recess sidewall facing each other in the first direction.

In some embodiments, maximum recess depths of sidewalls of the first and second recesses of the first semiconductor pattern may be substantially the same.

In some embodiments, a maximum recess depth of a sidewall of the first recess of the second semiconductor pattern may be greater than a maximum recess depth of a sidewall of the second recess of the second semiconductor pattern.

In some embodiments, the second thickness of the gate electrode may be greater than the first thickness of the second gate electrode.

According to exemplary embodiments of the present invention, stacked structures separated by a trench and disposed in the first direction and including insulating layers and gate electrodes alternately stacked may be formed on a substrate. Vertical channel structures each including a semiconductor pattern connected to the substrate and a vertical channel pattern disposed thereon may pass through each of the stacked structures. Among the sidewalls of the semiconductor patterns, sidewalls adjacent to the trench in the first direction may be more recessed than sidewalls distant from the trench. Accordingly, the width between sidewalls of the recesses of the adjacent semiconductor patterns in the second direction intersecting the first direction is secured to the maximum, so that the formation of the gate electrode surrounding the semiconductor patterns may be facilitated. Accordingly, a semiconductor memory device having high integration and high reliability can be secured.

1 is a schematic plan view of a semiconductor memory device according to exemplary embodiments of the present invention.
FIG. 2 is a cross-sectional view of a semiconductor memory device according to exemplary embodiments of the present invention, and is a cross-sectional view taken along line II′ of FIG. 1 .
3 is an enlarged view of part A of FIG. 2 .
FIG. 4 is a schematic plan view illustrating a part of a semiconductor memory device including the semiconductor patterns shown in FIG. 2 .
5A and 5B are schematic cross-sectional views of the semiconductor patterns shown in FIG. 2 ;
6 to 8 , 10 , 11 , 14 , 17 , and 18 are for explaining a method of manufacturing a semiconductor memory device according to exemplary embodiments of the present invention shown in FIGS. 1 to 4 . As cross-sectional views, they are cross-sectional views taken along line II′ of FIG. 1 .
9 is an enlarged view of part B of FIG. 8 .
Fig. 12 is a schematic plan view at the height of G in Fig. 11;
13 is an enlarged view of part G of FIG. 11 .
Fig. 15 is a schematic plan view at the height of G' in Fig. 14;
FIG. 16 is an enlarged view of a portion G′ of FIG. 14 .
19 is a schematic block diagram illustrating a semiconductor device system including a semiconductor memory device according to exemplary embodiments of the present invention.
20 is a schematic block diagram illustrating an electronic system including a semiconductor memory device according to exemplary embodiments of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, only this embodiment allows the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, 'comprises' and/or 'comprising' refers to the presence of one or more other components, steps, operations and/or elements mentioned. or addition is not excluded. Also, in this specification, when a certain film is referred to as being on another film or substrate, it means that it may be directly formed on the other film or substrate, or a third film may be interposed therebetween.

Further, the embodiments described herein will be described with reference to cross-sectional and/or plan views, which are ideal illustrative views of the present invention. In the drawings, thicknesses of films and regions are exaggerated for effective description of technical content. Accordingly, the form of the illustrative drawing may be modified due to manufacturing technology and/or tolerance. Accordingly, the embodiments of the present invention are not limited to the specific form shown, but also include changes in the form generated according to the manufacturing process. For example, the etched region shown at a right angle may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the drawings have a schematic nature, and the shapes of the regions illustrated in the drawings are intended to illustrate specific shapes of regions of the device and not to limit the scope of the invention.

Hereinafter, a semiconductor memory device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the drawings.

1 is a schematic plan view illustrating a semiconductor memory device according to exemplary embodiments of the present invention. FIG. 2 is a schematic cross-sectional view illustrating exemplary embodiments of a semiconductor memory device of the present invention, and is a cross-sectional view taken along line I-I' of FIG. 1 . 3 is an enlarged view of part A of FIG. 2 . FIG. 4 is a schematic plan view illustrating a part of a semiconductor memory device including the semiconductor patterns shown in FIG. 2 . 5A and 5B are schematic cross-sectional views illustrating the semiconductor patterns shown in FIG. 2;

1 to 5 , in a semiconductor memory device according to exemplary embodiments of the present invention, a stack including insulating layers 110 and gate electrodes 172 alternately and repeatedly stacked on a substrate 100 . The structures 30 and the vertical channel structures 200 passing through each of the stacked structures 30 and spaced apart from each other in the first direction D1 parallel to the upper surface of the substrate 100 may be included. The vertical channel structures 200 may extend on the substrate 100 in a third direction D3 perpendicular to the top surface of the substrate 100 .

The substrate 100 may include a semiconductor material. For example, the substrate 100 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon-germanium single crystal substrate. According to some embodiments, the substrate 100 may be a semiconductor on insulator (SOI) substrate. For example, the substrate 100 may include a semiconductor layer (eg, a silicon layer, a silicon-germanium layer, or a germanium layer) disposed on an insulating layer that protects transistors provided on the semiconductor substrate. The substrate 100 may be a semiconductor substrate of the first conductivity type (eg, P-type).

As shown in FIG. 1 , each of the stack structures 30 may have a line shape that crosses the first direction D1 and extends in the second direction D2 parallel to the upper surface of the substrate 100 . For example, the insulating layers 110 and the gate electrodes 172 included in each of the stack structures 30 may be line patterns extending in the second direction D2 . A plurality of insulating layers 110 may be stacked on the substrate 100 in the third direction D3 . The insulating layers 110 may include, for example, first to seventh insulating layers 110a, 110b, 110c, 110d, 110e, 110f, and 110g, but is not limited thereto. According to some embodiments, eight or more insulating layers 110 may be stacked on the substrate 100 . Some of the insulating layers 110 may have different thicknesses. For example, the thickness of the first insulating layer 110a, which is the lowest insulating layer, may be thinner than that of the second to seventh insulating layers 110b to 100g. The second, sixth, and seventh insulating layers 110b, 110f, and 110g may be formed to be thicker than the third to fifth insulating layers 110c, 100d, and 100e. The insulating layers 110 may include silicon oxide.

Each of the gate electrodes 172 may be stacked in plurality in the third direction D3 . The gate electrodes 172 may include, for example, first to sixth gate electrodes 172a, 172b, 172c, 172d, 172e, and 172f, but is not limited thereto. According to some embodiments, seven or more layers of gate electrodes 172 may be stacked on the substrate 100 . The gate electrodes 172 may include control gate electrodes of memory cells included in a semiconductor memory device (eg, a vertical NAND flash memory device). For example, the second to fifth gate electrodes 172b to 172e between the sixth gate electrode 172f as the uppermost gate electrode and the first gate electrode 172a as the lowermost gate electrode are control gate electrodes or It can be used as a word line connected to the control gate electrode. The gate electrodes 172 may be combined with the vertical channel structures 200 to form a plurality of memory cell strings. Accordingly, each of the memory cell strings may include memory cells arranged on the substrate 100 in the third direction D3 .

The first gate electrode 172a and the sixth gate electrode 172f may be used as gate electrodes of the selection transistors GST and SST. For example, the sixth gate electrode 172f is used as a gate electrode of the string select transistor SST for controlling the electrical connection between the bit line (not shown) and the vertical channel structures 200 , and the first gate electrode ( The 172a may be used as a gate electrode of the ground select transistor GST for controlling an electrical connection between the common source region 158 and the vertical channel structures 200 formed on the substrate 100 .

The gate electrodes 172 may surround the vertical channel structures 200 . Each of the gate electrodes 172 may have first and second ends 172 - TE1 and 172 - TE2 spaced apart from each other in the first direction D1 . The gate electrodes 172 may have substantially the same thickness and shape. A thickness of each of the gate electrodes 172 may vary according to a horizontal position. For example, each of the gate electrodes 172 may have a first thickness T1 in a region adjacent to the ends 172 - TE1 and 172 - TE2 and a second thickness ( T1 ) in a region between the vertical channel structures 200 . T2) may have. Each of the gate electrodes 172 may have a first thickness T1 in a portion of a region between the vertical channel structures 200 . The first thickness T1 may be greater than the second thickness T2 .

Each of the gate electrodes 172 may include a gate conductive layer. The gate conductive layer may include, for example, a metal silicide layer, a metal layer, a metal nitride layer, or a combination thereof. For example, the metal silicide layer may include cobalt silicide, titanium silicide, tungsten silicide, or tantalum silicide. The metal layer may include, for example, tungsten, nickel, cobalt, titanium, or tantalum. The metal nitride layer may include, for example, titanium nitride, tungsten nitride, or tantalum nitride.

The vertical channel structures 200 may pass through each of the stack structures 30 to be electrically connected to the substrate 100 . Referring to FIG. 1 , the vertical channel structures 200 included in each of the stack structures 30 may be arranged along a first column (①) and a second column (②) in the second direction D2. . The first vertical channel structure 200a of the first column (①) may be disposed to be spaced apart from the second vertical channel structure 200b of the second column (②) in the first direction D1. The vertical channel structures 200 may be arranged in a zigzag manner.

Additionally, the first and second vertical channel structures 200a and 200b of the first column (①) and the second column (②) are adjacent to each other in the first direction D1 in the third column (③) and the fourth column (②) Third and fourth vertical channel structures 200c and 200d in the column ④ may be further disposed. The first and third vertical channel structures 200a and 200c may be symmetrically disposed in the first direction D1 with respect to the second vertical channel structures 200b. The second and fourth vertical channel structures 200b and 200d may be symmetrically disposed in the first direction D1 with respect to the third vertical channel structures 200c. A plurality of vertical channel structures 200 arranged in four columns may form a group and may be repeatedly disposed in the first direction D1 with the common source region 158 interposed therebetween. According to some embodiments, the vertical channel structures 200 are not limited to being arranged in 4 columns, but may be arranged in a different number of columns (eg, 4 or less or 4 or more columns).

Each of the vertical channel structures 200 may include a semiconductor pattern 126 , an information storage pattern 130 , a vertical channel pattern 140 , and a buried insulating pattern 144 . The information storage pattern 130 , the vertical channel pattern 140 , and the buried insulating pattern 144 may be disposed on the semiconductor pattern 126 .

Each of the semiconductor patterns 126 may extend into the substrate 100 . A portion of each of the semiconductor patterns 126 may be embedded in the substrate 100 , and another portion thereof may have a pillar shape vertically protruding from the substrate 100 . The semiconductor patterns 126 may be disposed under the stack structure 30 . For example, the top surface of the semiconductor pattern 126 may be positioned at a higher level than the top surface of the first gate electrode 172a. Each of the semiconductor patterns 126 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V semiconductor compound, and/or a group II-VI semiconductor compound. The semiconductor patterns 126 may be epitaxial layers including single crystal silicon. The semiconductor patterns 126 may be patterns undoped with impurities or patterns doped with impurities having the same conductivity type as that of the substrate 100 .

The semiconductor patterns 126 may include a first semiconductor pattern 126 - 1 and a second semiconductor pattern 126 - 2 arranged side by side in the first direction D1 . The first semiconductor pattern 126 - 1 may be horizontally adjacent to the trench 154 , and the second semiconductor pattern 126 - 2 may be horizontally distant from the trench 154 . For example, as shown in FIG. 4 , the separation distance SL1 between the first semiconductor pattern 126 - 1 and the trench 154 is the spacing between the second semiconductor pattern 126 - 2 and the trench 154 . It may be shorter than the distance SL2. According to some embodiments, the first semiconductor pattern 126 - 1 corresponds to the first vertical structures 200a in the first column (①) and the fourth vertical structures 200d in the fourth column (④). and the second semiconductor pattern 126 - 2 may correspond to the second vertical structures 200a in the second column (②) and the third vertical structures 200d in the third column (③).

The semiconductor patterns 126 may include recessed sidewalls 126a. For example, each of the recessed sidewalls 126a of the semiconductor patterns 126 may include a first recessed sidewall 126a1 and a second recessed sidewall 126a2 facing each other in the first direction D1 . can do. The first recess sidewall 126a1 may be proximal to the trench 180 , and the second recess sidewall 126a2 may be remote from the trench 180 . 5A and 5B , the first recess sidewall 126a1 and the second recess sidewall 126a2 of the first semiconductor pattern 126 - 1 may have substantially the same maximum recess depth X3. can The first sidewall 126a1 and the second sidewall 126a2 of the second semiconductor pattern 126 - 2 may have different maximum recess depths. The maximum recess depth X3 of the first sidewall 126a1 of the second semiconductor pattern 126 - 2 may be greater than the maximum recess depth X2 of the second sidewall 126a2 . A difference between the maximum recess depths X3 and x2 of the first and second recess sidewalls 126a1 and 126a2 of the second semiconductor pattern 126 - 2 may be about 10 Å to about 60 Å.

The first and second recess sidewalls 126a1 and 126a2 of the first semiconductor pattern 126 - 1 and the first recess sidewall 126a1 of the second semiconductor pattern 126 - 2 have substantially the same maximum recess It may have a depth (X3).

The first and second recess sidewalls 126a1 and 126a2 of the first semiconductor pattern 126 - 1 may have substantially the same height H3 . A height H3 of the first recess sidewall 126a1 of the second semiconductor pattern 126 - 2 may be greater than a height H2 of the second recess sidewall 126a2 .

Each of the semiconductor patterns 126 may have a minimum width. The minimum width of each of the semiconductor patterns 126 may correspond to the minimum width between the recessed sidewalls 126a of each of the semiconductor patterns 126 . A minimum width of some semiconductor patterns 126 may be different from a minimum width of other semiconductor patterns 126 . For example, the first semiconductor pattern 126 - 1 and the second semiconductor pattern 126 - 2 may have different minimum widths. The first minimum width W1 of the first semiconductor pattern 126 - 1 may be smaller than the second minimum width W2 of the second semiconductor pattern 126 - 2 . For example, the difference between the first minimum width W1 of the first semiconductor pattern 126 - 1 and the minimum width W2 of the second semiconductor pattern 126 - 1 is the width of the second semiconductor pattern 126 - 2 . It may be substantially equal to a difference between the maximum recess depth X2 of the first sidewall 126a1 and the maximum recess depth X3 of the second sidewall 126a2 of the second semiconductor pattern 126-2. Upper portions of the first and second semiconductor patterns 126 - 1 and 126 - 2 may each have a maximum width W3. For example, each of the first and second semiconductor patterns 126 - 1 and 126 - 2 may have a maximum width W3 between upper sidewalls 126b in contact with the second insulating layer 110b. .

Referring to FIG. 4 , in the second direction D2 , the first semiconductor pattern 126 - 1 is adjacent to each other and is disposed between the upper sidewall 126b and the upper sidewall 126b of the second semiconductor pattern 126 - 2 . The second distance HD2 between the recess sidewall 126a of the first semiconductor pattern 126 - 1 and the recess sidewall 126a of the second semiconductor pattern 126 - 2 may be greater than the distance HD1 . . Accordingly, the width of the space in which the first gate electrode 172a is formed between the first semiconductor pattern 126 - 1 and the second semiconductor pattern 126 - 2 may be increased. The third distance HD3 between the recess sidewalls 126a of the adjacent second semiconductor patterns 126 - 2 in the second direction D2 may be shorter than the second distance HD2, but is not limited thereto. According to some embodiments, the third distance HD3 may be substantially equal to the second distance HD2 .

A gate oxide layer 164 may be disposed on the recess sidewall 126a of each of the semiconductor patterns 126 . The gate oxide layer 164 may be disposed between the first gate electrode 172a and the semiconductor patterns 126 . The gate oxide layer 164 may include, for example, silicon oxide.

The first gate electrode 172a has substantially the same first thickness T1 in a portion adjacent to the first and second sidewalls 126a1 and 126a2 of the first semiconductor pattern 126 - 1 , and the second semiconductor pattern The second semiconductor pattern 126 - 2 has a first thickness T1 close to the first sidewall 126a1 and a second thickness T2 close to the second sidewall 126a2 of the second semiconductor pattern 126 - 2 . can The first thickness T1 may be thicker than the second thickness T2 . A horizontal distance L1 between the sidewall 126a of the recess of the first semiconductor pattern 126 - 1 and the first end 172 - TE1 of the first gate electrode 172a is a distance L1 of the second semiconductor pattern 126 - 1 . The horizontal distance L2 between the recess sidewall 126a and the end 172 - TE2 of the first gate electrode 172a may be shorter than the horizontal distance L2.

Each of the vertical channel patterns 140 extending in the third direction D3 may be disposed on each of the semiconductor patterns 126 . The semiconductor patterns 126 and the vertical channel patterns 140 may be connected to each other, respectively. For example, a first vertical channel pattern 140-1 is disposed on the first semiconductor pattern 126-1, and a second vertical channel pattern 140-2 is disposed on the second semiconductor pattern 126-2. This can be placed

Each of the vertical channel patterns 140 may be disposed between the information storage pattern 130 and the buried insulating pattern 144 . Each of the vertical channel patterns 140 may have an open top and a hollow macaroni shape. According to some embodiments, each of the vertical channel patterns 140 may have a shape in which an upper end and a lower end are turned off. According to some embodiments, each of the vertical channel patterns 140 may have a cylindrical shape without the filling insulating pattern 144 . Each of the vertical channel patterns 140 may be a pattern including a polycrystalline semiconductor material, an amorphous semiconductor material, or a single crystal semiconductor material. For example, each of the vertical channel patterns 140 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V semiconductor compound, and/or a group II-VI semiconductor compound. For example, each of the vertical channel patterns 140 may include polycrystalline silicon. Each of the vertical channel patterns 140 may include an undoped semiconductor material or a semiconductor material doped with an impurity having the same conductivity type as that of the substrate 100 .

The information storage pattern 130 may be disposed between each of the stacked structures 30 and each of the vertical channel patterns 140 . The information storage pattern 130 may have an open top and an open bottom. The information storage pattern 130 may include a thin film for storing data. For example, data stored in the information storage pattern 130 may perform Fowler-Nordheim tunneling caused by a voltage difference between each of the vertical channel structures 200 and the gate electrodes 172 . may be changed using, but is not limited thereto. According to some embodiments, the information storage pattern 130 includes a thin film (eg, a thin film for a phase change memory device or a thin film for a variable resistance memory device) capable of storing data based on a different operating principle. You may.

Referring to FIG. 3 , the information storage pattern 130 includes a first blocking insulating layer 132 adjacent to the gate electrodes 172 , a tunnel insulating layer 136 adjacent to each of the vertical channel patterns 140 , and a space therebetween. A charge storage layer 134 may be included. The tunnel insulating layer 136 may be, for example, a silicon oxide layer. The charge storage layer 134 may be a trap insulating layer or an insulating layer including conductive nano dots. The trap insulating layer may include, for example, silicon nitride. The first blocking insulating layer 132 may include a silicon oxide layer and/or a high-k layer (eg, an aluminum oxide layer or a hafnium oxide layer). The first blocking insulating layer 132 may be formed of a single layer or a plurality of thin films. For example, the first blocking insulating layer 132 may be a single layer including a silicon oxide layer. For example, the first blocking insulating layer 132 may include a plurality of thin films including an aluminum oxide layer and/or a hafnium oxide layer.

A second blocking insulating layer 168 may be additionally provided between each of the stacked structures 30 and the vertical channel structures 200 to extend between the insulating layers 110 and the gate electrodes 172 . For example, the second blocking insulating layer 168 may extend substantially horizontally with respect to the substrate 100 to cover upper and lower surfaces of the gate electrodes 172 . The second blocking insulating layer 168 may be formed of a single layer or a plurality of thin films. The second blocking insulating layer 168 may include a high dielectric layer (eg, an aluminum oxide layer or a hafnium oxide layer). According to some embodiments, the second blocking insulating layer 168 may not be formed.

The buried insulating pattern 144 may be disposed inside each of the vertical channel patterns 140 . The buried insulating pattern 144 may include a silicon oxide layer or a silicon nitride layer.

Each of the conductive pads 128 may be disposed on top of each of the vertical channel structures 200 . For example, each of the conductive pads 128 may be connected to each of the vertical channel patterns 140 and disposed on top of each of the conductive pads 128 . Each of the conductive pads 128 may include a conductive material. For example, each of the conductive pads 128 may include polysilicon or amorphous silicon. According to some embodiments, each of the conductive pads 128 may be an impurity region doped with an impurity. An upper end of each of the vertical channel patterns 200 in contact with each of the conductive pads 128 may be a drain region. Each of the conductive pads 128 may be connected to a bit line (not shown).

A capping insulating layer 152 may be disposed on each of the stacked structures 30 to cover the conductive pads 128 . The capping insulating layer 152 may be formed of a silicon oxide layer.

A trench 154 separating the stacked structures 30 from each other may be provided on the substrate 100 . For example, a trench 154 separating vertical channel structure groups including four columns of vertical channel structures 200 arranged in the first direction D1 may be provided. The trench 154 may extend in the second direction D2 . The trench 154 may extend vertically from the top surface of the capping insulating layer 152 to the top surface of the substrate 100 . According to some embodiments, the trench 154 may extend to a predetermined depth into the substrate 100 .

The common source region 158 may be disposed in the substrate 100 between the stack structures 30 . For example, the common source region 158 may be formed in the substrate 100 exposed to the trench 150 and may extend along the second direction D2 . The common source region 158 may be a conductive impurity region. The common source region 158 may include an impurity of a second conductivity type different from that of the substrate 100 . For example, the common source region 158 may include an N-type impurity such as arsenic (As) or phosphorus (P).

A common source plug 180 may be disposed on the common source region 158 . The common source plug 180 may be disposed in the trench 154 and may be connected to the common source region 158 . The common source plug 180 may reduce the resistance of the common source region 158 . The common source plug 180 may extend along the second direction D2 in the form of a line. According to some embodiments, the common source plug 180 may have an island shape and may be disposed in plurality along the second direction D2 . The common source plug 180 may include a conductive material. The common source plug 180 may include, for example, polysilicon or a metal (eg, tungsten or copper).

The isolation insulating layer 178 may be disposed between the stacked structures 30 and the common source plug 180 . For example, the isolation insulating layer 178 may be disposed between the gate electrodes 172 and the common source plug 180 . The isolation insulating layer 178 may protect the ends 172 - TE1 and 172 - TE2 of the gate electrodes 172 . The isolation insulating layer 178 may include an oxide layer.

6 to 8 , 10 , 11 , 14 , 17 and 18 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to exemplary embodiments of the present invention shown in FIGS. 1 to 4 . For example, they are cross-sectional views taken along line II′ of FIG. 1 . 9 is an enlarged view of part B of FIG. 8 . Fig. 12 is a schematic plan view at the height of G in Fig. 11; 13 is an enlarged view of part G of FIG. 11 . Fig. 15 is a schematic plan view at the height of G' in Fig. 14; FIG. 16 is an enlarged view of a portion G′ of FIG. 14 .

Referring to FIG. 6 , the molding structure 10 may be formed on the substrate 100 . For example, the molding structure 10 may be formed by alternately repeatedly stacking insulating layers 110 and sacrificial layers 112 on the substrate 100 . Each of the insulating layers 110 and the sacrificial layers 112 may be formed in a plurality of layers. The insulating layers 110 may include, for example, first to seventh insulating layers 110a, 110b, 110c, 110d, 110e, 110f, and 110g, but is not limited thereto. According to some embodiments, eight or more insulating layers 110 may be stacked on the substrate 100 . The sacrificial layers 112 may be stacked on the substrate 100 and disposed between the insulating layers 112 , respectively. The sacrificial layers 112 may include, for example, first to sixth sacrificial layers 112a, 112b, 112c, 112d, 112e, and 112f, but is not limited thereto. According to some embodiments, seven or more sacrificial layers 112 may be stacked on the substrate 100 .

The substrate 100 may include a semiconductor material. For example, the substrate 100 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon-germanium single crystal substrate. According to some embodiments, the substrate 100 may be a semiconductor on insulator (SOI) substrate. For example, the substrate 100 may include a semiconductor layer (eg, a silicon layer, a silicon-germanium layer, or a germanium layer) disposed on an insulating layer that protects transistors provided on the semiconductor substrate. The substrate 100 may be a semiconductor substrate of the first conductivity type (eg, P-type).

The sacrificial layers 112 may be formed of a material having etch selectivity with respect to the insulating layers 110 . For example, the sacrificial layers 112 may have higher etch selectivity compared to the insulating layers 110 in a wet etching process using a chemical solution. For example, the insulating layers 110 may be a silicon oxide layer or a silicon nitride layer, and the sacrificial layers 112 are selected from a silicon oxide layer, a silicon nitride layer, silicon carbide, silicon, or silicon germanium. It may be a material having an etch selectivity with respect to the etchant. For example, the insulating layers 110 may be silicon oxide layers and the sacrificial layers 112 may be silicon nitride layers.

The sacrificial layers 112 may be formed using a thermal CVD process, a plasma enhanced CVD process, or an atomic layer deposition (ALD) process. The first to sixth sacrificial layers 112a to 112f may have substantially the same thickness. The insulating layers 112 may be formed using a thermal oxidation process, a thermal chemical vapor deposition process, a plasma enhanced CVD process, or an atomic layer deposition (ALD) process. can

According to some embodiments, some of the insulating layers 110 may have different thicknesses. For example, the first insulating layer 110a in contact with the substrate 100 may be formed thinner than the second to seventh insulating layers 110a to 110f. The second insulating layer 110b, the seventh insulating layer 110g, and the sixth insulating layer 110f may be formed to be thicker than the third to fifth insulating layers 110c, 110d, and 110e or the sacrificial layers 112. .

Referring to FIG. 7 , channel holes 120 penetrating through the molding structure 10 and exposing the substrate 100 may be formed.

The channel holes 120 may be formed by anisotropically etching the molding structure 10 . The channel holes 120 may be two-dimensionally arranged like the vertical channel structures 200 shown in FIG. 1 . For example, the channel holes 120 arranged in four columns each forming a column in the second direction D2 may form a group, and these groups may be arranged to be spaced apart from each other in the first direction D1 . The channel holes 120 may be arranged in 4 rows, but is not limited thereto, and may be arranged in 4 or less rows or 4 or more rows. When the channel holes 120 are formed, the substrate 100 may be over-etched and recessed.

8 and 9 , vertical channel structures 200 passing through the molding structure 10 on the substrate 100 and extending in the third direction D3 perpendicular to the substrate 100 are formed. can Each of the vertical channel structures 200 may fill each of the channel holes 120 and extend into the substrate 100 . Each of the vertical channel structures 200 may include a semiconductor pattern 126 , an information storage pattern 130 , a vertical channel pattern 140 , and a buried insulating pattern 144 .

The semiconductor pattern 126 may fill the recessed substrate 100 and may be formed to vertically protrude above the substrate 100 in a pillar shape. The semiconductor pattern 126 may fill the lower portions of each of the channel holes 120 . For example, each of the semiconductor patterns 126 is in contact with a side surface of the first insulating layer 110a and a side surface of the first sacrificial layer 112a of the molding structure 10 , and is in contact with a side surface of the second insulating layer 110b. so as to protrude above the substrate 100 . A top surface of the semiconductor pattern 126 may be lower than a top surface of the second insulating layer 110b. The semiconductor pattern 126 may be, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), or group III-V. compound, and/or a group II-VI compound. The semiconductor pattern 126 may be formed by selective epitaxial growth (SEG). The semiconductor pattern 126 may include impurities of the same conductivity type as that of the substrate 100 . For example, when the semiconductor pattern 126 is formed by selective epitaxial growth, impurities may be doped in-situ. Alternatively, impurities may be ion-implanted into the semiconductor pattern 126 .

Subsequently, the information storage pattern 130 passing through the molding structure 10 , the vertical channel pattern 140 , and the buried insulating pattern 144 may be formed on the semiconductor pattern 126 on the substrate 100 .

The information storage pattern 130 may cover the inner wall of each of the channel holes 120 . For example, the information storage pattern 130 may be formed in the form of a spacer on the inner wall of each of the channel holes 120 . The information storage pattern 130 may have an open top and an open bottom. The information storage pattern 130 may contact the insulating layers 110 and the sacrificial layers 112 of the molding structure 10 . The information storage pattern 130 may include a thin film capable of storing data. For example, the information storage pattern 130 may include a thin film capable of storing data using Fowler-Nordheim tunneling, but is not limited thereto. According to some embodiments, the information storage pattern 130 includes a thin film (eg, a thin film for a phase change memory device or a thin film for a variable resistance memory device) capable of storing data based on a different operating principle. can do. The information storage pattern 130 may be formed of a plurality of thin films.

The information storage pattern 130 may include, for example, a first blocking insulating layer 132 , a charge storage layer 134 , and a tunnel insulating layer 136 as shown in FIG. 9 . The first blocking insulating layer 132 , the charge storage layer 134 , and the tunnel insulating layer 136 may be sequentially formed on inner walls of each of the channel holes 120 . The first blocking insulating layer 132 may include a silicon oxide layer and/or a high-k layer (eg, an aluminum oxide layer or a hafnium oxide layer). The first blocking insulating layer 132 may be formed of a single layer or a plurality of thin films. According to some embodiments, the first blocking insulating layer 132 may be formed of a single layer including a silicon oxide layer. According to other embodiments, it may be formed of a plurality of thin films including a silicon oxide film, an aluminum oxide film, and/or a hafnium oxide film.

The charge storage layer 134 may be a trap insulating layer or an insulating layer including conductive nano dots. The trap insulating layer may include, for example, a silicon nitride layer. The first blocking insulating layer 132 and the charge storage layer 134 may be formed using a plasma enhanced CVD process or an atomic layer deposition (ALD) process.

The tunnel insulating layer 136 may be in contact with the vertical channel pattern 140 . The tunnel insulating layer 136 may be, for example, a silicon oxide layer. The tunnel insulating layer 136 may be formed using a plasma enhanced CVD process, an atomic layer deposition (ALD) process, or a thermal oxidation process.

The vertical channel pattern 140 may be connected to the semiconductor pattern 126 and may be formed in contact with the information storage pattern 130 . The vertical channel pattern 140 may be conformally formed in a liner shape inside each of the channel holes 120 to extend in the third direction D3 . The vertical channel pattern 140 may have an open top and a hollow macaroni shape. According to some embodiments, the vertical channel pattern 140 may have an upper end and a lower end turned off. According to some embodiments, the vertical channel pattern 140 may have a cylindrical shape filling each of the channel holes 120 without the buried insulating pattern 144 . The vertical channel pattern 140 may include a semiconductor material. For example, the vertical channel pattern 140 may include a polycrystalline semiconductor material, an amorphous semiconductor material, or a single crystal semiconductor material. The vertical channel pattern 140 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, and/or a group II-VI compound. The vertical channel pattern 140 may be an undoped semiconductor material that does not include impurities or a semiconductor material that includes impurities having the same conductivity type as that of the substrate 100 . The vertical channel pattern 140 may be formed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or an epitaxial growth process.

The filling insulation pattern 144 may be formed to fill the inside of each of the channel holes 120 in which the vertical channel pattern 140 is formed. The buried insulating pattern 144 may include a silicon oxide layer or a silicon nitride layer. Crystal defects that may exist in the vertical channel pattern 140 may be healed by further performing a hydrogen annealing process before forming the buried insulating pattern 144 .

Each of the conductive pads 128 may be formed on top of each of the vertical channel structures 200 . For example, each of the conductive pads 128 recesses an upper portion of each of the vertical channel pattern 140 and the buried insulating layer 144 of the vertical channel structures 200 , and deposits a conductive material in the recessed region. It can be formed by filling. Each of the conductive pads 128 may include, for example, polysilicon or amorphous silicon. According to some embodiments, each of the conductive pads 128 may be formed by implanting impurities into the vertical channel pattern 140 .

A capping insulating layer 152 may be formed on the seventh insulating layer 110g to cover the conductive pads 128 . The capping insulating layer 152 may include, for example, silicon oxide.

Referring to FIG. 10 , a trench 154 exposing the substrate 100 between the vertical channel structures 200 by patterning the capping layer 152 and the molding structure 10 , and the substrate exposed to the trench 154 . A common source region 158 may be formed in 100 . For example, the trench 154 may be formed by anisotropically etching the capping layer 152 and the molding structure 10 . Accordingly, the molding structure pattern 20 may be formed. For example, as shown in FIG. 1 , the trench 154 includes vertical channel structure groups each including four columns of vertical channel structures 200 each forming a column in the second direction D2 in the first direction D1 . ) can be separated from According to some embodiments, the trench 154 may separate vertical channel structure groups each including four or less or four or more columns of vertical channel structures 200 in the first direction D1 . The trench 154 may extend in the second direction D2 . The semiconductor patterns 126 may be divided into a first semiconductor pattern 126 - 1 and a second semiconductor pattern 126 - 2 by the trench 154 . In the first direction D1 , the first semiconductor pattern 126 - 1 is horizontally and relatively close to the trench 154 , and the second semiconductor pattern 126 - 2 is horizontally from the trench 154 . It may be a pattern arranged relatively far away from each other. For example, the separation distance SL1 between the first semiconductor pattern 126 - 1 and the trench 154 in the first direction D1 is the spacing between the second semiconductor pattern 126 - 2 and the trench 154 . It may be shorter than the distance SL2. The vertical channel patterns 140 may also be divided into a first vertical channel pattern 140 - 1 and a second vertical channel pattern 140 - 2 . The first vertical channel pattern 140 - 1 may be connected to the first semiconductor pattern 126 - 1 , and the second vertical panel pattern 140 - 2 may be connected to the second semiconductor pattern 126 - 2 .

The common source region 158 may be formed by ion-implanting an N-type impurity such as arsenic (As) or phosphorus (P) into the substrate 100 exposed through the trench 154 .

11 to 13 , first opening regions 160 may be formed in the molding structure pattern 20 . A portion of the sacrificial layers 112 exposed in the trench 154 may be removed to form first opening regions 160 between the insulating layers 110 . Sacrificial layer patterns 112PP may remain in a region between the vertical channel structures 200 . For example, when the sacrificial layers 112 are silicon nitride layers and the insulating layers 110 are silicon oxide layers, a portion of the sacrificial layers 112 is isotropically etched using an etchant containing phosphoric acid to form a first opening region. Fields 160 may be formed, and sacrificial layer patterns 112PP spaced apart from the trench 154 by a horizontal distance ED may be formed as shown in FIG. 12 . The sacrificial layer patterns 112PP are disposed between the vertical channel structures 200 and may cover some sidewalls of the vertical channel structures 200 distant from the trench 154 . The first opening regions 160 may completely expose some sidewalls of each of the vertical channel structures 200 adjacent to the trench 154 in the first and second directions D1 and D2 . The first opening regions 160 may expose some sidewalls adjacent to the trench 154 among some sidewalls of each of the vertical channel structures 200 distal from the trench 154 . For example, the vertical channel structures 200 close to the trench 154 are the first vertical structures 200a in the first column (①) and the fourth vertical structure in the fourth column (④) shown in FIG. 1 . The vertical channel structures 200 far from the trench 154 are the second vertical structures 200a in the second row (②) and the third vertical structures 200d in the third row (③). ) can be

Sidewalls of the first semiconductor pattern 126 - 1 may be completely exposed by the first opening regions 160 , and a portion of sidewalls of the second semiconductor pattern 126 - 2 may be exposed. Sidewalls of the semiconductor patterns 126 exposed in the first opening regions 160 may be etched and recessed. At this time, the insulating layers 110 may also be partially etched to reduce their thickness. The sidewalls of the semiconductor patterns 126 and the insulating layers 110 may be etched by an isotropic etching process. For example, the isotropic etching process may be a wet etching process using SC1 or ammonia. The insulating layers 110 may be removed by, for example, the first etch thickness VT. The etched sidewalls of the semiconductor patterns 126 may have a rounded shape. For example, a recess region having a maximum etch depth X1 and a first height H1 on sidewalls of the first semiconductor pattern 126 - 1 and some sidewalls of the second semiconductor pattern 126 - 2 . RA may be formed.

14 to 16 , second opening regions 162 may be formed by removing the sacrificial layer patterns 112PP. The sacrificial layer patterns 112PP may be removed in the same process as the etching process of the sacrificial layer patterns 112 for forming the first opening regions 160 to form the second opening regions 162 . For example, the sacrificial layer patterns 112PP may be removed by isotropic etching using an etchant including phosphoric acid. The first and second opening regions 160 and 162 extend in the first and second directions D1 and D2 and may completely expose some sidewalls of each of the vertical channel structures 200 . For example, some sidewalls of the first blocking insulating layer ( 132 of FIG. 9 ) of each information storage pattern 130 of the vertical channel structures 200 by the first and second opening regions 160 and 162 . And some sidewalls of the second semiconductor pattern 126 - 2 may be exposed.

A sidewall of the second semiconductor pattern 126 - 2 exposed to the second opening regions 162 may be recessed. For example, the sidewall of the second semiconductor pattern 126 - 2 exposed to the second opening regions 162 may be isotropically etched to a maximum recess depth X2. The isotropic etching may be performed by, for example, a wet etching process using SC1 or ammonia. At this time, the etched sidewalls of the first semiconductor pattern 126 - 1 exposed to the first opening regions 160 and the etched sidewalls of the second semiconductor pattern 126 - 2 are also to be further recessed by a depth X2 . can Accordingly, a first recess sidewall 126a1 and a second recess sidewall 126a2 may be formed in each of the semiconductor patterns 126 . The first and second recess sidewalls 126a1 and 126a2 of each of the semiconductor patterns 126 may have a rounded shape.

Referring to FIG. 16 , the first and second recess sidewalls 126a1 and 126a2 of the first semiconductor pattern 126 - 1 may have substantially the same maximum recess depth X3 . The first recess sidewall 126a1 of the second semiconductor pattern 126-2 has a maximum recess depth substantially equal to the first and second sidewalls 126a1 and 126a2 of the first semiconductor pattern 126-1. X3) may have. The second recess sidewall 126a2 of the second semiconductor pattern 126 - 2 may have a smaller maximum recess depth X2 than the first sidewall 126a1 . For example, the difference between the maximum recess depths X2 and X3 of the first and second recess sidewalls 126a1 and 126a2 of the second semiconductor pattern 126 - 2 may be about 10 Å to about 60 Å. have.

The minimum width W1 of the first semiconductor pattern 126 - 1 may be smaller than the minimum width W2 of the second semiconductor pattern 126 - 2 . The minimum width W1 of the first semiconductor pattern 126 - 1 may be a width between the first and second recess sidewalls 126a1 and 126a2 recessed to the maximum recess depth X3 . The minimum width W2 of the second semiconductor pattern 126 - 2 may be a width between the first and second recess sidewalls 126a1 and 126a2 recessed to the maximum recess depths X3 and X2 .

It may have a maximum width between the upper sidewalls 126b of each of the first and second semiconductor patterns 126 - 1 and 126 - 2 . The upper sidewalls 126b of each of the first and second semiconductor patterns 126 - 1 and 126 - 2 may contact the second insulating layer 110b. The first and second recess sidewalls 126a1 and 126a2 of the first semiconductor pattern 126 - 1 may have substantially the same height H3 . The first recess sidewall 126a1 of the second semiconductor pattern 126-2 has a height H3 substantially equal to that of the first and second sidewalls 126a1 and 126a2 of the first semiconductor pattern 126-1. and the second recess sidewall 126a2 of the second semiconductor pattern 126 - 2 may have a height H2 smaller than that of the first sidewall 126a1 .

As a result, as shown in FIG. 15 , the upper sidewalls 126b of the first and second semiconductor patterns 126 - 1 and 126 - 2 adjacent to each other in the second direction D2 are at least a first distance HD1 . ), the recess sidewalls 126a of the semiconductor patterns 126 - 1 and 126 - 2 may be spaced apart from each other by at least a second distance HD2 greater than the first distance HD1 . The recess sidewalls 126a of the second semiconductor patterns 126 - 2 adjacent to each other in the second direction D2 may be spaced apart from each other by at least a third distance HD3 . Accordingly, the first opening region 160 between the first and second semiconductor patterns 126 - 1 and 126 - 2 adjacent to each other in the second direction D2 is at least a second width greater than the first distance HD1 . It may be formed to have a width of 2 distances HD2. The second opening region 162 between the recess sidewalls 126a of the second semiconductor patterns 126 - 2 adjacent to each other in the second direction D2 may be formed to have a width of at least the third distance HD3. have. The second distance HD2 may be greater than the third distance HD3 , but may not be limited thereto. According to some embodiments, the second distance HD2 may be substantially equal to the third distance HD3 .

When the semiconductor patterns 126 are recessed, the insulating layers 110 exposed in the first and second opening regions 160 and 162 may also be further etched, but is not limited thereto. According to some embodiments, the insulating layers 110 may not be etched. As a result, each of the insulating layers 110 may have a greater thickness in the region between the vertical channel structures 200 than in the region adjacent to the trench 154 . Accordingly, the vertical widths of the first and second opening regions 160 and 162 may be further expanded.

Referring to FIG. 17 , a gate oxide layer 164 may be formed on the recess sidewalls 126a of the semiconductor patterns 126 . For example, the gate oxide layer 164 may be formed by a thermal oxidation process. The gate oxide layer 164 may be used as a gate oxide layer of the ground selection transistor.

A second blocking insulating layer 168 and a gate conductive layer 171 may be formed to fill the first and second opening regions 160 and 162 . The second blocking insulating layer 168 may be formed to conformally cover inner walls of the first and second opening regions 160 . For example, the second blocking insulating layer 168 may be in contact with the top and bottom surfaces of the insulating layers 110 , respectively. The second blocking insulating layer 168 may contact sidewalls of the vertical channel structures 200 . For example, the second blocking insulating layer 168 may be in contact with the first blocking insulating layer 132 of FIG. 9 . Also, the second blocking insulating layer 168 may contact the gate oxide layers 164 on the semiconductor patterns 126 . The second blocking insulating layer 168 may include a high dielectric layer (eg, an aluminum oxide layer or a hafnium oxide layer). According to some embodiments, the second blocking insulating layer 168 is not formed and may be omitted.

The gate conductive layer 171 may be formed to fill the first to second opening regions 160 and 162 in which the second blocking insulating layer 168 is formed. The gate conductive layer 171 may be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The gate conductive layer 171 is horizontally deposited to form the first and second opening regions ( 160, 162) can be filled. The first opening region 160 having the width of the second distance HD2 extended between the first and second semiconductor patterns 126 - 1 and 126 - 2 adjacent in the second direction D2 shown in FIG. 15 . ), the gate conductive layer 171 may be easily deposited in the second opening region 162 . Accordingly, the first and second opening regions 160 and 162 may be filled with the gate conductive layer 171 without defects.

The gate conductive layer 171 may include a metal. For example, the gate conductive layer 171 may include a metal layer, a metal silicide layer, a metal nitride layer, or a combination thereof. For example, the metal film may include nickel, cobalt, platinum, titanium, tantalum, or tungsten. For example, the metal silicide film may include nickel silicide, cobalt silicide, platinum silicide, titanium silicide, tantalum silicide, or tungsten silicide. may include. For example, the metal nitride layer may include titanium nitride, tungsten nitride, or tantalum nitride.

Referring to FIG. 18 , the gate electrodes 172 , the isolation insulating layer 178 , and the common source plug 180 may be formed. For example, the gate electrodes 172 may be formed by isotropically etching the gate conductive layer 171 . The gate electrodes 172 may be separated from each other in the third direction D3 and may be separated from each other by the trench 154 in the first direction D1 . For example, first to sixth gate electrodes 172a, 172b, 172c, 172d, 172e, and 172f vertically separated from each other may be formed. Each of the gate electrodes 172 may have first and second ends 172 - TE1 and 172 - TE2 cut adjacent to the trench 154 . The thickness of each of the gate electrodes 172 may vary according to positions. Each of the gate electrodes 172 has a first thickness T1 adjacent to the ends 172 - TE1 and 172 - TE2 of the gate electrodes 172 , and in a region between the vertical channel structures 200 . It may have a second thickness T2. Each of the gate electrodes 172 may have a first thickness T1 in a portion of a region between the vertical channel structures 200 . The first thickness T1 may be greater than the second thickness T2 .

Stacked structures 30 each including insulating layers 110 and gate electrodes 172 that are alternately repeatedly stacked in the third direction D3 may be formed on the substrate 100 . For example, each of the stacked structures 30 includes first to sixth gate electrodes 172a, 192b, 172c, 172d, 172e, and 172f and first to seventh insulating layers 110a, 110b, 110c, and 110d. , 110e, 110f, 100g) may be alternately stacked. The stacked structures 30 may be separated from each other by the trench 154 in the first direction D1 .

The isolation insulating layer 178 may be formed in the form of a liner on the inner wall of the trench 154 . The isolation insulating layer 178 may protect the ends 172 - TE1 and 172 - TE2 of the gate electrodes 172 . The isolation insulating layer 178 may include a nitride layer, an oxide layer, or an oxynitride layer.

The common source plug 180 may be formed to fill the trench 154 in which the isolation insulating layer 178 is formed. The common source plug 180 may be connected to the common source region 158 . The common source plug 180 may extend along the second direction D2 in the form of a line. According to some embodiments, the common source plug 180 may be provided as a plurality of islands spaced apart from each other. In this case, a plurality of common source plugs 180 may be disposed along the second direction D2 . The common source plug 180 may include a conductive material. The common source plug 180 may include, for example, polysilicon or a metal (eg, tungsten or copper).

19 is a schematic block diagram illustrating a semiconductor device system including a semiconductor memory device according to example embodiments.

Referring to FIG. 19 , a memory system 1000 according to an exemplary embodiment of the present invention may be a semiconductor storage device. For example, it may be a memory card or a solid state drive (SSD). The memory system 1000 may include a controller 1200 and a memory 1300 in a housing 1100 . The controller 1200 and the memory 1300 may exchange electrical signals. For example, according to a command of the controller 1200 , the memory 1300 and the controller 1200 may send and receive data. Accordingly, the memory system 1000 may store data in the memory 1300 or output data from the memory 1300 to the outside. The memory 1300 may include a semiconductor memory device according to example embodiments of the present invention.

20 is a block diagram illustrating an example of an electronic system including a semiconductor memory device according to exemplary embodiments of the present invention.

Referring to FIG. 20 , the electronic system 2000 may include a controller 2200 , a storage device 2300 , and an input/output device 2400 . The controller 2200 , the memory device 2300 , and the input/output device 2400 may be coupled through a bus 2100 . The bus 2100 may be referred to as a path through which data moves. For example, the controller 2200 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic devices capable of performing the same function. The input/output device 2400 may include at least one selected from a keypad, a keyboard, and a display device. The storage device 2300 is a device for storing data. The memory device 2300 may store data and/or instructions executed by the controller 2200 . The memory device 2300 may include a volatile memory device and/or a non-volatile memory device. The memory device 2300 may be formed of a flash memory. Such a flash memory may be configured as a solid state drive (SSD). In this case, the electronic system 2000 may stably store a large amount of data in the storage device 2300 . The memory device 2300 may include a semiconductor memory device according to example embodiments of the present invention. The electronic system 2000 may further include an interface 2500 for transmitting data to or receiving data from the communication network. The interface 2500 may be in a wired/wireless form. For example, the interface 2500 may include an antenna or a wired/wireless transceiver.

In the above, exemplary embodiments of the present invention have been described with reference to the accompanying drawings, but those of ordinary skill in the art to which the present invention pertains will implement the present invention in other specific forms without changing the technical spirit or essential features thereof. You will understand that it can be Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

10: molding structure 20: molding structure pattern
30: laminated structure 100: substrate
110: insulating film 112: sacrificial film
126: semiconductor pattern 126-1: first semiconductor pattern
126-2: second semiconductor pattern 128: conductive pad
130: information storage pattern 140; vertical channel pattern
140-1: first vertical channel pattern 140-2: second vertical channel pattern
144: buried insulating film 154: trench
158: common source region 172: gate electrode
180: A common source plug semiconductor memory device includes a stacked structure including gate electrodes and insulating layers arranged in a first direction and alternately repeatedly stacked on a substrate, and vertical channel structures passing through the stacking structure. Each of the vertical channel structures includes a semiconductor pattern connected to the substrate and a vertical channel pattern connected to the semiconductor pattern. Each of the semiconductor patterns included in the vertical channel structures has recessed sidewalls. The semiconductor patterns have different minimum widths.
200: vertical channel structure

Claims (10)

stacked structures including insulating layers and gate electrodes alternately repeatedly stacked on a substrate and disposed in a first direction;
first and second semiconductor patterns passing through each of the stack structures, connected to the substrate, and arranged side by side in the first direction;
first and second vertical channel patterns passing through each of the stack structures and disposed on each of the first and second semiconductor patterns;
a trench between the stacked structures; and
a common source plug disposed within the trench;
The first semiconductor pattern is disposed proximate to the trench, the second semiconductor pattern is disposed far from the trench, and a minimum width of the first semiconductor pattern is smaller than a minimum width of the second semiconductor pattern;
The first and second semiconductor patterns each have recessed sidewalls. According to claim 1,
Each of the stacked structures includes a first gate electrode penetrated by the semiconductor patterns and second gate electrodes that horizontally surround the vertical channel patterns and are vertically stacked on the first gate electrode. 3. The method of claim 2,
the first gate electrode surrounds sidewalls of the first and second semiconductor patterns, has ends spaced apart from each other in the first direction, and has a first thickness between the first semiconductor pattern and the second semiconductor pattern; A semiconductor memory device having a second thickness greater than the first thickness adjacent the ends. delete According to claim 1,
Each of the first and second semiconductor patterns has the minimum width between the recessed sidewalls. According to claim 1,
The recessed sidewalls of the second semiconductor pattern have a first recess sidewall and a second recessed sidewall opposite to each other in the first direction, and the maximum recess depth of the first recess sidewall is the second recess. A semiconductor memory device different from the maximum recess depth of the sidewall of the recess. 7. The method of claim 6,
A difference between the maximum recess depth in the first recess sidewall and the maximum recess depth in the second recess sidewall is 10 Å to 60 Å. According to claim 1,
Maximum recess depths of the recessed sidewalls of the first semiconductor pattern are substantially the same. stacked structures including insulating layers and gate electrodes alternately repeatedly stacked on a substrate and disposed in a first direction;
semiconductor patterns passing through each of the stack structures, connected to the substrate, and arranged side by side in the first direction;
vertical channel patterns passing through each of the stacked structures, each of which is disposed on each of the semiconductor patterns;
a trench disposed between the stacked structures; and
a common source plug disposed within the trench;
At least one of the semiconductor patterns has recess sidewalls opposite to each other in the first direction, and maximum recess depths of the sidewalls of the recess are different from each other. 10. The method of claim 9,
The recessed sidewalls of the at least one semiconductor pattern include a first recess sidewall proximal to the trench in the first direction and a second recess sidewall distal from the trench, wherein the maximum recessed sidewall of the first recess sidewall A recess depth is greater than a maximum recess depth of a sidewall of the second recess.

Images