KR102341716B1 - Semiconductor memory device and method of fabricating the same - Google Patents

Abstract

A laminate structure in which gate electrodes and insulating layers are alternately repeatedly stacked is provided on a substrate. A cell channel structure is provided on a substrate, the cell channel structure including a first semiconductor pattern passing through the stacked structure and connecting to the substrate, and a first channel pattern disposed on the first semiconductor pattern and connected to the first semiconductor pattern. A dummy vertical channel structure including a second semiconductor pattern spaced apart from the stacked structure and connected to the substrate, and a second channel pattern disposed on the second semiconductor pattern and connected to the second semiconductor pattern is provided on the substrate. The first height from the surface of the substrate to the upper surface of the first semiconductor pattern is greater than the second height from the surface of the substrate to the upper surface of the second semiconductor pattern.

Description

TECHNICAL FIELD [0002] Semiconductor memory device and method of fabricating the same

The technical idea of the present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a 3D semiconductor memory device with improved reliability and integration, and a method for manufacturing the same.

In order to meet the excellent performance and low price demanded by consumers, it is required to increase the degree of integration of semiconductor devices. Since the degree of integration of a semiconductor device is an important factor in determining the price of a product, an increased degree of integration is particularly required. Since the degree of integration of a conventional two-dimensional or planar semiconductor device is mainly determined by an area occupied by a unit memory cell, it is greatly affected by the level of a fine pattern forming technique. However, since ultra-expensive equipment is required for pattern miniaturization, the degree of integration of the 2D semiconductor device is increasing, but is still limited.

To overcome this limitation, three-dimensional semiconductor memory devices including memory cells arranged three-dimensionally have been proposed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device with improved reliability and integration.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device with improved reliability and integration.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, a semiconductor memory device according to embodiments of the technical idea of the present invention includes a stacked structure in which gate electrodes and insulating layers are alternately and repeatedly stacked on a substrate, passing through the stacked structure, , a cell channel structure including a first semiconductor pattern connected to the substrate, a cell channel structure disposed on the first semiconductor pattern and a first channel pattern connected to the first semiconductor pattern, and spaced apart from the stacked structure on the substrate and a first dummy channel structure including a second semiconductor pattern connected to the substrate and a second channel pattern disposed on the second semiconductor pattern and connected to the second semiconductor pattern. A first height from the surface of the substrate to the upper surface of the first semiconductor pattern may be greater than a second height from the surface of the substrate to the upper surface of the second semiconductor pattern.

In some embodiments, the memory device may further include a bit line electrically connected to the cell channel structure.

According to some embodiments, the cell channel structure may further include a first information storage pattern disposed between the first channel pattern and the stacked structure. The first dummy channel structure may further include a second data storage pattern in contact with a sidewall of the second channel pattern. The first channel pattern and the second channel pattern may include the same material, and the first data storage pattern and the second data storage pattern may include the same material.

In some embodiments, the substrate includes a cell region including a cell array region and a connection region adjacent to the cell array region, a peripheral region spaced apart from the cell region, and a boundary region between the cell region and the peripheral region. can do. The stacked structure may be disposed in the cell area and extend in the first direction, and may have an end of the step structure in the connection area.

In some embodiments, a mold insulating layer covering the end of the stack structure and disposed on the substrate in the connection region, the boundary region, and the peripheral region may be further included. The first dummy channel structure may pass through the mold insulating layer and may be connected to the substrate.

In some embodiments, a third semiconductor pattern passing through the mold insulating layer and the end portion of the stacked structure in the connection region, and connected to the substrate, and a third semiconductor pattern connected to the third semiconductor pattern and on the third semiconductor pattern It may further include a second dummy channel structure including a third channel pattern disposed on the .

According to some embodiments, the first dummy channel structure may have a circular shape, an elliptical shape, or a bar shape when viewed in a plan view.

In some embodiments, the memory device may further include a peripheral circuit device disposed on the substrate in the peripheral region. The peripheral circuit device may include a gate insulating layer, a gate electrode, and a source/drain region.

In some embodiments, the memory device may further include a gate oxide layer disposed on a sidewall of the first semiconductor pattern. The gate oxide layer may not be disposed on a sidewall of the second semiconductor pattern.

A semiconductor memory device according to embodiments of the inventive concept includes a cell region including a cell array region and a connection region, a peripheral region spaced apart from the cell region, and a boundary region between the connection region and the peripheral region. stacked structures spaced apart from each other in a first direction on the substrate in the cell region, each having an end of a step structure in the connection region, and including gate electrodes and insulating layers alternately stacked, the cell A cell channel structure penetrating through each of the stacked structures in an array region and including a first semiconductor pattern connected to the substrate and a first channel pattern disposed on the first semiconductor pattern and connected to the first semiconductor pattern, respectively a second semiconductor pattern passing through each end of the stacked structures in the connection region and connecting to the substrate and a second channel pattern disposed on the second semiconductor pattern and connected to the second semiconductor pattern, respectively A second dummy including first dummy channel structures including: a third semiconductor pattern connected to the substrate in the boundary region; and a third channel pattern disposed on the third semiconductor pattern and connected to the third semiconductor pattern; It may include a channel structure.

In some embodiments, each of the first semiconductor patterns has a first height from a surface of the substrate to an upper surface of each of the first semiconductor patterns, and the second semiconductor patterns are the closest to the third semiconductor pattern. an adjacent first sub-semiconductor pattern, wherein the first sub-semiconductor pattern has a second height from the surface of the substrate to an upper surface of the first sub-semiconductor pattern, and the third semiconductor pattern is formed from the surface of the substrate to the The third semiconductor pattern may have a third height to the upper surface, the third height may be smaller than the first height, and the second height may be smaller than the first height.

In some embodiments, the second semiconductor patterns may include a second sub-semiconductor pattern closest to the first semiconductor patterns, and the second sub-semiconductor pattern may be formed of the second sub-semiconductor pattern from the surface of the substrate. It has a fourth height to the top surface, and the fourth height may be substantially equal to the first height.

In some embodiments, the memory device may further include a peripheral circuit element disposed on the substrate in the peripheral region, and a peripheral protective layer covering the peripheral circuit element. The peripheral circuit device may include a gate insulating layer, a gate electrode, and a source/drain region.

In some embodiments, the memory device may further include a mold insulating layer covering the peripheral protective layer, the substrate in the boundary region, and the end portion of the stacked structure. The first and second dummy channel structures may penetrate the mold insulating layer.

According to some embodiments, each of the cell channel structures may further include a first data storage pattern in contact with a sidewall of the first channel pattern. Each of the first dummy channel structures may further include a second data storage pattern in contact with a sidewall of the second channel pattern. The second dummy channel structure may further include a third data storage pattern in contact with a sidewall of the third channel pattern. The first channel pattern, the second channel pattern, and the third channel pattern include the same material, and the first data storage pattern, the second data storage pattern, and the third data storage pattern include the same material. may include

According to some embodiments, a plurality of second dummy channel structures may be provided. Each of the second dummy channel structures may have a circular shape or an elliptical shape when viewed in a plan view, and may be arranged in the first direction.

According to some embodiments, the second dummy channel structure may have a bar shape and extend in the first direction when viewed in a plan view.

A semiconductor memory device according to embodiments of the inventive concept includes a stacked structure in which gate electrodes and insulating layers are alternately and repeatedly stacked on a substrate, and a first semiconductor pattern passing through the stacked structure and connecting to the substrate and a first channel pattern disposed on the first semiconductor pattern and connected to the first semiconductor pattern; and a second semiconductor pattern spaced apart from the stacked structure and disposed on the substrate and connected to the substrate. and a dummy channel structure disposed on the second semiconductor pattern and including a second channel pattern connected to the second semiconductor pattern, and a gate oxide layer disposed on a sidewall of the first semiconductor pattern. The gate oxide layer may not be disposed on a sidewall of the second semiconductor pattern.

In some embodiments, a portion of a sidewall of the first semiconductor pattern may be concave, and a sidewall of the second semiconductor pattern may not be concave.

In some embodiments, a first height from the surface of the substrate to the upper surface of the first semiconductor pattern may be greater than a second height from the surface of the substrate to the upper surface of the second semiconductor pattern.

A method of manufacturing a semiconductor memory device according to embodiments of the inventive concept provides a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, wherein the substrate in the cell region A stacked structure in which gate electrodes and insulating layers are alternately repeatedly stacked is formed on the first semiconductor pattern passing through the stacked structure, and disposed on the first semiconductor pattern and the first semiconductor pattern connected to the substrate. forming a cell channel structure including a first channel pattern connected to a semiconductor pattern, forming a mold insulating layer on the substrate in the peripheral region and the boundary region, and spaced apart from the stacked structure and forming the mold insulating layer A first dummy channel structure including a second semiconductor pattern passing through and connected to the substrate and a second channel pattern disposed on the second semiconductor pattern and connected to the second semiconductor pattern may be formed. A first height from the surface of the substrate to the upper surface of the first semiconductor pattern may be greater than a second height from the surface of the substrate to the upper surface of the second semiconductor pattern.

In a method of manufacturing a semiconductor memory device according to embodiments of the inventive concept, a cell region including a cell array region and a connection region, a peripheral region spaced apart from the cell region, and a boundary region between the connection region and the peripheral region providing a substrate comprising: forming a mold structure including insulating films and sacrificial films alternately stacked on the substrate of the cell region, covering a part of the mold structure, the connection region, the boundary region; and a first semiconductor pattern that forms a mold insulating layer on the substrate in the peripheral region, passes through the mold structure on the cell array region, and is connected to the substrate, and is disposed on the first semiconductor pattern forming a cell channel structure including a first channel pattern connected to the pattern, passing through the mold insulating layer on the connection region and the mold structure, and on the second semiconductor pattern and the second semiconductor pattern connected to the substrate forming first dummy channel structures disposed on the first dummy channel structures each including a second channel pattern connected to the second semiconductor pattern, and passing through the mold insulating layer in the boundary region and connecting to the substrate; and The method may include forming a second dummy channel structure disposed on the third semiconductor pattern and including a third channel pattern connected to the third semiconductor pattern.

A semiconductor memory device according to embodiments of the inventive concept is disposed on a substrate including a cell region including a cell array region and a connection region, a peripheral region spaced apart from the cell region, and the substrate in the cell region, A stacked structure having an end of a step structure in the connection region, in which gate electrodes and insulating layers are alternately stacked, a first semiconductor pattern passing through the stacked structure and connecting to the substrate, and on the first semiconductor pattern a cell channel structure disposed and including a first channel pattern connected to the first semiconductor pattern, and a second semiconductor pattern and the second semiconductor pattern passing through an end of the stack structure in the connection region and connected to the substrate It may include dummy channel structures disposed on the dummy channel structures each including a second channel pattern connected to the second semiconductor pattern. The first semiconductor pattern has a first height from the substrate to a top surface of the first semiconductor pattern, and the second semiconductor patterns include a sub-semiconductor pattern that is furthest from the first semiconductor pattern, and the sub-semiconductor The pattern may have a second height from the substrate to a top surface of the sub-semiconductor pattern, and the second height may be smaller than the first height.

According to embodiments of the inventive concept, a semiconductor memory device may include a cell region including a cell array region and a connection region, a peripheral region, and a boundary region between the cell region and the peripheral region. The first semiconductor patterns of the cell channel structures disposed in the cell array region, the second semiconductor patterns of the first dummy channel structure disposed in the connection region, and the third semiconductor pattern of the second dummy vertical channel structure disposed in the boundary region are It is formed by an epitaxial growth method. The influence of outgassing of impurities from the mold insulating layer on the epitaxial growth of the second semiconductor pattern adjacent to the third semiconductor pattern may be weakened. Accordingly, the upper surface of the second semiconductor pattern adjacent to the boundary region may be formed to be higher than the upper surface of the lowermost gate electrode, and the gate oxide layer may be uniformly formed on the side surface of the second semiconductor pattern. As a result, since insulation between the second semiconductor pattern and the gate electrode is secured, leakage current through the second semiconductor pattern is prevented, so that a highly reliable memory semiconductor device can be realized.

1 is a schematic plan view of a semiconductor memory device according to embodiments of the inventive concept.
2A to 2C are plan views of a semiconductor memory device according to embodiments of the inventive concept, and are enlarged views of an AR portion of FIG. 1 .
3 to 5 are cross-sectional views illustrating semiconductor memory devices according to embodiments of the inventive concept. FIG. 3 is a cross-sectional view taken along line II′ of FIG. 2 , and FIGS. 4 and 5 are FIG. 2 . These are cross-sectional views taken along the II-II' line.
6A to 6C are enlarged views of portions A1 of FIG. 3 , A2 of FIG. 4 , and portions A3 of FIG. 4 , respectively.
7A to 7D are schematic plan views of semiconductor memory devices according to embodiments of the inventive concept.
8A to 18A and 8B to 18B are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the inventive concept, and FIGS. 8A to 18A correspond to the line II′ of FIG. 2 . are cross-sectional views, and FIGS. 8B to 18B are cross-sectional views corresponding to the line II-II′ of FIG. 2 .
19A to 19C are enlarged views of portions B1 of FIG. 12A , B2 of FIG. 12B , and B3 of FIG. 12B .
20 is a schematic block diagram illustrating a memory system including a semiconductor memory device according to embodiments of the inventive concept.
21 is a schematic block diagram illustrating an electronic system including a semiconductor memory device according to embodiments of the inventive concept.

Advantages and features of the present invention, and methods for achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only this embodiment serves to complete the disclosure of the present invention, and to obtain common knowledge in the technical field to which the present invention pertains. It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, 'comprises' and/or 'comprising' means that a referenced component, step, operation and/or element is the presence of one or more other components, steps, operations and/or elements. or addition is not excluded. Also, in this specification, when a certain film is referred to as being on another film or substrate, it means that it may be directly formed on the other film or substrate, or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional and/or plan views, which are ideal illustrative views according to the technical spirit of the present invention. In the drawings, thicknesses of films and regions are exaggerated for effective description of technical content. Accordingly, the shape of the illustrative drawing may be modified due to manufacturing technology and/or tolerance. Accordingly, the embodiments of the present invention are not limited to the specific form shown, but also include changes in the form generated according to the manufacturing process. For example, the etched region shown at a right angle may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the drawings have a schematic nature, and the shapes of the illustrated regions in the drawings are intended to illustrate specific shapes of regions of the device and not to limit the scope of the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a schematic plan view of a semiconductor memory device according to embodiments of the inventive concept.

Referring to FIG. 1 , the cell region CR may be disposed in the center of the semiconductor memory device. The cell area CR may include a cell array area CAA and a connection area CTA at an edge of the cell array area CAA. The cell array area CAA may include memory cells arranged in an array.

Gate contacts connected to gate electrodes (or word lines) of memory cells may be disposed in the connection area CTA. A peripheral region PR may be disposed around the semiconductor memory device to surround the cell region CR. A peripheral circuit (eg, a row decoder, a sense amplifier, etc.) for controlling the memory cells may be disposed in the peripheral region PR. A boundary area BR may be provided between the cell area CR and the peripheral area PR.

2A to 2C are plan views of a semiconductor memory device according to embodiments of the inventive concept, and are enlarged views of an AR portion of FIG. 1 . 3 to 5 are cross-sectional views illustrating semiconductor memory devices according to embodiments of the inventive concept. FIG. 3 is a cross-sectional view taken along line II′ of FIG. 2A, and FIGS. 4 and 5 are FIGS. These are cross-sectional views taken along the II-II' line of 2a. 6A to 6C are enlarged views of A1 of FIG. 3 , A2 of FIG. 4 , and A3 of FIG. 4 , respectively. 7A to 7D are schematic plan views of semiconductor memory devices according to embodiments of the inventive concept.

2A and 3 to 5 , in the semiconductor memory device according to embodiments of the inventive concept, stacked structures 30 and stacked structures 30 disposed on a substrate 100 are respectively included. The cell channel structures 200a passing through the structure, the common source region 152 disposed on the substrate 100 between the stack structures 30 , and first and second dummy channels spaced apart from the cell channel structures 200a. It may include structures 200b and 200c, and at least one peripheral circuit device PT.

The substrate 100 includes a cell area CR including a cell array area CAA and a connection area CTA adjacent to the cell array area CAA, a peripheral area PR spaced apart from the cell area PR, and a cell. A boundary area BR between the area CR and the peripheral area PR may be included.

The substrate 100 may include a semiconductor material. For example, the substrate 100 may be a silicon (Si) single crystal substrate, a germanium (Ge) single crystal substrate, or a silicon-germanium (SiGe) single crystal substrate. According to some embodiments, the substrate 100 may be a semiconductor on insulator (SOI) substrate. For example, the substrate 100 may include a semiconductor active layer (eg, a silicon layer, a silicon-germanium layer, or a germanium layer) disposed on an insulating layer that protects transistors provided on the semiconductor substrate. The substrate 100 may be, for example, a P-type semiconductor substrate, but is not limited thereto. The substrate 100 may include a well region (not shown).

At least one peripheral circuit element PT may be disposed in the peripheral region PR. The peripheral circuit device PT may include a peripheral gate insulating film 101 , a peripheral gate electrode 103 on the peripheral gate insulating film 101 , and a source/drain region 107 adjacent to sidewalls of the peripheral gate electrode 103 . can The peripheral gate insulating film 101 is disposed on the substrate 100 and may include an oxide film, a high-k film, and/or a combination thereof. The peripheral gate electrode 103 is, for example, silicon (eg, polysilicon), metal silicide (eg, tungsten silicide (WSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicide). (TiSi), tantalum silicide (TaSi)), or a metal (eg, tungsten or aluminum), and/or combinations thereof. A peripheral gate spacer 105 may be disposed on sidewalls of the peripheral gate electrode 103 . The source/drain regions 107 are disposed in the substrate 100 and may include N-type impurities (eg, phosphorus (P)) or P-type impurities (eg, boron (B)). . A peripheral protective layer 109 covering the peripheral circuit element PT may be disposed on the substrate 100 . The peripheral passivation layer 109 may include a silicon oxide layer or a silicon nitride layer. The peripheral circuit element PT may include, for example, a high voltage or a low voltage transistor.

The stack structures 30 may be disposed in the cell region CR. For example, each of the stack structures 30 may extend from the cell area CAA to the connection area CTA. Each of the stack structures 30 may extend in a first direction D1 parallel to the surface of the substrate 100 . The stacked structures 30 may be disposed to be separated from each other in a second direction D2 parallel to the surface of the substrate 100 and perpendicular to the first direction D1 . For example, the stack structures 30 may be separated from each other in the second direction D2 by the trench 150 extending in the first direction D1 .

Each of the stack structures 30 may include gate electrodes GE and insulating layers 110 alternately and repeatedly stacked on the substrate 100 . Some of the insulating layers 110 may be thicker or thinner than other insulating layers 110 . For example, the thickness of the lowermost insulating layer 110 - 1 may be thinner than that of other insulating layers 110 . For example, the second insulating layer 110 - 2 and the uppermost insulating layer 110 - 3 from the substrate 100 may be thicker than the other insulating layers 110 . Each of the insulating layers 110 may include, for example, silicon oxide.

Each of the gate electrodes GE may include a conductive film. For example, each of the gate electrodes GE may include a semiconductor film (eg, a silicon film doped with impurities), a metal silicide film (eg, For example, a cobalt silicide film, a nickel silicide film, a titanium silicide film, a tungsten silicide film, or a tantalum silicide film), a metal nitride film (eg, a titanium nitride film, a tungsten nitride film, or a tantalum nitride film), a metal film (eg, tungsten film, nickel film, cobalt film, titanium film, or tantalum film) and/or a combination film thereof.

The semiconductor memory device may be a 3D memory device. For example, the semiconductor memory device may be a 3D NAND flash memory device. Accordingly, the gate electrodes GE may be used as control gate electrodes of the memory cells. For example, the gate electrodes GE2 between the uppermost gate electrode GE3 and the lowermost gate electrode GE1 may be used as control gate electrodes (eg, word lines). The gate electrodes GE2 may be combined with the cell channel structures 200a to form memory cells. Accordingly, vertical memory cell strings including vertically arranged memory cells may be provided in the cell array area CAA of the substrate 100 . The lowermost and uppermost gate electrodes GE1 and GE3 may be used as gate electrodes of the selection transistors SST and GST. For example, the uppermost gate electrode GE3 is used as a gate electrode of the string select transistor SST that controls the electrical connection between the bit line BL and the cell channel structures 200a, and the lowermost gate electrode GE1 ) may be used as a gate electrode of the ground selection transistor GST for controlling an electrical connection between the common source region 152 and the cell channel structures 200a.

Each of the stack structures 30 may have an end 30e of a stepwise structure in the connection area CTA. For example, in the connection area CTA, each of the gate electrodes GE may have a pad part GEP extending from the cell array area CAA in the first direction D1 . For example, in the connection area CTA, the vertical height of each of the stack structures 30 may be decreased in a stepwise manner as it approaches the boundary area BR. A mold insulating layer 118 covering the stacked structures 30 may be disposed in the connection area CTA, the boundary area BR, and the peripheral circuit area PR. For example, the mold insulating layer 118 may cover the ends 30e of the stacked structures 30 (eg, the pad parts GEP of the gate electrodes GE). The mold insulating layer 118 may contact the substrate 100 in the boundary region BR. The mold insulating layer 118 may be disposed on the peripheral protective layer 109 . The mold insulating layer 118 may cover the peripheral circuit device PT. The mold insulating layer 118 may include an oxide layer or a low-K dielectric layer.

The cell channel structures 200a may pass through each of the stack structures 30 to be connected to the substrate 100 . That is, the cell channel structures 200a may be connected to the substrate 100 and extend in a third direction D3 perpendicular to the surface of the substrate 100 , and may be surrounded by each of the stacked structures 30 . have. For example, the cell channel structures 200a may be surrounded by respective gate electrodes GE of the stack structures 30 . When viewed in a plan view, the cell channel structures 200a may be arranged in the first direction D1 and the second direction D2 . For example, as shown in FIG. 2A , the cell channel structures 200a are a pair of cell channel structures adjacent to each other in the second direction D2 and arranged in a zigzag shape along the first direction D1. Columns of the columns 200a may be repeatedly arranged along the second direction D2. That is, columns of the pair of cell channel structures 200a may pass through each of the stacked structures 30 . According to some embodiments, a row of one cell channel structures 200a arranged in a zigzag form in the first direction D1 is repeatedly disposed along the second direction D2 or the second direction D2 ), columns of three or more cell channel structures 200a adjacent to each other and arranged in a zigzag form in the first direction D1 may be repeatedly arranged along the second direction D2.

Each of the cell channel structures 200a may include a first semiconductor pattern 126a, a first channel pattern 140a, and a first data storage pattern 130a. Each of the cell structures 200a may further include a first buried insulating pattern 144a. The first data storage pattern 130a, the first channel pattern 140a, and the first buried insulating pattern 144a may be disposed on the first semiconductor pattern 126a.

The first semiconductor pattern 126a is directly connected to the substrate 100 and may extend into the substrate 100 . For example, a portion of the first semiconductor pattern 126a may be buried in the substrate 100 , and another portion thereof may have a pillar shape vertically protruding from the substrate 100 . The first semiconductor pattern 126a may have a first height T1 that is the maximum height from the surface of the substrate 100 to the top surface of the first semiconductor pattern 126a. That is, the first height T1 may be greater than the thickness of the lowermost gate electrode GE1 . For example, the upper surface of the first semiconductor pattern 126a may be positioned at a level higher than the upper surface of the lowermost gate electrode GE1 . The top surface of the first semiconductor pattern 126a may be positioned at a level lower than the top surface of the second insulating layer 110 - 2 from the substrate 100 . The first semiconductor pattern 126a may include silicon (Si). For example, the first semiconductor pattern 126a may be an epitaxial pattern including single crystal silicon or polysilicon. In some embodiments, the first semiconductor pattern 126a may include germanium (Ge), silicon germanium (SiGe), a group III-V semiconductor compound, or a group II-VI semiconductor compound. The first semiconductor pattern 126a may be an undoped pattern or a pattern doped with an impurity having the same conductivity type as that of the substrate 100 .

A gate oxide layer 156 may be disposed on a sidewall of the first semiconductor pattern 126a. The gate oxide layer 156 may be disposed between the lowermost gate electrode GE1 and the first semiconductor pattern 126a. The gate oxide layer 156 may include a silicon oxide layer (eg, a thermal oxide layer). The gate oxide layer 156 may have a bulging shape. The first semiconductor pattern 126a may have a partially concave sidewall 126as. For example, a portion of the sidewall 126as of the first semiconductor pattern 126a may be concave by the gate oxide layer 156 .

The first channel pattern 140a may be disposed on the first semiconductor pattern 126a and may extend in the third direction D3 . The first channel pattern 140a may be connected to the first semiconductor pattern 126a. The first channel pattern 140a may be disposed between the first data storage pattern 130a and the first buried insulating pattern 144a. An upper end of the first channel pattern 140a may have an open shape. According to some embodiments, the first channel pattern 140a may have an open top and bottom end, a hollow cylinder shape, or a macaroni shape. According to some embodiments, the first channel pattern 140a may have a cylindrical shape. In this case, the cell channel structure 200a may not include the first buried insulating pattern 144a. The first channel pattern 140a may include a polycrystalline semiconductor material, an amorphous semiconductor material, or a single crystal semiconductor material. The first channel pattern 140a may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. may contain one. The first channel pattern 140a may include a semiconductor material undoped with impurities or a semiconductor material doped with impurities having the same conductivity type as that of the substrate 100 .

The first data storage pattern 130a may be disposed between the stacked structure 30 and the first channel pattern 140a. The first data storage pattern 130a is disposed on the first semiconductor substrate 126a and may extend in the third direction D3. The first data storage pattern 130a may have an open top and bottom. The first data storage pattern 130a may include a thin film for storing data. For example, in the first data storage pattern 130a, the data stored therein is a voltage difference between the cell channel structure 200a and the gate electrodes GE or a Fowler-Nordheim tunneling effect resulting therefrom. It may be configured to be changed using , but is not limited thereto. According to some embodiments, the first data storage pattern 130a is a thin film capable of storing data based on a different operating principle (eg, a thin film for a phase change memory device or a thin film for a variable resistance memory device) may include

As shown in FIG. 6A , the first data storage pattern 130 includes a first blocking insulating layer 132 adjacent to the gate electrodes GE, a tunnel insulating layer 136 in contact with the first channel pattern 140a, and these It may include a charge storage layer 134 therebetween. The tunnel insulating layer 136 may be, for example, a silicon oxide layer. The charge storage layer 134 may be a trap insulating layer or an insulating layer including conductive nano dots. The trap insulating layer may include, for example, silicon nitride. The first blocking insulating layer 132 may include a silicon oxide layer and/or a high-k layer (eg, an aluminum oxide layer or a hafnium oxide layer). The first blocking insulating film 132 may be formed of a single film or a plurality of thin films. According to some embodiments, the first blocking insulating layer 132 may be a single layer including a silicon oxide layer. According to other embodiments, the first blocking insulating layer 132 may include a plurality of thin films including an aluminum oxide layer and/or a hafnium oxide layer.

A second blocking insulating layer 158 may be further disposed between the gate electrodes GE and the cell channel structure 200a and between the insulating layers 110 and the gate electrodes GE. For example, the second blocking insulating layer 158 may include a portion interposed between the gate electrodes GE and the cell channel structure 200a and a portion covering upper and lower surfaces of the gate electrodes GE. . The second blocking insulating layer 158 may be formed of a single layer or a plurality of thin films. The second blocking insulating layer 158 may include a high dielectric layer (eg, an aluminum oxide layer and/or a hafnium oxide layer). According to some embodiments, the second blocking insulating layer 158 may not be formed.

The first buried insulating pattern 144a is disposed on the first semiconductor pattern 126a and may extend in the third direction D3 . The first buried insulating pattern 144a may be disposed to fill a space provided by the first channel pattern 140a. The first buried insulating pattern 144a may include a silicon oxide layer or a silicon nitride layer.

The first dummy channel structures 200b may be disposed in the connection area CAA, and the second dummy channel structures 200c may be disposed in the boundary area BR. The first and second dummy channel structures 200b and 200c are inactive channel structures 200b and 200c.

The first dummy channel structures 200b may be disposed on the substrate 100 through each of the mold insulating layer 118 and the stack structures 30 . Each of the first dummy channel structures 200b may pass through each of the step-shaped ends 30e of the stacked structures 30 . For example, each of the first dummy channel structures 200b may include at least one end of the pad portion GEP of the corresponding gate electrodes GE, at least one gate electrode GE disposed below the corresponding gate electrode GE, and at least one of the first dummy channel structures 200b. One of the insulating layers 110 and the mold insulating layer 118 disposed thereon may be penetrated.

According to some embodiments, the first dummy channel structure 200b closest to the cell array area CAA may include the mold insulating layer 118 and the end of the pad part GEP of the uppermost gate electrode GE3, below the mold insulating layer 118 . It may be connected to the substrate 100 through the gate electrodes GE and the insulating layers 110 . The first dummy channel structure 200b disposed furthest from the cell array area CAA (or closest to the boundary area BR) has the mold insulating layer 118 and the second gate electrode GE2 from the substrate 100 . ) of the pad portion GEP, the lowermost gate electrode GE1, the second insulating layer 110-2 from the substrate 100, and the lowermost insulating layer 110-1 may pass through the substrate 100 to be connected to the substrate 100 . According to other embodiments, the first dummy channel structure 200b closest to the boundary region BR may include the mold insulating layer 118, the end of the pad portion GEP of the lowest gate electrode GE1, and the lowest insulating layer ( 110 - 1) and may be connected to the substrate 100 . The first dummy channel structures 200b may be arranged in two rows parallel to the first direction D1 as shown in FIG. 2A , but is not limited thereto, and may be arranged in one column or three or more columns.

Each of the first dummy channel structures 200b may include a second semiconductor pattern 126b, a second channel pattern 140b, a second data storage pattern 130b, and a second buried insulating pattern 144b. have. The second data storage pattern 130b, the second channel pattern 140b, and the second buried insulating pattern 144b may be disposed on the second semiconductor pattern 126b and may extend in the third direction D3.

The second semiconductor pattern 126b may be directly connected to the substrate 100 and may extend into the substrate 100 . For example, a portion of the second semiconductor pattern 126b may be buried in the substrate 100 , and another portion of the second semiconductor pattern 126b may have a pillar shape that protrudes vertically from the substrate 100 . According to some embodiments, a portion of the second semiconductor patterns 126b (eg, the second semiconductor pattern 126b - 1 closest to the boundary region BR) is larger than the first semiconductor pattern 126a by the substrate. It may extend deeper into (100). The second semiconductor pattern 126b may be disposed under the corresponding stacked structure 30 .

The upper surface of the second semiconductor pattern 126b may be positioned at a level higher than the upper surface of the lowermost gate electrode GE1 . The upper surface of the second semiconductor pattern 126b may be positioned at a level lower than the upper surface of the second insulating layer 110 - 2 from the substrate 100 . The second semiconductor patterns 126b may include a first sub-semiconductor pattern 126b-1 and a second sub-semiconductor pattern 126b-2. The first sub-semiconductor pattern 126b - 1 is closest to the boundary region BR (eg, the third semiconductor pattern 126c), and the cell array region CAA (eg, the first semiconductor pattern 126c) 126a))). The second sub-semiconductor pattern 126b - 2 may be closest to the cell array area CAA (eg, the first semiconductor pattern 126a). The first sub-semiconductor pattern 126b - 1 may have a second height T2 that is the maximum height from the surface of the substrate 100 to the top surface of the first sub-semiconductor pattern 126b - 1 . The second sub-semiconductor pattern 126b - 2 may have a third height T3 that is the maximum height from the surface of the substrate 100 to the top surface of the second sub-semiconductor pattern 126b - 2 . The second and third heights T2 and T3 may be greater than the thickness of the lowermost gate electrode GE1 . The third height T3 may be substantially the same as the first height T1 of the first semiconductor pattern 126a. The second height T2 may be smaller than the first and third heights T1 and T3 . The second semiconductor pattern 126b may include the same material as the first semiconductor pattern 126a.

A gate oxide layer 156 may be disposed on a sidewall of the second semiconductor pattern 126b. The gate oxide layer 156 may be disposed between the lowermost gate electrode GE1 and the second semiconductor pattern 126b. The gate oxide layer 156 may include an oxide layer (eg, a thermal oxide layer). The gate oxide layer 156 may have a bulging shape. The second semiconductor pattern 126b may have a partially concave sidewall 126bs. For example, a portion of the sidewall 126bs of the second semiconductor pattern 126b may be concave by the gate oxide layer 156 .

As a result, the upper surface of the first sub-semiconductor pattern 126b - 1 of the second semiconductor pattern 126b may be positioned at a higher level than the upper surface of the lowermost gate electrode GE1 . The gate oxide layer 156 is uniformly formed on the sidewall of the first sub-semiconductor pattern 126b - 1 to ensure insulation between the lowermost gate electrode GE1 and the first sub-semiconductor pattern 126b. Accordingly, a phenomenon of leakage current through the second semiconductor pattern 126b may be prevented, and thus a highly reliable memory semiconductor device may be realized.

The second channel pattern 140b may be connected to the second semiconductor pattern 126b. The second channel pattern 140b may be disposed between the second data storage pattern 130b and the second buried insulating pattern 144b. The second panel pattern 140b may have substantially the same shape as the first channel pattern 140a and may include substantially the same material. The second data storage pattern 130b may be disposed between the stacked structure 30 and the second channel pattern 140b.

The second data storage pattern 130b may include substantially the same material as the first data storage pattern 130a and may have substantially the same structure. For example, as shown in FIG. 6B , the second data storage pattern 130b includes a first blocking insulating layer 132 adjacent to the gate electrodes GE and a tunnel insulating layer 136 in contact with the second channel pattern 140b. ), and a charge storage layer 134 therebetween. One side of the first blocking insulating layer 132 may be adjacent to the gate electrode GE, and the other side of the first blocking insulating layer 132 may be in contact with the mold insulating layer 118 .

The second blocking insulating layer 138 may be further disposed between the gate electrodes GE and the first dummy channel structure 200b and between the insulating layers 110 and the gate electrodes GE. According to some embodiments, the second blocking insulating layer 138 may not be formed.

The second buried insulating pattern 144b is disposed on the second semiconductor pattern 126b and may extend in the third direction D3 . The second buried insulating pattern 144b may be disposed to fill a space provided by the second channel pattern 140b. The second buried insulating pattern 144b may include a silicon oxide layer or a silicon nitride layer.

The second dummy channel structures 200c may penetrate the mold insulating layer 118 in the boundary region BR. Each of the second dummy channel structures 200c may be connected to the substrate 100 . Each of the second dummy channel structures 200c may have a circular shape or an oval shape shown in FIG. 2A or a bar shape shown in FIG. 2B when viewed in plan view. 2A and 2B , the second dummy channel structures 200c may be arranged in a column along the second direction D2 in a plan view. For example, the second dummy channel structures 200c are spaced apart from the stacked structures 30 , and at least one is disposed adjacent to each of the stacked structures 30 and formed in a row in the second direction D2 . can be arranged. According to some embodiments, as shown in FIG. 2C , each of the second dummy channel structures 200c has a circular shape or an elliptical shape when viewed in a plan view, and has two rows parallel to the second direction D2. However, the present invention is not limited thereto and may be arranged in three or more rows parallel to the second direction D2. According to some embodiments, as shown in FIG. 7A , each of the second dummy channel structures 200c has a bar shape and moves in the second direction D2 between the connection area CTA and the peripheral area PR. It may be arranged to extend along. For example, each of the second dummy channel structures 200c may be spaced apart from the stack structures 30 in the first direction D1 and extend in the second direction D2 . According to some embodiments, as shown in FIGS. 7B and 7C , the second dummy channel structures 200c may surround the cell region CR. For example, the second dummy channel structures 200c are arranged between the connection area CTA and the peripheral area PR along the second direction D2 , and the cell area CR along the first direction D1 . ) and the peripheral region PR. According to some embodiments, as shown in FIG. 7D , the second dummy channel structure 200c may surround the cell region CR in a loop shape.

Each of the second dummy channel structures 200c may include a third semiconductor pattern 126c, a third channel pattern 140c, a third data storage pattern 130c, and a third buried insulating pattern 144c. have. The third data storage pattern 130c, the third channel pattern 140c, and the third buried insulating pattern 144c are disposed on the third semiconductor pattern 126c and may extend in the third direction D3.

The third semiconductor pattern 126c is directly connected to the substrate 100 and may extend into the substrate 100 . For example, a portion of the third semiconductor pattern 126c may be buried in the substrate 100 , and another portion thereof may have a pillar shape that protrudes vertically from the substrate 100 . According to some embodiments, the third semiconductor pattern 126c may extend deeper into the substrate 100 than the first semiconductor pattern 126a. The third semiconductor pattern 126c may have a fourth height T4 that is the maximum height from the surface of the substrate 100 to the upper surface of the third semiconductor pattern 126c. The fourth height T4 may be smaller than the first height T1 of the first semiconductor pattern 126a and the second and third heights T2 and T3 of the second semiconductor pattern 126b. According to some embodiments, as shown in FIG. 5 , the fourth height T4 may be greater than the second height T2 and smaller than the first and third heights T1 and T3 . The third semiconductor pattern 126c may include the same material as the first semiconductor pattern 126a.

The gate oxide layer 156 may not be formed on the sidewall of the third semiconductor pattern 126c. Accordingly, the third semiconductor pattern 126c may have a sidewall 126cs without a concave portion. The sidewall 126cs of the third semiconductor pattern 126c may directly contact the mold insulating layer 118 .

Top surfaces of the first to third semiconductor patterns 126a , 126b , and 126c may have various shapes. For example, upper surfaces of the first to third semiconductor patterns 126a , 126b , and 126c may have a flat shape, an inclined shape with respect to the substrate 100 , or a spire shape.

The third vertical channel pattern 140c may be connected to the third semiconductor pattern 126c. The third vertical channel pattern 140c may be disposed between the third data storage pattern 130c and the third buried insulating pattern 144c. The third channel pattern 140c may have substantially the same shape as the first channel pattern 140a and may include substantially the same material.

The third data storage pattern 130c may be disposed between the mold insulating layer 118 and the third channel pattern 140c. The third data storage pattern 130c may include substantially the same material as the first data storage pattern 130a and may have substantially the same structure. For example, as shown in FIG. 6C , the third data storage pattern 130c includes the first blocking insulating layer 132 in contact with the mold insulating layer 118 and the tunnel insulating layer 136 in contact with the third vertical channel pattern 140c. ), and a charge storage layer 134 therebetween.

The third buried insulating pattern 144c is disposed on the third semiconductor pattern 126c and may extend in the third direction D3 . The third buried insulating pattern 144c may be disposed to fill a space provided by the third channel pattern 140c. The third buried insulating pattern 144c may include a silicon oxide layer or a silicon nitride layer.

Each of the conductive pads 128 may be disposed on each of the cell channel structures 200a and on each of the first and second dummy channel structures 200b and 200c. Each of the conductive pads 128 may include a conductive material. Each of the conductive pads 128 may include an impurity region doped with an impurity. According to some embodiments, one end of the cell channel structure 200a in contact with the conductive pad 128 may include a drain region.

A common source region 152 may be formed in the substrate 100 exposed to the trench 150 separating the stack structures 30 from each other. For example, the common source region 152 may be disposed in the substrate 100 between the stack structures 30 and may extend in the first direction D1 . The common source region 152 may include, for example, N-type impurities (eg, arsenic (As) or phosphorus (P)).

A common source plug 166 may be formed in the trench 150 to be electrically connected to the common source region 152 . The common source plug 166 may extend in the first direction D1 . A separation insulating spacer 162 may be disposed between the stack structures 30 and the common source plug 166 . The isolation insulating spacer 162 may cover sidewalls of the stack structures 30 . According to some embodiments, the isolation insulating spacer 162 may fill between the stacked structures 30 adjacent to each other, and the common source plug 166 having a hole shape passes through the isolation insulating spacer 162 to provide a common common source plug 166 . It may contact the source region 152 . The isolation insulating spacer 162 may include silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. The common source plug 166 may include a conductive material (eg, tungsten, copper, silicon, or aluminum). Additionally, the common source plug 166 may include a barrier metal layer. For example, the barrier metal layer may include at least one of a transition metal (eg, titanium or tantalum) or a conductive metal nitride (eg, titanium nitride or tantalum nitride).

A capping insulating layer 148 and a first interlayer insulating layer 170 may be disposed on the stack structures 30 and the mold insulating layer 118 . The first interlayer insulating layer 170 may cover the common source plug 166 . Sub bit line contacts 168 passing through the first interlayer insulating layer 170 and the capping insulating layer 148 to connect to each of the conductive pads 128 , and sub bit line contacts 168 connecting to the sub bit line contacts 168 . The bit lines SBL may be disposed in the cell array area CAA. Each of the sub-bit lines SBL is disposed on the first interlayer insulating layer 170 and has a pair of cell vertical channel structures 200a adjacent in the second direction D2 with the trench 150 interposed therebetween. can be electrically connected.

A second interlayer insulating layer 174 covering the sub bit lines SBL may be disposed on the first interlayer insulating layer 170 . The capping insulating layer 148 and the first and second interlayer insulating layers 170 and 174 may include a nitride layer or an oxide layer.

Gate contacts 180 connecting to the pad parts GEP of the gate electrodes GE may be disposed in the connection area CTA. Each of the gate contacts 180 may penetrate the first and second interlayer insulating layers 170 and 174 , the capping insulating layer 148 , the mold insulating layer 118 , and the second blocking insulating layer 158 . have. Each of the gate contacts 180 may be connected to the pad portion GEP of the corresponding gate electrode GE. The height of each of the gate contacts 180 may increase as it approaches the boundary region BR in the first direction D1 .

A peripheral contact 182 may be disposed in the peripheral area PR. The peripheral contact 182 penetrates through the first and second interlayer insulating layers 170 and 174, the capping insulating layer 148, the mold insulating layer 118, and the peripheral protective layer 109 to at least the peripheral circuit element ( It can be connected to the source/drain region 107 of the PT).

Bit lines BL and first and second wirings M1 and M2 may be disposed on the second interlayer insulating layer 174 . The bit line BL may extend in the second direction D2 . Each of the bit lines BL may be connected to the corresponding sub bit lines SBL through the corresponding bit line contacts 176 . As a result, the bit lines BL may be electrically connected to the cell vertical channel structures 200a. The first wirings M1 may be electrically connected to the gate contacts 180 . Each of the first wirings M1 may electrically connect each gate electrode GE of the stacked structures 30 positioned at the same level. According to some embodiments, the first wirings M1 connected to the lowermost gate electrodes GE1 may not be electrically connected to each other. The second wirings M2 may be electrically connected to the peripheral contacts 182 . The second wirings M2 may be electrically connected to the first wirings M1 and/or the bit lines BL.

Sub bit line contact 168 , sub bit line SBL , bit line contact 176 , gate contact 180 , and peripheral contact 182 include a conductive material (eg, tungsten, silicon, or copper). can do. Additionally, the sub bit line contact 168 , the sub bit line SBL , the bit line contact 176 , the gate contact 180 , and the peripheral contact 182 may include a barrier metal layer. The barrier metal layer may include, for example, at least one of a transition metal (eg, titanium or tantalum) and/or a conductive metal nitride (eg, titanium nitride or tantalum nitride). The bit line BL and the first and second interconnections M1 and M2 may include metal (eg, aluminum or copper).

The first and second dummy channel structures 200b and 200c may not be electrically connected to the bit line BL, the first wiring M1, and the second wiring M2. Accordingly, the first and second dummy channel structures 200b and 200c may be electrically isolated.

8A to 18A and 8B to 18B are views for explaining a method of manufacturing a semiconductor memory device according to embodiments of the inventive concept. FIGS. 8A to 18A correspond to line I-I' of FIG. 2A. are cross-sectional views, and FIGS. 8B to 18B are cross-sectional views corresponding to the line II-II′ of FIG. 2A . 19A to 19C are enlarged views of portions B1 of FIG. 12A, B2 of FIG. 12B, and B3 of FIG. 12B.

8A and 8B , the peripheral circuit device PT and the stacked mold structure 10 may be formed on the substrate 100 . The substrate 100 includes a cell area CR including a cell array area CAA and a connection area CTA, a peripheral area PR spaced apart from the cell area CR, and a connection area of the cell area CR. CTA) and a boundary area BR between the peripheral area PR.

The substrate 100 may include a semiconductor material. For example, the substrate 100 may be a silicon (Si) single crystal substrate, a germanium (Ge) single crystal substrate, or a silicon-germanium (SiGe) single crystal substrate. According to some embodiments, the substrate 100 may be a semiconductor on insulator (SOI) substrate. For example, the substrate 100 may include a semiconductor active layer (eg, a silicon layer, a silicon-germanium layer, or a germanium layer) disposed on an insulating layer that protects transistors provided on the semiconductor substrate. The substrate 100 may be a semiconductor substrate of the first conductivity type (eg, P-type). A well region (not shown) may be formed in the substrate 100 .

The peripheral circuit device PT may be formed on the substrate 100 in the peripheral region PR. The peripheral circuit device PT may include a peripheral gate insulating layer 101 , a peripheral gate electrode 103 , and a source/drain region 107 adjacent to both sides of the peripheral gate electrode 103 . For example, in the formation of the peripheral circuit device PT, the peripheral gate insulating layer 101 and the peripheral gate electrode 103 are sequentially formed on the substrate 100 , and the substrate 100 adjacent to both sides of the peripheral gate electrode 103 . ) by implanting impurities into the source/drain region 107 . A peripheral gate spacer 107 may be formed on a sidewall of the peripheral gate electrode 103 . The peripheral circuit element PT may include, for example, a low-voltage or high-voltage transistor. A peripheral protective layer 109 may be formed on the substrate 100 to cover the peripheral circuit element PT. The peripheral passivation layer 109 may expose the substrate 100 in the cell region CR and the boundary region BR.

The peripheral gate insulating layer 101 may include an oxide layer (eg, a silicon oxide layer) or a high-k dielectic layer. The peripheral gate electrode 103 is formed of silicon (eg, polysilicon), metal silicide (eg, tungsten silicide (WSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicide (TiSi), tantalum) silicide (TaSi)), a metal (eg, tungsten or aluminum), and/or combinations thereof. The peripheral protective layer 109 may include an oxide film or a nitride film.

The mold structure 10 may be formed on the substrate 100 of the cell region CR, the substrate 100 of the boundary region BR, and the peripheral protective layer 109 of the peripheral region PR. The mold structure 10 may be formed by alternately repeatedly stacking insulating layers 110 and sacrificial layers 112 . The mold structure 10 may include a plurality of insulating layers 110 and a plurality of sacrificial layers 112 . The sacrificial layers 112 may be formed of a material having etch selectivity with respect to the insulating layers 110 . For example, the sacrificial layers 112 may have higher etch selectivity compared to the insulating layers 110 in a wet etching process using a chemical solution. For example, each of the insulating layers 110 may be a silicon oxide layer, and each of the sacrificial layers 112 may be a silicon nitride layer. According to some embodiments, each of the sacrificial layers 112 may be any one of a silicon carbide layer, a silicon layer, and a silicon germanium layer. According to other embodiments, each of the insulating layers 110 may be a silicon nitride layer, and each of the sacrificial layers 112 may be any one of a silicon oxide layer, a silicon carbide layer, a silicon layer, and a silicon germanium layer.

The insulating layers 110 and the sacrificial layers 112 are formed using a Thermal CVD process, a plasma enhanced CVD process, or an Atomic Layer Deposition (ALD) process. can be formed by

The sacrificial layers 112 may have the same thickness. According to some embodiments, the insulating layer 110 - 1 in contact with the substrate 100 may be a silicon oxide layer formed by a thermal oxidation process or a deposition process, and may be formed thinner than other insulating layers 110 . The second insulating layer 110 - 2 and the uppermost insulating layer 110 - 3 from the substrate 100 may be formed to be thicker than other insulating layers 110 or sacrificial layers 112 .

9A and 9B , the mold structure 10 may be patterned to have a stepwise structure in the connection area CTA. That is, the mold structure 10 may have an end 10e of a step structure. For example, the sacrificial layers 112 may have pad parts 112a forming a step structure. A portion of each of the pad portions 112a of the sacrificial layers 112 may be exposed. The vertical height of the mold structure 10 in the connection area CTA may increase in a stepwise manner as it is adjacent to the cell array area CAA.

A mold insulating layer 118 may be formed on the substrate 100 in the connection area CTA and the peripheral area PR. The mold insulating layer 118 may cover the end 10e of the mold structure 10 . For example, the mold insulating layer 118 may cover the pad portions 112a of the sacrificial layers 112 . The mold insulating layer 118 may cover the substrate 100 and the peripheral protective layer 109 of the boundary region BR. The mold insulating layer 118 may be in contact with the substrate 100 in the boundary region BR. The mold insulating layer 118 may include, for example, an oxide film or a low-k dielectic film.

10A and 10B , first channel holes 120a, second channel holes 120b, and third channel openings in the cell array area CAA, the connection area CTA, and the boundary area BR. 120c) may be formed respectively.

In the cell array area CAA, the first channel holes 120a may penetrate the mold structure 10 and expose the substrate 100 . For example, the first channel holes 120a may be formed by anisotropically etching the mold structure 10 . When the mold structure 10 is etched, the substrate 100 may be over-etched and recessed. When viewed from a plan view, the first channel holes 120a may be formed to be arranged in the same shape as the cell channel structures 200a illustrated in FIG. 2A .

In the connection area CTA, the second channel holes 120b may penetrate the mold insulating layer 118 and the end 10e of the step structure mold structure 10 to expose the substrate 100 . The second channel holes 120b may be formed by anisotropically etching the mold insulating layer 118 and the mold structure 10 . For example, the second channel holes 120b may include the mold insulating layer 118 and the end of the pad portion 112a of the step-shaped sacrificial layers 112 and at least one insulating layer 110 and the sacrificial layer below the mold insulating layer 118 . It may be formed by etching the layer 112 . When the second channel holes 120b are formed, the substrate 100 may be over-etched and recessed. The second channel holes 120b may be formed to be arranged in the same shape as the first dummy vertical channel structures 200b illustrated in FIG. 2A .

In the boundary region BR, the third channel opening 120c may be formed by etching the mold insulating layer 118 and the substrate 100 may be over-etched and recessed. The third channel opening 120c may have a hole shape as shown in FIG. 2A . A plurality of third channel openings 120c may be formed in a row in the second direction D2 . According to some embodiments, the third channel openings 120c may have a hole shape and may be arranged in a plurality of rows parallel to the second direction D2 as shown in FIG. 2C . According to some embodiments, each of the third channel openings 200c has a hole shape as shown in FIG. 7B , is disposed in the first direction D1 and the second direction D2 , and is disposed in the cell region CR. ) can be enclosed. According to some embodiments, as shown in FIG. 2B , the third channel opening 120c may have a trench shape (or a slit shape). As shown in FIG. 7A , the third channel opening 120c may have a trench shape (or a slit shape) and may extend in the second direction D2 . According to some embodiments, the third channel opening 120c has a trench shape and extends in the first and second directions D1 and D2 as shown in FIGS. 7C and 7D , or a cell region in a loop shape. (CR) can be surrounded.

11A to 11B , a first semiconductor pattern 126a and a second semiconductor pattern 126b are formed in the first channel holes 120a, the second channel holes 120b, and the third channel opening 120c; and third semiconductor patterns 126c may be respectively formed. Each of the first to third semiconductor patterns 126a , 126b , and 126c may be connected to the substrate 100 . A portion of each of the first to third semiconductor patterns 126a , 126b , and 126c may be embedded in the substrate 100 , and each other portion may protrude onto the substrate 100 to have a pillar shape. The first and second semiconductor patterns 126a and 126b are higher than the top surface of the lowermost sacrificial layer 112 among the sacrificial layers 112 , and are separated from the substrate 100 twice. Top surfaces of the insulating layer 110 - 2 may be positioned at a lower level than the top surface of the insulating layer 110 - 2 . Top surfaces of the first to third semiconductor patterns 126a , 126b , and 126c may have various shapes. For example, upper surfaces of the first to third semiconductor patterns 126a , 126b , and 126c may have a flat shape, an inclined shape with respect to the substrate 100 , or a spire shape.

Each of the first semiconductor patterns 126a may have a first height T1 . The first height T1 may be the maximum height from the surface of the substrate 100 to the top surface of the first semiconductor pattern 126a. The second semiconductor patterns 126b may include a first sub-semiconductor pattern 126b-1 and a second sub-semiconductor pattern 126b-2. The first sub-semiconductor pattern 126b - 1 is closest to the boundary region BR (eg, the third semiconductor pattern 126c) or the cell array region CAA (eg, the first semiconductor pattern). It may be located farthest from the fields 126a). The second sub-semiconductor pattern 126b - 2 may be closest to the cell array area CAA, for example, the first semiconductor patterns 120a. The first sub-semiconductor pattern 126b-1 may have a second height T2, and the second sub-semiconductor pattern 126b-2 may have a third height T3. The second height T2 is the maximum height from the surface of the substrate 100 to the top surface of the first sub-semiconductor pattern 126b - 1 , and the third height T3 is the height from the surface of the substrate 100 to the second sub-semiconductor pattern 126b - 1 . It may be the maximum height to the top surface of the pattern 126b - 2 . The third semiconductor pattern 126c may have a fourth height T4 . The fourth height T4 may be the maximum height from the surface of the substrate 100 to the top surface of the third semiconductor pattern 126c. The fourth height T4 may be smaller than the first to third heights T1 , T2 , and T3 . The first height T1 may be substantially equal to the third height T3 . The second height T2 may be smaller than the first and third heights T1 and T3 . According to some embodiments, as shown in FIG. 5 , the fourth height T4 may be higher than the second height T2 and smaller than the first and third heights T1 and T3 .

The first to third semiconductor patterns 126a , 126b , and 126c may be formed using the same process using a selective epitaxial growth method. The first to third semiconductor patterns 126a , 126b , and 126c may be epitaxial patterns including silicon (Si). For example, the first to third semiconductor patterns 126a , 126b , and 126c may be epitaxial patterns including single crystal silicon or polysilicon.

Selective epitaxial growth can be performed at high temperatures in the range of 700°C to 1000°C using, for example, Dichlorosilane (SiH2Cl2). Accordingly, impurities (eg, hydrogen, carbon, or nitrogen) generated from the mold insulating layer 118 may be outgassed through the third channel opening 120c. Due to the third channel opening 120c , the first sub-semiconductor pattern 126b - 1 formed in the second channel hole 120b closest to the boundary region BR can grow smoothly so that the lowermost sacrificial layer 112 is formed. It may have an upper surface higher than the upper surface.

According to a general technique without the third channel opening 120c, the amount of outgassing of impurities through the second channel hole 120b adjacent to the boundary region BR among the second channel holes 120b may be increased. Accordingly, growth of the second semiconductor patterns 126b adjacent to the boundary region BR may be suppressed. As a result, a top surface of the first sub-semiconductor pattern 126b - 1 may be lower than a top surface of the lowermost sacrificial layer 112 . Accordingly, the reliability of the memory semiconductor device may be deteriorated due to generation of a leakage current through the first sub-semiconductor pattern 126b - 1 .

According to the above-described embodiments of the present invention, since the third channel opening 120c is used as a passage through which impurities generated from the mold insulating layer 118 are discharged, the second semiconductor patterns 126b (eg, the second semiconductor pattern 126b) Inhibition of epitaxial growth of the first sub-semiconductor pattern 126b - 1 may be prevented.

According to some embodiments, the first to third semiconductor patterns 126a, 126b, and 126c may include germanium (Ge), silicon germanium (SiGe), a group III-V semiconductor compound, and/or a group II-VI semiconductor compound. Each of the first to third semiconductor patterns 126a , 126b , and 126c may be undoped with an impurity or doped with an impurity having the same conductivity type as that of the substrate 100 .

12A, 12B, 19A, 19B, and 19C , the cell channel structures 200a, the first dummy channel structures 200b, and the second dummy channel structure 200c are formed in the cell array area CAA. ), the connection area CTA, and the boundary area BR, respectively. Each of the cell channel structures 200a is formed in the first channel holes 120a, and the first dummy channel structures 200b ) may be formed in the second channel holes 120b, and the second dummy channel structure 200c may be formed in the third channel opening 120c. The cell channel structures 200a may be arranged in first and second directions D1 and D2 as shown in FIG. 2A .

Each of the cell channel structures 200a may include a first semiconductor pattern 126a , a first channel pattern 140a , a first data storage pattern 130a , and a first buried insulating pattern 144a . The first channel pattern 140a , the first data storage pattern 130a , and the first buried insulating pattern 144a may be formed on the first semiconductor pattern 126a .

The first data storage pattern 130a may cover inner walls of each of the first channel holes 120a. For example, the first data storage pattern 130a may be formed in the form of a spacer on each inner wall of the first channel hole 120a. For example, the first data storage pattern 130a may have an open top and an open bottom. The first data storage pattern 130a may contact the insulating layers 110 and the sacrificial layers 112 of the molding structure 10 . The first data storage pattern 130 may include a thin film capable of storing data. For example, the data storage pattern 130 may include a thin film capable of storing data using Fowler-Nordheim tunneling. According to some embodiments, the first data storage pattern 130a is a thin film capable of storing data based on a different operating principle (eg, a thin film for a phase change memory device or a thin film for a variable resistance memory device) may include

19A , the first data storage pattern 130a may include a first blocking insulating layer 132 , a charge storage layer 134 , and a tunnel insulating layer 136 . For example, the first blocking insulating layer 132 , the charge storage layer 134 , and the tunnel insulating layer 136 may be sequentially formed on the inner wall of the first channel hole 120a. The first blocking insulating layer 132 may include a silicon oxide layer and/or a high-k layer (eg, an aluminum oxide layer or a hafnium oxide layer). The first blocking insulating film 132 may be formed of a single film or a plurality of thin films. For example, the first blocking insulating layer 132 may be a single layer including a silicon oxide layer. For example, the first blocking insulating layer 132 may include a plurality of thin films including an aluminum oxide layer and/or a hafnium oxide layer.

The charge storage layer 134 may be a trap insulating layer or an insulating layer including conductive nano dots. The trap insulating layer may include, for example, a silicon nitride layer. The tunnel insulating layer 136 may be, for example, a silicon oxide layer. The first blocking insulating layer 132 and the charge storage layer 134 may be formed using a plasma enhanced CVD process or an atomic layer deposition (ALD) process. The tunnel insulating layer 136 may be formed using a plasma enhanced CVD process, an atomic layer deposition (ALD) process, or a thermal oxidation process. The tunnel insulating layer 136 may be in contact with the first channel pattern 140a.

The first channel pattern 140a may be in contact with the first data storage pattern 130a, and the first channel pattern 140a may be conformally formed in a liner shape in the first channel holes 120a. The first channel pattern 140a may be connected to the first semiconductor pattern 126a. The first channel pattern 140a may have an open top. According to some embodiments, the first channel pattern 140a may have an open top and bottom, a hollow cylinder shape, or a macaroni shape. According to some embodiments, the first channel pattern 140a may have a cylindrical shape filling the first channel holes 120a. The first channel pattern 140a may include a semiconductor material. The first channel pattern 140a may be a pattern including any one of a polycrystalline semiconductor material, an amorphous semiconductor material, or a single crystal semiconductor material. The first channel pattern 140a may be selected from among silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. It may include at least one. The first channel pattern 140a may be an undoped semiconductor material or a semiconductor material including impurities having the same conductivity type as that of the substrate 100 . The first channel pattern 140a may be formed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or an epitaxial growth process.

The first buried insulating pattern 144a may be formed to fill the first channel holes 120a in which the first channel pattern 140a is formed. The first buried insulating pattern 144a may include a silicon oxide layer or a silicon nitride layer.

Each of the first dummy channel structures 200b may include a second semiconductor pattern 126b, a second channel pattern 140b, a second data storage pattern 130b, and a second buried insulating pattern 144b. have. The second channel pattern 140b, the second data storage pattern 130b, and the second buried insulating pattern 144b may be formed on the second semiconductor pattern 126b.

The second data storage pattern 130b may cover inner walls of the second channel holes 120b. For example, the second data storage pattern 130b may be formed in the form of a spacer on inner walls of the second channel holes 120b. The second data storage pattern 130b has substantially the same structure as the first data storage pattern 130a of the cell channel structure 200a and may include the same material. For example, the second data storage pattern 130b may include a first blocking insulating layer 132, a charge storage layer 134, and a tunnel sequentially formed on inner walls of the second channel holes 120b as shown in FIG. 19B . An insulating layer 136 may be included.

The second channel pattern 140b may be in contact with the second data storage pattern 130b and may be conformally formed in the form of a liner in the second channel holes 120b. The second channel pattern 140b may be connected to the second semiconductor pattern 126b. The second channel pattern 140b may have substantially the same shape as the first channel pattern 140a and may include the same material. The second buried insulating pattern 144b may be formed to fill the second channel holes 120b in which the second channel pattern 140b is formed. The second buried insulating pattern 144b has substantially the same shape as the first buried insulating pattern 144a and may include the same material.

The second dummy channel structure 200c may include a third semiconductor pattern 126c, a third data storage pattern 130c, and a third buried insulating pattern 144c. The third channel pattern 140c, the third data storage pattern 130c, and the third buried insulating pattern 144c may be formed on the third semiconductor pattern 126c. The second dummy channel structure 200c may contact the mold insulating layer 118 .

The third data storage pattern 130c may cover the inner wall of the third channel opening 120c. For example, the third data storage pattern 130c may be formed in the form of a spacer on the inner wall of the third channel opening 120c. The third data storage pattern 130c may be in contact with the mold insulating layer 118 . The third data storage pattern 130c has substantially the same structure as the first data storage pattern 130a of the cell channel structures 200a and may include the same material. For example, as shown in FIG. 19C , the third data storage pattern 130c may include a first blocking insulating layer 132 , a charge storage layer 134 , and a tunnel insulating layer sequentially formed on the inner wall of the third channel opening 120c. (136). The first to third information storage patterns 130a, 130b, and 130c may be formed by the same process.

The third channel pattern 140c may be in contact with the third data storage pattern 130c and may be formed on the third semiconductor pattern 126c. The third channel pattern 140c may be conformally formed in a liner shape within the third channel opening 120c and may be connected to the third semiconductor pattern 126c. The third channel pattern 140c may have the same shape as the first channel pattern 140a and include the same material. The first to third channel patterns 140a, 140b, and 140c may be formed by the same process.

The third buried insulating pattern 144c may be formed to fill the third channel opening 120c in which the third channel pattern 140c is formed. The third buried insulating pattern 144c has substantially the same shape as the first buried insulating pattern 144a and may include the same material. The first to third channel patterns 140a, 140b, and 140c may be formed by the same process. The first to third buried insulating patterns 144a , 144b , and 144c may be formed by the same process.

The first to third data storage patterns 130a, 130b, and 130c may be formed using the same material and in the same process. The first to third channel patterns 140a, 140b, and 140c may be formed using the same material and in the same process. The first to third buried insulating patterns 144a , 144b , and 144c may be formed using the same material by the same process.

The second dummy channel structure 200c is viewed from a top view. It may have a circular shape or an elliptical shape shown in FIG. 2A , or a bar shape shown in FIG. 2B . 2A and 2B , the second dummy channel structures 200c may be arranged in a column along the second direction D2 in a plan view. For example, the second dummy channel structures 200c are spaced apart from the stacked structures 30 , and at least one is disposed adjacent to each of the stacked structures 30 and formed in a row in the second direction D2 . can be arranged. According to some embodiments, as shown in FIG. 2C , each of the second dummy channel structures 200c has a circular shape or an elliptical shape in a plan view, and is arranged in two rows parallel to the second direction D2. However, the present invention is not limited thereto and may be arranged in three or more rows parallel to the second direction D2. According to some embodiments, as shown in FIG. 7A , each of the second dummy channel structures 200c has a bar shape and moves in the second direction D2 between the connection area CTA and the peripheral area PR. It may be arranged to extend along. For example, each of the second dummy channel structures 200c may be spaced apart from the stack structures 30 in the first direction D1 and extend in the second direction D2 . According to some embodiments, as shown in FIGS. 7B and 7C , the second dummy channel structures 200c may surround the cell region CR. For example, the second dummy channel structures 200c are arranged between the connection area CTA and the peripheral area PR along the second direction D2 , and the cell area CR along the first direction D1 . ) and the peripheral region PR. According to some embodiments, as shown in FIG. 7D , the second dummy channel structure 200c may surround the cell region CR in a loop shape.

Conductive pads 128 may be formed on the cell channel structures 200a and the first and second dummy channel structures 200b and 200c, respectively. Each of the conductive pads 126 may include a conductive material. Each of the conductive pads 128 may include an impurity region doped with an impurity. According to some embodiments, one end of the cell channel structures 200 in contact with the conductive pads 128 may include a drain region. A capping insulating layer 148 may be formed on the mold structure 10 and the mold insulating layer 118 to cover the conductive pads 128 . The capping insulating layer 148 may include an oxide layer or a nitride layer.

13A and 13B , a trench 150 may be formed in the mold structure 10 in the cell region CR. The trench 150 may be formed by patterning the capping insulating layer 148 and the mold structure 10 to expose the substrate 100 . For example, as shown in FIG. 2A , the trench 150 may be formed to extend from the cell array area CAA to the connection area CTA in the first direction D1 , as shown in FIG. 2A . Similarly, the trench 150 may allow the cell channel structures 200a to be arranged in two rows in a zigzag shape in the first direction D1 . Accordingly, the cell channel structures 200a arranged in two rows in a zigzag form in the first direction D1 may be repeatedly disposed in the second direction D2 . According to some embodiments, the trench 150 may allow the cell channel structures 200a to be arranged in one or three or more rows in a zigzag form in the first direction D2 .

A common source region 152 may be formed in the substrate 100 exposed to the trench 150 . For example, the common source region 152 may be formed by ion-implanting N-type conductivity-type impurities (eg, phosphorus (P) or arsenic (As)) into the substrate 100 .

14A and 14B , openings 154 may be formed in the mold structure 10 in the cell array area CAA and the connection area CTA. For example, the openings 154 may be formed by removing the sacrificial layers 112 of the mold structure 10 exposed in the trench 150 . The openings 154 may be formed by removing the sacrificial layers 112 by isotropic etching. The openings 150 may be formed to expose some sidewalls of the cell channel structures 200a and the first dummy channel structures 200b.

A gate oxide layer 156 may be formed on the sidewalls 126as of the first semiconductor patterns 126a and the sidewalls 126bs of the second semiconductor patterns 126a. The gate oxide layer 156 may be formed by thermally oxidizing the sidewalls 126as and 126bs of the first and second semiconductor patterns 126a and 126b exposed by the openings 154 . In the cell region CR, the gate oxide layer 156 has a bulge shape and may be uniformly formed. For example, the gate oxide layer 156 may also be uniformly formed on the sidewalls 126bs of the first sub-semiconductor pattern 126b-1 of the second semiconductor patterns 126b. Since the gate oxide layer 156 is formed by a thermal oxidation process, the sidewalls 126as and 126bs of the first and second semiconductor patterns 126a and 126b may have concave cross-sections. Since the third semiconductor patterns 126c are not exposed by the openings 154 , the gate oxide layer 156 may not be formed on the sidewall 126cs of the third semiconductor pattern 126c in contact with the mold insulating layer 118 . can Accordingly, at least a portion of the sidewall 126cs of the third semiconductor pattern 126c may have a flat cross-section profile in the third direction D3 .

15A and 15B , a gate conductive layer 159 filling the openings 154 may be formed. The gate conductive layer 159 may include a semiconductor layer, a metal silicide layer, a metal layer, a metal nitride layer, or a combination thereof. For example, the semiconductor film may be a silicon film doped with impurities. As another example, the metal silicide layer may include cobalt silicide, titanium silicide, tungsten silicide, or tantalum silicide. The metal layer may include, for example, tungsten, nickel, cobalt, titanium, or tantalum. The metal nitride layer may include, for example, titanium nitride, tungsten nitride, or tantalum nitride.

Before the gate conductive layer 159 is formed, a second blocking insulating layer 158 may be formed in the opening 154 . Accordingly, the second blocking insulating layer 158 may surround the top, bottom, and side surfaces of the gate conductive layer 159 and may be in contact with the first blocking insulating layer 132 . The second blocking insulating layer 158 may be formed of a single layer or a plurality of thin films. The second blocking insulating layer 158 may include a high dielectric layer (eg, an aluminum oxide layer or a hafnium oxide layer). According to some embodiments, the second blocking insulating layer 158 may not be formed.

16A and 16B , the gate conductive layer 159 may be patterned to form gate electrodes GE. For example, an isotropic etching process may be performed to completely remove the gate conductive layer 159 formed in the trench 150 and on the capping insulating layer 148 . Accordingly, the gate electrodes GE separated by the insulating layers 110 in the third direction D3 may be formed.

The gate electrodes GE extend from the cell array area CAA to the connection area CTA, and may have pad parts GEP forming a stepwise structure in the connection area CTA. The horizontal lengths of the gate electrodes GE may decrease as they move away from the substrate 100 in the third direction D2.

As a result, stacked structures 30 including the insulating layer 110 and electrodes GE alternately repeatedly stacked in the third direction D3 may be formed on the substrate 100 in the cell region CR. have. As shown in FIG. 2A , the stack structures 30 may be formed to extend in a first direction D1 and to be separated from each other by a trench 150 in a second direction D2 . The cell channel structures 200a may pass through the stacked structures 30 , and the gate electrodes GE may surround the cell channel structures 200a. The first dummy channel structures 200b may penetrate a portion of the stack structures 30 . For example, the gate electrodes GE may surround a portion of the first dummy channel structures 200b. The stacked structures 30 may have an end 30e of a stepwise structure in the connection area CTA.

The gate electrodes GE may be combined with the cell channel structures 200a to form memory cells. Accordingly, vertical memory cell strings including vertically arranged memory cells may be provided in the cell array area CAA. The lowermost and uppermost gate electrodes GE1 and GE3 may be used as gate electrodes of the selection transistors SST and GST. The gate electrodes GE between the lowermost and uppermost gate electrodes GE1 and GE3 may be used as control gate electrodes of the memory cells.

A common source plug 166 and an isolation insulating spacer 162 may be formed on the common source region 152 to fill the trench 150 . The isolation insulating spacer 162 may protect side surfaces of the gate electrodes GE and may insulate the gate electrodes GE from the common source plug 166 . The isolation insulating spacers 162 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. The common source plug 166 may be formed in the trench 150 in which the insulating spacer 162 is formed to be electrically connected to the common source region 152 . The common source plug may be formed to extend in the first direction D1. According to some embodiments, the common source plug 166 having a hole shape may pass through the isolation insulating spacer 162 to contact the common source region 152 . The common source plug 166 may include a metal (eg, tungsten, copper, or aluminum). Additionally, the common source plug 166 may include a barrier metal layer. For example, the barrier metal layer may include at least one of a transition metal (eg, titanium or tantalum) and/or a conductive metal nitride (eg, titanium nitride or tantalum nitride). According to some embodiments, high-concentration impurities may be implanted into the common source region 152 before the common source plug 166 is formed.

17A and 17B , the sub bit line contacts 168 electrically connected to the cell channel structures 200a and the sub bit line contacts 168 are electrically connected to the cell channel structures 200a in the cell array area CAA. Sub-bit lines SBL may be formed.

A first interlayer insulating layer 170 may be formed on the capping insulating layer 148 . The first interlayer insulating layer 170 may include an oxide film, a low dielectric film, or a nitride film. Sub-bit line contacts 168 may be formed to penetrate the first interlayer insulating layer 170 and the camping insulating layer 148 to connect to the conductive pads 128 on the cell channel structures 200a.

The formation of the sub-bit line contacts 168 forms contact holes exposing the conductive pads 128 on the cell vertical channel structures 200a in the first interlayer insulating layer 170 and the capping insulating layer 148 , and , depositing a conductive film in the contact holes and planarizing the conductive film.

Sub bit lines SBL electrically connected to the sub bit line contacts 168 may be formed on the first interlayer insulating layer 170 . As shown in FIG. 2A , each of the sub bit lines SBL includes a pair of sub bit line contacts 168 connected to the neighboring cell channel structures 200a with the trench 150 interposed therebetween. It can be electrically connected. Each of the sub-bit lines SBL may have a pattern extending in the second direction D2 . Each of the sub-bit line contacts 168 and the sub-bit lines SBL may include a conductive material (eg, silicon, tungsten, or copper). Additionally, each of the sub bit line contacts 178 and the sub bit lines SBL may include a barrier metal layer. For example, the barrier metal layer may include at least one of a transition metal (eg, titanium or tantalum) and/or a conductive metal nitride (eg, titanium nitride or tantalum nitride).

18A and 18B , bit lines BL are formed in the cell array area CAA, gate contacts 180 and first wirings M1 are formed in the connection area CTA, and , peripheral contacts 182 and a second wiring M2 may be formed in the peripheral region PR.

A second interlayer insulating layer 174 covering the sub bit lines SBL may be formed on the first interlayer insulating layer 170 . The second interlayer insulating layer 170 may include an oxide film, a low dielectric film, or a nitride film. The second interlayer insulating layer 174 , the first interlayer insulating layer 170 , the capping insulating layer 148 , the mold insulating layer 118 , and the gate contact 180 passing through the second blocking insulating layer 158 are connected. It may be formed in the region CTA. Each of the gate contacts 180 may be connected to the pad portion GEP of the corresponding gate electrode GE. The height of each of the gate contacts 180 may increase as it approaches the boundary region BR in the first direction D1 .

Peripheral contacts 182 penetrating through the second interlayer insulating layer 174 , the first interlayer insulating layer 170 , the capping insulating layer 148 , the mold insulating layer 118 , and the peripheral protective layer 109 are formed around the periphery. It may be formed in the region PR. The peripheral contacts 182 may be connected to the source/drain region 107 of the peripheral circuit element PT.

The gate contacts 180 and the peripheral contacts 182 may include a conductive material (eg, silicon, tungsten, or copper). Additionally, gate contacts 180 and peripheral contacts 182 may include a barrier metal layer. For example, the barrier metal layer may include at least one of a transition metal (eg, titanium or tantalum) and/or a conductive metal nitride (eg, titanium nitride or tantalum nitride).

The bit lines BL may be formed on the second interlayer insulating layer 174 . The bit line BL may pass through the second interlayer insulating layer 174 and may be connected to bit line contacts 176 connected to the sub bit lines SBL. The bit lines BL may extend in the second direction D2 . The bit lines BL may be electrically connected to the cell channel structures 200a.

The first interconnections M1 that electrically connect the gate contacts 180 to each other may be formed in the connection area CTA. Each of the first wirings M1 may electrically connect the gate electrodes GE positioned at the same level. According to some embodiments, the first wirings M1 electrically connected to the lowermost gate electrodes GE1 may not be connected to each other.

The second interconnections M2 may be formed in the peripheral region PR and may be electrically connected to the peripheral contacts 182 . The second wirings M2 may be electrically connected to the first wirings M1 and/or the bit lines BL. The bit lines BL and the first and first interconnections M1 and M2 may include metal (eg, aluminum or copper).

The first and second dummy channel structures 200b and 200c may not be electrically connected to the bit line BL, the first wiring M1, and the second wiring M2. Accordingly, the first and second dummy channel structures 200b and 200c may be electrically isolated.

20 is a schematic block diagram illustrating a memory system including a semiconductor memory device according to embodiments of the inventive concept.

Referring to FIG. 20 , the memory system 1000 may be a semiconductor storage device. For example, the memory system 1000 may be a memory card or a solid state drive (SSD). The memory system 1000 may include a controller 1200 and a memory 1300 in a housing 1100 . The controller 1200 and the memory 1300 may exchange electrical signals. For example, according to a command of the controller 1200 , the memory 1300 and the controller 1200 may send and receive data. Accordingly, the memory system 1000 may store data in the memory 1300 or output data from the memory 1300 to the outside. The memory 1300 may include a semiconductor memory device according to embodiments of the inventive concept.

21 is a schematic block diagram illustrating an electronic system including a semiconductor memory device according to embodiments of the inventive concept.

Referring to FIG. 21 , the electronic system 2000 may include a controller 2200 , a storage device 2300 , and an input/output device 230 . The controller 2200 , the memory device 2300 , and the input/output device 230 may be coupled through a bus 2100 . The bus 2100 may be referred to as a path through which data moves. For example, the controller 2200 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic devices capable of performing the same function. The input/output device 230 may include at least one selected from a keypad, a keyboard, and a display device. The storage device 2300 is a device for storing data. The memory device 2300 may store data and/or instructions executed by the controller 2200 . The memory device 2300 may include a volatile memory device and/or a non-volatile memory device. The memory device 2300 may be formed of a flash memory. Such a flash memory may be configured as an SSD. In this case, the electronic system 2000 may stably store a large amount of data in the storage device 2300 . The memory device 2300 may include a semiconductor memory device according to embodiments of the inventive concept. The electronic system 2000 may further include an interface 2500 for transmitting data to or receiving data from the communication network. The interface 2500 may be in a wired/wireless form. For example, the interface 2500 may include an antenna or a wired/wireless transceiver.

In the above, embodiments of the technical idea of the present invention have been described with reference to the accompanying drawings, but those of ordinary skill in the art to which the present invention pertains can express the present invention in other specific forms without changing the technical spirit or essential features. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (18)

a stacked structure disposed on a substrate and in which gate electrodes and insulating layers are alternately stacked;
a cell channel structure penetrating the stack structure and including a first semiconductor pattern connected to the substrate and a first channel pattern disposed on the first semiconductor pattern and connected to the first semiconductor pattern; and
A first dummy spaced apart from the stacked structure and disposed on the substrate, the first dummy including a second semiconductor pattern connected to the substrate and a second channel pattern disposed on the second semiconductor pattern and connected to the second semiconductor pattern comprising a channel structure;
A first height from the surface of the substrate to the upper surface of the first semiconductor pattern is greater than a second height from the surface of the substrate to the upper surface of the second semiconductor pattern;
The substrate includes a cell region including a cell array region and a connection region adjacent to the cell array region, a peripheral region spaced apart from the cell region, and a boundary region between the cell region and the peripheral region;
The stacked structure is disposed in the cell region, extends in a first direction, and has an end of a step structure in the connection region. The method of claim 1,
The cell channel structure may further include a first data storage pattern disposed between the first channel pattern and the stacked structure. 3. The method of claim 2,
The first dummy channel structure further includes a second data storage pattern in contact with a sidewall of the second channel pattern, wherein the first channel pattern and the second channel pattern include the same material, and the first data storage pattern and the second data storage pattern include the same material. delete The method of claim 1,
Further comprising a peripheral circuit element disposed on the substrate in the peripheral region,
The peripheral circuit device includes a gate insulating layer, a gate electrode, and a source/drain region. The method of claim 1,
and a mold insulating layer covering the end portion of the stack structure and disposed on the substrate in the connection region, the boundary region, and the peripheral region, wherein the first dummy channel structure passes through the mold insulating layer and passes through the substrate and a semiconductor memory device to be connected to. 7. The method of claim 6,
A third semiconductor pattern passing through the mold insulating layer and the end of the stacked structure in the connection region and connected to the substrate, and a third channel pattern connected to the third semiconductor pattern and disposed on the third semiconductor pattern The semiconductor memory device further comprising a second dummy channel structure comprising: 8. The method of claim 7,
The first dummy channel structure may have a circular shape, an elliptical shape, or a bar shape when viewed in plan view. The method of claim 1,
The semiconductor memory device further includes a gate oxide layer disposed on a sidewall of the first semiconductor pattern, wherein the gate oxide layer is not disposed on a sidewall of the second semiconductor pattern. providing a substrate including a cell region including a cell array region and a connection region, a peripheral region spaced apart from the cell region, and a boundary region between the connection region and the peripheral region;
forming a mold structure including insulating layers and sacrificial layers alternately stacked on the substrate in the cell region;
forming a mold insulating layer covering a portion of the mold structure and on the substrate in the connection region, the boundary region, and the peripheral region;
a cell channel structure penetrating through the mold structure on the cell array region and including a first semiconductor pattern connected to the substrate and a first channel pattern disposed on the first semiconductor pattern and connected to the first semiconductor pattern; form;
a second semiconductor pattern passing through the mold insulating layer on the connection region and the mold structure and connected to the substrate; and a second channel pattern disposed on the second semiconductor pattern and connected to the second semiconductor pattern, respectively. forming first dummy channel structures to and
A second dummy channel structure including a third semiconductor pattern passing through the mold insulating layer in the boundary region and connected to the substrate, and a third channel pattern disposed on the third semiconductor pattern and connected to the third semiconductor pattern A method of manufacturing a semiconductor memory device comprising forming a. 11. The method of claim 10,
The first semiconductor pattern has a first height from a surface of the substrate to an upper surface of the first semiconductor pattern, the second semiconductor patterns include a first sub-semiconductor pattern closest to the third semiconductor pattern, and The first sub-semiconductor pattern has a second height from the surface of the substrate to the upper surface of the first sub-semiconductor pattern, and the third semiconductor pattern has a third height from the surface of the substrate to the upper surface of the third semiconductor pattern. , wherein the third height is smaller than the first height, and the second height is smaller than the first height. 12. The method of claim 11,
The second semiconductor patterns further include a second sub-semiconductor pattern closest to the first semiconductor pattern, wherein the sparse second sub-semiconductor pattern has a fourth height from the surface of the substrate to the upper surface of the second sub-semiconductor pattern. and wherein the fourth height is substantially equal to the first height. 12. The method of claim 11,
forming a peripheral circuit element on the substrate in the peripheral region; and
Further comprising forming a peripheral protective layer to protect the peripheral circuit element,
The peripheral circuit device includes a gate insulating layer and a gate electrode stacked on the substrate, and a source/drain region formed in the substrate adjacent to the gate electrode, wherein the mold insulating layer covers the peripheral protective layer. manufacturing method. 12. The method of claim 11,
The cell channel structure further includes a first data storage pattern in contact with a sidewall of the first channel pattern,
Each of the first dummy channel structures further includes a second data storage pattern in contact with a sidewall of the second channel pattern,
The second dummy channel structure further includes a third data storage pattern in contact with a sidewall of the third channel pattern, and
The first channel pattern, the second channel pattern, and the third channel pattern include the same material, and the first data storage pattern, the second data storage pattern, and the third data storage pattern include the same material. A method of manufacturing a semiconductor memory device comprising: 12. The method of claim 11,
The method of manufacturing a semiconductor memory device includes a plurality of second dummy channel structures, and each of the second dummy channel structures has a circular shape or an elliptical shape when viewed from a plan view and is arranged in one direction. 12. The method of claim 11,
The second dummy channel structure has a bar shape in a plan view and extends in one direction. 12. The method of claim 11,
The method further comprises forming a gate oxide layer on sidewalls of the first and second semiconductor patterns,
A method of manufacturing a semiconductor memory device in which the gate oxide layer is not formed on a sidewall of the third semiconductor pattern. 12. The method of claim 11,
removing the sacrificial layers to form openings;
forming a gate conductive film in the openings; and
The method of manufacturing a semiconductor memory device further comprising patterning the gate conductive layer to form gate electrodes.

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