KR101482633B1 - Nonvolatile memory device and method for fabricating the same - Google Patents

Abstract

A three-dimensional non-volatile memory device and a method of manufacturing the same are provided. A nonvolatile memory device includes a semiconductor substrate comprising a memory cell region and contact regions, active pillars extending perpendicular to the semiconductor substrate in the memory cell region, a plurality of active pillars extending from the memory region to the contact region, In the gate electrodes and the contact region, a plurality of supports extend perpendicular to the semiconductor substrate and pass through the gate electrodes.

3D, support, metal

Description

[0001] Nonvolatile memory device and method for fabricating the same [0001]

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device having a three-dimensional structure capable of reducing the resistance of gate electrodes and a method of manufacturing the same.

In general, a nonvolatile memory device is an element capable of electrically erasing and programming data, and capable of preserving data even when power is shut off. Accordingly, the use of nonvolatile memory devices is increasing in various fields in recent years.

Nonvolatile memory devices constitute various types of memory cell transistors, and are largely divided into NAND type and NOR type depending on the cell array structure. NAND type nonvolatile memory devices and NOR type nonvolatile memory devices have advantages and disadvantages that are divided into high integration and high performance.

In particular, the NAND type nonvolatile memory device is advantageous in high integration because of a cell string structure in which a plurality of memory cell transistors are serially connected. Since the NAND type nonvolatile memory device employs an operation method of simultaneously changing the information stored in the plurality of memory cell transistors, the information update speed is much faster than the NOR type nonvolatile memory device. Due to such high integration and fast update speed, NAND type nonvolatile memory devices are mainly used in portable electronic products requiring mass storage such as digital cameras or MP3 players. The advantages of such NAND type nonvolatile memory devices are continuously being explored and promoted, and a three-dimensional NAND type nonvolatile memory device is being developed.

The advantages of such NAND type nonvolatile memory devices are continuously being explored and promoted, and a three-dimensional NAND type nonvolatile memory device is being developed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a nonvolatile memory device capable of reducing the resistance of gate electrodes in a NAND type nonvolatile memory device having a three-dimensional structure.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of reducing the resistance of gate electrodes in a NAND type nonvolatile memory device having a three-dimensional structure.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a nonvolatile memory device including a semiconductor substrate including a memory cell region and contact regions, a plurality of active pillars extending perpendicularly to the semiconductor substrate, And a plurality of gate electrodes, each gate electrode including a first gate electrode across the active columns on the memory cell region and a second gate electrode connected to the first gate electrode and disposed on the contact region, .

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, comprising: preparing a semiconductor substrate including a memory cell region and contact regions; Forming a stack structure in which at least two insulating films are stacked, removing gate conductive films on the contact region in the stack structure to form first gate electrodes in the memory region, Forming second gate electrodes connected to and formed of a metallic material, and forming active columns through the first gate electrodes in the memory region.

The details of other embodiments are included in the detailed description and drawings.

According to the nonvolatile memory device of the three-dimensional structure of the present invention, it is possible to support the edge portions of the stacked gate electrodes by forming the support bars in the contact region. When a wet etching process is performed to fabricate a nonvolatile memory device having a three-dimensional structure, it is possible to prevent the interlayer insulating films from collapsing during the wet etching process.

In addition, the resistance of the gate electrode can be reduced by forming a part or all of the gate electrodes stacked in three dimensions from a metal material. Therefore, the operating speed of the nonvolatile memory device having a three-dimensional structure can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. Also, in this specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate, or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. A non-volatile memory device according to embodiments of the present invention has a three-dimensional structure.

1 is a circuit diagram showing a nonvolatile memory device according to embodiments of the present invention.

Referring to FIG. 1, a non-volatile memory device according to an embodiment of the present invention includes a cell array including a plurality of strings STR. The cell array includes a plurality of bit lines BL1 to BL3, word lines WL1 to WL4, upper and lower selection lines USL1 to USL3 and LSL, and a common source line CSL. And includes a plurality of strings STR between the bit lines BL1 to BL3 and the common source line CSL.

Each string STR includes a plurality of memory cell transistors MC connected in series between upper and lower selection transistors UST and LST and upper and lower selection transistors UST and LST. The drains of the upper select transistors UST are connected to the bit lines BL1 to BL3 and the sources of the lower select transistors LST are connected to the common source line CSL. The common source line CSL is a line to which the sources of the lower selection transistors LST are connected in common.

The upper select transistors UST are connected to the upper select lines USL1 to USL3 and the lower select transistors LST are connected to the lower select line LSL. Further, each memory cell MC is connected to the word lines WL1 to WL4.

Such cell arrays are arranged in a three-dimensional structure, and the strings STR have a structure in which memory cells MC are connected in series in a z-axis direction perpendicular to the xy plane parallel to the upper surface of the substrate. Accordingly, the channels of the selection transistors UST and LST and the memory cell transistors MC can be formed perpendicular to the xy plane.

In a nonvolatile memory device having a three-dimensional structure, m memory cells may be formed in each xy plane, and an xy plane having m memory cells may be stacked in n layers. (Where m and n are natural numbers).

Hereinafter, the nonvolatile memory device according to the first embodiment of the present invention will be described in detail with reference to FIGS. 2A to 2C and FIG.

2A is a top view of a nonvolatile memory device according to a first embodiment of the present invention. 2B and 2C are modified embodiments of the nonvolatile memory device according to the first embodiment of the present invention. 3 is a cross-sectional view of the nonvolatile memory device according to the first embodiment of the present invention, taken along the line I-I 'in FIGS. 2A to 2C.

Referring to FIGS. 2A and 3, on the semiconductor substrate 100, an interlayer insulating film 110 and gate electrodes are alternately laminated. More specifically, the semiconductor substrate 100 includes a memory cell region MR and a contact region CR disposed at an edge portion of the memory cell region MR. In the first embodiment of the present invention, the contact region CR is located around the memory cell region MR. And, in the embodiments of the present invention, the memory cell region MR and the contact regions CR are regions where gate electrodes are to be formed.

An impurity region (or well) 102 provided in a common source line (CSL in FIG. 1) is formed in the semiconductor substrate 100 and an interlayer insulating film 110 and gate electrodes LSL, WL, USL) are alternately stacked. In the stacked gate electrodes LSL, WL and USL, the uppermost and lowermost gate electrodes LSL and USL are used as selection lines and the remaining gate electrodes WL are used as word lines.

The lower selection lines LSL located in the lowermost layer may be formed in a plate form or in a line form separated from each other. The upper select lines USL located on the uppermost layer may be formed in the form of lines separated from each other. The word lines WL formed between the lower select line LSL and the upper select line USL may be formed in a plate shape. The area of the gate electrodes LSL, WL, and USL can be reduced and stacked as the area from the semiconductor substrate 100 to the upper portion is reduced.

In more detail, the gate electrodes LSL, WL and USL extend from the memory cell area MR to the contact area CR, and the gate electrode material on the memory cell area MR and the contact area CR The gate electrode material may be formed of different conductive materials. That is, the gate electrodes LSL, WL and USL of the memory cell region MR are formed of polysilicon and the gate electrodes LSL, WL and USL of the contact region CR have a resistivity specific resistance can be formed. For example, the gate electrodes LSL, WL, and USL of the contact region CR may be made of tungsten (W), aluminum (Al), titanium (Ti), or tantalum (Ta). Accordingly, the resistance of the gate electrodes LSL, WL, and USL can be reduced compared with the case where the gate electrodes LSL, WL, and USL are formed only of polysilicon. Therefore, the signal delay due to the increase of the resistance of the gate electrodes LSL, WL, USL can be reduced, so that the operating speed of the nonvolatile memory device can be improved. On the other hand, the gate electrode USL located in the uppermost layer and having a line shape may be made of a metal material in both the memory cell region MR and the contact regions CR.

Active pillars (PL) formed of a semiconductor material are formed in the memory cell region MR perpendicularly to the plane of the semiconductor substrate 100. The active pillars PL may pass through the gate electrodes LSL, WL, USL of the memory cell region MR. The active pillars PL are spaced apart from each other and can be arranged in a matrix form in a plane. The active pillars PL may be electrically connected to the impurity region 102 in the semiconductor substrate 100 through the gate electrodes LSL, WL and USL. These active pillars PL correspond to the respective strings of the non-volatile memory device according to the embodiments of the present invention, in which the channels of the memory cells are formed. That is, through the active pillars PL, the channels of the select transistors and memory cell transistors (LST, UST, MC in Fig. 1) of each string can be electrically connected.

Further, in the memory cell region MR, a charge storage film CS surrounding active pillars PL is formed. That is, the charge storage film CS is interposed between the active column PL and the gate electrodes LSL, WL, and USL. The bit lines BL are electrically connected to the active pillars PL.

The gate electrodes LSL, WL, USL on the contact region CR may be stacked in a stepped manner. In other words, since the area of the gate electrodes LSL, WL and USL of the planar structure is gradually reduced and stacked on the semiconductor substrate 100, the upper gate electrode can be stacked while exposing the end portion of the lower gate electrode . That is, the end portions of the gate electrodes LSL, WL, USL are not aligned with the sidewalls of the gate electrodes LSL, WL, USL at the upper and lower portions. Therefore, each gate electrode LSL, WL, USL of the contact region CR can be electrically connected to the global word lines GWL through the contacts CT.

In addition, in the contact region CR, a plurality of supporters SP may pass through a part of the gate electrodes LSL, WL, USL. The supporting posts SP may serve to support the edge portions of the interlayer insulating film 110 and the gate electrodes LSL, WL, and USL. Specifically, the support posts SP are formed in a column shape to penetrate the gate electrodes LSL, WL, USL and the interlayer insulating film 110. [ The supports SP are formed of an insulating material and can be connected to the interlayer insulating films 110 between the gate electrodes LSL, WL, and USL. In the first embodiment of the present invention, the supporting posts SP can penetrate the gate electrodes LSL and WL except the uppermost gate electrode USL. Further, in the first embodiment of the present invention, the plurality of support posts SP may have the same length. Supports SP having the same length can be formed at corner portions of the memory cell region MR, respectively. The support posts SP may be formed apart from each other at predetermined areas of the edge portions of the gate electrodes LSL, WL, USL as well as the edge portions.

Referring to FIGS. 2B, 2C, and 3, the support posts SP according to the first embodiment of the present invention may have various shapes instead of cylindrical columns.

That is, as shown in FIG. 2B, the support posts SP 'may be columns each having a line shape in a plan view. The line-shaped supports SP 'are located in the contact region CR of the gate electrodes LSL, WL and USL and are formed around the memory cell region MR. The support posts SP 'in the form of a line are spaced apart from each other, and may have the same or different lengths.

Further, as shown in Fig. 2C, the support posts SP '' may have a structure in which line patterns elongated in different directions are connected on a plane. The supports SP '' may take the form of wrapping the corner portions of the memory cell region MR, as shown in the figure.

Hereinafter, a nonvolatile memory device according to a second embodiment of the present invention will be described with reference to FIGS. 4 and 5. FIG. In the second embodiment, the detailed description of the technical features overlapping with the first embodiment of the present invention will be omitted, and the differences from the first embodiment will be described in detail.

4 is a top view of a nonvolatile memory device according to a second embodiment of the present invention. 5 is a cross-sectional view of a nonvolatile memory device according to a second embodiment of the present invention, taken along line II-II 'in FIG.

4 and 5, in the nonvolatile memory device according to the second embodiment of the present invention, the gate electrodes LSL, WL, USL extend from the memory cell region MR to the contact region CR Line shape. That is, the memory cell region MR corresponds to the central portion of the gate electrodes LSL, WL and USL in the form of a line, the contact region CR corresponds to one side or the other side of the gate electrodes LSL, And corresponds to both end portions. In the second embodiment of the present invention, it is described that the contact region CR corresponds to both side edge portions of the memory cell region MR.

The gate electrodes LSL, WL and USL in the form of a line on the memory cell region MR and the contact regions CR can all be formed of the same material. As in the first embodiment, the gate electrodes LSL , WL and USL may be formed of different conductive materials in the memory cell region MR and the contact regions CR. That is, the gate electrodes LSL, WL, and USL may be formed of a metal material in both the memory cell region MR and the contact regions CR. In addition, the gate electrodes LSL, WL, USL may be formed of polysilicon in the memory cell region MR and formed of a metal material in the contact region CR.

In the memory cell region MR, the plurality of active pillars PL extend through the stacked gate electrodes LSL, WL and USL, and in the contact region CR, the gate electrodes SP LSL, WL, and USL.

The active pillars PL are made of a semiconductor material and are connected to the semiconductor substrate 200 through the stacked gate electrodes LSL, WL and USL. A charge storage film CS is formed around the active pillars PL and bit lines BL across the gate electrodes LSL, WL and USL are electrically connected to the active pillars PL.

The supporting posts SP may be columns formed of an insulating material and may be spaced apart from the active pillars PL and formed in both end portions of the gate electrodes LSL, WL, USL (i.e., the contact region CR) . Specifically, in the second embodiment of the present invention, the supporting posts SP may be formed on one side of the active pillars PL located at the edge portion of the memory region MR, and the stacked gate electrodes LSL, WL, USL). In addition, each gate electrode LSL, WL, USL of the contact region CR can be electrically connected to the global word lines GWL through the contacts CT.

Meanwhile, the active pillars PL of the nonvolatile memory device according to the second embodiment of the present invention may be formed on one sidewalls of the gate electrodes LSL, WL, USL, as shown in Fig. 7 .

6 is a plan view of a nonvolatile memory device according to a third embodiment of the present invention. 7 is a cross-sectional view of a non-volatile memory device according to a third embodiment of the present invention, taken along line A-A 'and line B-B' in FIG.

Referring to FIGS. 6 and 7, gate electrodes WL and 250 in the form of a line are stacked, gate lines BL and 270 across the gate electrodes WL and 250 are stacked, (WL, 250). Active pillars PL ', 224, which are perpendicular to the semiconductor substrate 200, may be formed across one side walls of the stacked gate electrodes WL, 250. In the third embodiment, the active pillars PL ', 224 may be a structure formed through patterning on one side wall of stacked gate electrodes WL, 250 instead of a cylindrical shape. That is, on one sidewalls of the stacked gate electrodes WL and 250, the active pillars PL 'and 224 may be spaced apart from each other. The active pillars PL 'and 224 formed on one side wall of the gate electrodes WL and 250 are connected to the active pillars PL' and 224 crossing one side walls of the adjacent gate electrodes WL and 250, Can be formed to face each other. The charge storage film 245 is interposed between the upper and lower surfaces of the gate electrodes WL and 250 and one sidewalls contacting the active pillars PL 'and 224.

Further, as in the third embodiment, support posts SP for supporting the gate electrodes WL and 250 are formed on the contact region CR. The support posts SP may be circular columns formed of an insulating material and may penetrate all of the stacked gate electrodes WL and 250. Each of the gate electrodes WL and 250 of the contact region CR may be electrically connected to the global word lines GWL through the contacts CT.

Hereinafter, the nonvolatile memory device according to the fourth to sixth embodiments of the present invention will be described in detail.

8 is a plan view of a nonvolatile memory device according to a fourth embodiment of the present invention. FIG. 9 is a cross-sectional view of a nonvolatile memory device according to a fourth embodiment of the present invention, taken along the line I-I 'of FIG. In the fourth embodiment of the present invention, detailed description of technical features overlapping with the first embodiment of the present invention will be omitted, and differences from the first embodiment will be described in detail.

Referring to FIGS. 8 and 9, planar gate electrodes LSL, WL, and USL are stacked on the semiconductor substrate 100 via the interlayer insulating layers 110. FIG. Plate-shaped gate electrodes LSL, WL and USL are formed over the contact regions CR around the memory cell region MR and the memory cell region MR. In the contact region CR, the stacked gate electrodes LSL, WL, USL may have a stepped shape. In other words, the upper gate electrode is stacked while exposing the edge portion of the lower gate electrode. As the gate electrodes LSL, WL and USL are stacked in a stepwise manner, the interlayer insulating films between the gate electrodes LSL, WL and USL may also have a stacked structure in the form of a step.

A plurality of active pillars (PL) pass through the gate electrodes (LSL, WL, USL) of the memory cell region (MR). A plurality of support posts SP having different lengths may be formed on the gate electrodes LSL, WL, USL of the contact region CR. The supporting posts SP are formed between the interlayer insulating films 110 separated from each other and penetrate the gate electrodes LSL, WL, USL between the interlayer insulating films 110. [

A plurality of support posts SP having different lengths may be formed for each edge of each of the plate-shaped gate electrodes LSL, WL, USL. Then, the supporting posts SP adjacent to each other may gradually decrease in length from the memory cell region MR gradually. As the height of the support posts SP is different from each other, the number of the gate electrodes LSL, WL, USL through which the support posts SP pass is different. Therefore, the supporting posts SP can penetrate all or a part of the gate electrodes LSL, WL, USL. Also, between the adjacent supports SP, the interface of the upper and lower gate electrodes can be formed. Supports SP formed with different lengths in the contact region CR may be formed between the sidewalls of the vertically adjacent gate electrodes LSL, WL, USL.

10 is a plan view of a nonvolatile memory device according to a fifth embodiment of the present invention. 11 is a cross-sectional view of a nonvolatile memory device according to a fifth embodiment of the present invention, taken along line II-II 'in FIG.

10 and 11, the gate electrodes LSL, WL and USL are formed in a line shape and the active pillars PL are formed in the gate electrodes LSL, WL and USL of the memory cell region MR, Through. The gate electrodes LSL, WL and USL of the contact region CR and the supporting posts SP having different lengths pass through the gate electrodes LSL, WL and USL. That is, the support posts SP are located at both ends of the gate electrodes LSL, WL, USL. A plurality of support posts SP may be formed on the same line as the active posts PL, and the support posts SP on the same line are spaced apart from each other. Here, the active pillars PL and the adjacent pillars SP may pass through all the gate electrodes LSL, WL, and USL. The number of the first and second insulating films 210 and 215 through which the supporting posts SP pass may be sequentially reduced as the supporting posts SP are moved away from the memory cell region MR.

12 is a plan view of a nonvolatile memory device according to a sixth embodiment of the present invention.

Referring to FIG. 12, active pillars PL 'may be formed across one side walls of the stacked gate electrodes LSL, WL, USL. At this time, a charge storage film CS is formed between the active pillars PL 'and the gate electrodes LSL, WL and USL. 6, gate electrodes LSL, WL and USL of the contact region CR and support posts SP having different lengths pass through the gate electrodes LSL, WL and USL.

Although the support posts SP formed on the gate electrodes LSL, WL and USL of the contact region CR are described as pillars formed of an insulating material in the first to sixth embodiments of the present invention, May be the same structure as the active pillars PL. That is, the supporting posts SP of the contact region CR may also be formed of a semiconductor material, and between the supporting posts SP and the gate electrodes LSL, WL, USL, (CS) may be formed. In this case, since the supports SP of the contact region CR are not connected to the bit lines BL, they do not affect the operation of the non-volatile memory device.

Hereinafter, a method of manufacturing a non-volatile memory device according to embodiments of the present invention will be described in detail.

13A to 13G, a method of manufacturing a nonvolatile memory device according to the first and fourth embodiments of the present invention will be described in detail.

FIGS. 13A to 13G are views sequentially illustrating a method of manufacturing a non-volatile memory device according to the first and fourth embodiments of the present invention. In the method of manufacturing the nonvolatile memory device according to the first and fourth embodiments, the planar structure is described with reference to Fig. 2A, respectively.

Referring to FIG. 13A, an interlayer insulating film 110 and a conductive film 120 are repeatedly stacked on a semiconductor substrate 100 in order. The semiconductor substrate 100 includes a memory cell region MR and a contact region CR around the memory cell region MR and in the embodiments of the present invention the memory cell region MR and the contact region CR Are regions where gate electrodes are to be formed. The semiconductor substrate 100 may include an impurity region (or a well 102), and an interlayer insulating film 110 and a conductive film 120 may be formed on the entire surface of the semiconductor substrate 100. The interlayer insulating film 110 may be formed of a silicon oxide film, a silicon oxynitride film, or a silicon nitride film, and the conductive film 120 may be formed of a polysilicon film. The number of conductive films 120 to be stacked may vary depending on the capacity of the nonvolatile memory device.

The interlayer insulating layer 110 and the conductive layers 120 may be stacked on the entire surface of the semiconductor substrate 100 and then the dummy holes may be formed around the region where the memory cells are to be formed. That is, the laminated interlayer insulating film 110 and the conductive films 120 are subjected to a normal photolithography process to form dummy holes in the contact region CR. The dummy holes may penetrate the interlayer insulating film 110 and the conductive film 120 to expose the semiconductor substrate 100.

The dummy holes may be formed around the memory cell region MR, and specifically, at the corner portions of the contact region CR, as shown in FIG. Here, the planar structure of the dummy holes formed at the corner portions of the contact region CR may be formed in various shapes as shown in FIGS. 2A to 2C.

Further, as shown in FIG. 8, a plurality of dummy holes may be formed for each corner portion of the contact region CR. At this time, the dummy holes are gradually distanced from the memory cell area MR. The position at which the dummy holes are formed may be the interface between the upper and lower gate electrodes to be formed by a subsequent process.

Referring to FIG. 13B, an insulating material is buried in the dummy holes to form supports 130. At this time, the supporting members 130 may be formed of the same material as the interlayer insulating film 110. The insulating layer 115 may be formed up to the uppermost layer of the film when the supporting bars 130 are formed. The support rods 130 formed in this manner are in contact with the semiconductor substrate 100 through the interlayer insulating film 110 and the conductive films 120.

Thereafter, a planar interlayer insulating film 110 and a conductive film 120 are formed over the memory cell region MR and the contact region CR. That is, the stacked interlayer insulating film 110 and the conductive films 120 may be patterned to form square-shaped gate electrodes over the memory cell region MR and the contact region CR. In other words, by patterning the stacked interlayer insulating film 110 and the conductive films 120, a rectangular stack structure can be formed in the memory cell region MR and the contact regions CR of the semiconductor substrate 100 have. In the embodiments of the present invention, the stack structure means a structure in which the interlayer insulating film 110 and the conductive films 120 are alternately stacked. As the stacked structure of the rectangular shape is formed, the sidewalls of the stacked interlayer insulating film 110 and the conductive films 120 can be exposed. On the other hand, forming the rectangular stacked structure may proceed before forming the supports 130.

Referring to FIG. 13C, a portion of the conductive films 120 is removed by supplying an etching solution having a high etching selectivity to the conductive films 120 to the side walls of the rectangular stack structure. By using the etching solution, the conductive film 120 can be selectively etched while gradually penetrating the etching solution from the edge of the stack structure to the center. At this time, since the support rods 130 are spaced apart from each other in the contact region CR, the conductive films 120 can be removed to the inner portion of the support rods 130. That is, the conductive films 120 remain only on the memory cell region MR through the wet etching process, and the contact region CR includes the interlayer insulating films 110 and the supports 130 ). Here, the conditions of the wet etching process, such as the supply time of the etching solution, the concentration of the etching solution, the supply ratio of the etching solutions, etc., can be controlled to remove the conductive films 120 of the contact region CR. As such, after the wet etching process, the remaining conductive films 122 can define the memory cell region MR of the gate electrodes.

A capillary force is applied to the interlayer insulating film 110 by the voids formed between the interlayer insulating films 110 while the conductive films 120 of the contact region CR are removed through the wet etching process. Can occur. Accordingly, the upper and lower interlayer insulating films 110 may tend to adhere to each other. Therefore, as the etching solution is continuously supplied between the interlayer insulating films 110, the interlayer insulating films 110 may collapse. However, in the embodiments of the present invention, since the contact region (CR) supports 130 are formed perpendicular to the interlayer insulating films 110, the interlayer insulating films 110 of the contact region CR are broken, Can be prevented. That is, when removing a part of the conductive films 120 of the contact region CR, the supports 130 may serve to maintain a distance between the interlayer insulating films 110 stacked.

In other words, during the removal of the conductive films 120 of the contact region CR, interlayer insulating films 110, which are horizontal and spaced apart from the semiconductor substrate 100 in the contact region CR, The support rods 130 formed vertically with respect to the support rods 100 remain. That is, in the contact region CR, an empty space is formed between the interlayer insulating films 110, and the supporting bars 130 support the interlayer insulating films 110 separated from each other.

Referring to FIG. 13D, a metal film 140 is deposited on the entire surface of the stack structure where the conductive films 120 of the contact region CR are removed. That is, the metal film 140 may be filled between the interlayer insulating films 110 of the contact region CR, and may be deposited on the semiconductor substrate 100 and the top surface of the stack structure around the stack structure. The metal film 140 filled between the interlayer insulating films 110 of the capacitor CR may be in contact with the conductive film 120 of the memory cell region MR. At this time, the metal film 140 is, for example, a conductive metal such as W, Al, Cu, Pt, Ru, metal material such as Ir, TiN, TaN, conducting metal nitrides, or RuO _2, IrO _2, such as WN A single layer made of oxide, or a composite layer made of a combination of these.

13E, a metal film 140 covering the stack structure is patterned to form metal film patterns 142 in the form of a step in the contact region CR. At this time, when the metal film 140 is formed to the top surface of the stack structure, the metal film 140 of the uppermost layer may be covered with the insulating film 150. Accordingly, the metal film patterns 142 can be reduced in area from the semiconductor substrate 100 toward the upper portion. That is, as the metal film 140 is patterned in the form of a step, gate electrodes 122 and 142 having a flat plate shape and having an area reduced toward the top can be formed. The gate electrodes 122 and 142 may have a memory cell region MR made of a conductive film 122 and a contact region CR made of a metal film 142. [

On the other hand, when the metal film patterns 142 are formed in the contact region CR, the metal film 140 deposited on the insulating film 115 on the uppermost layer can be patterned into line patterns 144 separated from each other. That is, on the insulating film 115 on the uppermost layer, gate electrodes 144 in the form of a line may be formed. In the memory cell region MR and the contact regions CR, the uppermost gate electrodes 144 are made of a metal material. The gate electrodes 144 in the form of a line formed on the stack structure are used as the upper select lines (USL1 to USL3 in Fig. 1) in the embodiments of the present invention. Since the uppermost gate electrodes 144 are formed after forming the supports 130, the supports 130 do not penetrate the gate electrode 144 of the uppermost layer.

8, when a plurality of support posts SP are formed in the contact region CR, when the metal film patterns 142 in the form of a step are formed, the supports 130 adjacent to each other are also formed It can be etched in a stepped shape.

Referring to FIG. 13F, after the gate electrodes are formed on the semiconductor substrate 100, an insulating film 160 that completely covers the stacked gate electrodes may be formed. In the memory cell region MR, active pillars 174 passing through the stacked gate electrodes and a charge storage layer 172 surrounding the active pillars 174 are formed. In detail, a plurality of channel holes are formed through the interlayer insulating film 110 and the conductive film 122 stacked in the memory cell region MR. Specifically, a mask pattern (not shown) is formed on the uppermost insulating layer 150, and the interlayer insulating layer 110 and the conductive layers 122 are selectively anisotropically etched using the mask pattern to form channel holes can do. The channel holes thus formed can expose the impurity region 102 of the semiconductor substrate 100. The plurality of channel holes may be formed in a planar matrix.

Thereafter, the charge storage film 172 is conformally deposited along the surface of the channel holes. That is, the charge storage film 172 may be formed on the sidewalls of the interlayer insulating film 110 and the conductive film 122 exposed by the channel hole. In one embodiment, the charge storage layer 172 may be formed by depositing a charge tunneling layer, a charge trap layer, and a charge blocking layer sequentially. That is, an oxide film, a nitride film, and an oxide film can be sequentially formed on the surface of the channel hole

In the channel holes in which the charge storage film 172 is formed, the active materials 174 are formed by filling the semiconductor material. Here, the filling of the semiconductor material in the channel holes may be performed by performing an epitaxial process using the semiconductor substrate 100 as a seed layer, or by depositing a semiconductor material. The semiconductor material may be a polycrystalline or single crystal semiconductor. Thereafter, the semiconductor material filled in the channel holes may be planarized to expose the upper surface of the uppermost insulating film 150.

Referring to FIG. 13G, contact (CR in FIG. 2A) may be formed in the contact region (CR) gate electrodes 142, which are connected one-to-one with the gate electrodes 142. At this time, since the gate electrodes 142 of the contact region CR are formed in a stepped shape, the lengths of the contacts (CT of FIG. 2A) may also be different.

After forming the contacts (CT of FIG. 2A), bit lines 180 are formed which are connected to active pillars 174. The bit lines 180 are formed across the gate electrodes 144 formed on the top layer. And, when forming the bit lines 180, a global word line (GWL of FIG. 2) may be formed which is connected to the gate electrodes 42 of each layer on the contacts (CT of FIG. 2A).

14A to 14F, a method of manufacturing the nonvolatile memory device according to the second and fifth embodiments of the present invention will be described in detail.

FIGS. 14A to 14F are cross-sectional views taken along line II-II 'of FIG. 10, illustrating a method of fabricating a non-volatile memory device according to the second and fifth embodiments of the present invention.

14A, first and second insulating films 210 and 215 having different etch selectivities are alternately formed on a semiconductor substrate 200 including a memory cell region MR and contact regions CR Laminated. Specifically, the first and second insulating films 210 and 215 are formed of materials having different wet etching rates. For example, the first and second interlayer insulating films 210 and 215 may be formed of a silicon oxide film and a silicon nitride film, respectively.

Thereafter, active pillars 224 passing through the first and second insulating films 210 and 215 and a charge storage film 222 surrounding the active pillars 224 are formed in the memory cell region MR.

In detail, a plurality of channel holes are formed in the memory cell region MR through the first and second insulating films 210 and 215. The channel holes may be formed by performing a normal photolithography and etching process. The channel holes may expose the impurity region 202 of the semiconductor substrate 200 and may be formed in a matrix form in the planar memory cell region MR. Thereafter, the charge storage film 222 is formed conformally along the surface of the channel holes, and the deposited charge storage film is anisotropically etched to form a charge storage film 222 (only on the sidewalls of the first and second insulating films 210 and 215) ), And exposes the surface of the semiconductor substrate 200. For example, the charge storage film 222 may be formed by depositing a charge tunneling film, a charge trap film, and a charge blocking film in order. Subsequently, semiconductor material is buried in the channel holes to form the active pillars 224. In this case, the semiconductor material may be a polycrystalline or single crystal semiconductor, or may be formed by epitaxial processing using the semiconductor substrate 200 as a seed layer, or by depositing a semiconductor material. Thereafter, the semiconductor material filled in the channel holes may be planarized to expose the upper surface of the uppermost first insulating film 210.

Referring to FIG. 14B, support bars 230 penetrating the first and second insulating films 210 and 215 are formed in the contact region CR. More specifically, a plurality of dummy holes are formed for forming the supports 230 around the memory cell region MR. The dummy holes may expose the surface of the semiconductor substrate 200. Then, insulating material may be buried in the dummy holes, and the upper portion may be planarized to form columnar supports 230.

Specifically, the supports 230 may be formed in line with the active pillars 224 of the memory cell region MR, and the pillars 230 may be formed symmetrically with respect to each other with the memory cell region MR therebetween . 5, the support bars 230 may be formed on both sides of the memory cell region MR, respectively, or may be formed on both sides of the memory cell region MR, as shown in FIG. 10, A dog can be formed. The plurality of support bars 230 formed on both sides of the memory cell region MR may be spaced apart from each other by a predetermined distance.

Referring to FIG. 14C, the first and second insulating films 210 and 215 of the contact region CR in which the support bars 230 are formed are patterned in the form of a step.

In the contact region CR, the height of the stacked first and second insulating films 210 and 215 decreases gradually toward the edge. Here, by patterning the first and second insulating films 210 and 215 in a stepwise manner, the supports 230 of the contact region CR can also be etched together. That is, the support adjacent to the memory cell region MR penetrates both the first and second insulating films 210 and 215, and the remaining supports may be sequentially etched. Therefore, when the plurality of support bars 230 are formed on both sides of the memory cell region MR, the length of the plurality of support bars 230 decreases toward the edge of the contact region CR.

On the other hand, when the support bars 230 are formed on both sides of the memory cell region MR, the support bars 230 are not etched when patterning the stacked first and second insulation films 210 and 215 in a stepwise manner . That is, the support bars 230 may penetrate both the first and second insulating films 210 and 215 stacked.

After the first and second insulating films 210 and 215 of the contact region CR are patterned in a stepwise manner, an insulating film 240 is formed on the stepped first and second insulating films 210 and 215 .

Next, the first and second insulating films 210 and 215 stacked in the form of a plate across the memory cell region MR and the contact regions CR are patterned to form stacked structures in the form of a line. Patterning of the first and second insulating films 210 and 215 in a line shape may be performed before forming the active pillars 224 or the supporting pillars 230. At this time, the line-shaped stack structure can expose the sidewalls of the first and second insulating films 210 and 215, and includes active columns 224 and supports 230 arranged in a line.

Referring to FIG. 14D, the second insulating films 215 formed between the first insulating films 210 are removed. Specifically, the second insulating layer 215 may be removed by supplying an etching solution having a high etching selectivity to the second insulating layer 215 to the front surface of the semiconductor substrate 200 on which the stacked structures in a line form are formed. The first insulating layer 210 is spaced apart from the first insulating layer 210. The first insulating layer 210 is spaced apart from the active pillars 224 of the memory cell region MR, (Not shown).

Referring to FIG. 14E, a conductive material may be filled between the first insulating layers 210 to form the gate electrodes 250 in the form of a line. More specifically, when a conductive material is deposited between the first insulating layers 210, a conductive layer 250 may be formed between the first insulating layers 210 to surround the active columns 224 and the supports 230. have. Thereafter, the conductive film 250 filled in between the adjacent line-shaped stack structures may be removed to form the gate electrodes 250 in the form of a line. Here, the conductive material may be polysilicon or a metal material.

Referring to FIG. 14F, contact plugs 260 connected to the gate electrodes 250 of the respective layers are formed in the contact regions CR of the gate electrodes 250. In the contact plugs 260, since the gate electrodes 250 of the contact region CR are formed in a stepped shape, the lengths of the respective angles can be changed.

After forming the contact plugs 260, they are electrically connected to the active pillars 224 and form bit lines 270 across the gate electrodes 250. Global word lines 275 may also be formed on the contact plugs 260.

Meanwhile, the nonvolatile memory device according to the second and fifth embodiments of the present invention may be manufactured by the manufacturing method shown in Figs. 15A to 15E.

FIGS. 15A to 15E are views sequentially illustrating another method of manufacturing the nonvolatile memory device according to the second and fifth embodiments of the present invention, and are cross-sectional views taken along the line II-II 'in FIG.

15A, first and second insulating films 210 and 215 having different etch selectivities are repeatedly stacked on a semiconductor substrate 200, and the first and second insulating films 210 and 215 are stacked over the memory cell region MR and the contact region CR Thereby forming a stacked structure in the form of a flat plate. That is, the sidewalls of the first and second insulating films 210 and 215 are aligned.

In a stacked structure in the form of a flat plate, the first and second insulating films 210 and 215 stacked on the contact region CR are patterned in the form of a step. That is, in the contact region CR, the stacking height of the first and second insulating films 210 and 215 gradually decreases toward the edge of the first and second insulating films 210 and 215.

Then, the planar stack structure is covered with an insulating film and planarized to equalize the heights of the memory cell region MR and the contact region CR. That is, the insulating film 240 may be formed on the stack structure in the form of a step.

Referring to FIG. 15B, active pillars 224a are formed in the memory cell region MR and supports 224b are formed in the contact region CR.

More specifically, channel holes are formed in the memory cell region MR and dummy holes are formed in the contact region CR. The channel holes and the dummy holes may be formed by performing a normal photolithography process, and the channel holes may be formed in a planar matrix form. The dummy holes may be formed on one side of the channel holes located at the edge of the memory cell region MR, as shown in FIG. Also, as shown in FIG. 10, a plurality of dummy holes may be formed on the same line as the channel holes, and the dummy holes formed in the same line are spaced apart from each other. Here, the dummy hole adjacent to the channel hole may penetrate through all the first and second insulating films 210 and 215 stacked. The number of the first and second insulating films 210 and 215 passing through as the dummy holes are moved away from the memory cell region MR is sequentially reduced.

Then, charge storage films 222a and 222b are formed on the sidewalls of the channel holes and the dummy holes, and the semiconductor material is buried in the channel holes and the dummy holes to form the active pillars 224a and the supporting pillars 224b. That is, the charge storage layers 222a and 22b may be formed around the active pillars 224a of the memory cell region MR and the supports 224b of the contact region CR. Also, the active pillars 224a and the supporting members 224b may be formed to have the same length. On the other hand, the active pillars 224a of the memory cell region MR pass all of the stacked first and second insulating films 210 and 215, and the supports 224b of the contact region CR are connected to the first and second And may penetrate a part of the second insulating films 210 and 215.

 Referring to FIG. 15C, a planar stack structure including active pillars 224a and supports 224b may be patterned to form stacked structures in the form of a line. By forming the stack structures in the form of a line, the sidewalls of the first and second insulating films 210 and 215 can be exposed. Then, the second insulating film 215 is removed by supplying an etching solution having a high etching selection ratio to the first insulating film 210 between the stacked structures in the form of a line. As a result, an empty space is formed between the first insulating films 210 that are horizontal to the semiconductor substrate 200 and are spaced apart from each other. At this time, the first insulating films 210 separated from each other are electrically connected to the active pillars 224a of the memory cell region MR extending perpendicularly to the semiconductor substrate 200 and the supporting pillars 224b of the contact region CR, As shown in FIG. That is, when the second insulating films 215 are removed through the wet etching process, the distance between the first insulating films 210 can be reduced or collapsed.

Referring to FIG. 15D, a conductive material may be filled between the first insulating layers 210 to form gate electrodes 250 in the form of a line. Specifically, when a conductive material is deposited between the first insulating films 210, the conductive films 250 may be formed around the active pillars 224a and the supporting posts 224a. Thereafter, the gate electrode 250 in the form of a line may be formed between the first insulating films 210 by removing the conductive film 250 filled between the adjacent line-shaped stack structures. Here, the conductive material may be polysilicon or a metal material.

Referring to FIG. 15E, contact plugs 260 are formed in the contact region CR of the gate electrodes 250, which are connected to the gate electrodes 250 of the respective layers. In the contact plugs 260, since the gate electrodes 250 of the contact region CR are formed in a stepped shape, the lengths of the contact plugs 260 can be changed.

After forming the contact plugs 260, they are electrically connected to the active pillars 224 and form bit lines 270 across the gate electrodes 250. Global word lines 275 may also be formed on the contact plugs 260.

On the other hand, since the conductive pattern is not formed on the support lines 224b such as the bit line 270 or the global word line 275, the operation of the nonvolatile memory device according to the embodiment of the present invention is not affected.

Hereinafter, a method of manufacturing the nonvolatile memory device according to the third and sixth embodiments of the present invention will be briefly described.

The nonvolatile memory device according to the third and sixth embodiments of the present invention is a method of forming the supports of the contact region except for the method of forming the active columns of the memory cell region, The method of manufacturing the nonvolatile memory device may be the same as that of the nonvolatile memory device. Therefore, with reference to FIG. 6 and FIGS. 16A to 16E, a method of forming active columns of a memory cell region will be briefly described.

FIGS. 16A to 16E are views sequentially illustrating the method of manufacturing the nonvolatile memory device according to the third and sixth embodiments of the present invention, and are cross-sectional views taken along line A-A 'and line B-B' .

Referring to FIG. 16A, first and second insulating films 210 and 215 having different etching ratios are alternately stacked on a semiconductor substrate 200. The first trenches T1 are formed in a line shape to expose the semiconductor substrate 200 to the first and second insulating films 210 and 215. [ As the first trenches T1 are formed, the first sidewalls of the stacked first and second insulating films 210 and 215 can be exposed.

Referring to FIG. 16B, the active pillars 224 are formed on the first sidewalls of the first and second insulating films 210 and 215 exposed by the first trench T1. The active pillars 224 extend perpendicular to the semiconductor substrate 200. The active pillars 224 form a semiconductor layer conformally along the surface of the first trenches T 1 and are formed by anisotropically etching the semiconductor layer so that the active pillars 224 can be formed to face each other . After the active pillars 224 are formed, an insulating material is buried and planarized in the first trench Tl to form an insulating film 225 between the semiconductor layers.

After the insulating film 225 is formed, the semiconductor layers formed on the first sidewalls of the first and second insulating films 210 and 215 can be patterned. Accordingly, active pillars 224 spaced from each other on the first sidewalls of the first and second insulating films 210 and 215 can be formed.

Then, support posts SP penetrating the first and second insulating films 210 and 215 are formed in the contact region CR. The position and method of forming the supports SP are substantially the same as those described above in the second and fourth embodiments.

16C, second trenches T2 in the form of a line are formed on the first and second insulating films 210 and 215 so that the second trenches T2 of the first and second insulating films 210 and 215, Lt; / RTI > At this time, the second trenches T2 may be formed between the first trenches T1 to form stacked structures in the form of a line. The line-shaped stack structure includes support posts (SP) at the edge portion.

Referring to FIG. 16D, the second insulating films 215 between the stacked first insulating films 210 are removed through a wet etching process. Accordingly, second trenches T2 'may be formed to expose the sidewalls of the active pillars 224. At this time, the supporting posts SP on the contact region CR are formed of a material having an etching selection ratio in the second insulating film 215, and support the first insulating films 210 positioned vertically spaced apart from each other by a predetermined distance.

Then, as shown in FIG. 16E, the charge storage film 245 and the gate electrodes 250 are formed in order in the second trenches T2 '. The charge storage film 245 and the gate conductive film can be patterned so that the charge storage film 245 and the gate electrode 250 can be formed on the upper and lower portions of the first insulating films 210. That is, the gate conductive film in the second trench T2 'can be separated into the gate electrodes 250 in the form of a line. An insulating film 255 is buried between the gate electrodes 250 separated by the lines. Subsequently, bit lines 270 may be formed on the stacked gate electrodes 250 and electrically connected to the active pillars 224.

17 is a schematic diagram of a memory system including a non-volatile memory device in accordance with embodiments of the present invention.

17, the memory system 1100 may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, A memory card, or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes an input / output device 1120 such as a controller 1110, a keypad, a keyboard and a display, a memory 1130, an interface 1140, and a bus 1150. Memory 1130 and interface 1140 are in communication with one another via bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process device. Memory 1130 may be used to store instructions executed by the controller. The input / output device 1120 may receive data or signals from outside the system 1100, or may output data or signals outside the system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display device.

Memory 1130 includes a non-volatile memory device in accordance with embodiments of the present invention. Memory 1130 may also include other types of memory, volatile memory that may be accessed at any time, and various other types of memory.

The interface 1140 serves to transmit data to and receive data from the communication network.

18 is a block diagram briefly showing an example of a memory card having a flash memory device according to an embodiment of the present invention.

Referring to FIG. 18, a memory card 1200 for supporting a high capacity data storage capability mounts a flash memory device 1210 according to the present invention. The memory card 1200 according to the present invention includes a memory controller 1220 that controls the exchange of all data between the host and the flash memory device 1210.

The SRAM 1221 is used as the operating memory of the processing unit 1222. The host interface 1223 has a data exchange protocol of a host connected to the memory card 1200. Error correction block 1224 detects and corrects errors contained in data read from multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs all control operations for data exchange of the memory controller 1220. Although it is not shown in the drawing, the memory card 1200 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned.

According to the above flash memory device and memory card or memory system of the present invention, it is possible to provide a reliable memory system through the flash memory device 1210 with the erase characteristics of the dummy cells improved. In particular, the flash memory device of the present invention can be provided in a memory system such as a solid state disk (SSD) device which is actively in progress. In this case, a reliable memory system can be implemented by blocking read errors caused by dummy cells.

19 is a block diagram briefly showing an information processing system for mounting a flash memory system 1310 according to the present invention.

Referring to FIG. 19, the flash memory system 1310 of the present invention is installed in an information processing system such as a mobile device or a desktop computer. An information processing system 1300 according to the present invention includes a flash memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, a user interface 1350, . The flash memory system 1310 will be configured substantially the same as the memory system or flash memory system mentioned above. The flash memory system 1310 stores data processed by the central processing unit 1330 or externally input data. In this case, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can stably store a large amount of data in the flash memory system 1310. As the reliability increases, the flash memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention can be provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. It is clear to those who have learned.

Further, the flash memory device or memory system according to the present invention can be mounted in various types of packages. For example, the flash memory device or the memory system according to the present invention may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

1 is a simplified circuit diagram of a non-volatile memory device according to embodiments of the present invention.

2A is a top view of a nonvolatile memory device according to a first embodiment of the present invention.

2B and 2C are modified embodiments of the nonvolatile memory device according to the first embodiment of the present invention.

3 is a cross-sectional view of the nonvolatile memory device according to the first embodiment of the present invention, taken along the line I-I 'in FIGS. 2A to 2C.

4 is a top view of a nonvolatile memory device according to a second embodiment of the present invention.

5 is a cross-sectional view of a nonvolatile memory device according to a second embodiment of the present invention, taken along line II-II 'in FIG.

6 is a plan view of a nonvolatile memory device according to a third embodiment of the present invention.

7 is a cross-sectional view of a non-volatile memory device according to a third embodiment of the present invention, taken along line A-A 'and line B-B' in FIG.

8 is a plan view of a nonvolatile memory device according to a fourth embodiment of the present invention.

FIG. 9 is a cross-sectional view of a nonvolatile memory device according to a fourth embodiment of the present invention, taken along the line I-I 'of FIG.

10 is a plan view of a nonvolatile memory device according to a fifth embodiment of the present invention.

11 is a cross-sectional view of a nonvolatile memory device according to a fifth embodiment of the present invention, taken along line II-II 'in FIG.

12 is a plan view of a nonvolatile memory device according to a sixth embodiment of the present invention.

FIGS. 13A to 13G are views sequentially illustrating a method of manufacturing a non-volatile memory device according to the first and fourth embodiments of the present invention.

FIGS. 14A to 14F are views sequentially illustrating a method of manufacturing a nonvolatile memory device according to the second and fifth embodiments of the present invention. FIG.

15A to 15E are views showing another method of manufacturing the nonvolatile memory device according to the second and fifth embodiments of the present invention in order.

16A to 16E are views showing a method of manufacturing a nonvolatile memory device according to the third and sixth embodiments of the present invention in order.

17 is a schematic diagram of a memory system including a non-volatile memory device in accordance with embodiments of the present invention.

18 is a block diagram briefly showing an example of a memory card having a flash memory device according to an embodiment of the present invention.

19 is a block diagram briefly showing an information processing system equipped with a flash memory system according to the present invention.

Claims (10)

A semiconductor substrate including a memory cell region and a contact region; A plurality of gate electrodes parallel to an upper surface of the semiconductor substrate and vertically stacked on the semiconductor substrate; And In the memory cell region, active columns extending through the gate electrodes and extending perpendicular to the semiconductor substrate; Wherein each of the gate electrodes comprises a first gate electrode across the active pillars on the memory cell region and a second gate electrode horizontally connected to one end of the first gate electrode and disposed on the contact region, , Wherein the first gate electrode and the second gate electrode are formed of different conductive materials. The method according to claim 1, And a plurality of supports extending perpendicularly to the semiconductor substrate and passing through the gate electrodes in the contact region. The method according to claim 1, Wherein the first gate electrode of the memory cell region is formed of a metal material. The method according to claim 1, The plurality of gate electrodes are stacked on the semiconductor substrate by interposing an interlayer insulating film therebetween, Wherein the second gate electrode disposed on the upper portion of the plurality of gate electrodes exposes an upper portion of an edge portion of the second gate electrode disposed below the nonvolatile memory device. The method according to claim 1, And contact plugs connected to each of the second gate electrodes of the contact region. A semiconductor substrate including a memory cell region and a contact region is prepared, Forming a stacked structure in which at least two or more layers of a gate conductive film and an insulating film are alternately stacked on the semiconductor substrate, Removing portions of the gate conductive layers in the contact region to form first gate electrodes between the vertically stacked insulating films in the memory cell region, Forming second gate electrodes formed of a conductive material different from the first gate electrodes between the vertically stacked insulating films in the contact region, the first gate electrodes being horizontally connected to the first gate electrodes, And forming active columns through the first gate electrodes in the memory cell region. The method according to claim 6, Forming the first gate electrodes comprises: And supplying an etchant having an etch selectivity to the gate conductive layer to the sidewalls of the stack structure to remove the gate conductive layers on the contact region. The method according to claim 6, Wherein forming the second gate electrodes comprises filling a metal material between the insulating films on the contact region. The method according to claim 6, Before forming the first gate electrodes, Further comprising forming a plurality of supports through the stack structure in the contact region. ≪ Desc / Clms Page number 21 > The method according to claim 6, After forming the second gate electrodes, Further comprising patterning the stack structure such that the second gate electrode disposed on the top exposes an edge portion of the second gate electrode disposed below.

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