KR101495803B1 - Method for fabricating nonvolatile memory device and nonvolatile memory device fabricated by the method - Google Patents

Abstract

A method of manufacturing a non-volatile memory device of a three-dimensional structure is provided. A method of manufacturing a nonvolatile memory device includes: stacking a plurality of first and second material films having different etch selectivities alternately on a semiconductor substrate, forming an opening through the plurality of first and second material films Removing the first material films exposed by the opening to form expansions extending from the opening in a direction parallel to the semiconductor substrate and conformally forming a charge storage film along the surfaces of the openings and the expansions, Removing the charge storage film formed on the sidewall of the material film to locally form the charge storage film patterns in the extension.

Three-dimensional, charge storage film pattern, separation

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a nonvolatile memory device,

The present invention relates to a method of manufacturing a nonvolatile memory device and a nonvolatile memory device manufactured thereby, and more particularly, to a method of manufacturing a nonvolatile memory device having a three-dimensional structure capable of improving reliability and a non- Volatile memory device.

In general, a nonvolatile memory device is an element capable of electrically erasing and programming data, and capable of preserving data even when power is shut off. Accordingly, the use of nonvolatile memory devices is increasing in various fields in recent years.

Nonvolatile memory devices constitute various types of memory cell transistors, and are largely divided into NAND type and NOR type depending on the cell array structure. NAND type nonvolatile memory devices and NOR type nonvolatile memory devices have advantages and disadvantages that are divided into high integration and high performance.

In particular, the NAND type nonvolatile memory device is advantageous in high integration because of a cell string structure in which a plurality of memory cell transistors are serially connected. Since the NAND type nonvolatile memory device employs an operation method of simultaneously changing the information stored in the plurality of memory cell transistors, the information update speed is much faster than the NOR type nonvolatile memory device. Due to such high integration and fast update speed, NAND type nonvolatile memory devices are mainly used in portable electronic products requiring mass storage such as digital cameras or MP3 players. The advantages of such NAND type nonvolatile memory devices are continuously being explored and promoted, and a three-dimensional NAND type nonvolatile memory device is being developed.

The nonvolatile memory devices can be classified into floating gate type nonvolatile memory devices and charge trap type nonvolatile memory devices according to the types of storage layers constituting the unit cells. Of these, charge trap type nonvolatile memory devices are being developed in terms of being able to realize low power, low voltage and high integration.

A problem to be solved by the present invention is to provide a method of manufacturing a nonvolatile memory device having a three-dimensional structure capable of improving reliability.

Another object of the present invention is to provide a nonvolatile memory device having a three-dimensional structure capable of improving reliability.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of fabricating a nonvolatile memory device, comprising: stacking a plurality of first and second material layers having different etch selectivities on a semiconductor substrate, Forming an opening through the plurality of first and second material films and removing the first material films exposed by the opening to form expansions extending from the opening in a direction parallel to the semiconductor substrate, Forming a charge storage film conformally along the surface of the extensions and removing the charge storage film formed on the sidewalls of the second material film to locally form the charge storage film patterns in the extension.

According to another aspect of the present invention, there is provided a nonvolatile memory device including: a semiconductor substrate; a conductive layer stacked on the semiconductor substrate through an insulating layer; And a plurality of protrusions protruding from the body portion toward the sidewalls of the conductive films, and sidewalls of the conductive films and the charge storage film patterns formed between the protrusions of the active pillars.

According to another aspect of the present invention, there is provided a nonvolatile memory device including a plurality of conductive patterns arranged three-dimensionally on a semiconductor substrate, a plurality of semiconductor layers extending from the semiconductor substrate, And a charge storage film pattern interposed between the semiconductor pattern and the conductive pattern, wherein the charge storage pattern is separated from the charge storage film pattern that is in contact with another conductive pattern.

The details of other embodiments are included in the detailed description and drawings.

According to the method of manufacturing a nonvolatile memory device of the present invention, when word lines are stacked in a direction perpendicular to a semiconductor substrate, charge storage film patterns corresponding to one sidewalls of each word line can be formed. And the charge storage film patterns located at the upper and lower portions can be separated from each other.

Therefore, charges trapped in the charge storage film can be diffused in a direction perpendicular to the semiconductor substrate to prevent charges from being lost. Therefore, the reliability of the three-dimensional nonvolatile memory device can be improved.

In addition, after the word lines are formed, the charge storage film is separated to form the charge storage film patterns, so that the gate conductive material remains on the charge storage film, thereby preventing an electrical short between the vertically adjacent word lines.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. Also, in this specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate, or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. A non-volatile memory device according to embodiments of the present invention has a three-dimensional structure.

1 is a circuit diagram showing a nonvolatile memory device according to embodiments of the present invention.

Referring to FIG. 1, a non-volatile memory device according to an embodiment of the present invention includes a cell array including a plurality of strings STR. The cell array includes a plurality of bit lines BL1 to BL3, word lines WL1 to WL4, upper and lower selection lines USL1 to USL3 and LSL, and a common source line CSL. And includes a plurality of strings STR between the bit lines BL1 to BL3 and the common source line CSL.

Each string STR includes a plurality of memory cell transistors MC connected in series between upper and lower selection transistors UST and LST and upper and lower selection transistors UST and LST. The drains of the upper select transistors UST are connected to the bit lines BL1 to BL3 and the sources of the lower select transistors LST are connected to the common source line CSL. The common source line CSL is a line to which the sources of the lower selection transistors LST are connected in common.

The upper select transistors UST are connected to the upper select lines USL1 to USL3 and the lower select transistors LST are connected to the lower select line LSL. Further, each memory cell MC is connected to the word lines WL1 to WL4.

Such cell arrays are arranged in a three-dimensional structure, and the strings STR have a structure in which memory cells MC are connected in series in a z-axis direction perpendicular to the xy plane parallel to the upper surface of the substrate. Accordingly, the channels of the selection transistors UST and LST and the memory cell transistors MC can be formed perpendicular to the xy plane.

In a nonvolatile memory device having a three-dimensional structure, m memory cells may be formed in each xy plane, and an xy plane having m memory cells may be stacked in n layers. (Where m and n are natural numbers).

Hereinafter, a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 9. FIG.

2 is a perspective view of a non-volatile memory device according to an embodiment of the present invention. 3 is a cross-sectional view of a non-volatile memory device according to one embodiment of the present invention. 3 shows a cross-section of a memory cell region of a non-volatile memory device according to an embodiment of the present invention.

2 and 3, an interlayer insulating film 110 and conductive films LSL, WL, and USL are alternately repeatedly stacked on a semiconductor substrate 100.

Specifically, an impurity region (or well) 102 provided in a common source line (CSL in FIG. 1) is formed in the semiconductor substrate 100, and an interlayer insulating film 110 and a conductive The films (LSL, WL, USL) are stacked in order. In the stacked conductive films LSL, WL and USL, the uppermost and lowermost conductive films LSL and USL are used as selection lines and the remaining conductive films WL are used as word lines.

The lower selection line LSL located at the lowermost layer may be formed in a plate form or a line form separated from each other. The upper select lines USL located on the uppermost layer may be formed in the form of lines separated from each other. The word lines WL located between the lower select line LSL and the upper select line USL may be formed in a plate shape. The word lines of each layer are formed in a plate shape so that the same voltage can be applied to the word lines of the memory cells formed in the same layer.

In addition, the word lines WL can be gradually reduced in area, and the edge portions of the stacked interlayer insulating film 110 and the conductive films LSL, WL, and USL can be stacked in a stepwise manner.

A plurality of active pillars PL pass through the stacked interlayer insulating film 110 and the conductive films LSL, WL, and USL. The active pillars PL are formed of a semiconductor material and correspond to the respective strings of the non-volatile memory device. That is, through the active pillars PL, the channel of the select transistors and the memory cell transistors of each string can be electrically connected.

The active pillars PL are spaced apart from each other and can be arranged in a matrix form in a plane. The active pillars PL may be electrically connected to the impurity region 102 in the semiconductor substrate 100 through the conductive films LSL, WL, and USL. Each of the active pillars PL is protruded in the direction of the conductive films LSL, WL, USL in the respective layers in which the conductive films LSL, WL, USL are formed.

More specifically, the active pillars PL extend from the body portion 170 toward the conductive films LSL, WL, and USL, And a plurality of protrusions 172 spaced from each other. Each protrusion 172 may have a shape that wraps around the body 170 while facing the corresponding conductive films LSL, WL, and USL. Accordingly, the conductive films LSL, WL, and USL of the respective layers can be separated from the body portion 170 by the protrusions 172. According to one embodiment, the protrusions 172 may protrude beyond the thickness of at least the charge storage film pattern 142, and channels may be formed in the protrusions 172 during operation of the non-volatile memory device.

According to another embodiment of the present invention, in the active pillars including the body portion and the protrusions, protrusions contacting the conductive layers (USL, LSL) of the uppermost layer and the lowermost layer may be omitted.

The charge storage film patterns 142 are interposed between the protruding portions 172 of the active pillars PL and the sidewalls of the conductive films LSL, WL, USL. That is, the charge storage film pattern 142 contacts each of the conductive films LSL, WL, USL and covers the surface of the protrusion 172 of the active column PL. The charge storage film pattern 142 is removed from the side wall of the body portion 170 so that the charge storage film patterns 142 located at the upper and lower portions can be electrically separated from each other. That is, the charge storage film patterns 142 are in contact with the sidewalls of the conductive films LSL, WL, and USL, and can be isolated between the upper and lower interlayer insulating films 110.

Meanwhile, according to another embodiment of the present invention, charge storage film patterns formed locally on one side wall of the uppermost and lowermost conductive films USL and LSL may be omitted.

Bit lines BL, which are electrically connected to the active pillars PL, may be formed on the active pillars PL. The bit lines BL cross the upper select lines USL and can be electrically connected to the active pillars PL located in the same row or column among the active pillars PL arranged in a matrix.

As described above, when the charge storage film patterns 142 are separated into the respective layers, it is possible to prevent the charges trapped in the charge storage film pattern 142 from diffusing in the direction perpendicular to the word lines WL, that is, have. That is, after the charges are trapped, it is possible to prevent external disturbance due to external or internal stress and diffusion of charges with the lapse of time, thereby improving the reliability of the nonvolatile memory device having a three-dimensional structure.

Next, with reference to FIGS. 4 to 9, a method of manufacturing a nonvolatile memory device according to an embodiment will be described in detail.

FIGS. 4 to 9 are views sequentially illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 4, an interlayer insulating film 110 and a conductive film 120 are repeatedly stacked on a semiconductor substrate 100 in order. Here, the semiconductor substrate 100 may include an impurity region (or a well 102). The interlayer insulating film 110 may be formed of a silicon oxide film or a silicon nitride film, and the conductive film 120 may be formed of a polysilicon film or a metal film. The number of stacked conductive films may vary depending on the capacity of the nonvolatile memory device.

The interlayer insulating film 110 and the conductive films 120 may be stacked on the memory cell region of the semiconductor substrate 100 in a flat plate shape, and the area may gradually decrease toward the upper portion. That is, as shown in FIG. 3, the edge portions of the interlayer insulating film 110 and the conductive films 120 may be stacked to form a stepped shape. The conductive films 120 may be stacked while repeating the deposition and patterning of the conductive film 120. Alternatively, after stacking both the interlayer insulating film 110 and the conductive films 120, The conductive films 120 may be formed by patterning the edge portions by layers. In addition, the conductive film 120 located on the uppermost layer can be patterned in the form of a line.

Next, a plurality of first holes 132 penetrating the interlayer insulating film 110 and the conductive films 120 are formed. Specifically, a mask pattern (not shown) is formed on the interlayer insulating film 110, and the interlayer insulating film 110 and the conductive films 120 are selectively anisotropically etched using the mask pattern to form first holes 132 ). ≪ / RTI > The first holes 132 may expose the impurity region 102 of the semiconductor substrate 100. The diameter of the first holes 132 may decrease as the anisotropic etching process proceeds. In this case, the diameter of the first holes 132 may be smaller than the distance between the adjacent first holes 132. The plurality of first holes 132 passing through the interlayer insulating layer 110 and the conductive layers 120 may be formed in a planar matrix.

Referring to FIG. 5, the sidewalls of the conductive layers 120 exposed by the first holes 132 are selectively etched to form second holes 136 in which the extended portions 134 are formed. Specifically, an etching solution capable of selectively etching the conductive films 120 is supplied into the first holes 132, and a part of the conductive films 120 exposed by the first holes 132 is isotropically It can be etched. The etching rate of the conductive films 120 is higher than that of the interlayer insulating films 110 when the etching solution is supplied through the first holes 132. Therefore, The diameter of the hole formed in the hole can be increased. Therefore, in each layer on which the conductive films 120 are formed, extended portions 134 extending in the horizontal direction with the conductive films 120 can be formed. That is, the interlayer insulating layer 110 and the conductive layers 120 may have second holes 136 vertically penetrating the first interlayer insulating layer 110 and the second interlayer insulating layer 110, respectively.

Referring to FIG. 6, the charge storage film 140 is deposited conformally along the surface of the second holes 136. That is, the charge storage film 140 may be formed on the sidewalls of the interlayer insulating film 110 and the conductive film 120 exposed by the second hole 136, and on the impurity region 102. At this time, the charge storage film 140 may also be formed conformally along the surface of the extension portions 134. Therefore, the charge storage film 140 can be deposited on the sidewalls of the conductive films 120 exposed by the extension portions 134, and on the upper and lower surfaces of the interlayer insulating films 110. Here, the charge storage film 140 may be formed by sequentially depositing a charge blocking film, an electric charge trapping film, and a charge tunneling film. That is, an oxide film, a nitride film, and an oxide film can be formed in this order on the surface of the second hole 136.

Referring to FIG. 7, the sacrificial layer 150 is filled in the second hole 136 in which the charge storage layer 140 is formed. At this time, the sacrifice layer 150 can be formed sufficiently thick to the top of the charge storage layer 140. Here, the sacrifice layer 150 may be formed of a material having an etch selectivity with respect to the charge storage layer 140, and may be formed of a material having a good gap filling property. For example, the sacrificial layer 150 may be formed of a material selected from the group consisting of borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), Tonen SilaZene (TOSZ), undoped silicate glass (Spin On Glass).

After the sacrificial layer 150 is formed, the upper surface of the sacrificial layer 150 may be planarized, and the planarization process may be performed until the interlayer insulating layer 110 is exposed. Then, a mask pattern 165 for removing the charge storage film 140 formed on the sidewall of the interlayer insulating film 110 is formed on the planarized sacrificial layer 150. At this time, the width W ₂ of the sacrificial layer exposed by the mask pattern 165 may be larger than the width W ₁ of the holes formed in the interlayer insulating films 110. Alternatively, the mask pattern 165 may use a mask pattern used in forming the first hole (132 in FIG. 4).

8, anisotropic etching of the charge storage film 140 and a part of the sacrificial films 150 is performed using the mask pattern 165 so as to pass through the stacked interlayer insulating film 110 and the conductive films 120 Third holes 132 'may be formed. The third holes 132 'may expose the impurity region 102 and expose the sidewalls of the stacked interlayer insulating films 110. The diameters of the third holes 132 'may be larger than the diameters of the first holes 132 and smaller than the diameters of the extension portions 134. A part of the charge storage film 140 on the sidewall of the interlayer insulating film 110 and a part of the charge storage film 140 formed on the upper and lower surfaces of the interlayer insulating film 110 can be removed when the third holes 132 'are formed. Then, the charge storage film 140 and the portions 152 of the sacrificial films remain between the interlayer insulating films 110 stacked.

As the third holes 132 'are formed, the charge storage layers 140 formed on the sidewalls of the interlayer insulating layers 110 are removed. Therefore, the charge storage layers 140 (shown in FIG. 6) Patterns 142 may be formed. A charge storage film pattern and a sacrificial layer may be formed between the third hole 132 'and the sidewalls of the conductive layers 120. The charge storage layer pattern 142 may be formed between the interlayer insulating layer 110 and the conductive layer 120 ). ≪ / RTI >

On the other hand, the charge storage film 140 and the sacrifice film 150 are anisotropically etched using the interlayer insulating films 110 as an etching mask without a mask pattern to locally form the charge storage film pattern 142 may be formed.

Referring to FIG. 9, the sacrificial layers 152 remaining between the interlayer insulating layers 110 are removed. The removal of the sacrificial film 152 may use a wet etching solution having an etching selectivity ratio with respect to the charge storage film pattern 142 and the interlayer insulating film 110. That is, the wet etching solution may be supplied to the third holes 132 'to remove the sacrificial films 152 remaining on the charge storage film pattern 142. Accordingly, fourth holes 136 'having extension portions 134' may be formed between the interlayer insulating films 110. The fourth holes 136 'may be formed on the surface of the charge storage film pattern 142 by the extension portions 134' Lt; / RTI >

Referring to FIG. 10, semiconductor materials are filled into fourth holes 136 'having extension portions 134' to form active pillars 170 and 172. At this time, a semiconductor material may also be filled in the extensions 134 'formed between the interlayer insulating films 110. Here, the semiconductor material may be a polycrystalline or single crystal semiconductor. Thereafter, the semiconductor material filled in the fourth holes 136 'may be planarized to expose the upper surface of the uppermost interlayer insulating film 100.

Thus, by filling the semiconductor material in the fourth holes 136 'having the extensions 134' to form the active columns, the active pillars pass through the stacked interlayer insulating layer 110 and the conductive layer 120 A body portion 170, and protrusions 172 protruding into the conductive film. Since the charge storage film patterns 142 are formed in the extension portions 134, the charge storage film patterns 142 on the upper and lower sides are separated from each other.

Hereinafter, a nonvolatile memory device and a method of manufacturing the same according to another embodiment of the present invention will be described in detail.

11 is a perspective view of a non-volatile memory device according to another embodiment of the present invention.

11, an impurity region (or a well) 202 provided in a common source line may be formed in the semiconductor substrate 200, and an insulating layer and a conductive layer may be alternately formed on the impurity region 202 And repeatedly laminated. Specifically, the insulating layer and the conductive layer are patterned in the form of a line, so that separate conductive word lines 282 can be formed in each of the conductive layers. In other words, structures in which the word line 282 and the insulating line 210 are alternately stacked may be formed on the semiconductor substrate 200, spaced apart from each other. That is, the word lines 282 are three-dimensionally arranged on the semiconductor substrate 200.

On the first sidewalls of the word lines 282 and the insulating lines 210, the active patterns 230 are disposed apart from each other and the insulating film 290 is formed on the second sidewall opposite to the first sidewall. The active patterns 230 may be formed in a line pattern perpendicular to the semiconductor substrate 200, respectively. The active patterns 230 are formed to face the active patterns 230 formed on the first adjacent sidewalls of the horizontally adjacent word lines 282 and the isolation lines 210 and between the active patterns 230 Is filled with an insulating film 240. In other words, the active patterns 230 extend in a direction perpendicular to the semiconductor substrate 200, and a plurality of word lines 282 are formed across one side walls of each active pattern 230.

A charge storage film pattern 252 is interposed between the active pattern 230 and the word line 282 and the charge storage film pattern 252 can extend in the direction of the word line 282. Then, the charge storage film patterns 252 are locally formed between the vertically adjacent interlayer insulating film patterns 210.

More specifically, the charge storage film pattern 252 may conformally cover a portion of the sidewalls of the active patterns 230 and upper and lower surfaces of the vertically adjacent interlayer insulating layer 210 patterns. That is, the charge storage film patterns 252 are formed between the interlayer insulating films 210 which are spaced apart from each other, and are electrically separated from the other charge storage film patterns 252 located on the upper and lower sides.

In addition, active patterns 230 extending in a direction perpendicular to the semiconductor substrate 200 are electrically connected to the bit lines BL across the word lines 282. The bit lines BL may be in direct contact with the top surface of the active pattern 230, or may be electrically connected through the bit line contacts.

Since the charge storage film patterns 252 are separated from each other in the direction perpendicular to the semiconductor substrate 200 as described above, charges trapped in the charge storage film patterns 252 are transferred to the upper and lower portions along the surface of the active pattern 230 Can be prevented from spreading. Therefore, the reliability of the three-dimensional nonvolatile memory device due to the loss of charges can be prevented.

Hereinafter, a method of manufacturing a nonvolatile memory device according to another embodiment of the present invention will be described in detail with reference to FIGS. 12 to 21. FIG.

Referring to FIG. 12, first and second insulating films 210 and 215 having different etching selection ratios are alternately stacked on a semiconductor substrate 200. Specifically, the first and second insulating films 210 and 215 are formed of materials having different wet etching rates. For example, the first and second interlayer insulating films 210 and 215 may be formed of, for example, a silicon oxide film and a silicon nitride film, respectively.

The first trenches 220 in the form of a line are formed on the first and second insulating films 210 and 215 stacked. The first trenches 220 may be formed by a conventional photolithography and etching process. As the first trenches 220 are formed, the first sidewalls of the stacked first and second insulating films 210 and 215 can be exposed.

Referring to FIG. 13, a semiconductor layer 230 is formed on first sidewalls of the first and second insulating films 210 and 215 exposed by the first trenches 220. A method of forming the semiconductor layer 230 will be briefly described. A semiconductor material is conformally deposited along the first sidewalls of the first and second insulating films 210 and 215. Thereafter, the semiconductor layer 230 may be anisotropically removed to remove the impurity region 202 and the semiconductor layer 230 formed on the first insulating layer 210. Accordingly, the semiconductor layer 230 covering the first sidewalls of the first and second insulating films 210 and 215 may be formed. After the semiconductor layer 230 is formed, an insulating material is buried in the first trench 220 and planarized to form an insulating layer 240 between the semiconductor layers 230.

Meanwhile, an epitaxial process using the semiconductor substrate 200 exposed by the first trenches 220 as a seed layer may be performed to form a semiconductor layer in the first trenches 220 .

Referring to FIG. 14, second trenches 222 in the form of a line are formed between the first trenches (220 in FIG. 12) in which the insulating film 240 is buried. The second trenches 222 may expose the second sidewalls of the stacked first and second insulating films 210 and 215. As the second trenches 222 are formed, the stacked first and second insulating films 210 and 215 can be patterned in a line shape.

15, the second trenches 222 exposing the second sidewalls of the stacked first and second insulating films 210 and 215 are etched with an etching solution having a high etching selectivity to the second insulating film 215 And the second insulating films 215 are removed. That is, the extended portion 226 extending in the horizontal direction with respect to the semiconductor substrate 200 may be formed between the stacked first insulating films 210, and a portion of the sidewall of the semiconductor layer 230 may be formed in the extended portion 226, Lt; / RTI > In other words, between the insulating films 230 buried in the first trench (220 in FIG. 12), a semiconductor layer 230 having expansions 226 exposing the impurity region 202 and exposing the sidewalls of the semiconductor layer 230 Three trenches 224 may be formed.

Referring to FIG. 16, the charge storage film 250 is formed conformally along the surface of the third trenches 224. That is, the charge storage film 250 is formed conformally along the surface of the extension portions 226 exposing portions of the sidewalls of the semiconductor layer 230. The charge storage layer 250 may be formed using a chemical vapor deposition process and may include a portion of the sidewalls of the semiconductor layer 230 and the second sidewalls of the first insulating layer 210, And on the underside. The charge storage layer 250 may be formed by sequentially depositing a charge tunneling layer, a charge trapping layer, and a charge blocking layer. For example, the charge tunneling film may be formed of a silicon oxide film (SiO ₂ ) or a silicon oxynitride film (SiON). In addition, the charge tunneling film may be formed of a high dielectric constant material such as Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Ta ₂ O ₃ , TiO ₂ , SrTiO ₃ (STO), (Ba, Sr) TiO ₃ Or a combination of these layers. At this time, the charge tunneling film may be formed of a material lower in dielectric constant than the charge blocking film. The charge trapping film may be formed of a silicon nitride film and / or a silicon oxynitride film. The charge blocking film may be made of a material such as Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Ta ₂ O ₃ , TiO ₂ , SrTiO ₃ (STO), (Ba, Sr) TiO ₃ Or a combination thereof, or a combination thereof. The charge blocking film may be formed of a material having a higher dielectric constant than the charge tunneling film.

Referring to FIG. 17, a sacrificial layer 260 is formed by filling a sacrificial material in the third trenches 224 in which the charge storage layer 250 is formed.

As the sacrifice layer 260, a material having excellent gap filling characteristics may be used, and the sacrifice layer 260 may be formed to a sufficient thickness to the upper portion of the first insulating layer 210 located on the uppermost layer. At this time, the upper surface of the sacrifice layer 260 can be planarized, and further, the upper surface of the first insulation layer 210 can be planarized. A mask pattern 275 is then formed on the sacrificial layer 260 or the first insulating layer 210 to expose the second sidewalls of the first insulating layers 210. The mask pattern 275 may be the same as the mask pattern for forming the second trench (222 in Fig. 14).

Referring to FIG. 18, the sacrificial layer 260 and the charge storage layer 260 formed on the second sidewalls of the first insulating layer 210 are etched using the mask pattern 275. Accordingly, the fourth trenches 222 'may be formed between the insulating films 240 buried in the first trenches 220 (FIG. 12). The fourth trenches 222 'again expose the second sidewall of the first insulating layer 240 and the impurity region 202. At this time, the width of the fourth trench 222 'may be equal to or greater than the width of two trenches (222 in FIG. 14).

In addition, as the fourth trenches 222 'are formed, the charge storage films 250, which have been formed conformally to the surfaces of the second trenches (222 in FIG. 14), can be separated into charge storage film patterns 252 have. That is, the charge storage film patterns 252 can be locally formed in the extensions (226 in FIG. 16) formed between the stacked first insulating films 210. Then, a portion 262 of the sacrificial film remains on the charge storage film pattern 252 in the extensions (226 in Fig. 16).

Referring to FIG. 19, the sacrificial films 262 remaining in the expansions (226 in FIG. 16) are removed through a wet etching process. The wet etch process can selectively remove only the remaining sacrificial films 262 by using an etch solution having a high etch rate for the sacrificial films 262. Accordingly, the surface of the charge storage film patterns 252 can be exposed by the fifth trench 224 'having the extended portions 226'.

Referring to FIG. 20, a gate conductive film 280 is formed to completely fill the fifth trenches 224 'on the charge storage film patterns 252. The gate conductive film 280 'may be formed using a chemical vapor deposition method, whereby the gate conductive film 280 may be filled in the extension portions 226'. That is, the gate conductive films 280 in the extension portions 226 'may be electrically connected to each other. Here, the gate conductive film 280 may be formed of a polysilicon film or a metal film.

Referring to FIG. 21, the gate conductive layer 280 is patterned so that the charge storing pattern 252 and the conductive lines 282 can be formed in the extension portions 226 '. That is, the gate conductive film 280 can be separated into the word lines 282 in the form of a line. The word lines 282 may be formed between the stacked first insulating films 210 and the patterns of the word lines 282 and the first insulating film 210 may be formed in a direction perpendicular to the semiconductor substrate 200 As shown in FIG. After the word lines 282 are separated from each other, an insulating film 290 is buried between the stacked word lines 282 and the first insulating film 210 patterns, and the upper surface of the insulating film 290 is planarized.

Thereafter, the semiconductor layer 230 covering the first sidewalls of the charge storage film patterns 252 may be separated into respective lines. That is, as shown in FIG. 11, the semiconductor layers 230 may be formed to be spaced apart from each other in a line form on the first sidewalls of the stacked word lines 282. On the semiconductor layers 230 separated in the form of a line, bit lines BL may be formed which extend across the word lines 282 and are electrically connected to the semiconductor layers 230.

In this way, in the three-dimensional nonvolatile memory device, when the word lines 282 are stacked in the direction perpendicular to the semiconductor substrate 200, the charge storage patterns 252 contacting the word line 282 are formed at the top and bottom The charge storage patterns 252 may be separated from each other. Therefore, the charges trapped in the charge storage patterns 252 can be prevented from being diffused and lost in the direction perpendicular to the semiconductor substrate 200.

In another embodiment of the present invention, the charge storage film patterns 252 can be formed locally without using the sacrificial layer shown in FIGS. 17 to 19. This will be described in detail with reference to FIGS. 22 to 24. FIG.

Referring now to FIG. 16 and FIG. 22, a charge storage film 250 is formed conformally along the surface of a third trench (224 of FIG. 16) including extensions (226 of FIG. 16) The gate conductive film 280 is buried in the trench (224 in Fig. 16). As the conductive material, a polysilicon film or a metal film may be used, and after filling the gate conductive film 280, the upper portion of the charge storage film 250 and the gate conductive film 280 may be planarized.

23, the gate conductive layer 280 formed between the horizontally adjacent first insulating layers 210 may be removed, and the gate conductive layer 280 may be separated into the word lines 282. That is, word lines 282 may be formed in the extension portions (222 in FIG. 16), respectively. The charge storage film 250 of the sidewalls of the first insulating films 210 may be removed together with the gate conductive film 280 or may remain partially while anisotropically etching the gate conductive film made of the conductive material. That is, a trench 233 is formed again between the first insulating films 210 which are horizontally adjacent to each other.

Referring to FIG. 24, after the word lines 282 are formed, the charge storage film 250 formed on the sidewalls of the first insulating films 210 is removed. Accordingly, charge storage film patterns 252 covering one side wall and upper and lower surfaces of the word line 282 can be locally formed in the extension (226 in FIG. 16).

The separation of the charge storage film 250 into the charge storage film patterns 252 may be performed by performing an anisotropic or isotropic etching process. When the charge storage film 250 is removed, the charge storage film 250 of the sidewalls of the first insulating films 210 is selectively etched using a material having an etch selectivity to the gate conductive film with an etching gas or an etching solution. can do. For example, when the charge storage layer 250 on the sidewalls of the first insulating layers 210 is removed through an isotropic etching process, etching solutions such as HF, O ₃ / HF, phosphoric acid, sulfuric acid, and LAL may be used have. Further, in order to remove the charge storage film 250, a fluoride series etching solution and a phosphoric acid or a sulfuric acid solution may be sequentially used.

On the other hand, when the charge storage film (250 in FIG. 23) on the sidewalls of the first insulating films 210 is removed after the word lines 283 are formed, The material can be removed together. Therefore, the charge storage film patterns 252 are separated from each other, so that the charges trapped in the charge storage patterns 252 can be prevented from being diffused and lost in the direction perpendicular to the semiconductor substrate 200, The conductive material may remain on the storage film 250 to prevent an electrical short between the word lines 282 from occurring.

25 is a schematic diagram of a memory system including a non-volatile memory device in accordance with embodiments of the present invention.

25, the memory system 1100 may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, A memory card, or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes an input / output device 1120 such as a controller 1110, a keypad, a keyboard and a display, a memory 1130, an interface 1140, and a bus 1150. Memory 1130 and interface 1140 are in communication with one another via bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process device. Memory 1130 may be used to store instructions executed by the controller. The input / output device 1120 may receive data or signals from outside the system 1100, or may output data or signals outside the system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display device.

Memory 1130 includes a non-volatile memory device in accordance with embodiments of the present invention. Memory 1130 may also include other types of memory, volatile memory that may be accessed at any time, and various other types of memory.

The interface 1140 serves to transmit data to and receive data from the communication network.

26 is a block diagram schematically illustrating an example of a memory card 1200 having a flash memory device according to an embodiment of the present invention.

Referring to FIG. 26, a memory card 1200 for supporting a high capacity data storage capability mounts a flash memory device 1210 according to the present invention. The memory card 1200 according to the present invention includes a memory controller 1220 that controls the exchange of all data between the host and the flash memory device 1210.

The SRAM 1221 is used as the operating memory of the processing unit 1222. The host interface 1223 has a data exchange protocol of a host connected to the memory card 1200. Error correction block 1224 detects and corrects errors contained in data read from multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs all control operations for data exchange of the memory controller 1220. Although it is not shown in the drawing, the memory card 1200 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned.

According to the above flash memory device and memory card or memory system of the present invention, it is possible to provide a reliable memory system through the flash memory device 1210 with the erase characteristics of the dummy cells improved. In particular, the flash memory device of the present invention can be provided in a memory system such as a solid state disk (SSD) device which is actively in progress. In this case, a reliable memory system can be implemented by blocking read errors caused by dummy cells.

Figure 27 is a block diagram that schematically illustrates an information processing system 1300 for mounting a flash memory system 1310 in accordance with the present invention.

Referring to FIG. 27, the flash memory system 1310 of the present invention is installed in an information processing system such as a mobile device or a desktop computer. An information processing system 1300 according to the present invention includes a flash memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, a user interface 1350, . The flash memory system 1310 will be configured substantially the same as the memory system or flash memory system mentioned above. The flash memory system 1310 stores data processed by the central processing unit 1330 or externally input data. In this case, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can stably store a large amount of data in the flash memory system 1310. As the reliability increases, the flash memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention can be provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. It is clear to those who have learned.

Further, the flash memory device or memory system according to the present invention can be mounted in various types of packages. For example, the flash memory device or the memory system according to the present invention may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

1 is a simplified circuit diagram of a non-volatile memory device according to embodiments of the present invention.

2 is a perspective view of a non-volatile memory device according to an embodiment of the present invention.

3 is a cross-sectional view of a non-volatile memory device according to one embodiment of the present invention.

FIGS. 4 to 10 are views sequentially illustrating a method of manufacturing a non-volatile memory device according to an embodiment of the present invention.

11 is a perspective view of a non-volatile memory device according to another embodiment of the present invention.

FIGS. 12 to 21 are views sequentially illustrating a method of manufacturing a non-volatile memory device according to another embodiment of the present invention.

FIGS. 22 to 24 are views sequentially illustrating a method of manufacturing a nonvolatile memory device according to another embodiment of the present invention.

25 is a schematic diagram of a memory system including a non-volatile memory device in accordance with embodiments of the present invention.

26 is a block diagram briefly showing an example of a memory card having a flash memory device according to an embodiment of the present invention.

27 is a block diagram briefly showing an information processing system equipped with a flash memory system according to the present invention.

Claims (14)

A plurality of first and second material films having different etch selectivities are alternately laminated on a semiconductor substrate, Forming an opening through the plurality of first and second material films, Removing the first material films exposed by the opening to form expansions extending from the opening in a direction parallel to the semiconductor substrate, Forming a charge storage film conformally along the surface of the openings and extensions, Removing the charge storage film formed on a sidewall of the second material film to locally form charge storage film patterns in the extension. The method according to claim 1, Wherein forming the openings forms holes or trenches through the first and second material layers. delete delete delete delete The method according to claim 1, Further comprising, after forming the charge storage film patterns, embedding a semiconductor material in the opening and in the extensions to form a semiconductor column. ≪ Desc / Clms Page number 19 > The method according to claim 1, Further comprising forming semiconductor patterns through the first and second material layers before forming the openings, Wherein the openings are formed between a pair of the semiconductor patterns. 9. The method of claim 8, Wherein the extension portions are formed by removing all of the first material layers, Wherein the charge storage film patterns are in contact with the sidewalls of the semiconductor patterns. The method according to claim 1, Before forming the charge storage film patterns, Further comprising forming a conductive pattern in each of the extensions formed with the charge storage film. Conductive films stacked on a semiconductor substrate via an insulating film; A plurality of protrusions protruding from the body toward the side walls of the conductive layers; And And charge storage film patterns formed between the side walls of the conductive films and the protrusions of the active pillars. 12. The method of claim 11, Wherein the protrusions are formed between the insulating films adjacent to each other in the vertical direction, and the charge storage film patterns extend between the protrusions and the insulating films. A plurality of conductive patterns and insulating patterns vertically stacked alternately on a semiconductor substrate; A semiconductor pattern passing through the conductive patterns and the insulating patterns; And And charge storage film patterns interposed between the semiconductor pattern and the conductive patterns, Non-volatile memory device that is locally disposed between the insulating pattern adjacent to each of the charge storage layer pattern to be jikjeok. 14. The method of claim 13, Wherein each of the charge storage film patterns horizontally extends between the insulating patterns and the conductive patterns between the semiconductor pattern and the conductive patterns.

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