JP2011049561A - Semiconductor memory device comprising three-dimensional memory cell array, and method for manufacturing same - Google Patents

Semiconductor memory device comprising three-dimensional memory cell array, and method for manufacturing same Download PDF

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JP2011049561A
JP2011049561A JP2010189800A JP2010189800A JP2011049561A JP 2011049561 A JP2011049561 A JP 2011049561A JP 2010189800 A JP2010189800 A JP 2010189800A JP 2010189800 A JP2010189800 A JP 2010189800A JP 2011049561 A JP2011049561 A JP 2011049561A
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Japan
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substrate
disposed
word lines
conductive
includes
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Japanese (ja)
Inventor
Eishu An
Genshaku Cho
Jaehyoung Choi
Sukhun Choi
Han-Soo Kim
Jinho Kim
Mingu Kim
Ju-Young Lim
Jae-Joo Shim
Sunil Shim
Byoungkeun Son
炳 根 孫
永 洙 安
在 亨 崔
錫 憲 崔
周 永 林
善 一 沈
載 株 沈
源 錫 趙
敏 求 金
漢 洙 金
鎮 瑚 金
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Samsung Electronics Co Ltd
三星電子株式会社Samsung Electronics Co.,Ltd.
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Priority to KR1020090079243A priority Critical patent/KR101548674B1/en
Priority to US12/752,485 priority patent/US8284601B2/en
Application filed by Samsung Electronics Co Ltd, 三星電子株式会社Samsung Electronics Co.,Ltd. filed Critical Samsung Electronics Co Ltd
Publication of JP2011049561A publication Critical patent/JP2011049561A/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11575Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11568Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
    • H01L27/1157Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11578Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H01L27/1158Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H01L27/11582Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor memory device including a three-dimensional memory cell array with high density and a sufficient process margin is provided.
A word line includes a flat substrate, a memory string array formed of a plurality of memory strings formed perpendicular to the substrate and each including a plurality of storage cells, and a plurality of word lines overlapping each other in the horizontal direction. Each including a first portion parallel to the substrate and connected to the memory string and a second portion extending from the first portion and inclined upwardly with respect to the substrate, wherein the memory string array includes a first portion of each of the plurality of word lines. Disposed in the middle portion of the portion and connected to each of the word lines to form a corresponding storage cell, the first and second groups of the plurality of word lines being respectively the first and second sides of the memory string array Are electrically connected to each of the groups of first and second conductive lines arranged in the direction.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device having an improved three-dimensional structure having distributed contact pads.

  With the advanced development of the semiconductor industry, high integration, low power consumption and / or high speed of semiconductor elements have been deepened. In particular, the high integration of semiconductor elements can increase the specifications of various electronic devices and is an important factor that determines the price of a product. Thus, in order to realize a highly integrated semiconductor device, the semiconductor technology has been developed to manufacture semiconductor devices having various structures by moving away from the existing flat plate type device.

  Due to the high integration and diversification of structures of semiconductor devices, it becomes increasingly difficult to secure a margin for the process of connecting various and complex patterns existing in semiconductor devices to conductive lines and other patterns. When a defect occurs in the process of a semiconductor element, the reliability of the semiconductor element is reduced, which directly leads to a decrease in the performance of electronic equipment including the semiconductor element. As a result, various researches have been conducted to secure a process margin in a semiconductor element having a complex pattern and improve reliability in a highly integrated semiconductor element.

Japanese Patent Application Publication No. 2008-263029

An object of the present invention relates to a memory cell array and a configuration including an electrical connection between the memory cell array and its external electric network, and a memory device having a three-dimensional structure with a high density and a process margin secured. It is to provide.
Therefore, the present invention is not limited to the vertical NAND and VNAND, and can be applied to a memory element having a three-dimensional structure such as RRAM, MRAM, and PRAM.

Another object of the present invention relates to a memory cell array and a configuration including an electrical connection between the memory cell array and an external electric network thereof, and has a high-density and three-dimensional structure with a sufficient process margin. It is in providing the manufacturing method of.
Therefore, the present invention is not limited to the vertical NAND or VNAND, and can be applied to manufacture of a memory element having a three-dimensional structure such as PRAM, MRAM, RRAM.

  According to an embodiment of the present invention, a semiconductor memory device includes a flat substrate, a memory string that is perpendicular to the substrate and includes a plurality of storage cells, and a plurality of word lines, and each word line is formed on the substrate. A first portion connected to the memory string and a second portion intersecting the substrate, wherein the first group of word lines is electrically connected to a first conductive line on a first side of the memory string. And a second group of the plurality of word lines is electrically connected to a second conductive line on the second side of the memory string.

  The word lines of the first group of word lines and the word lines of the second group of word lines are alternately positioned in a direction extending from the top to the bottom of the memory string. The extending memory string intersects the substrate at 90 °, and the first side of the memory string faces the second side of the memory string.

  The first portions of each of the plurality of word lines are parallel to each other. The second portions of each of the plurality of word lines on the first side of the memory string are parallel to each other.

  The first alternating word line counts from the top to the bottom of the memory string and is disposed in each odd-numbered storage cell, and the second alternating word line is the top of the memory string. Counting from the bottom to the bottom and placed in each even-numbered storage cell.

  The semiconductor memory device includes the extended end of the second portion of the even-numbered word line on the first side of the memory string and the second portion of the odd-numbered word line on the second side of the memory string. And further including an insulating cap disposed at the extended end.

  The semiconductor memory device further includes a third group of word lines connected to a second conductive line and disposed on a third side of the memory string, the first group of word lines extending from the top of the memory string to the bottom. Are connected to the first storage cell by modulo 3, and the second group of word lines is counted from the top to the bottom of the memory string, and modulo 3 Each of the word lines is connected to a second storage cell, and the third group of the word lines is counted from the top to the bottom of the memory string and connected to the 0th storage cell by a modulo 3.

  Each of the plurality of storage cells and the corresponding word line are disposed on another plane disposed parallel to the plane of the substrate. Successive portions of word lines located in the same plane on the other side of the memory string are electrically connected to one word line. The substrate is horizontal, the memory string is vertical, and the semiconductor memory device is further disposed on the substrate or further includes a peripheral region disposed on the vertical memory string.

  The semiconductor memory device may include the first alternating word line of the plurality of word lines and the first conductive line, and the second alternating word line of the plurality of word lines and the second conductive line. The semiconductor device further includes a plurality of conductive patterns disposed on the contact pads between the lines. The semiconductor memory device further includes a peripheral region disposed on the flat substrate.

  The peripheral region may be disposed at the same level as the lower surface of the conductive pattern, or may be disposed on the upper portion of the chamber. The intersecting second extensions of the word lines have an angle of 50 ° to 90 ° with the substrate. The intersecting second extensions extend from both ends of the first portion of each word line, and one of each pair of second portions intersecting from each word line is covered with an insulating cap.

  The semiconductor memory device may further include a plurality of bit lines disposed perpendicularly to each of the word lines and the memory strings. The chamber further includes a chamber on the flat substrate, the chamber including a silicon recess in the substrate, and the extending memory string and the extending word line are disposed in the silicon recess.

  The chamber further includes a chamber on the planar substrate, the chamber including an insulating wall on an upper surface of the substrate, and the extending memory string and the extending word line are disposed around the insulating wall. . The extending word line includes metal or silicide. The memory string including the plurality of storage cells may be a columnar, tubular, or bar-sided shape.

  The semiconductor memory device further includes at least two row decoders, wherein one row decoder is disposed on the side surface of the odd-numbered storage cell and the other row decoder is disposed on the side surface of the even-numbered storage cell. The first row decoder of the two row decoders is connected to any one of the even or odd string selection lines, and the second row decoder of the two row decoders is connected to the even or odd string selection lines. Each connected to the other one. Of the two row decoders, the first row decoder is connected to all of the string selection lines and one of the even or odd word lines, and the second row decoder of the two row decoders is odd or Each is connected to the other one of the even word lines.

  The substrate includes silicon, the insulating film includes a silicon oxide film, and the word line includes a metal. The storage cell includes a control gate, a first insulating region, a charge storage region, and a second insulating region. The storage cell includes a metal gate as a control gate, a high-K region as a blocking film, a nitride region as a charge storage film, and an oxide region as a tunnel film.

  According to one embodiment of the present invention, a method of manufacturing a semiconductor memory device includes providing a substrate, forming a chamber on the substrate, and alternately depositing an insulating film and a sacrificial film in the chamber, Forming a hole that includes a horizontal first portion and at least one second portion intersecting the substrate, the hole being perpendicular to the substrate, extending through the film to the substrate, and the substrate in the hole; A vertical memory string is deposited, and the memory string includes a plurality of storage cells, each of the sacrificial layers is replaced with a conductive layer to form a plurality of extended word lines, and a first alternating of the plurality of word lines. ) Connecting a word line to a conductive line on a first side of the memory string, and connecting a second alternating word line of the plurality of word lines to the memory string; It includes connecting the second side of the conductive lines and each of the ring.

  The method for manufacturing the semiconductor memory device further includes forming a peripheral region on a top surface of the memory string. The vertical memory string has a bar-sided shape, and the method for manufacturing the semiconductor memory device further includes forming a trench for X-cut to divide the memory string into two parallel strings. The substrate includes silicon, the insulating film includes a silicon oxide film, and the word line includes a metal. The chamber directly recesses the substrate.

  The chamber is formed on the substrate by forming an insulating sidewall on the substrate. Each storage cell includes a control gate, a first insulating region, a charge storage region, and an insulating region. Each storage cell includes a metal gate as a control gate, a high-K region as a blocking film, a nitride region as a charge storage film, and an oxide region as a tunnel film.

  According to an embodiment of the present invention, the semiconductor memory device includes a substrate, a memory string perpendicular to the substrate, the memory string includes a plurality of storage cells, a plurality of word lines, and each word line includes the substrate. A first portion coupled to the memory string parallel to the substrate, and a second portion extending across and extending over the substrate, wherein a first alternating word line of a plurality of word lines includes a first portion of the memory string. A first conductive line on one side is electrically connected, and a second alternating word line of the plurality of word lines is electrically connected to a second conductive line on the second side of the memory string.

  According to an embodiment of the present invention, the semiconductor memory device includes a substrate, a memory string perpendicular to the substrate, the memory string includes a plurality of storage cells, a plurality of word lines, and each word line includes the substrate. And a first portion coupled to the memory string, and a second portion that intersects and extends above the substrate, the word line including a first conductive line on a first side of the memory string. A first word line selectively connected and a second conductive line selectively connected to a second conductive line on a second side of the memory string.

The word line includes at least one dummy word line. The first side has a first row decoder and the second side has a second row decoder.
According to an embodiment of the present invention, the semiconductor memory device includes a substrate, a memory string perpendicular to the substrate, the memory string includes a plurality of storage cells, a plurality of word lines and at least two row decoders. And a plurality of word lines are electrically connected to a first group of word lines electrically connected to one row decoder on the first side of the memory string and to other row decoders on the second side of the memory string. Includes a second group of wordlines connected to. The first row decoder is connected to one group of string selection lines on the first side of the memory string, and the second row decoder is connected to another group of string selection lines on the second side of the memory string. Any one of the two row decodes is connected to the entire string selection line.

  According to an embodiment of the present invention, a method for manufacturing a semiconductor memory device includes providing a substrate, forming a chamber on the substrate, and alternately depositing an insulating film and a conductive film in the chamber, Forming a plurality of word lines, each film including a horizontal first part and at least one second part intersecting the substrate, perpendicular to the substrate and extending through the film to the substrate; Forming a hole, forming a memory string perpendicular to the substrate in the hole, the memory string including a plurality of storage cells, a first alternating word line of the plurality of word lines and the memory string; A contact pad on one side is connected to a second alternating word line of the plurality of word lines and a second side of the memory string; It includes connecting the tact pads.

According to the present invention, the connection between the word line and the memory string can be achieved in a self-aligned manner by the planar word line superimposed in the vertical direction on the flat substrate and the memory string provided in the hole vertically penetrating the word line. Since the process margin of the contact from the word line to the external conductive line is substantially unlimited, a high-density three-dimensional memory device having a sufficiently large process margin can be provided.
According to an embodiment of the present invention, at least two active bars are uniformly laminated on a semiconductor substrate without failure of electrical connection. Therefore, the dispersion of a plurality of cells formed in such a structure can be improved. In other words, it is possible to realize a non-volatile memory device that is optimized for high integration and has improved electrical characteristics.

1 is a schematic plan view for explaining a semiconductor element according to an embodiment of the present invention. 1 is a schematic plan view for explaining a semiconductor element according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view cut along I-I ′ of FIGS. 1 and 2 according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view cut along I-I ′ of FIGS. 1 and 2 according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view cut along I-I ′ of FIGS. 1 and 2 according to an embodiment of the present invention. It is a schematic diagram for demonstrating the information storage film (for example, charge storage film) which concerns on one Embodiment of this invention. It is a schematic plan view for demonstrating the semiconductor element which concerns on other embodiment of this invention. It is a schematic plan view for demonstrating the semiconductor element which concerns on other embodiment of this invention. FIG. 9 is a schematic cross-sectional view taken along the line II-II ′ of FIGS. 7 and 8 according to an embodiment of the present invention. FIG. 9 is a schematic cross-sectional view taken along the line II-II ′ of FIGS. 7 and 8 according to an embodiment of the present invention. FIG. 9 is a schematic cross-sectional view taken along the line II-II ′ of FIGS. 7 and 8 according to an embodiment of the present invention. It is a schematic diagram for demonstrating the information storage film which concerns on one Embodiment of this invention. It is a figure which shows partially the active part which concerns on one Embodiment of this invention. 1 is a schematic plan view for explaining a semiconductor element according to an embodiment of the present invention. FIG. 15 is a schematic cross-sectional view taken along III-III ′ of FIG. 14 according to an embodiment of the present invention. FIG. 15 is a schematic cross-sectional view taken along III-III ′ of FIG. 14 according to an embodiment of the present invention. FIG. 15 is a schematic cross-sectional view taken along III-III ′ of FIG. 14 according to an embodiment of the present invention. 1 is a schematic plan view for explaining a semiconductor element according to an embodiment of the present invention. FIG. 19 is a schematic cross-sectional view taken along IV-IV ′ of FIG. 18 according to an embodiment of the present invention. FIG. 19 is a schematic cross-sectional view taken along IV-IV ′ of FIG. 18 according to an embodiment of the present invention. FIG. 19 is a schematic cross-sectional view taken along IV-IV ′ of FIG. 18 according to an embodiment of the present invention. 1 is a schematic plan view for explaining a semiconductor element according to an embodiment of the present invention. 1 is a schematic plan view for explaining a semiconductor element according to an embodiment of the present invention. FIG. 24 is a schematic cross-sectional view taken along V-V ′ of FIGS. 22 and 23 according to an embodiment of the present invention. FIG. 24 is a schematic cross-sectional view taken along V-V ′ of FIGS. 22 and 23 according to an embodiment of the present invention. FIG. 24 is a schematic cross-sectional view taken along V-V ′ of FIGS. 22 and 23 according to an embodiment of the present invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. 1 is a schematic plan view for explaining a semiconductor element according to an embodiment of the present invention. 1 is a schematic plan view for explaining a semiconductor element according to an embodiment of the present invention. FIG. 37 is a schematic cross-sectional view taken along VI-VI ′ of FIGS. 35 and 36 according to one embodiment of the present invention. FIG. 37 is a schematic cross-sectional view taken along VI-VI ′ of FIGS. 35 and 36 according to one embodiment of the present invention. FIG. 37 is a schematic cross-sectional view taken along VI-VI ′ of FIGS. 35 and 36 according to one embodiment of the present invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing for demonstrating the formation method of the semiconductor element which concerns on one Embodiment of this invention. 1 is a block diagram of a memory system including a semiconductor device according to an embodiment of the present invention. 1 is a block diagram of a memory card including a semiconductor element according to an embodiment of the present invention. It is a block diagram of the information processing system with which the semiconductor element concerning one embodiment of the present invention was equipped. 1 is a block diagram of a nonvolatile memory device including a semiconductor device according to an embodiment of the present invention.

  Embodiments of the present invention provide an improved three-dimensional semiconductor memory structure having distributed contact pads. The preferred embodiment provides an improved contact area margin that can ensure high reliability. The present invention also provides a connection between a word line or a word line and a memory string (hereinafter simply referred to as “string”) selection line, and a layout of at least two row decoders.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described here, and can be embodied in other forms. Furthermore, the embodiments introduced herein are provided so that the disclosed content will be thorough and complete, and will fully convey the spirit of the invention to those skilled in the art. Moreover, since it is based on desirable embodiment, the referential mark presented by the procedure of description is not necessarily limited to the procedure. In the figures, the thickness of the films and regions are exaggerated for clarity. Also, when a film is referred to as being on another film or substrate, it can be formed directly on the other film or substrate, or a third film can be interposed therebetween. In the present specification, the expression 'and / or' is used as a meaning including at least one of the constituent elements arranged one after the other.

  A semiconductor device according to the first embodiment of the present invention will be described. 1 and 2 are plan views according to the embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along the line I-I ′ of FIGS. 1 and 2.

  The semiconductor device according to the present invention includes a memory cell array region, a row decoder, a column decoder, a wiring (for example, a voltage generator) connecting the memory cell array and an external device of the semiconductor device, and a control unit. . The wiring is connected to conductive vias, plugs, or pads that extend perpendicular to other layers, patterns or lines.

  The memory cell array of the semiconductor memory device according to the present invention includes a plurality of memory cells having a three-dimensional structure. According to an embodiment of the present invention, the memory cell array includes an array of a plurality of memory strings that are vertically formed on a flat substrate and each include a plurality of memory cells. Each of the memory strings includes a control gate, a first insulating film, a charge storage film, a second insulating film, and an active part in which a channel is formed. The charge storage film includes an insulating film or a film that stores charges, such as nano-dots. The insulating film for storing charges includes a silicon nitride film or a silicon oxynitride film in which nitrogen is sufficiently more than oxygen. The first insulating film is located between the active part and the charge storage film. The first insulating film includes a silicon oxide film, or a thin (about 50 to 150 mm) multilayer film including any of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film. The second insulating film is located between the charge storage film and the control gate. The second insulating layer may be a silicon oxide layer, a high-K material, an aluminum oxide layer, or a combination thereof.

  The shape of the active part may be various types. For example, it may be a pillar, a columnar, a tubular or a bar-sided shape. The tube active part surrounds an insulating material inside.

  With reference to FIGS. 1, 2, and 3, a substrate 101 is provided. The substrate 101 is a semiconductor-based semiconductor substrate and is substantially flat. The substrate comprises silicon, preferably single crystal silicon. The substrate 101 includes a doping region such as a well doped with a dopant of a first conductivity type. A common source region (not shown) is disposed in the substrate 101. The plurality of memory strings share one source region as a common source line. The common source region is disposed in a plate form in a region of the substrate 101 where a memory cell is formed (a recess A described later). The common source region may include a high concentration of dopant. The dopant included in the common source region may be a second conductivity type having a conductivity type different from that of the dopant included in the well. For example, when the well includes a p-type dopant, the common source region includes a high concentration of n-type dopant.

Referring to FIG. 4, the substrate 100 is flat. A protrusion 104 is formed on the substrate 100. The protrusion 104 is deposited on the substrate 100. The material of the protrusion 104 may be silicon or an insulating film. The resulting surface includes a recess A and a raised portion B due to the protrusion 104 in the flat substrate 100. The recess A includes a bottom surface 103 and first and second side walls 105 and 106 facing each other. The substrate 101 includes a raised portion B extending from the first side wall 105 and the second side wall 106. The top surface of the raised portion B may be parallel to the bottom surface 103 of the recess A.
In contrast, referring to FIG. 3 again, the concave portion A and the raised portion B are formed by etching the portion where the concave portion A of the semiconductor substrate 101 is disposed and leaving the portion where the raised portion B is disposed. The In this case, the substrate 101 may be an integral substrate. A memory cell is disposed in the recess A. If the protrusion is formed of an insulating film and the peripheral circuit is formed on the protrusion, a silicon film is further formed on the protrusion (Silicon on Insulator type, SOI).
Hereinafter, the substrates 100 and 101 on which the concave portions A and the raised portions B are formed are represented by the substrate 101.

  The semiconductor memory device will be described.

The recess A includes a first contact region CR1 adjacent to the first sidewall 105 and a second contact region CR2 adjacent to the second sidewall 106. A cell array region CAR is disposed between the first contact region CR1 and the second contact region CR2. The first contact region CR1 and the second contact region CR2 are spaced apart from each other across the cell array region CAR.
The array of memory strings is formed in the cell array region CAR.

  Conductive patterns GSL, WL1 to WL4, SSL spaced apart from each other are disposed on the substrate 101. The conductive patterns GSL, WL1 to WL4, and SSL include a ground selection line GSL, word lines WL1 to WL4, and a string selection line SSL that are sequentially stacked on the recess A of the substrate 101.

  In order to prevent undesired shorts between adjacent conductors, an interlayer insulating film is disposed between adjacent word lines. The memory device according to the present invention includes a dummy word line in the vicinity of the ground selection line GSL and / or the string selection line SSL or between the word lines. The word line WL, the ground selection line GSL, and the string selection line SSL are formed by laminating a conductive film and an interlayer insulating film. According to another embodiment, the stacked word lines WL, ground selection line GSL and string selection line SSL, and interlayer insulating film are stacked in multiple steps.

  The memory cell array may have a three-dimensional structure of a plurality of memory cells arranged on a flat substrate and capable of storing information. The switching element for activating the memory cell can be a transistor or a diode type. The type of memory cell can be volatile or non-volatile. For example, the memory device according to the present invention is a flash memory device.

  The active part of the three-dimensional memory device is perpendicular or parallel to the flat substrate 101. Preferably, the active part is a vertical active part on the substrate. The active part is made of silicon. The active part may be a pillar, tubular or bar-sided type. The active part is formed of single crystal silicon or polycrystalline silicon. The active part is formed of amorphous silicon and crystallized into polycrystalline silicon.

  The memory string including the control gate, the first insulating film, the charge storage film, the second insulating film, and the active part is formed perpendicular to the planar substrate. The insulating film for storing charges may include a silicon nitride film or a silicon oxynitride film having a sufficient amount of nitrogen than oxygen. The first insulating film is located between the active part and the charge storage film. The first insulating film may include a silicon oxide film or a thin (about 50 to 150 mm) multilayer film including any of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film. The second insulating film is located between the charge storage film and the control gate. The second insulating layer may be a silicon oxide layer, a high-K material, an aluminum oxide layer, or a combination thereof.

  On the other hand, the conductive patterns GSL, WL1 to WL4, and SSL are spaced apart from each other with the inter-gate insulating films 111 to 115 interposed therebetween. For example, the ground selection line GSL, the first inter-gate insulating film 111, the first word line WL1, the second inter-gate insulating film 112, the second word line WL2, the third inter-gate insulating film 113, the third word line WL3, A fourth inter-gate insulating film 114, a fourth word line WL4, a fifth inter-gate insulating film 115, and a string selection line SSL are sequentially stacked.

  A ground selection insulating film 110 is disposed between the bottom surface 103 of the recess A, the first and second side walls 105 and 106, and the ground selection line GSL. A string selection insulating layer 116 is disposed on the string selection line SSL. The insulating films 110 to 116 together form the interlayer insulating film. Each of the insulating films 110 to 116 includes a bottom portion disposed on and parallel to the bottom surface 103 of the recess A, and the first sidewall 105 from the bottom portion. And a side wall portion extending along the second side wall 106.

The conductive patterns GSL, WL1 to WL4, and SSL include a bottom BP disposed on the bottom surface 103 of the recess A. The bottom BP is parallel to the bottom surface 103.
The memory string is formed through the conductive patterns GSL, WL1 to WL4, SSL and the interlayer insulating film in the cell array region, and the through holes of the conductive pattern and the interlayer insulating film are formed in the memory string. In contact with the second insulating film.
The active portion of the memory cell includes a portion of the memory string corresponding to a through-hole wall with the word lines WL1 to WL4.

  The conductive patterns GSL, WL1 to WL4, and SSL include an upper extension (upper inclined portion). The upper extension includes a contact extension CT. The contact extension CT extends from one end of the bottom BP onto one of the first side wall 105 and the second side wall 106. A contact region in which a contact extension of any one of the conductive patterns GSL, WL1 to WL4, SSL is disposed, and a contact extension of a conductive pattern adjacent to the one of the conductive patterns are disposed. The contact area can be different. For example, when the contact extension CT of the ground selection line GSL is disposed in the first contact region CR1, the contact extension CT of the first word line WL1 adjacent to the ground selection gate film GSL is the second contact region. Located in CR2.

  The contact extension CT is inclined with respect to the bottom surface 103. For example, the contact extension CT may be inclined at a right angle with respect to the bottom surface 103. In one embodiment of the present invention, the upper surface of the contact extension CT is coplanar with the upper surface of the raised portion B. An angle between the contact extension CT and the bottom BP may be 50 ° to 90 °.

  The conductive patterns GSL, WL1 to WL4, and SSL are extended from the other end of the bottom portion BP on the bottom surface 103 to another side surface of the first side surface 105 and the second side surface 106 (extended over). ) Includes dummy extension DCT. A contact region where a dummy extension of any one of the conductive patterns GSL, WL1 to WL4, SSL is disposed, and a dummy extension of another conductive pattern adjacent to any one of the conductive patterns The arranged contact regions can be different. For example, when the dummy extension DCT of the string selection line SSL is disposed in the first contact region CR1, the dummy extension DCT of the fourth word line WL4 adjacent to the string selection line SSL is the second contact region. Located in CR2.

  Each of the conductive patterns GSL, WL1 to WL4, SSL includes one contact extension CT and one dummy extension DCT. In one conductive pattern among the conductive patterns GSL, WL1 to WL4, and SSL, the length of the dummy extension DCT may be shorter than the length of the contact extension CT. The contact extension CT is disposed between the adjacent dummy extensions DCT. The contact extension CT adjacent to the dummy extension DCT is separated by the side wall of the insulating film interposed therebetween. In other words, a part of the word line can be connected to the conductive line on the first side of the memory string (left side in FIGS. 1 and 2, ie, in the first contact region CR1) (described later), and the rest of the word line is the memory. Since it can be connected to a conductive line on the second side of the string (on the right side in FIGS. 1 and 2, that is, in the second contact region CR2) (described later), the connection contact margin can be improved.

  A dummy insulating pattern 124 is disposed on the dummy extension DCT. The upper surface of the dummy insulating pattern 124 is flush with the upper surface of the raised portion B. The upper surface of the dummy insulating pattern 124 is flush with the upper surface of the string selection insulating film 116. The side wall of the dummy insulating pattern 124 is flush with the side wall of the dummy extension DCT. The dummy insulating pattern 124 may include the same material as the insulating layers 110 to 116.

  Conductive plugs are respectively disposed on the contact extensions CT of the word lines WL1 to WL4. The conductive plug may be a word line contact plug CP. Each of the word lines WL1 to WL4 is electrically connected to the word line contact plug CP. The word line contact plug CP may be wider than the upper surface of the contact extension CT of the word lines WL1 to WL4. The word line contact plug CP may be wider than a width between the contact extension CT of the word lines WL1 to WL4 and the adjacent dummy extension DCT. The word line contact plug CP penetrates the first interlayer insulating layer 160. A first conductive line ML1 is disposed on the word line contact plug CP and the first interlayer insulating layer 160. The word line contact plug CP is electrically connected to the first conductive line ML1. A portion of the first conductive line ML1 extends in a first direction (leftward in FIGS. 1 and 2). The remaining part of the first conductive line ML1 is extended in a second direction (rightward in FIGS. 1 and 2) opposite to the first direction. For example, the first conductive lines ML1 connected to the word lines WL2 and WL4 disposed on the odd layers from the substrate 101 are extended in the first direction, and the word lines WL1 and WL3 disposed on the even layers from the substrate 101. The first conductive line ML1 connected to is extended in the second direction. The first conductive line ML1 is electrically connected to the word lines WL1 to WL4 through the word line contact plug CP. In contrast, the word lines WL1 to WL4 and the conductive line ML1 may be directly connected. A second interlayer insulating layer 170 is disposed to cover the first conductive line ML1. The first interlayer insulating layer 160 and the second interlayer insulating layer 170 may include the same material.

  A conductive plug is disposed on the contact extension CT of the ground selection line GSL. The conductive plug may be a ground selection contact plug GCP. The ground selection line GSL is electrically connected to the ground selection contact plug GCP. The width of the ground selection contact plug GCP may be wider than the width of the upper surface of the contact extension CT of the ground selection line GSL. The ground selection contact plug GCP penetrates the first interlayer insulating layer 160. A second conductive line ML2 is disposed on the ground selection contact plug GCP and the first interlayer insulating layer 160. The ground selection contact plug GCP is electrically connected to the second conductive line ML2. The second conductive line ML2 extends in the first direction. The second conductive line ML2 is electrically connected to the ground selection line GSL through the ground selection contact plug GCP. In contrast, the ground selection line GSL and the second conductive line ML2 may be directly connected. The second interlayer insulating layer 170 covers the second conductive line ML2.

  A conductive plug is disposed on the contact extension CT of the string selection line SSL. The conductive plug may be a string selection contact plug SCP. The string selection line SSL is electrically connected to the string selection contact plug SCP. The width of the string selection contact plug SCP may be wider than the width of the upper surface of the contact extension CT of the string selection line SSL. The string selection contact plug SCP penetrates the first interlayer insulating layer 160. A third conductive line ML3 is disposed on the string selection contact plug SCP and the first interlayer insulating layer 160. The string selection contact plug SSL is electrically connected to the third conductive line ML3. Referring to FIGS. 1 and 2, a plurality of string selection lines SSL are provided in the recess A. The third conductive lines ML3 of the string selection lines SSL adjacent to each other extend in the same direction in the case of FIG. 1 and in different directions in the case of FIG. In another embodiment of the present invention, the conductive pad is interposed between the contact pad and the contact extension CT.

  The conductive lines ML1 to ML3 are divided and extended in the first direction and the second direction with the cell array region CAR interposed therebetween. For example, the conductive lines ML1, ML2 connected to the conductive patterns GSL, WL2, WL4 disposed in the first contact region CR1 in the first contact region CR1 are extended in the first direction, and the contact extension CT is in the second direction. Conductive lines ML1 and ML3 connected to the conductive patterns WL1, WL3, and SSL disposed in the contact region CR2 extend in the second direction.

  An active portion AP extending upward from the bottom surface 103 of the recess A is disposed. The active part AP extends vertically to the substrate 101. The active part AP penetrates the conductive patterns GSL, WL1 to WL4, SSL, and one end of the active part AP is electrically connected to the common source region 102. A drain region D is disposed at the other end of the active part AP. The drain region D may be a region doped with a high concentration of dopant. For example, the active part AP includes a single crystal semiconductor.

In an embodiment of the present invention, a bit line contact plug BLCP is disposed on the drain region D of the active part AP. The bit line contact plug BLCP is electrically connected to the drain region D and penetrates the first interlayer insulating layer 160. A bit line BL is disposed on the bit line contact plug BLCP. The bit line BL is connected to the drain region D of the active part AP through the bit line contact plug BLCP. In contrast, the bit line BL may be directly connected to the drain region D. The bit line BL extends in a third direction that intersects the first direction and the second direction. The third direction can intersect the first and second directions at right angles, and in this case, the third direction is parallel to the horizontal direction of the first and second side walls 105 and 106.
A plurality of the bit lines BL are arranged, and each bit line BL has the bit line contact plug BLCP in the drain region D of the plurality of memory strings aligned along the third direction in the array of memory strings. Connected through. Therefore, the bit line BL also intersects with the string selection line SSL.

  An information storage layer 132 is interposed between the sidewall of the active part AP and the conductive patterns GSL, WL1 to WL4, SSL. The information storage layer 132 is disposed in a cylinder type that penetrates the conductive patterns GSL, WL1 to WL4, and SSL. The information storage layer 132 is disposed to surround the active part AP. The information storage layer 132 is disposed between the sidewall of the active part AP and the conductive patterns GSL, WL1-WL4, SSL and the insulating layers 110-116.

  The active part, the information storage film, and the conductive pattern according to the first embodiment of the present invention will be described in detail. FIG. 6 is a view for explaining an information storage film according to the first embodiment of the present invention.

  Referring to FIG. 6, the information storage film 132 includes a first insulating film (hereinafter also referred to as “tunnel dielectric film”) 136, a charge storage film 135, and a second insulating film (hereinafter also referred to as “blocking film”). 134.

Referring to FIGS. 1 and 2, one wiring extending outside one end of the cell array unit is electrically connected to a contact extension of the word line on one side, and is connected outside the other end of the cell array unit. The other wiring to be extended is electrically connected to the contact extension of the other word line.
As shown in FIG. 1, all the string selection lines SSL are connected to wiring on one side, while as shown in FIG. 2, some of the string selection lines are connected to wiring on one side to select the remaining strings. The line is connected to the wiring on the other side. The word lines are selected alternately. That is, for example, the odd-numbered word lines (first, third, and fifth word lines) from the bottom to the top of the string are connected to the wiring on one side (right side in FIGS. 1 and 2) of the string, The second word line (second, fourth and sixth word lines) is connected to the wiring on the other side of the string (left side in FIGS. 1 and 2).

  The tunnel dielectric layer 136 covers the sidewall of the active part AP. The tunnel dielectric layer 136 may be a single layer or a multilayer. For example, the tunnel dielectric film 136 includes at least one selected from a silicon oxynitride film, a silicon nitride film, a silicon oxide film, and a metal oxide film.

  The charge storage film 135 covers the tunnel dielectric film 136. The charge storage layer 135 is separated from the active part AP by the tunnel dielectric layer 136. The charge storage layer 135 may include a charge trap site that can store charges. For example, the charge storage layer 135 includes at least one of a silicon nitride film, a metal nitride film, a metal oxynitride film, a metal silicon oxide film, a metal silicon oxynitride film, and nanodots.

A blocking layer 134 is interposed between the charge storage layer 135 and the conductive patterns GSL, WL1 to WL4, SSL. A blocking film 134 is interposed between the charge storage film 135 and the insulating films 110 to 116. The blocking film 134 covers the charge storage film 135. The blocking film 134 includes at least one selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a high dielectric film. The high dielectric film includes at least one selected from a metal oxide film, a metal nitride film, and a metal oxynitride film. The high dielectric film includes hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), lanthanum (La), cerium (Ce), praseodymium (Pr), and the like. The blocking film 134 may have a dielectric constant greater than that of the tunnel insulating film 136.

  A modification of the first embodiment of the present invention will be described. FIG. 5 is a view for explaining a modification of the first embodiment of the present invention, and is a cross-sectional view taken along the line I-I ′ of FIGS. 1 and 2.

  With reference to FIGS. 1, 2, and 5, a substrate 101 is provided. A common source region is disposed in the substrate 101. The substrate 101 includes a recess A. The recess A includes a first side wall 105 and a second side wall 106 that face the bottom surface 103. The substrate 101 includes a ridge B extending from the first and second side walls 105 and 106. The upper surface of the raised portion B is parallel to the bottom surface 103 of the recess A. The raised portion B is defined by a protruding portion 104 disposed on the substrate 101.

  A memory cell is disposed in the recess A. The recess A includes a first contact region CR 1 adjacent to the first side wall 105 and a second contact region CR 2 adjacent to the second side wall 106. The memory cell may be the memory cell described with reference to FIG.

  A semiconductor device according to another modification of the first embodiment of the present invention will be described. FIG. 5 is a view for explaining another modified example of the first embodiment of the present invention, and is a cross-sectional view taken along line I-I ′ of FIG. 1.

  1, 2 and 5, a substrate 101 is provided. A common source region is disposed in the substrate 101. The substrate 101 includes a recess A. The recess A includes a first side wall 105 and a second side wall 106 that face the bottom surface 103. One of the first side wall 105 and the second side wall 106 is inclined toward the bottom surface 103 of the recess A. For example, the first side wall 105 and the second side wall 106 may be 50 ° or smaller than 90 ° with respect to the bottom surface 103. The slope that the first side wall 105 has with respect to the bottom surface 103 and the slope that the second side wall 106 has with respect to the bottom surface 103 may be the same. In contrast, the slope of the first side wall 105 with respect to the bottom surface 103 may be different from the slope of the second side wall 106 with respect to the bottom surface 103. The substrate 101 includes a ridge B extending from the first and second side walls 105 and 106. The upper surface of the raised portion B is parallel to the bottom surface 103 of the recess A. In the substrate 101, the recess A and the raised portion B are defined through an etching process. In contrast, as described with reference to FIG. 4, the raised portion B is defined by a protrusion 104 formed by selective vapor deposition on the substrate 101.

  A memory cell is disposed in the recess A. The memory cell will be described. The recess A includes a first contact region CR1 adjacent to the first side wall 105 and a second contact region CR2 adjacent to the second side wall 106. The memory cell described with reference to FIG. 3 is arranged. In one of the conductive patterns GSL, WL1 to WL4, and SSL, the contact extension CT and the dummy extension DCT have a slope inclined with respect to the bottom BP.

  The angle formed by the side wall adjacent to the contact region where the contact extension CT is disposed and the bottom surface 103 may be the same as the angle formed by the contact extension CT and the bottom BP. Taking the first word line WL1 as an example, the slope of the contact extension CT with respect to the bottom BP may be the same as the slope of the second sidewall 106 with respect to the bottom surface 103. When the slopes of the first sidewall 105 and the second sidewall 106 with respect to the bottom surface 103 are different from each other, the slope of the contact extension CT with respect to the bottom BP in one conductive pattern is determined by the dummy extension DCT. It can be different from the slope it has for the bottom BP.

FIG. 1 shows a memory device including at least two row decoders assigned to a cell array, in which all the string selection lines SSL are combined with a row decoder on one side, while FIG. 2 shows an odd number of string selection lines. Are coupled to the row decoder on one side, and even string select lines indicate memory elements coupled to the row decoder on the other side.

  A semiconductor device according to a second embodiment of the present invention will be described. 7 to 8 are plan views for explaining a semiconductor device according to the second embodiment of the present invention. FIG. 9 is a cross-sectional view taken along the line II-II ′ of FIGS. is there.

  Referring to FIGS. 7, 8, and 9, a substrate 201 is provided. The substrate 201 is a semiconductor substrate. The substrate 201 includes a well. The well includes a first conductivity type dopant. A common source region 202 is disposed in the substrate 201. The common source region 202 is disposed in a plate form in the cell region of the substrate 201. The common source region 202 may include a high concentration of dopant. The dopant included in the common source region 202 may have a second conductivity type that is different from the dopant included in the well. For example, when the well includes a p-type dopant, the common source region 202 includes a high concentration of n-type dopant.

  The substrate 201 includes a recess A. The recess A includes a first side wall 205 and a second side wall 206 that face the bottom surface 203. The substrate 201 includes a ridge B extending from the first and second sidewalls 205 and 206. The upper surface of the raised portion B is parallel to the bottom surface 203 of the concave portion A. The recessed portion A and the raised portion B are formed by etching a portion where the recessed portion A of the semiconductor substrate is disposed, and leaving a portion where the raised portion B is disposed. In this case, the substrate 201 may be an integral substrate. A memory cell is disposed in the recess A.

  The recess A includes a first contact region CR1 adjacent to the first sidewall 205 and a second contact region CR2 adjacent to the second sidewall 206. A cell array region CAR is disposed between the first contact region CR1 and the second contact region CR2. The first contact region CR1 and the second contact region CR2 are spaced apart from each other across the cell array region CAR.

  Conductive patterns GSL, WL1 to WL4, SSL spaced apart from each other are disposed on the substrate 201. The conductive patterns GSL, WL1 to WL4, and SSL include a ground selection line GSL, word lines WL1 to WL4, and a string selection line SSL that are sequentially stacked on the recess A of the substrate 201. The conductive patterns GSL, WL1-WL4, SSL are spaced apart from each other with the inter-gate insulating films 210-214 interposed therebetween. For example, the ground selection line GSL, the first inter-gate insulating film 210, the first word line WL1, the second inter-gate insulating film 211, the second word line WL2, the third inter-gate insulating film 212, the third word line WL3, A fourth inter-gate insulating film 213, a fourth word line WL4, a fifth inter-gate insulating film 214, and a string selection line SSL are sequentially stacked. The insulating films 210 to 214 include a bottom portion on the bottom surface 203 of the recess A of the substrate 201, and sidewall portions extending from the bottom portion to the first sidewall 205 and the second sidewall 206. A string selection insulating film 215 is disposed on the string selection line SSL. The conductive patterns GSL, WL1 to WL4, and SSL may have a line shape extending in the first direction. The first direction is a direction II-II ′. That is, the memory element of the present embodiment is an element including an X-cut trench that separates word line planes in a cell array memory. The separated word lines at substantially the same level are electrically connected to each other and act as one word line plane.

  The conductive patterns GSL, WL1 to WL4, and SSL include a bottom BP disposed on the bottom surface 203 of the recess A. The length of the bottom BP becomes shorter as the distance from the recess A of the substrate 201 increases. The bottom BP is parallel to the bottom surface 203. The bottom portion BP is parallel to the upper surface of the raised portion B.

  The conductive patterns GSL, WL1 to WL4, and SSL include a contact extension CT that extends from one end of the bottom BP to one of the first sidewall 205 or the second sidewall 206. A contact region in which a contact extension of any one of the conductive patterns GSL, WL1 to WL4, SSL is disposed; and a contact extension of another conductive pattern adjacent to the one of the conductive patterns. The arranged contact regions can be different. For example, when the contact extension CT of the ground selection line GSL is disposed in the first contact region CR1, the contact extension CT of the first word line WL1 adjacent to the ground selection line GSL is the second contact region CR2. Placed in.

  The contact extension CT is inclined with respect to the bottom surface 203. The contact extension CT may be inclined at a right angle with respect to the bottom surface 203. The contact extension CT decreases in length as the distance from the recess A of the substrate 201 increases. The upper surface of the contact extension CT is flush with the upper surface of the raised portion B. An angle between the contact extension CT and the bottom BP may be 90 °.

  The conductive patterns GSL, WL1 to WL4, and SSL are extended from the other end of the bottom BP on the bottom surface 203 to the other one of the first side surface 205 and the second side surface 206 (extended over). ) Includes dummy extension DCT. A contact region where a dummy extension of any one of the conductive patterns GSL, WL1 to WL4, SSL is disposed, and a dummy extension of another conductive pattern adjacent to any one of the conductive patterns The arranged contact regions can be different. For example, when the dummy extension DCT of the string selection line SSL is disposed in the first contact region CR1, the dummy extension DCT of the fourth word line WL4 adjacent to the string selection line SSL is the second contact region. Located in CR2.

  Each of the conductive patterns GSL, WL1 to WL4, SSL includes one contact extension CT and one dummy extension DCT. In one conductive pattern among the conductive patterns GSL, WL1 to WL4, and SSL, the length of the dummy extension DCT may be shorter than the length of the contact extension CT. The contact extension CT is disposed between the adjacent dummy extensions DCT. The contact extension CT adjacent to the dummy extension DCT is separated by the side wall of the insulating film interposed therebetween.

  A dummy insulating pattern 264 is disposed on the dummy extension DCT. The upper surface of the dummy insulating pattern 264 is flush with the upper surface of the raised portion B. The upper surface of the dummy insulating pattern 264 is flush with the upper surface of the string selection insulating film 215. The side wall of the dummy insulating pattern 264 is flush with the side wall of the dummy extension DCT. The dummy insulating pattern 264 may include the same material as the insulating layers 210 to 215.

  Conductive plugs are disposed on the contact extensions CT of the word lines WL1 to WL4. The conductive plug may be a word line contact plug CP. Each of the word lines WL1 to WL4 is electrically connected to the word line contact plug CP. The word line contact plug CP may be wider than the upper surface of the contact extension CT of the word lines WL1 to WL4. The word line contact plug CP may be wider than a width between the contact extension CT of the word lines WL1 to WL4 and the adjacent dummy extension DCT. The word line contact plug CP penetrates the first interlayer insulating layer 280. A first conductive line ML1 is disposed on the word line contact plug CP and the first interlayer insulating layer 280. The word line contact plug CP is electrically connected to the first conductive line ML1. The first conductive line ML1 extends in a second direction that intersects the first direction. The first conductive line ML1 is electrically connected to the word lines WL1 to WL4 through the word line contact plug CP. In contrast, the first conductive line ML1 and the word lines WL1 to WL4 may be directly connected. A second interlayer insulating layer 290 is disposed to cover the first conductive line ML1. The first interlayer insulating layer 280 and the second interlayer insulating layer 290 may include the same material.

  A conductive plug is disposed on the contact extension CT of the ground selection line GSL. The conductive plug may be a ground selection contact plug GCP. The ground selection line GSL is electrically connected to the ground selection contact plug GCP. The width of the ground selection contact plug GCP may be wider than the width of the upper surface of the contact extension CT of the ground selection line GSL. The ground selection contact plug GCP penetrates the first interlayer insulating layer 280. A second conductive line ML2 is disposed on the ground selection contact plug GCP and the first interlayer insulating layer 280. The ground selection contact plug GSP is electrically connected to the second conductive line ML2. The second conductive line ML2 extends in the second direction. The second conductive line ML2 is electrically connected to the ground selection line GSL through the ground selection contact plug GCP. In contrast, the second conductive line ML2 may be directly connected to the ground selection line GSL. The second interlayer insulating layer 290 covers the second conductive line ML2.

  A conductive plug is disposed on the contact extension CT of the string selection line SSL. The conductive plug may be a string selection contact plug SCP. The string selection line SSL is electrically connected to the string selection contact plug SCP. The width of the string selection contact plug SCP may be wider than the width of the upper surface of the contact extension CT of the string selection line SSL. The string selection contact plug SCP penetrates the first interlayer insulating layer 280 and the second interlayer insulating layer 290. A third conductive line ML3 is disposed on the string selection contact plug SCP and the second interlayer insulating layer 280. The string selection contact plug SSL is electrically connected to the third conductive line ML3. The third conductive line ML3 extends in the first direction. Referring to FIG. 8, a plurality of string selection lines SSL are disposed in the recess A. The third conductive lines ML3 of the string selection lines SSL adjacent to each other are extended in the other direction.

  The conductive lines ML1 and ML2 are arranged separately on both sides of the cell array region CAR. The conductive line connected to any one of the conductive patterns GSL, WL1 to WL is arranged in a different contact region from the conductive line connected to the other conductive pattern adjacent to the one conductive pattern. Is done. For example, the first conductive line ML1 connected to the first word line WL1 is disposed in the second contact region CR2, and the ground selection line GSL and the second word line adjacent to the first word line WL1. The second conductive line ML2 and the first conductive line ML1 respectively connected to WL2 are disposed in the first contact region CR1.

  An active part AP extending upward from the bottom surface 203 of the recess A of the substrate 201 is disposed. The active part AP extends perpendicularly to the substrate 201. The active part AP penetrates the conductive patterns GSL, WL1 to WL4, SSL. In contrast, the active part AP may face the side surfaces of the conductive patterns GSL, WL1 to WL4, and SSL. One end of the active part AP is electrically connected to the common source region 202. A drain region 223 is disposed at the other end of the active part AP. The drain region D may be a region doped with a high concentration of dopant. The active part AP includes a single crystal semiconductor.

  A bit line contact plug BLCP is disposed on the drain region D of the active part AP. The bit line contact plug BLCP is electrically connected to the drain region 223 and penetrates the first interlayer insulating film 280 and the second interlayer insulating film 290. A bit line BL is disposed on the bit line contact plug BLCP. The bit line BL is connected to the drain region 223 of the active part AP through the bit line contact plug BLCP. In contrast, the bit line BL may be directly connected to the drain region D. The bit line BL is extended in the second direction. The bit line BL intersects the third conductive line ML3.

  An information storage layer 240 is interposed between the sidewall of the active part AP and the conductive patterns GSL, WL1 to WL4, SSL. The information storage layer 240 is disposed between the conductive patterns GSL, WL1 to WL4, SSL and a sidewall of the active part AP. The information storage layer 240 is disposed between the conductive patterns GSL, WL1-WL4, SSL and the insulating layers 210-215.

  An active part, an information storage film, and a conductive pattern according to the second embodiment of the present invention will be specifically described. FIG. 12 is a view for explaining an information storage film according to the second embodiment of the present invention.

  FIG. 7 shows a memory device including at least two row decoders assigned to a cell array, all of the string selection lines SSL being combined with one row decoder, while FIG. 8 shows an odd number of string selection lines. Coupled to one row decoder, even string select lines indicate memory elements coupled to other row decoders.

  Referring to FIG. 12, the information storage layer 240 includes a tunnel dielectric layer 242, a charge storage layer 244, and a blocking layer 246.

  The tunnel dielectric layer 242 covers the sidewall of the active part AP. The tunnel dielectric layer 242 may be a single layer or a multilayer. For example, the tunnel dielectric film 242 includes at least one selected from a silicon oxynitride film, a silicon nitride film, a silicon oxide film, and a metal oxide film.

  The charge storage film 244 covers the tunnel dielectric film 242. The charge storage layer 244 is separated from the active part AP by the tunnel dielectric layer 242. The charge storage layer 244 may include a charge trap site that can store charges. For example, the charge storage layer 244 includes at least one of a silicon nitride layer, a metal nitride layer, a metal oxynitride layer, a metal silicon oxide layer, a metal silicon oxynitride layer, and nanodots.

A blocking layer 246 is interposed between the charge storage layer 244 and the conductive patterns GSL, WL1-WL4, SSL. A blocking film 246 is interposed between the charge storage film 244 and the insulating films 110 to 116. The blocking film 246 covers the charge storage film 244. The blocking film 246 includes at least one selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a high dielectric film. The high dielectric film includes at least one selected from a metal oxide film, a metal nitride film, and a metal oxynitride film. The high dielectric film includes hafnium (Hf), zirconium (Zr), aluminum (AP), tantalum (Ta), lanthanum (Pa), cerium (Ce), praseodymium (Pr), and the like. The blocking film 246 may have a dielectric constant greater than that of the tunnel insulating film 242.
The modification of the active part of 2nd Embodiment of this invention is demonstrated. FIG. 13 is a diagram for explaining an active part according to a modification of the second embodiment of the present invention.

  Referring to FIG. 13, the information storage layer 240 including the tunnel dielectric layer 242, the charge storage layer 244 and the blocking layer 246 described with reference to FIG. 12 is disposed between the conductive patterns WL1 and GSL and the active part AP. The The active part AP faces the side surface of the bottom part BP of the conductive patterns GSL, WL1.

  A modification of the second embodiment of the present invention will be described. FIG. 10 is a view for explaining a modification of the second embodiment of the present invention, and is a cross-sectional view taken along the line II-II ′ of FIGS. 7 and 8.

  Referring to FIGS. 7, 8, and 10, a substrate 200 is provided. A common source region 202 is disposed in the substrate 200. The substrate 200 includes a recess A. The recess A includes a first side wall 205 and a second side wall 206 that face the bottom surface 203. The substrate 200 includes a ridge B extending from the first and second sidewalls 205 and 206. The upper surface of the raised portion B is parallel to the bottom surface 203 of the concave portion A. The raised portion B is defined by an insulating film 204 disposed on the substrate 201.

  A memory cell is disposed in the recess A. The recess A includes a first contact region CR1 adjacent to the first sidewall 205 and a second contact region CR2 adjacent to the second sidewall 206. The memory cell described with reference to FIG. 9 is disposed in the recess A of the substrate 200.

  A semiconductor device according to another modification of the second embodiment of the present invention will be described. FIG. 11 is a view for explaining another modification of the second embodiment of the present invention, and is a cross-sectional view taken along the line II-II ′ of FIGS. 7 and 8.

  Referring to FIGS. 7, 8, and 11, a substrate 201 is provided. A common source region 102 is disposed in the substrate 201. The substrate 201 includes a recess A. The recess A includes a first side wall 205 and a second side wall 206 that face the bottom surface 203. One of the first side wall 205 and the second side wall 206 is inclined to the bottom surface 203 of the recess A. For example, the first sidewall 205 and the second sidewall 206 may be 50 ° or less than 90 ° with respect to the bottom surface 203. The slope of the first side wall 205 with respect to the bottom surface 203 and the slope of the second side wall 206 with respect to the bottom surface 203 may be the same. In contrast, the slope of the first side wall 205 with respect to the bottom surface 203 may be different from the slope of the second side wall 206 with respect to the bottom surface 203. The substrate 201 includes a ridge B extending from the first and second sidewalls 205 and 206. The upper surface of the raised portion B is parallel to the bottom surface 203 of the concave portion A. The recesses and ridges of the substrate are defined through an etching process. In contrast, as described with reference to FIG. 10, the raised portion B is defined by the insulating film 104 disposed on the substrate 201.

  A memory cell is disposed in the recess A. The recess A includes a first contact region CR1 adjacent to the first side wall 205 and a second contact region CR2 adjacent to the second side wall 206. The memory cell described with reference to FIG. 9 is arranged. In one of the conductive patterns GSL, WL1 to WL4, and SSL, the contact extension CT and the dummy extension DCT have a slope inclined with respect to the bottom BP.

  The angle formed by the side wall adjacent to the contact region where the contact extension CT is disposed and the bottom surface 203 may be the same as the angle formed by the contact extension CT and the bottom BP. Taking the first word line WL1 as an example, the slope of the contact extension CT with respect to the bottom BP may be the same as the slope of the second sidewall 206 with respect to the bottom surface 203. When the slopes of the first sidewall 205 and the second sidewall 206 with respect to the bottom surface 203 are different, the slope of the contact extension CT with respect to the bottom BP in one conductive pattern is determined by the dummy extension DCT. It can be different from the slope it has for the bottom BP.

  Referring to FIGS. 12 and 13, the active part is formed of silicon. The active part may be a pillar, a tubular, or a bar-sided shape. The active part is formed of single crystal silicon or polycrystalline silicon. The active part is formed of amorphous silicon and crystallized into polycrystalline silicon. FIG. 13 shows a barside vertical active part. According to the present invention, the shape of the active part is not limited. Therefore, a tube or column-shaped active part can be applied to FIGS. 1, 2, 7, and 8.

  A semiconductor device according to a third embodiment of the present invention will be described. FIG. 14 is a plan view for explaining a semiconductor device according to the third embodiment of the present invention, and FIG. 15 is a cross-sectional view taken along the line III-III 'of FIG.

  Referring to FIGS. 14 and 15, a substrate 301 is provided. The substrate 301 is a semiconductor substrate. The intermediate substrate 301 includes a well. The well includes a first conductivity type dopant. A common source region 302 is disposed in the substrate 301. The common source region 302 is disposed in a plate form in the cell region of the substrate 301. The common source region 302 may include a high concentration of dopant. The dopant included in the common source region 302 may be a second conductivity type having a conductivity type different from that of the dopant included in the well. For example, when the well includes a p-type dopant, the common source region 302 includes a high concentration of n-type dopant.

  The substrate 301 includes a recess A. The recess A includes a bottom surface 303 and a first side wall 306. The substrate 301 includes a ridge B extending from the first side wall 306. The upper surface of the raised portion B is parallel to the bottom surface 303 of the concave portion A. The recessed portion A and the raised portion B are formed by etching a portion where the recessed portion A of the semiconductor substrate is disposed, and leaving a portion where the raised portion B is disposed. In this case, the substrate 301 is an integral substrate.

  The substrate 301 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. The cell region α includes the concave portion A and the raised portion B. A peripheral circuit is disposed in the peripheral circuit region β. The peripheral circuit region β includes the raised portion B.

  The cell region α of the substrate 301 will be described.

  Conductive patterns GSL, WL1 to WL4, SSL spaced apart from each other are disposed on the recess A of the substrate 301. The conductive patterns GSL, WL1 to WL4, and SSL include a ground selection line GSL, word lines WL1 to WL4, and a string selection line SSL that are sequentially stacked on the recess A of the substrate 301. The conductive patterns GSL, WL1 to WL4, and SSL are spaced apart from each other with inter-gate insulating films 311 to 315 interposed therebetween. For example, the ground selection line GSL, the first inter-gate insulating film 311, the first word line WL1, the second inter-gate insulating film 312, the second word line WL2, the third inter-gate insulating film 313, the third word line WL3, A fourth inter-gate insulating film 314, a fourth word line WL4, a fifth inter-gate insulating film 315, and a string selection line SSL are sequentially stacked.

  A ground selection insulating film 310 is disposed between the bottom surface 303 and the first sidewall 306 of the recess A of the substrate 301 and the ground selection line GSL. A string selection insulating layer 316 is disposed on the string selection line SSL. The insulating films 310 to 116 include a bottom portion on the bottom surface 303 of the recess A of the substrate 301 and a sidewall portion extending from the bottom portion onto the first sidewall 306.

  The conductive patterns GSL, WL1 to WL4, and SSL include a bottom portion BP disposed on the bottom surface 303 of the recess A. The length of the bottom BP can be shortened as the distance from the recess A of the substrate 301 increases. The bottom BP is parallel to the bottom surface 303. The bottom portion BP is parallel to the upper surface of the raised portion B.

  The conductive patterns GSL, WL1 to WL4, and SSL include a contact extension CT that extends from the one end of the bottom BP to the first sidewall 206. An extension line of the contact extension CT may intersect the bottom surface 303. An extension line of the contact extension CT may intersect the bottom surface 303 at a right angle. The contact extension CT decreases in length as the distance from the recess A of the substrate 301 increases. The upper surface of the contact extension CT is flush with the upper surface of the raised portion B. An angle between the contact extension CT and the bottom BP may be 90 °.

  Conductive plugs are disposed on the contact extensions CT of the word lines WL1 to WL4. The conductive plug may be a word line contact plug CP. Each of the word lines WL1 to WL4 is electrically connected to the word line contact plug CP. The word line contact plug CP penetrates the first interlayer insulating layer 360. A first conductive line ML1 is disposed on the word line contact plug CP and the first interlayer insulating layer 360. The word line contact plug CP is electrically connected to the first conductive line ML1. The first conductive line ML1 extends in the first direction. The first conductive line ML1 is electrically connected to the word lines WL1 to WL4 through the word line contact plug CP. In contrast, the first conductive line ML1 may be directly connected to the word lines WL1 to WL4. A second interlayer insulating layer 370 is disposed to cover the first conductive line ML1. The first interlayer insulating layer 360 and the second interlayer insulating layer 360 may include the same material.

  A conductive plug is disposed on the contact extension CT of the ground selection line GSL. The conductive plug may be a ground selection contact plug GCP. The ground selection line GSL is electrically connected to the ground selection contact plug GCP. The ground selection contact plug GCP penetrates the first interlayer insulating layer 360. A second conductive line ML2 is disposed on the ground selection contact plug GCP and the first interlayer insulating layer 360. The ground selection contact plug GCP is electrically connected to the second conductive line ML2. The second conductive line ML2 extends in the first direction. The first direction is a III-III ′ direction. The second conductive line ML2 is electrically connected to the ground selection line GSL through the ground selection contact plug GCP. In contrast, the second conductive line ML2 may be directly connected to the ground selection line GSL. The second interlayer insulating layer 370 covers the second conductive line ML2.

  A conductive plug is disposed on the contact extension CT of the string selection line SSL. The conductive plug may be a string selection contact plug SCP. The string selection line SSL is electrically connected to the string selection contact plug SCP. The string selection contact plug SCP penetrates the first interlayer insulating layer 360 and the second interlayer insulating layer 370. A third conductive line ML3 is disposed on the string selection contact plug SCP and the first interlayer insulating layer 360. The string selection contact plug SSL is electrically connected to the third conductive line ML3. The third conductive line ML3 extends in the first direction.

  An active portion AP extending upward from the bottom surface 303 of the recess A is disposed. The active part AP extends perpendicularly to the substrate 301. The active part AP penetrates the conductive patterns GSL, WL1 to WL4, SSL, and one end of the active part AP is electrically connected to the common source region 302. A drain region D is disposed at the other end of the active part AP. The drain region D may be a region doped with a high concentration of dopant. The active part AP includes a single crystal semiconductor.

  A bit line contact plug BLCP is disposed on the drain region D of the active part AP. The bit line contact plug BLCP is electrically connected to the drain region D and penetrates the first interlayer insulating layer 360. A bit line BL is disposed on the bit line contact plug BLCP. The bit line BL is connected to the drain region D of the active part AP through the bit line contact plug BLCP. In contrast, the bit line BL may be directly connected to the drain region D. The bit line BL extends in a second direction that intersects the first direction. The bit line BL intersects the third conductive line ML3.

  An information storage layer 332 is interposed between the sidewall of the active part AP and the conductive patterns GSL, WL1 to WL4, SSL. The information storage layer 332 is disposed in a cylinder type that penetrates the conductive patterns GSL, WL1 to WL4, and SSL. The information storage layer 332 is disposed so as to surround the active part AP. The information storage layer 332 is disposed between the sidewall of the active part AP and the conductive patterns GSL, WL1 to WL4, SSL and the insulating layers 310 to 116.

  The information storage film 332 according to the third embodiment of the present invention is the information storage film described with reference to FIG.

  The peripheral circuit region β of the substrate 301 will be described.

  A peripheral circuit is disposed on the upper surface of the raised portion B of the peripheral circuit region β. A gate insulating layer 354 is disposed on the upper surface of the raised portion B. The gate insulating layer 354 includes a silicon oxide layer. The gate insulating layer 354 is formed by thermally oxidizing the upper surface of the raised portion B. A gate electrode 356 is disposed on the gate insulating layer 354. The gate electrode 356 includes any one of doped polysilicon, metal, and metal silicide. Spacers 358 are disposed on both side walls of the gate electrode 356. Source / drain regions 353 are disposed on the raised portions B on both side walls of the gate electrode 356. The source / drain region 353 is a region doped with a high concentration dopant.

  A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer 360 is disposed on the gate electrode 356 and the source / drain region 353. A fourth conductive line ML4 is disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer 370 is disposed on the fourth conductive line ML4.

  A modification of the third embodiment of the present invention will be described. FIG. 16 is a view for explaining a modification of the third embodiment of the present invention, and is a cross-sectional view taken along III-III ′ of FIG. 14.

  Referring to FIGS. 14 and 16, a substrate 300 is provided. A common source region 302 is disposed in the substrate 300. The substrate 300 includes a recess A. The recess A includes a bottom surface 303 and a first side wall 306. The substrate 300 includes a ridge B extending from the first sidewall 306. The upper surface of the raised portion B is parallel to the bottom surface 303 of the concave portion A. The raised portion B is defined by an insulating film 304 disposed on the substrate 300.

  The substrate 300 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. A peripheral circuit is disposed in the peripheral circuit region β.

  The cell region α of the substrate 300 will be described.

  The memory cells described with reference to FIG. 15 are disposed in the cell region α of the substrate 300.

  The peripheral circuit region β of the substrate 300 will be described.

  A peripheral circuit is disposed on the upper surface of the raised portion B of the peripheral circuit region β. A semiconductor film 352 is disposed on the upper surface of the insulating film 304. The semiconductor layer 352 includes other semiconductor materials including polysilicon, crystalline silicon, and single crystal silicon. A gate insulating film 354 is disposed on the semiconductor film 352. The gate insulating layer 354 includes a silicon oxide layer. The gate insulating film 354 includes the semiconductor film 352 formed by thermal oxidation. A gate electrode 356 is disposed on the gate insulating layer 354. The gate electrode 356 includes any one of doped polysilicon, metal, and metal silicide. Spacers 358 are disposed on both side walls of the gate electrode 356. Source / drain regions 353 are disposed in the semiconductor film 352 on both side walls of the gate electrode 356. The source / drain region 353 may be a region doped with a high concentration of dopant.

  A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer 360 is disposed on the gate electrode 356 and the source / drain region 353. A fourth conductive line ML4 is disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer 370 is disposed on the fourth conductive line ML4.

  A semiconductor device according to another modification of the third embodiment of the present invention will be described. FIG. 17 is a view for explaining another modified example of the third embodiment of the present invention, and is a cross-sectional view taken along the line III-III ′ of FIG. 14.

  14 and 17, a substrate 301 is provided. A common source region 302 is disposed in the substrate 301. The substrate 301 includes a recess A. The recess A includes a bottom surface 303 and a first side wall 306. The first side wall 306 is inclined to the bottom surface 303 of the recess A. For example, the first side wall 305 may have an angle of 90 ° to 130 ° with respect to the bottom surface 303. The substrate 301 includes a raised portion B extending from the first side wall 306. The upper surface of the raised portion B is parallel to the bottom surface 303 of the concave portion A. The recesses and ridges of the substrate are defined through an etching process. In contrast, as described with reference to FIG. 16, the raised portion B is defined by the insulating film 304 disposed on the substrate 301.

  The substrate 301 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. The peripheral circuit region β includes a peripheral circuit.

  The cell region α of the substrate 301 will be described.

  The memory cell described with reference to FIG. 15 is arranged in the recess A of the cell region α. Contact extensions CT of the conductive patterns GSL, WL1 to WL4, and SSL have a slope inclined with respect to the bottom surface 303. The angle formed between the contact extension CT of the conductive patterns GSL, WL1 to WL4, and SSL and the bottom surface 303 may be the same as the angle formed by the first sidewall 306 with respect to the bottom surface 303.

  The peripheral circuit region β of the substrate 301 will be described.

  The peripheral circuit described with reference to FIG. 15 is disposed in the peripheral circuit region β of the substrate 301. On the other hand, as described above, when the substrate is the substrate described with reference to FIG. 16, the semiconductor film 352 is added.

  A semiconductor device according to a fourth embodiment of the present invention will be described. 18 is a plan view for explaining a semiconductor device according to the fourth embodiment of the present invention. FIG. 19 is a cross-sectional view taken along the line IV-IV ′ of FIG.

  Referring to FIGS. 18 and 19, a substrate 401 is provided. The substrate 401 is a semiconductor substrate. The substrate 401 includes a well. The well includes a first conductivity type dopant. A common source region 402 is disposed in the substrate 401. The common source region 402 is disposed in a plate form in the cell region of the substrate 401. The common source region 402 may include a high concentration of dopant. The dopant included in the common source region 402 may have a second conductivity type different from the dopant included in the well. For example, when the well includes a p-type dopant, the common source region 402 includes a high concentration of n-type dopant.

  The substrate 401 includes a recess A. The recess A includes a bottom surface 403 and a first side wall 406. The substrate 401 includes a ridge B extending from the first side wall 406. The upper surface of the raised portion B is parallel to the bottom surface 403 of the recessed portion A. The recessed portion A and the raised portion B are formed by etching a portion where the recessed portion A of the semiconductor substrate is disposed, and leaving a portion where the raised portion B is disposed. In this case, the substrate 401 is an integral substrate.

  The substrate 401 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. The cell region α includes the concave portion A and the raised portion B. A peripheral circuit is disposed in the peripheral circuit region β. The peripheral circuit region β includes the raised portion B.

  The cell region α of the substrate 401 will be described.

  Conductive patterns GSL, WL1 to WL4, SSL spaced apart from each other are disposed on the concave portion A of the cell region α of the substrate 401. The conductive patterns GSL, WL1 to WL4, and SSL include a ground selection line GSL, word lines WL1 to WL4, and a string selection line SSL that are sequentially stacked on the recess A of the substrate 401. The conductive patterns GSL, WL1 to WL4, and SSL are spaced apart from each other with the inter-gate insulating films 410 to 414 interposed therebetween. For example, the ground selection line GSL, the first inter-gate insulating film 410, the first word line WL1, the second inter-gate insulating film 411, the second word line WL2, the third inter-gate insulating film 412, the third word line WL3, A fourth inter-gate insulating film 413, a fourth word line WL4, a fifth inter-gate insulating film 414, and a string selection line SSL are sequentially stacked.

  A string selection insulating layer 415 is disposed on the string selection line SSL. The insulating films 410 to 414 include a bottom portion on the bottom surface 403 of the concave portion A of the substrate 401 and a side wall portion extending from the bottom portion onto the first side wall 405. The conductive patterns GSL, WL1 to WL4, and SSL may have a line shape extending in the first direction. The first direction is a direction of IV-IV ′.

  The conductive patterns GSL, WL1 to WL4, and SSL include a bottom portion BP disposed on the bottom surface 403 of the recess A. The length of the bottom BP becomes shorter as the distance from the recess A of the substrate 401 increases. The bottom BP is parallel to the bottom surface 403. The bottom portion BP is parallel to the upper surface of the raised portion B.

  The conductive patterns GSL, WL1 to WL4, and SSL include a contact extension CT that extends from the one end of the bottom BP to the first sidewall 406. An extension line of the contact extension CT intersects the bottom surface 403. An extension line of the contact extension CT may intersect the bottom surface 403 at a right angle. The contact extension CT decreases in length as the distance from the recess A of the substrate 401 increases. The upper surface of the contact extension CT is flush with the upper surface of the raised portion B. An angle between the contact extension CT and the bottom BP may be 90 °.

  Conductive plugs are disposed on the contact extensions CT of the word lines WL1 to WL4. The conductive plug may be a word line contact plug CP. Each of the word lines WL1 to WL4 is electrically connected to the word line contact plug CP. The word line contact plug CP penetrates the first interlayer insulating layer 480. A first conductive line ML1 is disposed on the word line contact plug CP and the first interlayer insulating layer 480. The word line contact plug CP is electrically connected to the first conductive line ML1. The first conductive line ML1 extends in a second direction that intersects the first direction. The first conductive line ML1 is electrically connected to the word lines WL1 to WL4 through the word line contact plug CP. In contrast, the first conductive line ML1 may be directly connected to the word lines WL1 to WL4. A second interlayer insulating layer 490 is disposed to cover the first conductive line ML1. The first interlayer insulating layer 480 and the second interlayer insulating layer 490 may include the same material.

  A conductive plug is disposed on the contact extension CT of the ground selection line GSL. The conductive plug may be a ground selection contact plug GCP. The ground selection line GSL is electrically connected to the ground selection contact plug GCP. The ground selection contact plug GCP penetrates the first interlayer insulating film 480. A second conductive line ML2 is disposed on the ground selection contact plug GCP and the first interlayer insulating layer 480. The ground selection contact plug GCP is electrically connected to the second conductive line ML2. The second conductive line ML2 extends in the second direction. The second conductive line ML2 is electrically connected to the ground selection line GSL through the ground selection contact plug GCP. In contrast, the second conductive line ML2 may be directly connected to the ground selection line GSL. The second interlayer insulating layer 490 covers the second conductive line ML2.

  A conductive plug is disposed on the contact extension CT of the string selection line SSL. The conductive plug may be a string selection contact plug SCP. The string selection line SSL is electrically connected to the string selection contact plug SCP. The string selection contact plug SCP penetrates the first interlayer insulating film 480 and the second interlayer insulating film 490. A third conductive line ML3 is disposed on the string selection contact plug SCP and the first interlayer insulating layer 480. The string selection contact plug SSL is electrically connected to the third conductive line ML3. The third conductive line ML3 extends in the first direction.

  An active part AP extending upward from the bottom surface 403 of the recess A of the substrate 401 is disposed. The active part AP extends perpendicularly to the substrate 401. The active part AP penetrates the conductive patterns GSL, WL1 to WL4, SSL. In contrast, as described with reference to FIG. 13, the active part AP faces the side surfaces of the conductive patterns GSL, WL1 to WL4, and SSL. One end of the active part AP is electrically connected to the common source region 402. A drain region 423 is disposed at the other end of the active part AP. The drain region D may be a region doped with a high concentration of dopant. The active part AP includes a single crystal semiconductor.

  A bit line contact plug BLCP is disposed on the drain region D of the active part AP. The bit line contact plug BLCP is electrically connected to the drain region 423 and penetrates the first interlayer insulating film 480 and the second interlayer insulating film 490. A bit line BL is disposed on the bit line contact plug BLCP. The bit line BL is connected to the drain region 423 of the active part AP through the bit line contact plug BLCP. In contrast, the bit line BL may be directly connected to the drain region 423. The bit line BL is extended in the second direction. The bit line BL intersects the string selection line SSL.

  An information storage layer 440 is interposed between the sidewall of the active part AP and the conductive patterns GSL, WL1 to WL4, SSL. The information storage layer 440 is disposed between the conductive patterns GSL, WL1 to WL4, SSL and a sidewall of the active part AP. The information storage layer 440 is disposed between the conductive patterns GSL, WL1-WL4, SSL and the insulating layers 410-415.

  The information storage film 420 according to the fourth embodiment of the present invention may be the information storage film described with reference to FIG.

  The peripheral circuit region β will be described.

  A peripheral circuit is disposed on the upper surface of the raised portion B of the peripheral circuit region β. A gate insulating layer 474 is disposed on the upper surface of the raised portion B. The gate insulating layer 474 includes a silicon oxide layer. The gate insulating layer 474 may be formed by thermally oxidizing the semiconductor substrate 401. A gate electrode 476 is disposed on the gate insulating layer 474. The gate electrode 476 includes any one of doped polysilicon, metal, and metal silicide. Gate spacers 478 are disposed on both side walls of the gate electrode 476. Source / drain regions 473 are disposed on the raised portions B on both side walls of the gate electrode 476. The source / drain region 473 may be a region doped with a high concentration dopant.

  A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer 480 is disposed on the gate electrode 476 and the source / drain region 473. A fourth conductive line ML4 is disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer 490 is disposed on the fourth conductive line ML4.

  A modification of the fourth embodiment of the present invention will be described. FIG. 20 is a view for explaining a modification of the fourth embodiment of the present invention, and is a cross-sectional view taken along the line IV-IV ′ of FIG. 18.

  Referring to FIGS. 18 and 20, a substrate 400 is provided. A common source region 402 is disposed in the substrate 400. The substrate 400 includes a recess A. The recess A includes a bottom surface 403 and a first side wall 405. The substrate 400 includes a ridge B extending from the first side wall 405. The upper surface of the raised portion B is parallel to the bottom surface 403 of the recessed portion A. The raised portion B is defined by an insulating film 404 disposed on the substrate 400.

  The substrate 400 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. A peripheral circuit is disposed in the peripheral circuit region β.

  The cell region α of the substrate 400 will be described.

  The memory cell described with reference to FIG. 19 is arranged in the recess A of the cell region α.

  The peripheral circuit region β of the substrate 400 will be described.

  A peripheral circuit is disposed on the upper surface of the raised portion B of the peripheral circuit region β. A semiconductor film 472 is disposed on the upper surface of the insulating film 404. The semiconductor layer 472 may be other semiconductor materials including polysilicon, crystalline silicon, and single crystal silicon. A gate insulating layer 474 is disposed on the semiconductor layer 472. The gate insulating layer 474 includes a silicon oxide layer. The gate insulating layer 474 includes the semiconductor layer 472 formed by thermal oxidation. A gate electrode 476 is disposed on the gate insulating layer 474. The gate electrode 476 includes any one of doped polysilicon, metal, and metal silicide. Spacers 478 are disposed on both side walls of the gate electrode 476. Source / drain regions 473 are disposed in the semiconductor film 472 on both side walls of the gate electrode 476. The source / drain region 473 may be a region doped with a high concentration dopant.

  A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer 480 is disposed on the gate electrode 476 and the source / drain region 473. A fourth conductive line ML4 is disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer 490 is disposed on the fourth conductive line ML4.

  A semiconductor device according to another modification of the fourth embodiment of the present invention will be described. FIG. 21 is a view for explaining another modified example of the fourth embodiment of the present invention, and is a cross-sectional view taken along the line IV-IV ′ of FIG. 18.

  18 and 21, a substrate 401 is provided. A common source region 402 is disposed in the substrate 401. The substrate 401 includes a recess A. The recess A includes a bottom surface 403 and a first side wall 405. The first side wall 405 is inclined to the bottom surface 403 of the recess A. For example, the first side wall 405 may have an angle of 90 ° to 130 ° with respect to the bottom surface 403. The substrate 401 includes a raised portion B extending from the first side wall 405. The upper surface of the raised portion B is parallel to the bottom surface 403 of the recessed portion A. The recesses and ridges of the substrate are defined through an etching process. In contrast, as described with reference to FIG. 20, the raised portion B is defined by the insulating film 404 disposed on the substrate 401.

  The substrate 401 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. The peripheral circuit region β includes a peripheral circuit.

  The cell region α of the substrate 401 will be described.

  The memory cells described with reference to FIG. 19 are arranged in the cell region α. The contact extensions CT of the conductive patterns GSL, WL1 to WL4, and SSL have a slope inclined with respect to the bottom surface 403. The angle formed by the contact extension CT of the conductive patterns GSL, WL1 to WL4, and SSL and the bottom surface 403 may be the same as the angle formed by the first side wall 406 and the bottom surface 403.

  The peripheral circuit region β of the substrate 401 will be described.

  The peripheral circuit described with reference to FIG. 19 is disposed in the peripheral circuit region β of the substrate 401. Unlike this, as described above, when the substrate is the substrate described with reference to FIG. 20, the semiconductor film 472 is added.

  A semiconductor device according to a fifth embodiment of the present invention will be described. 22 and 23 are plan views for explaining a semiconductor device according to the fifth embodiment of the present invention, and FIG. 24 is a cross-sectional view taken along line VV ′ of FIGS. 22 and 23. .

  With reference to FIGS. 22, 23, and 24, a substrate 501 is provided. The substrate 501 is a semiconductor substrate. The substrate 501 includes a well. The well includes a first conductivity type dopant. A common source region 502 is disposed in the substrate 501. The common source region 502 is disposed in a plate form in the cell region of the substrate 501. The common source region 502 may include a high concentration of dopant. The dopant included in the common source region 502 may have a second conductivity type different from that of the dopant included in the well. For example, when the well includes a p-type dopant, the common source region 502 includes a high concentration of n-type dopant.

  The substrate 501 includes a recess A. The recess A includes a first side wall 505 and a second side wall 506 that face the bottom surface 503. The substrate 501 includes a raised portion B extending from the first side wall 505 and the second side wall 506. The upper surface of the raised portion B is parallel to the bottom surface 503 of the recessed portion A. The recessed portion A and the raised portion B are formed by etching a portion where the recessed portion A of the semiconductor substrate is disposed, and leaving a portion where the raised portion B is disposed. In this case, the substrate 501 is an integral substrate.

  The substrate 501 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. The cell region α includes the concave portion A and the raised portion B. A peripheral circuit is disposed in the peripheral circuit region β. The peripheral circuit region β includes the raised portion B.

The cell region α of the substrate 501 will be described.
The cell region α includes a first contact region CR1 adjacent to the first sidewall 505 of the recess A and a second contact region CR2 adjacent to the second sidewall 506. A cell array region CAR is disposed between the first contact region CR1 and the second contact region CR2. The first contact region CR1 and the second contact region CR2 are spaced apart from each other across the cell array region CAR.

  Conductive patterns GSL, WL1 to WL4, SSL spaced apart from each other are disposed on the substrate 501. The conductive patterns GSL, WL1 to WL4, and SSL include a ground selection line GSL, word lines WL1 to WL4, and a string selection line SSL that are sequentially stacked on the recess A of the substrate 501. The conductive patterns GSL, WL1-WL4, SSL are spaced apart from each other with inter-gate insulating films 511-515 interposed therebetween. For example, the ground selection line GSL, the first inter-gate insulating film 511, the first word line WL1, the second inter-gate insulating film 512, the second word line WL2, the third inter-gate insulating film 513, the third word line WL3, The fourth inter-gate insulating film 514, the fourth word line WL4, the fifth inter-gate insulating film 515, and the string selection line SSL are sequentially stacked. The insulating films 510 to 516 include a bottom portion on the bottom surface 503 of the recess A of the substrate 501 and side wall portions extending from the bottom portion to the first side wall 505 and the second side wall 506.

  A ground selection insulating film 510 is disposed between the bottom surface 503 of the recess A of the substrate 501, first and second side walls 505 and 506, and the ground selection line GSL. A string selection insulating layer 516 is disposed on the string selection line SSL. The word lines WL1 to WL4 may have a flat plate shape parallel to the recess A.

  The conductive patterns GSL, WL1 to WL4, and SSL include a bottom portion BP disposed on the bottom surface 503 of the recess A. The length of the bottom portion BP becomes shorter as the distance from the concave portion A of the substrate 501 increases. The bottom BP is parallel to the bottom surface 503. The bottom portion BP is parallel to the upper surface of the raised portion B.

  The conductive patterns GSL, WL1-WL4, and SSL include a contact extension CT that extends from one end of the bottom BP to one of the first sidewall 505 and the second sidewall 506. A contact region in which a contact extension of any one of the conductive patterns GSL, WL1 to WL4, SSL is disposed; and a contact extension of another conductive pattern adjacent to the one of the conductive patterns. The arranged contact regions can be different. For example, when the contact extension CT of the ground selection line GSL is disposed in the first contact region CR1, the contact extension CT of the first word line WL1 adjacent to the ground selection line GSL is the second contact region CR2. Placed in. An extension line of the contact extension CT intersects the bottom surface 503. An extension line of the contact extension CT may intersect the bottom surface 503 at a right angle. The contact extension CT decreases in length as the distance from the recess A of the substrate 501 increases. The upper surface of the contact extension CT is flush with the upper surface of the raised portion B. An angle between the contact extension CT and the bottom BP may be 90 °.

  The conductive patterns GSL, WL1 to WL4, SSL are extended from the other end of the bottom portion BP on the bottom surface 503 to the other one side of the first side surface 505 and the second side surface 506 (extended over). ) Includes dummy extension DCT. A contact region where a dummy extension of any one of the conductive patterns GSL, WL1 to WL4, SSL is disposed, and a dummy extension of another conductive pattern adjacent to any one of the conductive patterns The arranged contact regions can be different. For example, when the dummy extension DCT of the string selection line SSL is disposed in the first contact region CR1, the dummy extension DCT of the fourth word line WL4 adjacent to the string selection line SSL is the second contact region. Located in CR2. Each of the conductive patterns GSL, WL1 to WL4, SSL includes one contact extension CT and one dummy extension DCT. In one conductive pattern among the conductive patterns GSL, WL1 to WL4, and SSL, the length of the dummy extension DCT may be shorter than the length of the contact extension CT. The contact extension CT is disposed between the adjacent dummy extensions DCT. The contact extension CT adjacent to the dummy extension DCT is separated by the side wall of the insulating film interposed therebetween.

  A dummy insulating pattern 524 is disposed on the dummy extension DCT. The upper surface of the dummy insulating pattern 524 is flush with the upper surface of the raised portion B. The upper surface of the dummy insulating pattern 524 is flush with the upper surface of the string selection insulating film 516. The side wall of the dummy insulating pattern 524 is flush with the side wall of the dummy extension DCT. The dummy insulating pattern 524 may include the same material as the insulating films 510 to 516.

  Conductive plugs are disposed on the contact extensions CT of the word lines WL1 to WL4. The conductive plug may be a word line contact plug CP. Each of the word lines WL1 to WL4 is electrically connected to the word line contact plug CP. The word line contact plug CP may be wider than the upper surface of the contact extension CT of the word lines WL1 to WL4. The word line contact plug CP may be wider than a width between the contact extension CT of the word lines WL1 to WL4 and the adjacent dummy extension DCT. The word line contact plug CP penetrates the first interlayer insulating layer 560. A first conductive line ML1 is disposed on the word line contact plug CP and the first interlayer insulating layer 560. The word line contact plug CP is electrically connected to the first conductive line ML1. A portion of the first conductive line ML1 extends in the first direction. The remaining part of the first conductive line ML1 extends in a second direction opposite to the first direction. For example, the first conductive lines ML1 connected to the word lines WL2 and WL4 disposed on the odd layers from the substrate 501 extend in the first direction, and the word lines WL1 and WL3 disposed on the even layers from the substrate 501. The first conductive line ML1 connected to is extended in the second direction. The first direction is a V-V 'direction. The first conductive line ML1 is electrically connected to the word lines WL1 to WL4 through the word line contact plug CP. In contrast, the first conductive line ML1 may be directly connected to the word lines WL1 to WL4. A second interlayer insulating layer 570 is disposed to cover the first conductive line ML1. The first interlayer insulating layer 560 and the second interlayer insulating layer 570 may include the same material.

  A conductive plug is disposed on the contact extension CT of the ground selection line GSL. The conductive plug may be a ground selection contact plug GCP. The ground selection line GSL is electrically connected to the ground selection contact plug GCP. The width of the ground selection contact plug GCP may be wider than the width of the upper surface of the contact extension CT of the ground selection line GSL. The ground selection contact plug GCP penetrates the first interlayer insulating layer 560. A second conductive line ML2 is disposed on the ground selection contact plug GCP and the first interlayer insulating layer 560. The ground selection contact plug GCP is electrically connected to the second conductive line ML2. The second conductive line ML2 extends in the first direction. The second conductive line ML2 is electrically connected to the ground selection line GSL through the ground selection contact plug GCP. In contrast, the second conductive line ML2 may be directly connected to the ground selection line GSL. The second interlayer insulating layer 570 covers the second conductive line ML2.

  A conductive plug is disposed on the contact extension CT of the string selection line SSL. The conductive plug may be a string selection contact plug SCP. The string selection line SSL is electrically connected to the string selection contact plug SCP. The width of the string selection contact plug SCP may be wider than the width of the upper surface of the contact extension CT of the string selection line SSL. The string selection contact plug SCP penetrates the first interlayer insulating layer 560 and the second interlayer insulating layer 570. A third conductive line ML3 is disposed on the string selection contact plug SCP and the first interlayer insulating layer 560. The string selection contact plug SSL is electrically connected to the third conductive line ML3. The third conductive line ML3 extends in the second direction. The second interlayer insulating layer 570 covers the third conductive line ML3. Referring to FIG. 20, a plurality of string selection lines SSL are disposed in the recess A. The third conductive lines ML3 of the string selection lines SSL adjacent to each other are extended in the other direction.

  The conductive lines ML2, ML1, and ML3 are divided and extended in the first direction and the second direction with the cell array region CAR interposed therebetween. For example, the conductive lines ML2 and ML1 connected to the conductive patterns GSL, WL2, and WL4 disposed in the first contact region CR1 in the first contact region CR1 are extended in the first direction, and the contact extension CT is in the second direction. Conductive lines ML1 and ML3 connected to the conductive patterns WL1, WL3, and SSL disposed in the contact region CR2 extend in the second direction.

  An active portion AP extending upward from the bottom surface 503 of the recess A is disposed. The active part AP extends perpendicularly to the substrate 501. The active part AP penetrates the conductive patterns GSL, WL1 to WL4, SSL, and one end of the active part AP is electrically connected to the common source region 502. A drain region D is disposed at the other end of the active part AP. The drain region D may be a region doped with a high concentration of dopant. The active part AP includes a single crystal semiconductor.

  A bit line contact plug BLCP is disposed on the drain region D of the active part AP. The bit line contact plug BLCP is electrically connected to the drain region D and penetrates the first interlayer insulating layer 560. A bit line BL is disposed on the bit line contact plug BLCP. The bit line BL is connected to the drain region D of the active part AP through the bit line contact plug BLCP. In contrast, the bit line BL may be directly connected to the drain region D. The bit line BL extends in a third direction that intersects the first direction and the second direction. The third direction may intersect the first and second directions at a right angle. The bit line BL intersects the string selection line SSL.

An information storage layer 532 is interposed between the sidewall of the active part AP and the conductive patterns GSL, WL1 to WL4, SSL. The information storage layer 532 is disposed in a cylinder type that penetrates the conductive patterns GSL, WL1 to WL4, and SSL. The information storage layer 532 is disposed so as to surround the active part AP. The information storage layer 532 is disposed between the sidewall of the active part AP and the conductive patterns GSL, WL1-WL4, SSL and the insulating layers 510-516.
The information storage film 532 according to the fifth embodiment of the present invention may be the information storage film described with reference to FIG.

  The peripheral circuit region β of the substrate 501 will be described.

  A peripheral circuit is disposed on the upper surface of the raised portion B of the peripheral circuit region β. A gate insulating layer 554 is disposed on the upper surface of the raised portion B. The gate insulating layer 554 includes a silicon oxide layer. The gate insulating layer 554 may be formed by thermally oxidizing the upper surface of the raised portion B. A gate electrode 556 is disposed on the gate insulating layer 554. The gate electrode 556 includes any one of doped polysilicon, metal, and metal silicide. Spacers 558 are disposed on both side walls of the gate electrode 556. Source / drain regions 553 are disposed on the raised portions B on both side walls of the gate electrode 556. The source / drain region 553 may be a region doped with a high concentration dopant.

  A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer 560 is disposed on the gate electrode 556 and the source / drain region 553. A fourth conductive line ML4 is disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer 570 is disposed on the fourth conductive line ML4.

  A modification of the fifth embodiment of the present invention will be described. FIG. 25 is a view for explaining a modification of the fifth embodiment of the present invention, and is a cross-sectional view taken along the line V-V ′ in FIGS. 22 and 23.

  Referring to FIGS. 25, 22 and 23, a substrate 500 is provided. A common source region 502 is disposed in the substrate 500. The substrate 500 includes a recess A. The recess A includes a first side wall 505 and a second side wall 506 that face the bottom surface 503. The substrate 500 includes a ridge B extending from the first and second sidewalls 505 and 506. The upper surface of the raised portion B is parallel to the bottom surface 503 of the recessed portion A. The raised portion B is defined by an insulating film 504 disposed on the substrate 500.

  The substrate 501 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. A peripheral circuit is disposed in the peripheral circuit region β.

  The cell region α of the substrate 500 will be described.

  The cell region α includes a first contact region CR1 adjacent to the first sidewall 505 of the recess A and a second contact region CR2 adjacent to the second sidewall 506. The memory cell described with reference to FIG. 24 is disposed in the cell region α of the substrate 500.

  The peripheral circuit region β of the substrate 500 will be described.

  A peripheral circuit is disposed on the upper surface of the raised portion B of the peripheral circuit region β. A semiconductor film 552 is disposed on the upper surface of the insulating film 504. The semiconductor layer 552 may be other semiconductor materials including polysilicon, crystalline silicon, and single crystal silicon. A gate insulating layer 554 is disposed on the semiconductor layer 552. The gate insulating layer 554 includes a silicon oxide layer. The gate insulating film 554 includes the semiconductor film 552 formed by thermal oxidation. A gate electrode 556 is disposed on the gate insulating layer 554. The gate electrode 556 includes any one of doped polysilicon, metal, and metal silicide. Spacers 558 are disposed on both side walls of the gate electrode 556. Source / drain regions 553 are disposed in the semiconductor film 552 on both side walls of the gate electrode 556. The source / drain region 553 may be a region doped with a high concentration dopant.

  A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer 560 is disposed on the gate electrode 556 and the source / drain region 553. A fourth conductive line ML4 is disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer 570 is disposed on the fourth conductive line ML4.

  A semiconductor device according to another modification of the fifth embodiment of the present invention will be described. FIG. 26 is a view for explaining another modification of the fifth embodiment of the present invention, and is a cross-sectional view taken along the line V-V ′ of FIGS. 22 and 23.

  Referring to FIGS. 22, 23, and 26, a substrate 501 is provided. A common source region 502 is disposed in the substrate 501. The substrate 501 includes a recess A. The recess A includes a first side wall 505 and a second side wall 506 that face the bottom surface 503. One of the first side wall 505 and the second side wall 506 is inclined toward the bottom surface 503 of the recess A. For example, the first side wall 505 and the second side wall 506 may have an angle of 50 ° to 90 ° with respect to the bottom surface 503. The slope of the first side wall 505 with respect to the bottom surface 503 and the slope of the second side wall 506 with respect to the bottom surface 503 may be the same. In contrast, the slope of the first side wall 505 with respect to the bottom surface 503 may be different from the slope of the second side wall 506 with respect to the bottom surface 503. The substrate 501 includes a raised portion B extending from the first side wall 505 and the second side wall 506. The upper surface of the raised portion B is parallel to the bottom surface 503 of the recessed portion A. The concave portion A and the raised portion B of the substrate are defined through an etching process. In contrast, as described with reference to FIG. 25, the raised portion B is defined by the insulating film 504 disposed on the substrate 500.

  The substrate 501 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. The peripheral circuit region β includes a peripheral circuit.

  The cell region α of the substrate 501 will be described.

  The cell region α includes a first contact region CR1 adjacent to the first sidewall 505 of the recess A and a second contact region CR2 adjacent to the second sidewall 506. The memory cell described with reference to FIG. 24 is arranged. In one of the conductive patterns GSL, WL1 to WL4, and SSL, the contact extension CT and the dummy extension DCT have a slope inclined with respect to the bottom BP.

  The angle formed by the side wall adjacent to the contact region where the contact extension CT is disposed and the bottom surface 503 may be the same as the angle formed by the contact extension CT and the bottom BP. Taking the first word line WL1 as an example, the slope of the contact extension CT with respect to the bottom BP may be the same as the slope of the second sidewall 506 with respect to the bottom surface 503. When the slopes of the first sidewall 505 and the second sidewall 506 with respect to the bottom surface 503 are different, the slope of the contact extension CT with respect to the bottom BP in one conductive pattern is determined by the dummy extension DCT. It can be different from the slope it has for the bottom BP.

  The peripheral circuit region β of the substrate 501 will be described.

  The peripheral circuit described with reference to FIG. 24 is disposed in the peripheral circuit region β of the substrate 501. On the other hand, as described above, when the substrate is the substrate described with reference to FIG. 25, the semiconductor film 552 is added.

  A formation method according to the fifth embodiment of the present invention will be described. 27 to 34 are sectional views for explaining a forming method according to the fifth embodiment of the present invention.

  Referring to FIG. 27, a substrate 501 is provided. The substrate 501 includes a recess A. The recess A includes a bottom surface 503, a first side wall 505 and a second side wall 506 that face each other. The substrate 501 includes a raised portion B extending from the first side wall 505 and the second side wall 506. The upper surface of the raised portion B is parallel to the bottom surface 503 of the recessed portion A. Forming the recess A and the raised portion B of the substrate 501 includes etching the portion of the semiconductor substrate where the recess A is formed, and leaving the portion of the semiconductor substrate where the raised portion B is formed.

  The substrate 501 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. The cell region α includes the concave portion A and the raised portion B. The peripheral circuit region β includes a peripheral circuit. The peripheral circuit region β includes the raised portion B.

  The cell region α includes a first contact region CR1 adjacent to the first sidewall 505 of the recess A and a second contact region CR2 adjacent to the second sidewall 506. A cell array region CAR is disposed between the first contact region CR1 and the second contact region CR2. The first contact region CR1 and the second contact region CR2 are spaced apart from each other across the cell array region CAR.

  The substrate 501 may be a single crystal semiconductor (for example, a P-type silicon wafer). The substrate 501 includes a well. The well is formed by implanting a dopant into the substrate 501. The dopant is implanted into the substrate 501 by a doping process including ion implantation or plasma implantation. A common source region 502 is provided on the upper surface of the substrate 501. The common source region 502 is formed by doping a dopant in the well. The common source region 502 may include a dopant having a conductivity type different from that of the well. For example, the well includes a p-type dopant and the common source region 502 includes an n-type dopant.

  Referring to FIG. 28, conductive patterns GSL, WL1 to WL4, SSL and insulating films 510 to 516 are alternately formed on the recess A of the substrate 501. For example, the ground selection insulating film 510, the ground selection line GSL, the first inter-gate insulating film 511, the first word line WL1, the second inter-gate insulating film 512, the second word line WL2, and the third gate are formed on the substrate 501. The insulating film 513, the third word line WL3, the fourth inter-gate insulating film 514, the fourth word line WL4, the fifth inter-gate insulating film 515, the string selection line SSL, and the string selection insulating film 516 are sequentially deposited. The conductive patterns GSL, WL1 to WL4, SSL and the insulating films 510 to 516 are also formed on the upper surface of the raised portion B. The conductive patterns GSL, WL1-WL4, SSL include a metal or a polycrystalline semiconductor material. The insulating films 510 to 516 include a silicon oxide film.

  An etching process is performed using the upper surface of the raised portion B as an etching stop layer. The planarization process is performed by any one of etch back or chemical mechanical polishing (CMP). Through the etching process, the conductive patterns GSL, WL1 to WL4, SSL and the insulating films 510 to 516 formed on the upper surface of the raised portion B are removed.

  The conductive patterns GSL, WL1 to WL4, and SSL include a bottom portion BP disposed on the bottom surface 503 of the recess A. The conductive patterns GSL, WL1-WL4, and SSL include a contact extension CT that extends from one end of the bottom BP to one of the first sidewall 505 and the second sidewall 506. A contact region in which a contact extension of any one of the conductive patterns GSL, WL1 to WL4, SSL is disposed; and a contact extension of another conductive pattern adjacent to the one of the conductive patterns. The arranged contact regions can be different. The exposed upper surface of the contact extension CT is flush with the upper surface of the raised portion B.

  The conductive patterns GSL, WL1 to WL4, SSL are extended from the other end of the bottom portion BP on the bottom surface 503 to the other one side of the first side surface 505 and the second side surface 506 (extended over). ) Includes dummy extension DCT. A contact region where a dummy extension of any one of the conductive patterns GSL, WL1 to WL4, SSL is disposed, and a dummy extension of a conductive pattern adjacent to any one of the conductive patterns is disposed. The contact area can be different. Each of the conductive patterns GSL, WL1 to WL4, SSL includes one contact extension CT and one dummy extension DCT.

  A mask pattern 520 is formed to cover the exposed upper surface of the contact extension CT. The mask pattern 520 exposes the dummy extension DCT. Forming the mask pattern 520 includes forming a mask film on the substrate 501 and patterning the mask film. The mask pattern 520 includes a material having an etching selectivity with respect to the conductive patterns GSL, WL1 to WL4, SSL and the insulating layers 510 to 516. For example, the mask pattern 520 includes a silicon nitride film or a photoresist pattern.

  Referring to FIG. 29, a portion of the dummy extension DCT exposed by the mask pattern 520 is etched using the mask pattern 520 as an etching mask. A portion of the dummy extension DCT is etched to form a dummy recess 522. The length of the dummy extension DCT may be shorter than the length of the contact extension CT. A portion of the sidewalls of the insulating films 510 to 516 is exposed by the dummy recess 522. Etching the dummy extension DCT may use an etching recipe having an etching rate higher than that of the mask pattern 520 and the insulating films 510 to 516 with respect to the conductive patterns GSL, WL1 to WL4 and SSL. The mask pattern 520 is removed.

  The string selection line SSL is patterned and formed in a line shape extending in the first direction. The first direction is a V-V 'direction.

  Referring to FIG. 30, a dummy insulating pattern 524 is formed to bury the dummy recess 522. The dummy insulating pattern 524 is formed by forming a dummy insulating film on the substrate 501 and performing a planarization process using the upper surface of the raised portion B or the upper surface of the string selection insulating film 516 as an etching stop film. Including doing. The upper surface of the dummy insulating pattern 524 is flush with the upper surface of the raised portion B. The upper surface of the dummy insulating pattern 524 is flush with the upper surface of the string selection insulating film 516. The side walls of the dummy insulating pattern 524 are flush with the side walls of the insulating films 510 to 516.

  The conductive patterns GSL, WL1 to WL4, SSL and the insulating films 510 to 516 are etched to form an active opening 530 that exposes the common source region 502 of the bottom surface 503 of the recess A. The active opening 530 exposes the sidewalls of the conductive patterns GSL, WL1 to WL4 and SSL and the sidewalls of the insulating layers 510 to 516. Etching the conductive patterns GSL, WL1 to WL4, SSL and the insulating films 510 to 516 may use an anisotropic etching process.

  Referring to FIG. 31, an information storage layer 532 is formed to cover the conductive patterns GSL, WL1 to WL4, SSL, and the insulating layers 510 to 516 exposed through the active openings 530. The information storage layer 532 covers the common source region 502 exposed by the active opening 530. The information storage film 532 is formed on the upper surface of the raised portion B, the upper surface of the string selection insulating film 516, the side walls of the insulating films 510 to 515, the upper surface of the dummy insulating pattern 524, and the upper surface of the contact extension CT. It is formed.

  Referring to FIG. 6 again, a method for forming the information storage film 532 will be described. Forming the information storage layer 532 includes forming a blocking layer 134 in the active opening 530, forming a charge storage layer 135 that covers the blocking layer 134, and a tunnel insulating layer 136 that covers the charge storage layer 135. Forming.

  Referring back to FIG. 31, a spacer 534 is formed in the active opening 530. The spacer 534 covers an information storage layer 532 formed on the sidewall of the active opening 530 and a part of the information storage layer 532 formed on the bottom surface of the active opening 530. Forming the spacer 534 includes forming a spacer film on the substrate 501 and etching the bottom portion with anisotropy. The spacer 534 includes silicon. The spacer 534 includes a material having an etching selectivity with respect to the information storage layer 532.

  Referring to FIG. 32, the information storage layer 532 exposed by the spacer 534 is etched using the spacer 534 as an etching mask. The information storage layer 532 is etched to expose the surface of the substrate 503. An information storage film formed on the upper surface of the raised portion B, the upper surface of the string selection insulating film 516, the side walls of the insulating films 510 to 515, the upper surface of the dummy insulating pattern 524, and the upper surface of the contact extension CT. 532 is removed. The spacer 534 is removed or not removed and can be used as an active part. When the spacer 534 includes polysilicon, the spacer 534 is not removed and can be used as an active portion. In contrast, when the spacer 534 is an insulating material, the spacer 534 is removed, and a semiconductor material for forming an active portion is formed on the bottom and side walls of the opening.

  An active part AP that fills the active opening 530 is formed. The active part AP includes a single crystal semiconductor, but is not limited thereto. When the active part AP includes a single crystal semiconductor, the active part AP is formed by epitaxial growth used as a seed layer of the substrate 501. In contrast, the active part AP forms a polycrystalline or amorphous semiconductor film that fills the active opening 530 and then provides heat and / or laser to form the polycrystalline or amorphous semiconductor film. It can also be formed by phase transition. If the spacer 534 is not removed, the active part AP may include the same material as the spacer 534. The active part AP may be formed to fill the active opening 530 or may be formed into a cylinder type by removing a part of the active part AP that fills the active opening 530.

  A drain region D is formed on the active part AP. The drain region D is formed by doping the upper part of the active part AP. The drain region D may be a region containing a high concentration of a dopant having a conductivity type different from that of the well. For example, the drain region D includes a high concentration of n-type dopant. The drain region D may have a tubular pad shape.

  Referring to FIG. 33, a gate insulating layer 554 is formed on the upper surface of the raised portion B. Forming the gate insulating film 554 includes thermally oxidizing the semiconductor substrate 501. When the gate insulating film 554 is formed by a thermal oxidation process, an oxide film is formed on the upper surface of the contact extension CT, so that the recess A is covered before forming the gate insulating film 554. A mask layer that exposes the raised portion B is additionally formed. The mask layer may be an insulating film.

  The gate insulating layer 554 includes a silicon oxide layer. A gate electrode 556 is formed on the gate insulating layer 554. Source / drain regions 553 are formed in the semiconductor film 552 on both sides of the gate electrode 556. The source / drain region 553 is formed by implanting impurities into the semiconductor film 552.

  Referring to FIG. 34, gate spacers 558 are formed on both side walls of the gate electrode 556. A first interlayer insulating layer 560 is formed on the substrate 501. The first interlayer insulating layer 560 covers a peripheral circuit on the raised portion B. The first interlayer insulating layer 560 includes a silicon oxide layer.

  The first interlayer insulating layer 560 is etched so that the contact patterns CT, WL1 to WL4 of the conductive patterns GSL, the drain region D of the active part AP, and the upper surface of the gate electrode 556 of the peripheral circuit are respectively formed. An exposed contact opening 562, a bit line opening 564, and a peripheral circuit opening 566 are formed. At this time, an opening exposing the source / drain region of the peripheral circuit region β is formed. The first interlayer insulating layer 560 may be etched using an anisotropic etching process.

  As described above, when the gate insulating film 554 is formed by a thermal oxidation process and an oxide film is formed on the upper surface of the contact extension CT of the conductive patterns GSL, WL1 to WL4, SSL in the cell region α. In the process of etching the first interlayer insulating layer 560, the mask layer is etched to expose the contact extension CT. Unlike this, the gate insulating film 554 is formed by a thermal oxidation process, but a mask layer is not formed on the contact extension CT of the conductive patterns GSL, WL1 to WL4, and SSL, so that an oxide film is formed. In this case, in the process of etching the first interlayer insulating layer 560, the oxide layer may be etched.

  Referring to FIG. 24 again, contact plugs GCP, CP, a bit line contact plug BLCP, and a peripheral circuit contact plug PCP are formed to fill the contact opening 562, the bit line opening 564, and the peripheral circuit opening 566, respectively. The

  The ground selection contact plug GCP is electrically connected to the contact extension CT of the ground selection line GSL. The word line contact plug CP is electrically connected to the word lines WL1 to WL4. The contact plugs GCP and CP each include a material having higher conductivity than the conductive patterns GSL and WL1 to WL4. The peripheral circuit contact plug PCP is electrically connected to the gate electrode 556. The peripheral circuit contact plug PCP includes a material having higher conductivity than the gate electrode 556. For example, the contact plugs GCP and CP, the bit line contact plug BLCP, and the peripheral circuit contact plug PCP include tungsten.

  A second conductive line ML2 is formed on the ground selection contact plug GCP. A first conductive line ML1 is formed on the word line contact plug CP. A bit line BL is formed on the bit line contact plug BLCP. A fourth conductive line ML4 is formed on the peripheral circuit contact plug PCP. The formation of the second conductive line ML2, the first conductive line ML1, the bit line BL, and the fourth conductive line ML4 includes forming a conductive film on the first interlayer insulating film 560 and patterning the conductive film. .

  A second interlayer insulating layer 570 is formed to cover the second conductive line ML2, the first conductive line ML1, and the fourth conductive line ML4. The second interlayer insulating layer 570 may include the same material as the first interlayer insulating layer 560. A string selection contact plug SCP that penetrates through the second interlayer insulating layer 570 and fills an opening that exposes the contact extension CT of the string selection line SSL is formed. The string selection contact plug SCP includes a material having higher conductivity than the string selection line SSL. A third conductive line ML3 is formed on the string selection contact plug SCP. Forming the third conductive line ML3 includes forming a conductive film on the second interlayer insulating film 570 and patterning it. Thus, the semiconductor element described with reference to FIG. 24 is provided.

  A method for forming a semiconductor device according to a modification of the fifth embodiment of the present invention described with reference to FIG. 25 will be described.

  Referring to FIG. 25, in the method of forming a semiconductor device described with reference to FIGS. 27 to 34 and FIG. 24, the recess A and the raised portion B form an insulating film 504 on the substrate 500, and the recess A is disposed. The insulating film on the portion of the substrate 500 to be formed is etched to leave the insulating film 504 on the portion of the substrate 500 where the raised portion B is disposed.

  A semiconductor film 552 is formed on the raised portion B of the peripheral circuit region β. Forming the semiconductor film 652 includes bonding the semiconductor film 552 on the upper surface of the raised portion B or growing the semiconductor film 552. The semiconductor layer 552 may include silicon. A gate insulating layer 554 is formed on the semiconductor layer 552. Thereafter, the peripheral circuit is formed by the peripheral circuit forming method described with reference to FIGS.

  A method for forming a semiconductor device according to another modification of the fifth embodiment of the present invention described with reference to FIG. 26 will be described.

  Referring to FIG. 26, in the method of forming a semiconductor device described with reference to FIGS. 27 to 34 and FIG. 24, at least one of the first sidewall 505 and the second sidewall 506 is the bottom surface. It is formed so as to be inclined to 503. In this case, the contact extension portion CT and the dummy extension portion DCT are formed to be inclined toward the bottom surface 503 and the bottom portion BP. Side walls of the insulating films 510 to 516 are formed to be inclined toward the bottom surface 503.

  A semiconductor device according to a sixth embodiment of the present invention will be described. 35 and 36 are plan views for explaining a semiconductor device according to the sixth embodiment of the present invention. FIG. 37 is a cross-sectional view taken along the line VI-VI ′ of FIGS. is there.

  Referring to FIGS. 35 to 36 and 37, a substrate 601 is provided. The substrate 601 is a semiconductor substrate. The substrate 601 includes a well. The well includes a first conductivity type dopant. A common source region 202 is disposed in the substrate 601. The common source region 602 is disposed in a plate form in the cell region of the substrate 601. In contrast, the common source region may be in the form of a line on the substrate. For example, the common source region is formed by realizing a trench formed by a gate replacement process.

  The common source region 602 may include a high concentration of dopant. The dopant included in the common source region 202 may have a second conductivity type that is different from the dopant included in the well. For example, when the well includes a p-type dopant, the common source region 202 includes a high concentration of n-type dopant.

  The substrate 601 includes a recess A. The recess A includes a first side wall 605 and a second side wall 606 that face the bottom surface 603. The substrate 601 includes a ridge B extending from the first and second side walls 605 and 606. The upper surface of the raised portion B is parallel to the bottom surface 603 of the recessed portion A. The concave portion A and the raised portion B are formed by etching a portion where the concave portion A of the semiconductor substrate is disposed, and leaving a portion where the raised portion B is disposed. In this case, the substrate 601 is an integral substrate.

  The substrate 601 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. The cell region α includes the concave portion A and the raised portion B. A peripheral circuit is disposed in the peripheral circuit region β. The peripheral circuit region β includes the raised portion B.

  The cell region α of the substrate 601 will be described.

  The cell region α includes a first contact region CR1 adjacent to the first sidewall 605 of the recess A and a second contact region CR2 adjacent to the second sidewall 606. A cell array region CAR is disposed between the first contact region CR1 and the second contact region CR2. The first contact region CR1 and the second contact region CR2 are spaced apart from each other across the cell array region CAR.

  Conductive patterns GSL, WL1 to WL4, SSL spaced apart from each other are disposed on the substrate 601. The conductive patterns GSL, WL1 to WL4, and SSL include a ground selection line GSL, word lines WL1 to WL4, and a string selection line SSL that are sequentially stacked on the recess A of the substrate 601. The conductive patterns GSL, WL1-WL4, SSL are spaced apart from each other with an inter-gate insulating film 610-614 interposed therebetween. For example, the ground selection line GSL, the first inter-gate insulating film 610, the first word line WL1, the second inter-gate insulating film 611, the second word line WL2, the third inter-gate insulating film 612, the third word line WL3, A fourth inter-gate insulating film 613, a fourth word line WL4, a fifth inter-gate insulating film 614, and a string selection line SSL are sequentially stacked. The insulating films 610 to 614 include a bottom portion on the bottom surface 603 of the recess A of the substrate 601 and side wall portions extending from the bottom portion to the first side wall 605 and the second side wall 606. A string selection insulating layer 615 is disposed on the string selection line SSL. The conductive patterns GSL, WL1 to WL4, and SSL may have a line shape extending in the first direction. The first direction is a direction VI-VI '.

  The conductive patterns GSL, WL1 to WL4, and SSL include a bottom portion BP disposed on the bottom surface 603 of the recess A. The length of the bottom BP becomes shorter as the distance from the recess A of the substrate 601 increases. The bottom BP is parallel to the bottom surface 603. The bottom portion BP is parallel to the upper surface of the raised portion B.

  The conductive patterns GSL, WL1 to WL4, and SSL include a contact extension CT that extends from one end of the bottom BP to one of the first and second sidewalls 605 and 606. A contact region in which a contact extension of any one of the conductive patterns GSL, WL1 to WL4, SSL is disposed; and a contact extension of another conductive pattern adjacent to the one of the conductive patterns. The arranged contact regions can be different. For example, when the contact extension CT of the ground selection line GSL is disposed in the first contact region CR1, the contact extension CT of the first word line WL1 adjacent to the ground selection line GSL is the second contact region CR2. Placed in.

  An extension line of the contact extension CT intersects the bottom surface 603. An extension line of the contact extension CT may intersect the bottom surface 603 at a right angle. The contact extension CT decreases in length as the distance from the recess A of the substrate 601 increases. The upper surface of the contact extension CT is flush with the upper surface of the raised portion B. An angle between the contact extension CT and the bottom BP may be 90 °.

  The conductive patterns GSL, WL1 to WL4, and SSL are extended from the other end of the bottom BP on the bottom surface 603 to one of the first side surface 605 and the second side surface 606 (extended over). ) Includes dummy extension DCT. A contact region where a dummy extension of any one of the conductive patterns GSL, WL1 to WL4, SSL is disposed, and a dummy extension of another conductive pattern adjacent to any one of the conductive patterns The arranged contact regions can be different. For example, when the dummy extension DCT of the string selection line SSL is disposed in the first contact region CR1, the dummy extension DCT of the fourth word line WL4 adjacent to the string selection line SSL is the second contact region. Located in CR2.

  Each of the conductive patterns GSL, WL1 to WL4, SSL includes one contact extension CT and one dummy extension DCT. In one conductive pattern among the conductive patterns GSL, WL1 to WL4, and SSL, the length of the dummy extension DCT may be shorter than the length of the contact extension CT. The contact extension CT is disposed between the adjacent dummy extensions DCT. The contact extension CT adjacent to the dummy extension DCT is separated by the side wall of the insulating film interposed therebetween.

  A dummy insulating pattern 664 is disposed on the dummy extension DCT. The upper surface of the dummy insulating pattern 664 is flush with the upper surface of the raised portion B. The upper surface of the dummy insulating pattern 664 is flush with the upper surface of the string selection insulating film 615. The side wall of the dummy insulating pattern 664 is flush with the side wall of the dummy extension DCT. The dummy insulating pattern 664 may include the same material as the insulating layers 610 to 615.

  Conductive plugs are disposed on the contact extensions CT of the word lines WL1 to WL4. The conductive plug may be a word line contact plug CP. Each of the word lines WL1 to WL4 is electrically connected to the word line contact plug CP. The word line contact plug CP may be wider than the upper surface of the contact extension CT of the word lines WL1 to WL4. The word line contact plug CP may be wider than a width between the contact extension CT of the word lines WL1 to WL4 and the adjacent dummy extension DCT. The word line contact plug CP penetrates the first interlayer insulating layer 680. A first conductive line ML1 is disposed on the word line contact plug CP and the first interlayer insulating layer 680. The word line contact plug CP is electrically connected to the first conductive line ML1. The first conductive line ML1 extends in a second direction that intersects the first direction. The first conductive line ML1 is electrically connected to the word lines WL1 to WL4 through the word line contact plug CP. In contrast, the first conductive line ML1 may be directly connected to the word lines WL1 to WL4. A second interlayer insulating layer 690 is disposed to cover the first conductive line ML1. The first interlayer insulating layer 680 and the second interlayer insulating layer 690 may include the same material.

  A conductive plug is disposed on the contact extension CT of the ground selection line GSL. The conductive plug may be a ground selection contact plug GCP. The ground selection line GSL is electrically connected to the ground selection contact plug GCP. The width of the ground selection contact plug GCP may be wider than the width of the upper surface of the contact extension CT of the ground selection line GSL. The ground selection contact plug GCP penetrates the first interlayer insulating film 680. A second conductive line ML2 is disposed on the ground selection contact plug GCP and the first interlayer insulating layer 680. The ground selection contact plug GCP is electrically connected to the second conductive line ML2. The second conductive line ML2 extends in the second direction. The second conductive line ML2 is electrically connected to the ground selection line GSL through the ground selection contact plug GCP. In contrast, the second conductive line ML2 may be directly connected to the ground selection line GSL. The second interlayer insulating layer 690 covers the second conductive line ML2.

  A conductive plug is disposed on the contact extension CT of the string selection line SSL. The conductive plug may be a string selection contact plug SCP. The string selection line SSL is electrically connected to the string selection contact plug SCP. The width of the string selection contact plug SCP may be wider than the width of the upper surface of the contact extension CT of the string selection line SSL. The string selection contact plug SCP penetrates the first interlayer insulating film 680 and the second interlayer insulating film 690. A third conductive line ML3 is disposed on the string selection contact plug SCP and the second interlayer insulating layer 680. The string selection contact plug SSL is electrically connected to the third conductive line ML3. The third conductive line ML3 extends in the first direction.

  The conductive lines GSL and WL1 to WL4 are arranged separately on both sides of the cell array region CAR. The conductive line connected to any one of the conductive patterns GSL, WL1 to WL4 is arranged in a different contact region from the conductive line connected to the conductive pattern adjacent to any one of the conductive patterns. . For example, the first conductive line ML1 connected to the first word line WL1 is disposed in the second contact region CR2, and the ground selection line GSL and the second word line WL2 adjacent to the first word line WL1 The second conductive line ML2 and the first conductive line ML1 connected to each other are disposed in the first contact region CR1. In the embodiment, a trench for cutting the conductive patterns WL1 to WL4 and GSL and an inter-gate insulating film are formed (not shown). The trench can be used to fill a film including a gate replacement and an information storage film.

  An active part AP extending upward from the bottom surface 603 of the recess A is disposed. The active part AP extends perpendicularly to the substrate 601. The active part AP penetrates the conductive patterns GSL, WL1 to WL4, SSL. In contrast, the active part AP may face the side surfaces of the conductive patterns GSL, WL1 to WL4, and SSL. One end of the active part AP is electrically connected to the common source region 602. A drain region 623 is disposed at the other end of the active part AP. The drain region 623 may be a region doped with a high concentration of dopant. The active part AP includes a single crystal semiconductor.

  A bit line contact plug BLCP is disposed on the drain region 623 of the active part AP. The bit line contact plug BLCP is electrically connected to the drain region 623 and penetrates the first interlayer insulating film 680 and the second interlayer insulating film 690. A bit line BL is disposed on the bit line contact plug BLCP. The bit line BL is connected to the drain region 623 of the active part AP through the bit line contact plug BLCP. In contrast, the bit line BL may be directly connected to the drain region 623. The bit line BL extends in a second direction that intersects the first direction. The bit line BL intersects the third conductive line ML3.

  An information storage layer 640 is interposed between the sidewall of the active part AP and the conductive patterns GSL, WL1 to WL4, SSL. The information storage layer 640 is disposed between the conductive patterns GSL, WL1 to WL4, SSL and a sidewall of the active part AP. The information storage layer 640 is disposed between the conductive patterns GSL, WL1-WL4, SSL and the insulating layers 610-615.

  The information storage film 640 according to the sixth embodiment of the present invention may be the information storage film described with reference to FIG.

  The peripheral circuit region β will be described.

  A peripheral circuit is disposed on the upper surface of the raised portion B of the peripheral circuit region β. A gate insulating layer 674 is disposed on the upper surface of the raised portion B. The gate insulating film 674 includes a silicon oxide film. The gate insulating layer 674 may be formed by thermally oxidizing the upper surface of the raised portion B. A gate electrode 676 is disposed on the gate insulating layer 674. The gate electrode 676 includes any one of doped polysilicon, metal, and metal silicide. Spacers 678 are disposed on both side walls of the gate electrode 676. Source / drain regions 673 are disposed on the raised portions B on both side walls of the gate electrode 676. The source / drain region 673 may be a region doped with a high concentration dopant.

  A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer 670 is disposed on the gate electrode 676 and the source / drain region 673. A fourth conductive line ML4 is disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer 690 is disposed on the fourth conductive line ML4.

  A modification of the sixth embodiment of the present invention will be described. FIG. 38 is a view for explaining a modification of the second embodiment of the present invention, and is a cross-sectional view taken along the line VI-VI ′ of FIGS. 35 and 36.

  Referring to FIGS. 35, 36, and 38, a substrate 600 is provided. A common source region 602 is disposed in the substrate 600. The substrate 600 includes a recess A. The recess A includes a first side wall 605 and a second side wall 606 that face the bottom surface 603. The substrate 600 includes a ridge B extending from the first and second sidewalls 605 and 606. The upper surface of the raised portion B is parallel to the bottom surface 603 of the recessed portion A. The raised portion B is defined by an insulating film 204 disposed on the substrate 601.

  Referring to FIGS. 35 and 36, as shown in FIGS. 1 and 2, one wiring extending outside one end of the cell array unit is electrically connected to a contact extension of the word line on one side. Another wiring extending outside the other end of the cell array portion is electrically connected to a contact extension portion of the other word line. As shown in FIG. 35, all string selection lines SSL are connected to wiring on one side, while several string selection lines are connected to wiring on one side as shown in FIG. Are connected to wiring in other layers. The word lines are selected alternately. That is, for example, odd-numbered word lines (first, third, and fifth word lines) from the bottom to the top of the string are connected to wiring on one side of the string, and even-numbered word lines (second, fourth, The sixth word line is connected to the wiring on the other side of the string.

  The substrate 600 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. A peripheral circuit is disposed in the peripheral circuit region β.

  The cell region α of the substrate 600 will be described.

  The cell region α includes a first contact region CR1 adjacent to the first sidewall 605 of the recess A and a second contact region CR2 adjacent to the second sidewall 606. The memory cells described with reference to FIG. 37 are disposed in the cell region α of the substrate 600.

  The peripheral circuit region β of the substrate 600 will be described.

  A peripheral circuit is disposed on the upper surface of the raised portion B of the peripheral circuit region β. A semiconductor film 672 is disposed on the upper surface of the insulating film 604. The semiconductor layer 672 includes other semiconductor materials including polysilicon, crystalline silicon, and single crystal silicon. A gate insulating film 674 is disposed on the semiconductor film 672. The gate insulating film 674 includes a silicon oxide film. The gate insulating layer 674 may be formed by thermally oxidizing the upper surface of the raised portion B. A gate electrode 676 is disposed on the gate insulating layer 674. The gate electrode 676 includes any one of doped polysilicon, metal, and metal silicide. Gate spacers 678 are disposed on both side walls of the gate electrode 676. A source / drain region 673 is disposed on the upper surface of the semiconductor film 672 on both side walls of the gate electrode 676. The source / drain region 673 may be a region doped with a high concentration dopant.

  A peripheral circuit contact plug PCP penetrating the first interlayer insulating layer 160 is disposed on the gate electrode 676 and the source / drain region 673. A fourth conductive line ML4 is disposed on the peripheral circuit contact plug PCP. A second interlayer insulating layer 690 is disposed on the fourth conductive line ML4.

  A semiconductor device according to another modification of the sixth embodiment of the present invention will be described. FIG. 39 is a view for explaining another modification of the sixth embodiment of the present invention, and is a cross-sectional view taken along the line VI-VI ′ of FIGS. 35 and 36.

  Referring to FIGS. 35, 36, and 39, a substrate 601 is provided. A common source region 602 is disposed in the substrate 601. The substrate 601 includes a recess A. The recess A includes a first side wall 605 and a second side wall 606 that face the bottom surface 603. One of the first side wall 605 and the second side wall 606 is inclined toward the bottom surface 603 of the recess A. For example, the first side wall 605 and the second side wall 606 may have an angle of 50 ° to 90 ° with respect to the bottom surface 603. The slope that the first side wall 605 has with respect to the bottom surface 603 may be the same as the slope that the second side wall 606 has with respect to the bottom surface 603. In contrast, the slope of the first side wall 605 with respect to the bottom surface 603 may be different from the slope of the second side wall 606 with respect to the bottom surface 603. The substrate 601 includes a raised portion B extending from the first and second sidewalls 605 and 606. The upper surface of the raised portion B is parallel to the bottom surface 603 of the recessed portion A. The concave portion A and the raised portion B of the substrate 601 are defined through a semiconductor substrate etching process. In contrast, as described with reference to FIG. 38, the raised portion B may be defined by an insulating film 604 disposed on the substrate 600.

  The substrate 601 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. The peripheral circuit region β includes a peripheral circuit.

  The cell region α of the substrate 601 will be described.

  The cell region α includes a first contact region CR1 adjacent to the first sidewall 605 of the recess A and a second contact region CR2 adjacent to the second sidewall 606. The memory cell described with reference to FIG. 37 is arranged. In one of the conductive patterns GSL, WL1 to WL4, and SSL, the contact extension CT and the dummy extension DCT have a slope inclined with respect to the bottom BP.

  The angle formed between the side wall adjacent to the contact region where the contact extension CT is disposed and the bottom surface 603 may be the same as the angle formed between the contact extension CT and the bottom BP. Taking the first word line WL1 as an example, the slope of the contact extension CT with respect to the bottom BP may be the same as the slope of the second sidewall 606 with respect to the bottom surface 603. If the slopes of the first sidewall 605 and the second sidewall 606 with respect to the bottom surface 603 are different, the slope of the contact extension CT with respect to the bottom BP in one conductive pattern is determined by the dummy extension DCT. It can be different from the slope it has for the bottom BP.

  The peripheral circuit region β of the substrate 601 will be described.

  The peripheral circuit described with reference to FIG. 24 is disposed in the peripheral circuit region β of the substrate 601. On the other hand, as described above, when the substrate is the substrate described with reference to FIG. 26, the semiconductor film 672 is added.

  A method for forming a semiconductor device according to a sixth embodiment of the present invention will be described. 40 to 48 are views for explaining a semiconductor device according to the sixth embodiment of the present invention.

  Referring to FIG. 40, a substrate 601 is provided. The substrate 601 includes a recess A. The recess A includes a first side wall 605 and a second side wall 606 that face the bottom surface 603. The substrate 601 includes a ridge B extending from the first and second side walls 605 and 606. The upper surface of the raised portion B is parallel to the bottom surface 603 of the recessed portion A. The recess A and the raised portion B of the substrate are defined by etching a part of the semiconductor substrate in which the recess A is disposed. In this case, the substrate 600 is an integral substrate.

  The substrate 601 includes a cell region α and a peripheral circuit region β. Memory cells are arranged in the cell region α. The cell region α includes the concave portion A and the raised portion B. The peripheral circuit region β includes a peripheral circuit. The peripheral circuit region β includes the raised portion B.

  The cell region α includes a first contact region CR1 adjacent to the first sidewall 605 of the recess A and a second contact region CR2 adjacent to the second sidewall 606. A cell array region CAR is disposed between the first contact region CR1 and the second contact region CR2. The first contact region CR1 and the second contact region CR2 are spaced apart from each other across the cell array region CAR.

  The substrate 601 may be a single crystal semiconductor (for example, a P-type silicon wafer). The substrate 601 includes a well. The well is formed by implanting a dopant into the substrate 601. The dopant is implanted into the substrate 601 by a doping process including ion implantation or plasma implantation. A common source region 602 is provided on the upper surface of the substrate 601. The common source region 202 is formed by doping a dopant in the well. The common source region 202 includes a dopant having a conductivity type different from that of the well. In one embodiment of the invention, the common source region is formed in the bottom region of the trench. For example, the well includes a p-type dopant and the common source region 602 includes an n-type dopant.

  Sacrificial films SC <b> 1 to SC <b> 6 and insulating films 610 to 615 are alternately stacked on the recesses A of the substrate 601. For example, a first sacrificial film SC1, a first intergate insulating film 610, a second sacrificial film SC2, a second intergate insulating film 611, a third sacrificial film SC3, a third intergate insulating film 612, The fourth sacrificial film SC4, the fourth inter-gate insulating film 613, the fifth sacrificial film SC5, the fifth inter-gate insulating film 614, the sixth sacrificial film SC6, and the string selection insulating film 615 are included in this order. The sacrificial films SC1 to SC6 and the insulating films 610 to 615 are formed on the upper surface of the raised portion B. The sacrificial films SC <b> 1 to SC <b> 6 and the insulating films 610 to 615 include a bottom portion of the recess A on the bottom surface 603 and sidewall portions extending from the bottom portion to the first sidewall 605 and the second sidewall 606, respectively.

  The material of the sacrificial layer may be a material that can be selectively removed. For example, the sacrificial film includes a silicon nitride film that can selectively remove phosphoric acid or an acid including phosphorus (P). The insulating films 610 to 615 include a silicon oxide film. The sacrificial films SC1 to SC6 are formed of a material that is selectively etched while minimizing the etching of the insulating films 610 to 615. For example, the sacrificial films SC1 to SC6 include silicon nitride films.

  A planarization process is performed using the upper surface of the raised portion A as an etch stop layer. The planarization process is performed by etch back or chemical mechanical polishing. The upper surface of the raised portion A is flush with the upper surfaces of the side wall portions of the insulating films 610 to 615. The upper surfaces of the side walls of the sacrificial films SC1 to SC6 are flush with the upper surfaces of the side walls of the insulating films 610 to 615 and the upper surface of the raised portion B.

  Referring to FIG. 41, the insulating films 610 to 615 and the sacrificial films SC <b> 1 to SC <b> 6 that are alternately stacked are patterned to form a first opening 620 that exposes the bottom surface 603 of the recess A of the substrate 601. The The patterning for forming the first opening 620 can be performed using an anisotropic etching technique. The first opening 620 exposes the bottom surface 603 of the recess A, the side surfaces of the insulating films 610 to 615, and the side surfaces of the sacrificial films SC1 to SC6.

  Referring to FIG. 42, an active part AP that covers the inner wall of the first opening 620 is formed. The active portion AP is formed to conformally cover the inner wall of the first opening 620 using one of chemical vapor deposition (CVD) and atomic layer chemical vapor deposition (ALD). The The active part AP is formed to have the same conductivity type as the substrate 601 with which the active part AP comes into contact, and thereby the active part AP and the substrate 601 are electrically connected. For example, the active part AP includes single crystal silicon that is continuously connected to the substrate 601 without crystal defects. For this, the active part AP is grown from the exposed substrate 601 using one of the epitaxial techniques. The remaining space of the first opening 620 is filled with an insulating material 624 (for example, a silicon oxide film, a silicon nitride film, or air). A drain region 623 is formed on the active part AP. The active part AP may have a pillar shape, a tubular shape, or a bar-sided shape.

  The insulating films 610 to 615 and the sacrificial films SC1 to SC6 are patterned to form a preliminary gate isolation region that exposes the bottom surface 603 of the recess A of the substrate 601. The preliminary gate isolation region is formed between the active portions AP adjacent in the second direction (see FIG. 14). Side walls of the insulating films 610 to 615 and the sacrificial films SC1 to SC6 are exposed by the preliminary gate isolation region. Forming the preliminary gate isolation region may be the same as the method for forming the first opening 620.

  Referring to FIG. 43, the sacrificial films SC1 to SC6 exposed by the preliminary gate isolation region are removed. A trench exposing the sacrificial film is formed, and removing the sacrificial film is performed using a region formed by the trench. A gate region 630 is formed between the insulating layers 610 to 615 to expose the sidewall of the active part AP. The sacrificial films SC1 to SC6 may be removed using an etching method having an etching selectivity with respect to the insulating films 610 to 615, the substrate 601, the active part AP, and the insulating material 624. Can do. The step of removing the sacrificial films SC1 to SC6 may be a dry or wet method, or an isotropic etching method. At the same time, the filled active portion AP and the core portion of the insulating material can act as a support base on which the insulating films 610 to 615 are maintained.

  Referring to FIG. 44, a low information storage layer 640 is conformally formed on the resultant structure where the gate region 630 is formed. The information storage layer 640 is formed on the sidewall of the active part AP exposed by the gate region 630. The information storage layer 640 is formed on the upper surface of the raised portion B, the upper surface of the string selection insulating layer 615, and the insulating layers 610 to 615 exposed by the gate region 630.

  Referring to FIG. 6 again, a method for forming the information storage film 640 will be described. Forming the information storage layer 640 includes forming a tunnel insulating layer 242 that covers the exposed sidewall of the active part AP, forming a charge storage layer 244 that covers the tunnel insulating layer 242, and forming the charge storage layer 244. Forming a blocking film 246 covering the substrate.

  Referring to FIG. 44 again, a preliminary gate conductive layer 650 that fills the preliminary gate isolation region and the gate region 630 is formed on the information storage layer 640. The preliminary gate conductive layer 650 includes a polycrystalline silicon film, a silicide film, and a metal film formed by chemical vapor deposition (CVD) or atomic layer chemical vapor deposition (ALD), which provides excellent step coverage. Including at least one of the following. Meanwhile, the information storage layer 640 is also formed on the substrate 601, and the preliminary gate conductive layer 650 is electrically separated from the substrate 601.

  Referring to FIG. 45, after the preliminary gate conductive layer 650 is formed, an etching process is performed. The etching process is performed using a wet etching method and a dry etching method. The preliminary gate conductive layer 650 and the information storage layer 640 on the upper surface of the raised portion B are removed. The preliminary gate conductive layer 650 in the preliminary gate isolation region is removed.

  The next step is similar to the embodiment described in FIGS. 14F and 14G.

  The preliminary gate conductive layer 650 is patterned to form conductive patterns GSL, WL1 to WL4, and SSL.

  The conductive patterns GSL, WL1 to WL4, and SSL include a bottom portion BP disposed on the bottom surface 503 of the recess A. The conductive patterns GSL, WL1 to WL4, and SSL include a contact extension CT that extends from one end of the bottom BP to one of the first and second sidewalls 605 and 606. A contact region in which a contact extension of any one of the conductive patterns GSL, WL1 to WL4, SSL is disposed; and a contact extension of another conductive pattern adjacent to the one of the conductive patterns. The arranged contact regions can be different. The exposed upper surface of the contact extension CT is flush with the upper surface of the raised portion B.

  The conductive patterns GSL, WL1 to WL4, and SSL are extended from the other end of the bottom BP on the bottom surface 603 to one of the first side surface 605 and the second side surface 606 (extended over). ) Includes dummy extension DCT. A contact region where a dummy extension of any one of the conductive patterns GSL, WL1 to WL4, SSL is disposed, and a dummy extension of another conductive pattern adjacent to any one of the conductive patterns The arranged contact regions can be different. Each of the conductive patterns GSL, WL1 to WL4, SSL includes one contact extension CT and one dummy extension DCT.

  A mask pattern 660 is formed to cover the exposed upper surface of the contact extension CT. The mask pattern 660 exposes the dummy extension DCT. Forming the mask pattern 660 includes forming a mask film on the substrate 601 and patterning the mask film. The mask pattern 660 includes a material having an etching selectivity with respect to the conductive patterns GSL, WL1 to WL4, SSL and the insulating layers 610 to 615. For example, the mask pattern 660 includes a silicon nitride film or a photoresist pattern.

  Referring to FIG. 46, a part of the dummy extension DCT exposed by the mask pattern 660 is etched using the mask pattern 660 as an etching mask. A portion of the dummy extension DCT is etched to form a dummy recess 662. The length of the dummy extension DCT may be shorter than the length of the contact extension CT. The dummy recess portion 662 exposes a portion of the sidewall portions of the insulating films 610 to 615. Etching the dummy extension DCT may use an etching recipe having an etching rate higher than that of the mask pattern 660 and the insulating films 610 to 615 with respect to the conductive patterns GSL, WL1 to WL4, and SSL. The mask pattern 660 is removed.

  Referring to FIG. 47, a dummy insulating pattern 664 for embedding the dummy recess 662 is formed. The dummy insulating pattern 664 is formed by forming a dummy insulating film on the substrate 601 and performing a planarization process using the upper surface of the raised portion B or the upper surface of the string selection insulating film 615 as an etching stop film. Including doing. The upper surface of the dummy insulating pattern 664 is flush with the upper surface of the raised portion B. The upper surface of the dummy insulating pattern 664 is flush with the upper surfaces of the string selection insulating film 615 and the contact extension CT.

  A gate insulating layer 674 is formed on the upper surface of the raised portion B. The gate insulating layer 674 is formed through a thermal oxidation process. The gate insulating layer 674 includes a silicon oxide layer having a thickness of 40 to 300 mm. When the gate insulating layer 674 is formed by a thermal oxidation process, an oxide layer is formed on the upper surface of the contact extension CT of the conductive patterns GSL, WL1 to WL4 and SSL in the exposed cell region α. Before the gate insulating film 674 is formed, a mask layer that covers the recess A and exposes the raised portion B is additionally formed. The mask layer may be an insulating film.

  A gate electrode 676 is formed on the gate insulating layer 674. Source / drain regions 673 are formed in the raised portions B on both sides of the gate electrode 676. The source / drain region 673 may be a region doped with a high concentration dopant.

  Referring to FIG. 48, gate spacers 678 are formed on both sides of the gate electrode 676. A first interlayer insulating layer 680 is formed to cover the entire surface of the substrate 601. The first interlayer insulating layer 680 includes a silicon oxide layer. The first interlayer insulating film 680 is etched to expose a contact opening 686 exposing the upper surface of the contact extension CT, a bit line opening 684 exposing the drain region 623, and the gate of the peripheral circuit region β. A peripheral circuit opening 686 exposing the electrode 676 is formed. An opening exposing the source / drain region is formed. Etching the first interlayer insulating layer 680 includes using an anisotropic etching process.

  As described above, when the gate insulating film 674 is formed by a thermal oxidation process and a mask layer is formed on the upper surface of the contact extension CT of the conductive patterns GSL, WL1 to WL4, SSL in the cell region α, In the process of etching the first interlayer insulating layer 680, the mask layer is etched to expose the contact extension CT. Unlike this, the gate insulating film 674 is formed by a thermal oxidation process, but a mask layer is not formed on the contact extension CT of the conductive patterns GSL, WL1 to WL4, and SSL, so that an oxide film is formed. In this case, in the process of etching the first interlayer insulating layer 680, the oxide layer is removed to expose the contact extension CT.

  Referring to FIG. 37 again, contact plugs GCP, CP, bit line contact plugs BLCP, and peripheral circuit contact plugs PCP filling the contact openings 682, the bit line openings 684, and the peripheral circuit openings 686 are formed. Is done.

  The ground selection contact plug GCP is electrically connected to the contact extension CT of the ground selection line GSL. The word line contact plug CP is electrically connected to the word lines WL1 to WL4. The contact plugs GCP and CP each include a material having higher conductivity than the conductive patterns GSL, WL1 to WL4 and SSL. The peripheral circuit contact plug PCP is electrically connected to the gate electrode 676. The peripheral circuit contact plug PCP includes a material having higher conductivity than the gate electrode 676. For example, the contact plugs GCP and CP, the bit line contact plug BLCP, and the peripheral circuit contact plug PCP include tungsten.

  A second conductive line ML2 is formed on the ground selection contact plug GCP. A first conductive line ML1 is formed on the word line contact plug CP. A bit line BL is formed on the bit line contact plug BLCP. A fourth conductive line ML4 is formed on the peripheral circuit contact plug PCP. Forming the second conductive line ML2, the first conductive line ML1, the bit line BL, and the fourth conductive line ML4 includes forming a conductive layer on the first interlayer insulating layer 680 and patterning the conductive layer. .

  A second interlayer insulating layer 690 is formed to cover the second conductive line ML2, the first conductive line ML1, and the fourth conductive line ML4. The second interlayer insulating layer 690 may include the same material as the first interlayer insulating layer 680. A string selection contact plug SCP penetrating through the second interlayer insulating layer 690 and filling an opening exposing the contact extension CT of the string selection line SSL is formed. The string selection contact plug SCP includes a material having higher conductivity than the string selection line SSL. A third conductive line ML3 is formed on the string selection contact plug SCP. Forming the third conductive line ML3 includes forming a conductive film on the second interlayer insulating film 690 and patterning it. As a result, the semiconductor device described with reference to FIG. 37 is provided.

  A method for forming a semiconductor device according to a modification of the sixth embodiment of the present invention described with reference to FIG. 38 will be described.

  Referring to FIG. 38, in the method of forming a memory cell described with reference to FIGS. 40 to 48 and 37, forming the concave portion A and the raised portion B on the substrate 600 is performed on the substrate 600. Forming an insulating film 604, etching the insulating film 604 on the recess A, and leaving the insulating film 604 on the raised portion B.

  In the method for forming a peripheral circuit described with reference to FIG. 47, a semiconductor film 672 is formed on the upper surface of the raised portion B in the peripheral circuit region β. For example, the semiconductor film 672 is formed by using a step of bonding on the insulating film 604 of the raised portion B or by growing the semiconductor film 672. For example, the semiconductor film 672 includes polycrystalline silicon or single crystal silicon. A gate insulating film 674 is formed on the semiconductor film 672.

  A method for forming a semiconductor device according to another modification of the sixth embodiment of the present invention described with reference to FIG. 39 will be described.

  Referring to FIG. 39, in the method of forming a semiconductor device described with reference to FIGS. 40 to 48 and 37, at least one of the first sidewall 605 and the second sidewall 606 is the bottom surface. It is formed so as to be inclined to 603. In this case, the contact extension portion CT and the dummy extension portion DCT are formed to be inclined toward the bottom surface 603 and the bottom portion BP. Side walls of the insulating films 610 to 615 are formed to be inclined toward the bottom surface 603.

  The semiconductor elements according to the first and third embodiments of the present invention are formed with reference to the method for forming a semiconductor element described with reference to FIGS. 24 to 26 and FIGS. 27 to 34 described above.

  The semiconductor elements according to the second and fourth embodiments of the present invention are formed with reference to the method for forming a semiconductor element described with reference to FIGS. 37 to 39 and FIGS. 40 to 48 described above.

  An application example of the present invention will be described.

  FIG. 49 is a schematic block diagram showing an example of a memory system including the semiconductor element according to the embodiment of the present invention.

  Referring to FIG. 49, the memory system 1100 includes a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, Or it can be applied to all elements that can transmit and / or receive information in a wireless environment.

  The memory system 1100 includes a controller 1110, an input / output device 1120 such as a keypad, a keyboard and a display, a memory 1130, an interface 1140, and a bus 1150. The memory 1130 and the interface 1140 communicate with each other through the bus 1150.

  The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other process device similar thereto. Memory 1130 can be used to store instructions executed by the controller. The input / output device 1120 receives data or signals from the outside of the system 1100 or outputs data or signals to the outside of the system 1100. For example, the input / output device 1120 includes a keyboard, a keypad, or a display element.

  The memory 1130 includes a nonvolatile memory device according to an embodiment of the present invention. The memory 1130 also includes other types of memory, volatile memory that can be accessed at any time, and various other types of memory.

  The interface 1140 is responsible for sending data to or receiving data from the communication network.

  FIG. 50 is a schematic block diagram showing an example of a memory card including the semiconductor element according to the embodiment of the present invention.

  Referring to FIG. 50, a memory card 1200 for supporting a high-capacity data storage capability is equipped with a flash memory device 1210 according to the present invention. The memory card 1200 according to the present invention includes a memory controller 1220 that controls various data exchanges between the host (Host) and the flash memory device 1210.

  The SRAM 1221 is used as an operation memory of the processing unit 1222. The host interface 1223 includes a host data exchange protocol connected to the memory card 1200. The error correction block 1224 detects and corrects errors included in the data read from the multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs various control operations for data exchange of the memory controller 1220. Although not shown, the memory card 1200 according to the present invention can further provide a ROM (not shown) for storing code data for interfacing with a host (Host). It is obvious to those who have learned it.

  FIG. 51 is a schematic block diagram showing an example of an information processing system for mounting a semiconductor element according to the present invention.

  Referring to FIG. 51, the flash memory system 1310 of the present invention is installed in an information processing system such as a mobile device or a desktop computer. The information processing system 1300 according to the present invention includes a flash memory system 1310, a modem 1320 electrically connected to the system bus 760, a central processing unit 1330, a RAM 1340, and a user interface 1350. The flash memory system 1310 is configured substantially the same as the above-described memory system or flash memory system. The flash memory system 1310 stores data processed by the central processing unit 1330 or data input from the outside. Here, the above-described flash memory system 1310 can be configured as a semiconductor disk device (SSD). In this case, the information processing system 1300 can stably store a large amount of data in the flash memory system 1310. Since the flash memory system 1310 can reduce resources necessary for error correction due to the increase in reliability, a high-speed data exchange function can be provided to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention has acquired general knowledge in this field that it can further include an application chipset, a camera image processor (CIS), and an input / output device. It will be self-explanatory.

  In addition, the flash memory device or the memory system according to the present invention can be mounted in various forms of packages. For example, the flash memory device or the memory system according to the present invention includes PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), and Plastic-In-DneP ), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat (TQF) C), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), MultiChip Package (MCP), W It is packaged and implemented by a method such as Level Processed Stack Package (WSP).

  FIG. 52 is a block diagram of a nonvolatile memory element according to an embodiment of the present invention.

  Referring to FIG. 52, a nonvolatile memory device 1400 according to the present invention includes a memory cell array 1430, a control logic circuit 1440, a voltage generator 1410, a decoding circuit 1420 disposed on both sides of the cell array 1430, and a page buffer 1450. .

  The semiconductor memory device includes a substrate, a memory string disposed substantially normal to the substrate, and at least two row decoders. The memory string includes a plurality of storage cells and a plurality of word lines. The plurality of word lines are electrically connected to a first group of word lines electrically connected to one row decoder on the first side of the memory string and to another row decoder on the second side of the memory string. A second group of word lines. Wirings extending outside one end and the other end of the cell array portion are connected to row decoders on both sides. Accordingly, the first row decoder is connected to one group of string selection lines on the first side of the memory string, and the second row decoder is connected to another group of string selection lines on the second side of the memory string. In contrast, any one of the two row decoders can be connected to all the string selection lines.

  The memory cell array 1400 includes memory cells arranged in a mat rinse composed of rows (or word lines) and columns (or bit lines). The memory cells are arranged in a NAND or NOR structure. In the NAND structure, each memory cell includes a transistor connected in series.

  It is obvious to those skilled in the art that the concept of the present invention can be applied to a semiconductor device having word lines WL1 to WLn that are formed in a staircase form at an end and connected to a conductive plug.

  The control logic circuit 1440 is configured to control the overall operation of the nonvolatile memory device 1400. In an embodiment, the control logic circuit 1440 controls serial program operations. For example, the control logic circuit 1440 may be a state machine that stores a program sequence. However, it will be apparent to those skilled in the art that the control logic circuit 1440 is not limited to what is described herein. For example, the control logic circuit 1440 is configured to control read and erase operations.

  The control logic circuit 1440 drives a word line selected in response to a row address, a non-selected word line, a string selection line SSL, a ground selection line GSL, and a common source line CSL.

  The decoding circuit 1429 drives the upper line using the voltage generated by the voltage generator 1410. For example, in a program operation, the decoding circuit 1420 applies a program voltage Vpgm and a pass voltage Vpass to a selected word line and a non-selected word line, respectively.

  The page buffer 1450 may operate as a sense amplifier or a write driver. In the read operation, the page buffer 1450 reads data from the memory cell array 1430. In particular, the page buffer 1450 senses a bit line voltage, distinguishes data according to the bit line voltage, and stores the distinguished data therein.

100, 101 Substrate 103 Bottom surface of recess A 104 Projection 105, 106 First and second side walls 110 Ground selection insulating film 111-115 First to fifth inter-gate insulating film 116 String selection insulating film 124 Dummy insulating pattern 132 Information storage Film 134 First insulating film (tunnel dielectric film)
135 Charge storage film 136 Second insulating film (blocking film)
160 First interlayer insulating film 170 Second interlayer insulating film

Claims (43)

  1. A flat substrate;
    It is assumed that the memory string array (aligned in the X and Y directions) is formed perpendicular to the substrate (referred to as the Z direction) and includes a plurality of memory strings each including a plurality of storage cells (memory cells). )When,
    A plurality of word lines overlapped with each other in the Z direction,
    Each of the word lines is formed in parallel with the substrate, and includes a first portion connected to the memory string, and a second portion extending from the first portion and inclined upward (in the Z direction) with respect to the substrate. Including
    The memory string array is disposed in a first portion of each of the plurality of word lines and connected to each of the word lines to form a corresponding storage cell;
    The first group of the plurality of word lines is electrically connected to each of the first group of conductive lines disposed on the first side of the memory string array, and the second group of the plurality of word lines is A semiconductor memory device, wherein the semiconductor memory device is electrically connected to each of a group of second conductive lines disposed on a second side of the memory string array.
  2.   Among the word lines, the first group word lines and the second group word lines are alternately positioned along a vertical direction (Z direction) extending from the top to the bottom of the memory string. The semiconductor memory device according to claim 1.
  3.   The extending direction of the memory string intersects the substrate at 90 °, and the first side of the memory string array sandwiches the memory string array with the second side of the memory string array. The semiconductor memory device according to claim 1, wherein the semiconductor memory device faces each other.
  4.   The semiconductor memory device of claim 1, wherein first portions of each of the plurality of word lines are parallel to each other.
  5.   The second portions of each of the plurality of word lines located on the first side of the memory string array are parallel to each other, and the plurality of pieces located on the second side of the memory string array The semiconductor memory device of claim 1, wherein the second portions of each of the word lines are parallel to each other.
  6.   The first group of word lines count from the top to the bottom of the memory string and are connected to the odd-numbered storage cells, respectively, and the second group of word lines are arranged from the top to the bottom of the memory string. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is arranged so as to count toward each other and to be connected to each even-numbered storage cell.
  7.   An end extending obliquely above the second portion of the even-numbered word line located on the first side of the memory string array, and on the second side of the memory string array 2. The semiconductor memory device of claim 1, further comprising insulating caps disposed at ends of the odd-numbered word lines that are positioned and inclined and extended upward.
  8. A third group of word lines connected to a third conductive line and disposed on a third side of the memory string array;
    A first group of word lines is connected from a top to a bottom of the memory string and connected to a first storage cell by a modulo 3;
    A second group of word lines is connected from the top to the bottom of the memory string array and connected to a second storage cell by modulo 3;
    2. The semiconductor memory device of claim 1, wherein the third group of word lines is counted from the top to the bottom of the memory string array and is connected to the 0th storage cell in a modulo 3 manner. .
  9.   The semiconductor memory device of claim 1, wherein each of the plurality of storage cells and a corresponding word line are disposed on another plane disposed in parallel with a flat surface of the substrate.
  10.   10. The semiconductor memory device according to claim 9, wherein successive portions of the word lines arranged in the same plane on the other side of the memory string array are electrically connected to one word line. .
  11. The substrate is horizontal and the memory string is vertical;
    The semiconductor memory device of claim 1, further comprising a peripheral region disposed on the substrate.
  12.   And further including a plurality of conductive patterns disposed as contact pads between the first group of word lines and the first conductive lines and between the second group of word lines and the second conductive lines. The semiconductor memory device according to claim 1.
  13.   The semiconductor memory device of claim 12, further comprising a peripheral region disposed on the flat substrate.
  14.   The semiconductor memory device of claim 13, wherein the peripheral region is disposed at the same level as a lower surface of the conductive pattern.
  15.   The semiconductor memory device of claim 1, wherein the second portion of the word line inclined upward has an angle of 50 ° to 90 ° with the substrate.
  16.   The second portion inclined upward is extended from both ends of the first portion of each word line, and one of each pair of the second portions is covered with an insulating cap. Semiconductor memory device.
  17.   And further including a plurality of bit lines (Y direction) arranged orthogonal to each of the word lines and the memory strings (Z direction), and each of the plurality of bit lines is arranged along the bit line. The semiconductor memory device according to claim 1, further comprising an upper end of the plurality of memory strings connected to the memory string.
  18. A chamber (recess) on the flat substrate;
    The semiconductor memory of claim 1, wherein the chamber includes a silicon recess in the substrate, and an extension of each of the memory string, bit line, and word line is disposed in the silicon recess. element.
  19. Further comprising a chamber on the flat substrate;
    The semiconductor of claim 1, wherein the chamber includes an insulating wall on an upper surface of the substrate, and the memory string, bit line, and word line extensions are disposed around the insulating wall. Memory element.
  20.   The semiconductor memory device of claim 1, wherein the extension of the word line includes metal or silicide.
  21.   The semiconductor memory device of claim 1, wherein the memory string including the plurality of storage cells has a pillar, tube, or barside shape.
  22. Further comprising at least two row decoders;
    7. The semiconductor according to claim 6, wherein one row decoder is disposed on a side of the first group of word lines, and another row decoder is disposed on a side of the second group of word lines. Memory element.
  23. And a plurality of string selection lines each connected to a plurality of memory strings aligned in the X direction and spaced apart and aligned in parallel with each other in the Y direction,
    The first row decoder of the two row decoders is connected to any one of the groups of the string selection lines that are even-numbered or odd-numbered counting in the Y direction,
    23. The semiconductor memory device of claim 22, wherein a second row decoder of the two row decoders is connected to the other one of the group of string selection lines.
  24. The first row decoder of the two row decoders is connected to any one of all string selection lines and a group of even-numbered or odd-numbered word lines counted along the Z direction,
    23. The semiconductor memory device of claim 22, wherein a second row decoder of the two row decoders is connected to all string selection lines and the other one of the group of word lines.
  25.   The semiconductor memory device of claim 1, wherein the substrate includes silicon, the insulating film includes a silicon oxide film, and the word line includes a metal.
  26.   The semiconductor memory device of claim 1, wherein the storage cell includes a control gate, a first insulating region, a charge storage region, and a second insulating region.
  27.   The semiconductor memory device of claim 1, wherein the storage cell includes a metal gate as a control gate, a high-K region as a blocking film, a nitride region as a charge storage film, and an oxide region as a tunnel film.
  28. Provide a flat substrate,
    Forming a chamber (recess) on the substrate;
    Insulating films and sacrificial films are alternately deposited in the chamber, each film including a horizontal first portion and at least one second portion inclined upward with respect to the substrate;
    Forming a hole (through hole) perpendicular to the substrate and penetrating the superimposed film to reach the substrate;
    A memory string array is formed by depositing a memory string perpendicularly to the substrate in the hole,
    The memory string includes a plurality of storage cells;
    Each sacrificial film is replaced with a conductive film to form a plurality of stretched word lines,
    Of the plurality of word lines that are spaced apart from each other, odd-numbered word lines are connected to conductive lines arranged on the first side of the memory string array, and even-numbered word lines are connected to the memory string array. A method of manufacturing a semiconductor memory device, comprising connecting each of the conductive lines to a second side.
  29.   30. The method of claim 28, further comprising forming a peripheral region on a top level surface of the memory string.
  30. The vertical memory string is a barside shape;
    29. The method of claim 28, further comprising forming a trench for X-cut and dividing the memory string into two parallel strings.
  31.   29. The method of claim 28, wherein the substrate includes silicon, the insulating film includes a silicon oxide film, and the word line includes a metal.
  32.   30. The method of claim 28, wherein the chamber is formed by directly recessing the substrate.
  33.   29. The method of claim 28, wherein the chamber is formed on the substrate by forming an insulating sidewall on the substrate.
  34.   The storage cell includes a control gate formed as the memory string, connected to a word line, a first insulating region, a charge storage region, a second insulating region, and an active region in which a channel is formed. 30. A method of manufacturing a semiconductor memory device according to claim 28.
  35.   The storage cell includes a metal gate film as a control gate, a high-K film as a blocking region (second insulating region), a nitride film as a charge storage region, and an oxide film as a tunnel region (first insulating region). A method for manufacturing a semiconductor memory device according to claim 28.
  36. A substrate,
    A memory string array (assumed to be aligned in the X and Y directions) composed of a plurality of memory strings formed perpendicular to the substrate (referred to as the Z direction);
    The memory string includes a plurality of storage cells (memory cells),
    A plurality of word lines overlapped with each other in the Z direction,
    Each of the word lines is formed in parallel to the substrate, and includes a first portion coupled to the memory string, and a second portion extending from the first portion and inclined upward (in the Z direction) with respect to the substrate. Including
    An array of memory strings is disposed in a first portion of each of the plurality of word lines and coupled to each of the word lines to form a corresponding storage cell;
    Of the plurality of word lines superimposed in the Z direction, odd-numbered word lines are electrically connected to the respective conductive lines in the group of first conductive lines arranged on the first side of the memory string array. And
    The even-numbered word line is electrically connected to each conductive line in a group of second conductive lines arranged on the second side of the memory string array.
  37. A substrate,
    A memory string array (assumed to be aligned in the X and Y directions) composed of a plurality of memory strings formed perpendicular to the substrate (referred to as the Z direction);
    The memory string includes a plurality of storage cells (memory cells),
    A plurality of word lines overlapped with each other in the Z direction,
    Each of the word lines is formed in parallel to the substrate, and includes a first portion coupled to the memory string, and a second portion extending from the first portion and inclined upward (in the Z direction) with respect to the substrate. Including
    An array of memory strings is disposed in a first portion of each of the plurality of word lines and coupled to each of the word lines to form a corresponding storage cell;
    The word line is a first word line selectively connected to a first conductive line disposed on a first side of the memory string array, and a second word line disposed on a second side of the memory string array. A semiconductor memory device comprising a second word line selectively connected to two conductive lines.
  38.   38. The semiconductor memory device of claim 37, wherein the word line includes at least one dummy word line.
  39.   38. The semiconductor memory device of claim 37, further comprising a first row decoder on the first side and a second row decoder on the second side.
  40. A substrate,
    A memory string array (assumed to be aligned in the X and Y directions) composed of a plurality of memory strings formed perpendicular to the substrate (referred to as the Z direction);
    The memory string includes a plurality of storage cells (memory cells),
    A plurality of word lines that are spaced apart from each other in the Z direction;
    And at least two row decoders,
    The plurality of word lines include a first group of word lines electrically connected to one row decoder disposed on a first side of the memory string array, and a second side of the memory string array. And a second group of word lines electrically connected to another row decoder disposed in the semiconductor memory device.
  41. And a plurality of string selection lines each connected to a plurality of memory strings aligned in the X direction and spaced apart and aligned in parallel with each other in the Y direction,
    The first row decoder is connected to the first group of string selection lines via a conductive line disposed on a first side of the memory string array;
    41. The semiconductor of claim 40, wherein the second row decoder is connected to a group consisting of the rest of the string selection lines through a conductive line disposed on a second side of the memory string array. Memory element.
  42.   41. The semiconductor memory device of claim 40, wherein any one of the two row decoders is connected to the entire string selection line.
  43. Provide a flat substrate,
    Forming a chamber (recess) on the substrate;
    Insulating films and conductive films are alternately deposited in the chamber,
    The conductive film forms a plurality of word lines;
    Each membrane includes a horizontal first portion and at least one second portion inclined upwardly relative to the substrate;
    Forming a hole (through hole) perpendicular to the substrate and penetrating the superimposed film to reach the substrate;
    A memory string array is formed by forming a memory string perpendicular to the substrate in the hole,
    The memory string includes a plurality of storage cells;
    Out of the plurality of spaced apart word lines, odd-numbered word lines are connected to contact pads arranged on the first side of the memory string array, and even-numbered word lines are connected to the first number of the memory string array. 2. A method of manufacturing a semiconductor memory device, wherein the semiconductor memory device is connected to a contact pad disposed on a side of the semiconductor device.
JP2010189800A 2009-04-01 2010-08-26 Semiconductor memory device comprising three-dimensional memory cell array, and method for manufacturing same Pending JP2011049561A (en)

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