TWI575666B - Three dimensional memory device and method for fabricating the same - Google Patents

Description

Stereo memory element and manufacturing method thereof

The present disclosure relates to a high density memory device and a method of fabricating the same. In particular, there is a memory device having a three-dimensional (3D) three-dimensional memory array structure and a method of fabricating the same.

With the development of electronic technology, semiconductor memory components have been widely used in electronic products, such as MP3 players, digital cameras, notebook computers, mobile phones, and the like. The current demand for memory components is moving toward smaller sizes and larger memory capacities. In order to meet the demand for such high component density, a variety of different structural morphological three-dimensional memory components have been developed.

A typical three-dimensional memory element includes a three-dimensional memory cell array stacked by a plurality of memory cell planes, and a tandem selection transistor electrically connected in series between the memory plane layer and the corresponding bit line. In order to increase the density of memory components, in addition to reducing the size of individual memory cells in the memory cell array, Start by reducing the size of the transistor by narrowing the series. A conventional three-dimensional memory element uses a field effect transistor as a tandem selection transistor. However, a typical field effect transistor is a horizontal structure having a horizontally oriented gate with a large lateral cross-sectional area or footprint, which limits the density of the memory cell array.

In order to solve this problem, the prior art has adopted bipolar junction transistors and diodes as series-selective transistors. However, since the change between the current and voltage (I/V) of the bipolar junction transistor or diode exhibits an exponential function, it is less controllable for multi-bit operation.

Therefore, there is a need to provide a more advanced three-dimensional memory component and a method of fabricating the same to improve the problems faced by conventional techniques.

According to an embodiment of the present specification, a stereo memory device is provided, including: a semiconductor substrate, a source line, a gate line, and a plurality of serially connected memory cells. The semiconductor substrate has a projection. The source line is located in the semiconductor substrate and extends below the protrusion. The gate line is surrounded and covers the protrusion and is electrically isolated from the protrusion and the source line. A plurality of serially connected memory cells are located above the substrate and are in series with the top end of the projection.

According to another embodiment of the present specification, a method of fabricating a three-dimensional memory device is provided, comprising the steps of: first, providing a semiconductor substrate such that It has at least one projection. Further, at least one source line is formed in the semiconductor substrate, and the source line is extended below the protrusion. Thereafter, at least one gate line is formed to surround and cover the protrusion, and is electrically isolated from the protrusion and the source line. Subsequently, a plurality of serially connected memory cells are formed on the substrate so as to be in series with the top end of the protrusion.

According to still another embodiment of the present specification, a method of fabricating a stereo memory device is provided, comprising the steps of: first, providing a semiconductor substrate having an active region and a peripheral region. At least one source line is formed in the active area. Thereafter, a Selective Epitaxial Growth (SEG) process is performed to form at least one columnar channel structure on the source line, such that the bottom of the columnar channel structure is connected to the source line. Then, at least one gate line is formed to intersect the source line, and surrounds the columnar channel structure, and is electrically isolated from the columnar channel structure and the source line. Subsequently, a plurality of serially connected memory cells are formed above the active area to be connected in series with the top end of the columnar channel structure.

According to still another embodiment of the present specification, a method of fabricating a three-dimensional memory device is provided, comprising the steps of: first, providing a semiconductor substrate; and forming at least one source line in the semiconductor substrate. Thereafter, at least one gate line is formed, crossing the source lines, and electrically isolated from each other. Forming at least one through hole in the gate line exposes a portion of the gate line and a portion of the source line to the outside. Then, a spacer is formed on the sidewall of the through hole; a selective epitaxial growth process is performed to form a columnar channel structure in the through hole. Subsequently, a plurality of serially connected memory cells are formed on the substrate to be connected in series with the top end of the columnar channel structure.

According to the above embodiment, the present invention provides a stereo memory Components and how to make them. The three-dimensional memory component uses a field effect transistor having a vertical channel as a tandem selection transistor of a serial memory cell. In some embodiments of the invention, the vertical channel of the field effect transistor can be directly constructed in a projection that is convexly disposed on the surface of the semiconductor substrate. In some embodiments of the invention, a selective epitaxial growth process can be employed to form a vertical channel of the field effect transistor on the surface of the semiconductor substrate.

Because the vertical channel field effect transistor has a small footprint, and the linear relationship between the current and voltage (I / V) changes, it is easier to control and other technical advantages when performing multi-bit operation. A field effect transistor having a vertical channel is used as a tandem selection transistor for a tandem memory cell, which can simultaneously solve the density and bipolar junction of a conventional lateral channel field effect transistor-limited memory cell array. The problem that the transistor or diode is not easy to operate and control.

100, 200, 300, 400‧‧‧ stereo memory components

101, 301, 401‧‧ ‧ semiconductor substrate

101a‧‧‧Active Area

101b‧‧‧ surrounding area

102, 302, 402‧‧‧ shallow trench isolation structure

103, 303, 403‧‧‧ 垫 矽 layer

104, 304, 404‧‧‧ tantalum nitride layer

105, 305, 409‧‧‧ source line

106‧‧‧First dielectric layer

107‧‧‧ Sacrifice layer

108‧‧‧Second dielectric layer

109, 209, 313, 418‧‧‧through holes

110, 119, 210, 308, 314, 408, 412, 420‧‧ ‧ spacers

111, 315‧‧‧ columnar channel structure

112, 312‧‧‧Oxidized coating

113, 310, 416‧‧‧ hard mask layer

114a, 114b, 114c‧‧‧ planar metal-oxide-semiconductor field effect transistor components

115, 123, 311, 318, 417‧‧ ‧ interlayer dielectric layer

116, 216‧‧‧ strip structure

117‧‧ ‧ alcove

118, 218, 307, 410‧‧ ‧ gate line

120, 415‧‧‧ metal telluride layer

121, 316, 413‧‧ ‧ bungee

122, 222, 317, 414‧‧‧ tandem selection transistor

124, 125, 319, 419 ‧ ‧ contact

126, 320, 422‧‧‧ tandem memory cells

127, 321, 421‧‧‧ memory cell array

127a, 321a, 421a‧‧‧ conductive plane

127b, 321b, 421b‧‧‧ conductive columnar body

127c, 321c, 421c‧‧‧ memory layer

207‧‧‧ conductor layer

305a‧‧‧ heavily doped area

306, 411‧‧ ‧ gate dielectric layer

309‧‧‧矽Oxide layer

405‧‧‧ ridge

406‧‧‧Protruding

407‧‧‧Side etching opening

409a‧‧‧Diffusion zone

409b‧‧‧First source area

409c‧‧‧Second source area

PW‧‧‧P-well zone

NW‧‧‧N-well zone

S1a1, S1a2, S1b1, S1b2, S1c1, S1c2, S1d1, S1d2, S1e1, S1e2, S1f1, S1f2, S1g1, S1g2, S1g3, S1h1, S1h2, S1h3, S1i1, S1i2, S1i3, S1j1, S1j2, S1j3, S1k1 S1k2, S1k3, S2a1, S2a2, S2b1, S2b2, S2c1, S2c2, S2d1, S2d2, S2e1, S2e2, S2e3, S2f1, S2f2, S2f3, S3a, S3b, S3c1, S3c2, S3d1, S3d2, S3e1, S3e2, S3f1 S3f2, S3g1, S3g2, S4a, S4b, S4c1, S4c2, S4c3, S4d1, S4d2, S4d3, S4e1, S4e2, S4e3, S4f1, S4f2, S4f3, S4g1, S4g2, S4g3, S4h1, S4h2, S4h3‧‧

The above-described embodiments and other objects, features and advantages of the present invention will become more apparent from the embodiments of the invention. The top view of the structure of the semiconductor substrate shown in the embodiment; the first A2 is a cross-sectional view taken along the tangential line S1a1 shown in FIG. 1A1; the first AA3 is taken along the tangential line S1a2 shown in FIG. Structural section 1B1 is a top view of the structure after the ion implantation process of the structure of FIG. 1A1; FIG. 1B2 is a structural cross-sectional view taken along the tangential line S1b1 shown in FIG. 1B1; A cross-sectional view of the structure taken along the tangential line S1b2 shown in FIG. 1B1; the first C1 is a structure after forming the patterned first dielectric layer, the sacrificial layer and the second dielectric layer on the structure of the first B1. 1C2 is a structural cross-sectional view taken along the tangential line S1c1 shown in FIG. 1C1; the 1C3 is a cross-sectional view taken along the tangential line S1c2 shown in FIG. 1C1; the 1D1 drawing is shown A top view of the structure after forming a spacer on the structure of the first C1; the first D2 is a cross-sectional view taken along a tangent S1d1 shown in FIG. 1D1; and the first D3 is a tangent along the first D1. FIG. 1E1 is a plan view showing a structure after performing a selective epitaxial growth process on the structure of the first D1; FIG. 1E2 is a structure taken along a tangent S1e1 shown in FIG. section Figure 1E3 is a cross-sectional view of the structure taken along the tangential line S1e2 shown in Fig. 1E1; the first F1 is a diagram showing the formation of a plurality of planar metal-oxide-semiconductor field-effects on the structure of the first E1. a top view of the structure after the crystal element; the first F2 is a cross-sectional view taken along the tangent S1f1 shown in FIG. 1F1; the first F3 is a cross-sectional view taken along the tangent S1f2 shown in the first F1; 1G1 is a top view of the structure of the first dielectric layer, the sacrificial layer and the second dielectric layer in the first F1 after the single patterning process; the first G2 is a tangent along the first G1 A structural sectional view made by S1g1; a 1G3 drawing is a structural sectional view taken along a tangential line S1g2 shown in Fig. 1G1; a 1G4 drawing is a structural sectional view taken along a tangential line S1g3 shown in Fig. 1G1; The 1H1 diagram shows a top view of the structure after removing the sacrificial layer in the 1G1 diagram; the 1H2 diagram is a cross-sectional view of the structure taken along the tangent S1h1 shown in the 1H1 diagram; the 1H3 diagram is along the 1H1 diagram. A cross-sectional view of the structure taken by the tangent S1h2; 1H4 is a structural cross-sectional view taken along a tangent line S1h3 shown in FIG. 1H1; FIG. 1I1 is a plan view showing a structure after forming a plurality of gate lines in the structure of the 1H1 diagram; The structural cross-sectional view of the tangential line S1i1 shown in Fig. 1I1; the 1I3 figure is a structural cross-sectional view taken along the tangential line S1i2 shown in Fig. 1I1; the 1I4 figure is shown along the 1I1 figure. A cross-sectional view of the structure of the tangent S1i3; the first J1 is a top view of the structure after forming the spacer in the structure of the first embodiment; the first J2 is a cross-sectional view taken along the tangent S1j1 of the first J1; 1J3 is a structural cross-sectional view taken along a tangential line S1j2 shown in FIG. 1J1; the first JJ is a structural cross-sectional view taken along a tangent S1j3 shown in FIG. 1J1; the 1K1 is shown in the first a top view of the structure after forming the tandem selection transistor in the structure of FIG. 1J; the first K2 diagram is a structural cross-sectional view taken along the tangent S1k1 shown in FIG. 1K1; 1K3 is a structural sectional view taken along a tangential line S1k2 shown in FIG. 1K1; the 1K4 is a structural sectional view taken along a tangential line S1k3 shown in FIG. 1K1; FIG. 1L is a perspective view according to the present invention. A perspective view of a structure of a three-dimensional memory device according to an embodiment; FIG. 2A is a plan view showing a structure after forming a patterned first dielectric layer, a conductor layer and a second dielectric layer on the structure of FIG. 2A2 is a structural sectional view taken along a tangent line S2a1 shown in FIG. 2A1; 2A3 is a structural sectional view taken along a tangent line S2a2 shown in FIG. 2A1; FIG. 2B1 is shown in FIG. FIG. 2A1 is a plan view showing a structure after forming a spacer; FIG. 2B2 is a structural cross-sectional view taken along a tangent line S2b1 shown in FIG. 2A1; and FIG. 2B3 is a tangent S2b2 shown along FIG. 2B1. FIG. 2C1 is a plan view showing a structure after performing a selective epitaxial growth process on the structure of FIG. 2B1; and FIG. 2C2 is a structural section taken along a tangent line S2c1 shown in FIG. 2C1. Figure 2; Figure 2C3 is taken along the tangent S2c2 shown in Figure 2C1 Structural section 2D1 is a top view of a structure after forming a plurality of planar metal-oxide-semiconductor field effect transistor elements on the structure of the 2C1; the 2D2 figure is shown along the 2D1 figure. The structural cross-sectional view made by the tangent line S2d1; the 2D3 figure is a structural cross-sectional view taken along the tangent line S2d2 shown in FIG. 2D1; the 2E1 figure shows the first dielectric layer again on the structure of the 2D1 figure. a top view of the structure after the patterning process of the conductor layer and the second dielectric layer; the second E2 figure is a structural cross-sectional view taken along the tangent line S2e1 shown in FIG. 2E1; and the second E3 figure is drawn along the 2E1 figure. A cross-sectional view of the structure shown by the tangent line S2e2; the second E4 figure is a cross-sectional view taken along the tangent line S2e3 shown in FIG. 2E1; and the second F1 figure shows the formation of the tandem selection transistor in the structure of the second E1 figure. The rear view of the structure; the second F2 is a structural cross-sectional view taken along the tangential line S2f1 shown in the second F1; the second F3 is a cross-sectional view taken along the tangential line S2f2 shown in the second F1; a structural cross-sectional view taken along a tangent line S2f3 depicted in FIG. 2F1; 2G is a stereo memory element according to another embodiment of the present invention. 3A1 is a top view of a structure of a semiconductor substrate according to an embodiment of the present invention; and 3A2 is a cross-sectional view of a structure taken along a tangential line S3a shown in FIG. 3A1; 3B1 is a top view of the structure after the ion implantation process of the structure of FIG. 3A1; FIG. 3B2 is a structural cross-sectional view taken along the tangential line S3b shown in FIG. 3B1; FIG. 3C1 is shown in the figure 3A1 is a top view of the structure after forming the gate dielectric layer 306 and the gate line; the 3C2 is a structural cross-sectional view taken along the tangent line S3c1 shown in FIG. 3C1; and the 3C3 is along the 3C1 diagram. The structural cross-sectional view of the tangent line S3c2 is shown; the 3D1 figure shows the top view of the structure after the structure of the 3C1 is covered with the tantalum oxide layer 309 and the tantalum nitride hard mask layer; the 3D2 figure is along the 3D1 is a cross-sectional view of the structure taken by the tangential line S3d1; the 3D3 is a cross-sectional view taken along the tangential line S3d2 shown in FIG. 3D1; and the 3E1 is shown on the structure of the 3D1. a top view of the structure after the conventional perforation 313 and the spacer; the 3E2 is along the 3E1 The structural section of the tangent S3e1 shown in the figure 3E3 is a structural cross-sectional view taken along a tangent line S3e2 shown in FIG. 3E1; FIG. 3F1 is a top view showing a structure after forming a columnar channel structure in the structure of the 3E1; 3F2 The structural cross-sectional view taken along the tangential line S3f1 shown in FIG. 3F1; the 3F3 is a structural cross-sectional view taken along the tangential line S3f2 shown in FIG. 3F1; the 3G1 drawing is shown in the 3F1 The top view of the structure after forming the tandem selection transistor in the structure; the 3G2 figure is a structural cross-sectional view taken along the tangential line S3g1 shown in the 3G1 figure; the 3G3 figure is made along the tangential line S3g2 shown in the 3G1 figure. 3H is a perspective view of a structure of a three-dimensional memory device according to another embodiment of the present invention; and FIG. 4A1 is a structure of a semiconductor substrate according to an embodiment of the invention. 4A2 is a structural cross-sectional view taken along the tangential line S4a shown in FIG. 4A1; FIG. 4B1 is a view showing the structure after the etching process is performed on the structure of the 4A1, and a part of the shallow trench isolation structure is removed. Top view; Figure 4B2 is shown along Figure 4B1 Structural section made by tangent S4b Figure 4C1 is a plan view showing the structure after the etching process is performed on the structure of the 4B1, and a part of the ridges is removed; and the 4C2 is a cross-sectional view of the structure taken along the tangential line S4c1 shown in Fig. 4C1. 4C3 is a structural cross-sectional view taken along a tangent line S4c2 shown in FIG. 4C1; FIG. 4C4 is a cross-sectional view taken along a tangent line S4c3 shown in FIG. 4C1; FIG. 4D1 is shown in FIG. 4A1 is a top view of the structure after forming a side etching opening; 4D2 is a structural sectional view taken along a tangent line S4d1 shown in FIG. 4D1; and 4D3 is a tangent shown along the 4D1 drawing. The structural cross-sectional view made by S4d2; the 4D4 is a structural cross-sectional view taken along the tangential line S4d3 shown in FIG. 4D1; and the 4E1 is a top view of the structure after the source line is formed on the structure of the 4D1; 4E2 is a structural sectional view taken along a tangential line S4e1 shown in FIG. 4E1; and FIG. 4E3 is a structural sectional view taken along a tangential line S4e2 shown in FIG. 4E1; 4E4 is a structural cross-sectional view taken along line S4e3 shown in FIG. 4E1; FIG. 4F1 is a plan view showing a structure after forming a gate line on the structure of FIG. 4E1; 4F1 is a cross-sectional view of the structure taken by the tangential line S4f1; the 4F3 is a cross-sectional view taken along the tangential line S4f2 shown in FIG. 4F1; the 4F4 is a tangential line S4f3 shown along the 4F1 FIG. 4G1 is a plan view showing a structure after forming a plurality of tandem selection transistors in the structure of FIG. 4F1; and FIG. 4G2 is a structure along a tangent S4g1 shown in FIG. 4G1. The cross-sectional view; the fourth G3 is a structural cross-sectional view taken along the tangential line S4g2 shown in Fig. 4G1; the fourth G4 is a structural cross-sectional view taken along the tangential line S4g3 shown in Fig. 4G1; The top view of the structure after forming a plurality of contact plugs in the structure of FIG. 4G1; the fourth H2 figure is a structural cross-sectional view taken along the tangent line S4h1 shown in FIG. 4H1; the fourth H3 figure is along the 4th H1 figure. A cross-sectional view of the structure taken by the tangent S4h2; 4H4 is a structural sectional view taken along a tangential line S4h3 shown in FIG. 4H1; and FIG. 4I is a perspective view showing a structure of a three-dimensional memory element according to still another embodiment of the present invention.

The invention provides a three-dimensional memory component and a manufacturing method thereof, which can solve the problems of the density of the conventional lateral channel field effect transistor-limited memory cell array and the difficulty in operation control of the bipolar junction transistor or the diode. The above-described embodiments and other objects, features and advantages of the present invention will become more apparent and understood.

However, it must be noted that these specific embodiments and methods are not intended to limit the invention. The invention may be practiced with other features, elements, methods and parameters. The preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the invention. Equivalent modifications and variations will be made without departing from the spirit and scope of the invention. In the different embodiments and the drawings, the same elements will be denoted by the same reference numerals.

A method of fabricating a stereo memory device 100 is provided in accordance with an embodiment of the present invention. It comprises the steps of first providing a semiconductor substrate 101 such that the semiconductor substrate 101 has an active region 101a and a peripheral region 101b, and A plurality of Shallow Trench Isolation (STI) 102 are formed in the conductor substrate 101.

Referring to FIGS. 1A1 to 1A3, FIG. 1A is a plan view showing a structure of a semiconductor substrate 101 according to an embodiment of the present invention; and FIG. 1A2 is a tangent S1a1 shown in FIG. 1A1. A cross-sectional view of the structure; and a cross-sectional view of the structure taken along line S1a2 shown in Fig. 1A1.

In some embodiments of the present invention, as shown in FIGS. 1A2 and 1A3, after the shallow trench isolation structure 102 is formed, padding is preferably formed on the surface of the semiconductor substrate 101 and the shallow trench isolation structure 102. The pad oxide layer 103 and the tantalum nitride layer 104 are formed as a stop layer by the shallow trench isolation structure 102, and the shallow trench isolation structure 102 is planarized, for example, chemical mechanical polishing (CMP).

After removing the tantalum nitride layer 104, at least one ion implantation process is performed on the active region 101a and the peripheral region 101b of the substrate 101, respectively. Referring to FIGS. 1B1 to 1B3, FIG. 1B1 is a plan view showing the structure after the ion implantation process of the structure of FIG. 1A; FIG. 1B2 is a structure taken along the tangent S1b1 shown in FIG. 1B1. The cross-sectional view; and the 1B3 figure is a cross-sectional view of the structure taken along the tangent S1b2 shown in Fig. 1B1.

By the ion implantation process, a P-type well region PW and an N-type well region NW can be formed in the substrate 101 of the peripheral region 101b. A P-type well region PW and an N-type doped layer in the P-type well region PW are formed in the substrate 101 of the active region 101a. In some embodiments of the invention, active area 101a and surrounding The P-type well region PW and the N-type well region NW of the region 101b can be formed by the same doping portions, respectively. In addition, in the embodiment, since the shallow trench isolation structure 102 is strip-shaped, the N-type doped layer in the active region 101a can be divided into a plurality of parallel shallow trench isolation structures 102, which can be used as a stereo memory component. The source line 105 of 100.

After the pad layer 103 is removed, a patterned first dielectric layer 106, a sacrificial layer 107, and a second dielectric layer 108 are formed on the surface of the substrate 101. Referring to FIGS. 1C1 to 1C3, FIG. 1C1 is a plan view showing a structure after forming the patterned first dielectric layer 106, the sacrificial layer 107, and the second dielectric layer 108 on the structure of the first B1; The figure is a structural cross-sectional view taken along the tangential line S1c1 shown in Fig. 1C1; and the 1C3 figure is a structural cross-sectional view taken along the tangential line S1c2 shown in Fig. 1C1.

The patterned first dielectric layer 106, the sacrificial layer 107, and the second dielectric layer 108 include the steps of sequentially forming a first dielectric layer 106 and a sacrificial layer stacked on each other on the surface of the substrate 101. 107 and a second dielectric layer 108. Then, the first dielectric layer 106, the sacrificial layer 107 and the second dielectric layer 108 are etched, and a plurality of through holes 109 are formed in the active region 101a, through the first dielectric layer 106, the sacrificial layer 107 and the second dielectric. Layer 108 and exposes a portion of source line 105 to the outside.

Then, the spacer 110 is formed on a portion where the sacrificial layer 107 is exposed through the through hole 109. Referring to FIGS. 1D1 to 1D3, FIG. 1D1 is a plan view showing a structure after the spacer 110 is formed on the structure of the 1C1; the 1D2 is a structure along the tangent S1d1 shown in FIG. Sectional view And the 1D3 figure is a structural cross-sectional view taken along the tangential line S1d2 shown in FIG. 1D1.

In some embodiments of the present invention, the step of forming the spacers 110 includes the steps of first performing a thermal oxidation process (eg, an in situ steam generation (ISSG) oxidation process) or a deposition process in the through holes. A sidewall oxide layer is formed on the sidewall of the 109 and the source line 105 exposed through the via 109. A portion of the source line 105 is again exposed by an anisotropic etch, such as a dry etch step, to remove the tantalum oxide layer overlying the exposed source line 105. At the same time, a portion of the tantalum oxide layer formed on the sidewall of the sacrificial layer 107 exposed through the through hole 109 is left as the spacer 110.

Next, a selective 矽 or 矽锗 (SiGex) epitaxial growth process is performed. Referring to FIGS. 1E1 to 1E3, FIG. 1E1 is a plan view showing a structure after performing a selective epitaxial growth process on the structure of the first D1; FIG. 1E2 is a tangent S1e1 along the first E1 diagram. A structural sectional view taken; and a 1E3 drawing is a structural sectional view taken along a tangent S1e2 shown in Fig. 1E1. Polycrystalline germanium is deposited in each of the through holes 109 by a selective epitaxial growth process to form a columnar channel structure 111. In this embodiment, the germanium or germanium epitaxial growth process is performed on the surface of the second dielectric layer 108, and after the germanium or germanium epitaxial growth process, the second mechanical dielectric polishing is removed. The epitaxial growth on the surface of the dielectric layer 108 is 矽 or 矽锗, leaving only the epitaxial growth 矽 or 位于 in the through hole 109.

Thereafter, a plurality of planar metal-oxide-semiconductor field effect transistors (Metal-Oxide-Semiconductor) are formed in the peripheral region 101b. Field-Effect Transistor (MOSFET) elements 114a, 114b and 114c. Referring to FIGS. 1F1 to 1F3, FIG. 1F1 is a plan view showing a structure after forming a plurality of planar metal-oxide-semiconductor field effect transistor elements 114a, 114b, and 114c on the structure of FIG. 1F2 is a structural sectional view taken along a tangent S1f1 shown in FIG. 1F1; and a 1F3 is a structural sectional view taken along a tangent S1f2 shown in FIG.

In the present embodiment, the formation of the planar metal-oxide-semiconductor field effect transistor elements 114a, 114b, and 114c includes the steps of first covering the substrate 101 with an oxide cap layer 112 for protecting the active region 101a and A tantalum nitride hard mask layer 113. After removing a portion of the oxide cap layer 112 and a portion of the hard mask layer 113 on the peripheral region 101b, planar N-type metal-oxide-semiconductor field effect transistor elements 114a and 114b are formed in the peripheral region 101b. P-type metal-oxide-semiconductor field effect transistor element 114c; and overlying interlayer metal-oxide-semiconductor field effect transistor elements 114a, 114b and 114c overlying interlayer dielectric (Inter-Layer Dielectric, ILD) 115 And planarizing with the hard mask layer 113 as a stop layer.

Referring to FIGS. 1G1 to 1G4, FIG. 1G1 is a plan view showing a structure after the first dielectric layer 106, the sacrificial layer 107, and the second dielectric layer 108 in the first F1 pattern are further patterned; 1G2 is a structural cross-sectional view taken along the tangential line S1g1 shown in FIG. 1G1; the 1G3 is a structural cross-sectional view taken along the tangential line S1g2 shown in FIG. 1G1; and the 1G4 image is along the first A structural cross-sectional view of the tangent S1g3 shown in Fig. 1G1. In this embodiment, The patterning process retains a portion of the first dielectric layer 106, a portion of the sacrificial layer 107, and a portion of the second dielectric layer 108 surrounding the perimeter of the columnar channel structure 111 to form a plurality of strip structures 116 that intersect the source lines 105.

Next, the remaining sacrificial layer 107 is removed. Referring to FIGS. 1H1 to 1H4, the 1H1 is a top view of the structure after removing the sacrificial layer 107 in the 1G1 diagram; the 1H2 is a structural section taken along the tangent S1h1 shown in the 1H1 diagram. Fig. 1H3 is a structural sectional view taken along a tangent line S1h2 shown in Fig. 1H1; and a sectional view taken along a tangent line S1h3 shown in Fig. 1H1. In the present embodiment, while the remaining sacrificial layer 107 is removed, the remaining hard mask layer 113 is removed together, and a spacer wall 110 and a columnar channel are formed in each strip structure 116. The recess 117 of the structure 111. In general, the sacrificial layer 107 is composed of tantalum nitride and has a higher etching selectivity with respect to tantalum and niobium oxide, which can be removed by hot phosphoric acid (H ₃ PO ₄ ).

Subsequently, a plurality of gate lines 118 are formed. Referring to FIGS. 1I1 to 1I4, FIG. 1I1 is a plan view showing a structure in which a plurality of gate lines 118 are formed in the structure of FIG. 1H1; and 1I2 is a tangent S1i1 shown along FIG. A cross-sectional view of the structure is taken; a 1A3 diagram is a cross-sectional view taken along a tangent line S1i2 shown in FIG. 1I1; and a 1A4 diagram is a cross-sectional view taken along a tangent S1i3 shown in FIG.

In the present embodiment, the formation of the gate line 118 includes the steps of first forming a conductive material in the trench between adjacent strip structures 116, such as Polycrystalline germanium, metal (such as tungsten (W)), alloy, metal nitride (such as titanium nitride (TiN)) or any combination of the above (wherein a combination of titanium nitride / tungsten is preferred), thereby filling each Alcove 117. Subsequent etchback is performed to remove a portion of the conductive material leaving only the conductive material in the recess 117 to form a plurality of strips that radially surround the gate lines 118 corresponding to the spacers 110 and the columnar channel structures 111, respectively. The gate line 118 intersects the source line 105 and is electrically isolated from each other by the first dielectric layer 106. In addition, the gate line 118 is also electrically isolated by the spacer 110 and the columnar channel structure 111. The combination of gate line 118 and strip structure 116 may be referred to as a surrounding gate structure that substantially reduces the resistance of gate line 118.

In some embodiments of the present invention, it is preferable to selectively form a spacer 119 made of tantalum nitride around the strip structure 116. Referring to FIGS. 1J1 to 1J4, the first JJ is a plan view showing a structure in which the spacers 119 are formed in the structure of the first embodiment, and the first J2 is a structure along the tangent S1j1 shown in FIG. A cross-sectional view; a 1J3 figure is a structural cross-sectional view taken along a tangent line S1j2 shown in Fig. 1J1; and a 1J4 figure is a cross-sectional view taken along a tangent line S1j3 shown in Fig. 1J1.

In this embodiment, a portion of the first dielectric layer 106 between the two adjacent strip structures 116 must be removed prior to forming the spacers 119 to expose a portion of the source lines 105. After the spacers 119 are formed, the metal halide layer 120 may preferably be formed on the source lines 105 exposed to the outside to reduce the resistance of the source lines 105.

Thereafter, a bungee is formed at the top end of each of the columnar channel structures 111. 121, whereby a plurality of tandem selection transistors 122 having a vertical channel structure are formed in the active region 101a. Referring to FIG. 1K1 to FIG. 1K4, FIG. 1K1 is a plan view showing a structure after forming the tandem selection transistor 122 in the structure of the first J1 diagram; the first K2 diagram is a tangent S1k1 along the first K1 diagram. A cross-sectional view of the structure taken; a 1K3 figure is a cross-sectional view taken along a tangent line S1k2 shown in Fig. 1K1; and a 1K4 figure is a cross-sectional view taken along a tangent S1k3 shown in Fig. 1K1.

After the tandem selection transistor 122 is formed, a planarized interlayer dielectric layer 123 is preferably formed on the active region 101a and the peripheral region 101b, and a plurality of contact plugs 124 are formed in the interlayer dielectric layer 123. The planar metal-oxide-semiconductor field effect transistor elements 114a, 114b, and 114c are connected to external components or circuits (not shown). A plurality of contact plugs 125 are formed in the interlayer dielectric layer 123 for connecting the serial selection transistor 122 to a plurality of serially connected memory cells 126 formed on the active region 101a.

Referring to FIG. 1L, a first perspective view is a perspective view of a three-dimensional memory device 100 according to an embodiment of the invention. A plurality of tandem memory cells 126 are formed in the stereo memory cell array 127 above the structure depicted in Figures 1K1 through 1K4. And each of the series memory cells 126 is connected in series with the drain 121 of the top of the columnar channel structure 111 of one of the tandem selection transistors 122.

In this embodiment, the memory cell array 127 includes a plurality of conductive planar layers 127a stacked in parallel and electrically isolated from each other, a plurality of conductive pillars 127b penetrating through the plurality of conductive planar layers, and a conductive planar layer. 127a and guide The memory layer 127c between the electric pillars 127b. Each of the series memory cells 126 is formed at the intersection of each of the conductive pillars 127b, the memory layer 127c, and the different conductive plane layers 127a. The serially connected memory cells 126 are connected in series with the drain electrodes 121 of the tandem selection transistors 122 located under the three-dimensional memory cell array 127 by the conductive columns 127b.

It should be noted that the foregoing memory cell array 127 is not limited thereto, and any vertical memory cell array having vertical channels can be applied in series with the serial selection transistor 122 to fabricate the stereo memory device 100. .

Another method of making a stereoscopic memory element 200 is provided in accordance with another embodiment of the present invention. Among them, the method of fabricating the three-dimensional memory element 200 is substantially similar to the method of fabricating the three-dimensional memory element 100, with the difference that the manner in which the gate lines are formed is different. Since the manner of forming the semiconductor substrate 101, the shallow trench isolation structure 102, and the source line 105 has been described as before (as shown in FIGS. 1A1 to 1B3), the same steps will not be described again. A method of fabricating the stereo memory device 200 will be described with reference to FIGS. 1B1 through 1B3.

First, a patterned first dielectric layer 106, a conductor layer 207, and a second dielectric layer 108 are formed on the structure of FIG. 1B1. Referring to FIGS. 2A1 to 2A3, FIG. 2A1 is a plan view showing a structure after forming the patterned first dielectric layer 106, the conductor layer 207, and the second dielectric layer 108 on the structure of the first B1; 2A2 is a structural sectional view taken along a tangent line S2a1 shown in FIG. 2A1; and 2A3 is a structural sectional view taken along a tangent line S2a2 shown in FIG. 2A1.

In this embodiment, the patterned first dielectric layer 106 is formed and guided. The bulk layer 207 and the second dielectric layer 108 include the steps of first forming a first dielectric layer 106, a sacrificial layer 107, and a second dielectric layer 108 which are sequentially stacked on the surface of the substrate 101. A plurality of through holes 209 are formed in the active region 101a by an etching process, through the first dielectric layer 106, the conductor layer 207, and the second dielectric layer 108, and a portion of the source lines 105 are exposed.

Then, a spacer 210 is formed on a portion of the conductor layer 207 that is exposed through the through hole 209. Referring to FIGS. 2B1 to 2B3, FIG. 2B1 is a plan view showing a structure after the spacer 210 is formed on the structure of FIG. 2A; and FIG. 2B is a structure taken along a tangent S2b1 shown in FIG. 2A1. The cross-sectional view; and the 2B3 figure are structural cross-sectional views taken along the tangent S2b2 shown in FIG. 2B1.

In some embodiments of the present invention, the step of forming the spacers 210 includes first forming a tantalum oxide layer on the sidewalls of the through vias 209 by a thermal oxidation process or a deposition process. A portion of the source line 105 is again exposed by an anisotropic etch, such as a dry etch step, to remove the tantalum oxide layer overlying the bottom of the via 209. At the same time, a portion of the tantalum oxide layer formed on the sidewall of the conductor layer 207 exposed through the through hole 209 is left as the spacer 210.

Next, a selective 矽 or 矽锗 epitaxial growth process is performed. Referring to FIGS. 2C1 to 2C3, the second C1 is a top view of the structure after performing the selective epitaxial growth process on the structure of the second B1; the second C2 is a tangent S2c1 along the second C1. The structural cross-sectional view made; and the 2C3 figure is a structural cross-sectional view taken along the tangential line S2c2 shown in Fig. 2C1. By choosing In the epitaxial growth process, polycrystalline germanium is deposited in each of the through holes 209 to form a columnar channel structure 111. In this embodiment, the germanium or germanium epitaxial growth process is performed on the surface of the second dielectric layer 108, and after the germanium or germanium epitaxial growth process, the second mechanical dielectric polishing is removed. The epitaxial growth on the surface of the dielectric layer 108 is 矽 or 矽锗, leaving only the epitaxial growth 矽 or 位于 in the through hole 209.

Thereafter, a plurality of planar metal-oxide-semiconductor field effect transistor elements 114a, 114b, and 114c are formed in the peripheral region 101b. Referring to FIGS. 2D1 to 2D3, FIG. 2D1 is a plan view showing a structure after forming a plurality of planar metal-oxide-semiconductor field effect transistor elements 114a, 114b, and 114c on the structure of the 2C1; 2D2 is a structural sectional view taken along a tangent line S2d1 shown in FIG. 2D1; and 2D3 is a structural sectional view taken along a tangent line S2d2 shown in FIG. 2D1.

In some embodiments of the invention, the steps of forming planar metal-oxide-semiconductor field effect transistor elements 114a, 114b, and 114c in peripheral region 101b include first overlying substrate 101 for protecting active region 101a. The oxide cap layer 112 and the tantalum nitride hard mask layer 113. After removing a portion of the oxide cap layer 112 and a portion of the hard mask layer 113 on the peripheral region 101b, planar N-type metal-oxide-semiconductor field effect transistor elements 114a and 114b are formed in the peripheral region 101b. P-type metal-oxide-semiconductor field effect transistor element 114c.

Referring to FIGS. 2E1 to 2E4, FIG. 2E1 illustrates the structure after patterning the first dielectric layer 106, the conductor layer 207, and the second dielectric layer 108 again on the structure of the second D1. Top view; 2E2 is along the first 2E1 is a cross-sectional view of the structure taken by the tangent S2e1; the 2E3 is a cross-sectional view taken along the tangent S2e2 shown in FIG. 2E1; and the 2E4 is a tangent shown along the 2E1. A structural section view made by S2e3.

In the present embodiment, the patterning process retains a portion of the first dielectric layer 106, a portion of the conductor layer 207, and a portion of the second dielectric layer 108 surrounding the perimeter of the columnar channel structure 111, forming a plurality of stripes crossing the source line 105. Strip structure 216. Wherein, the remaining conductor layer 207 forms a plurality of gate lines 218 in the strip structure 216 radially surrounding the corresponding spacers 210 and the columnar channel structures 111, respectively. The gate line 218 intersects the source line 105 and is electrically isolated from each other by the first dielectric layer 106. In addition, the gate line 218 is also electrically isolated by the spacer 210 and the columnar channel structure 111.

Thereafter, a drain electrode 121 is formed at the top end of each of the columnar channel structures 111, thereby forming a plurality of tandem selection transistors 222 having a vertical channel structure in the active region 101a. Referring to FIGS. 2F1 to 2F4, FIG. 2F1 is a plan view showing a structure in which the tandem selection transistor 222 is formed in the structure of the second E1 diagram; and the second F2 is a tangent S2f1 along the second F1 diagram. A cross-sectional view of the structure is made; a 2F3 figure is a cross-sectional view taken along a tangent line S2f2 shown in FIG. 2F1; and a 2F4 figure is a cross-sectional view taken along a tangent line S2f3 shown in FIG.

In some embodiments of the invention, the metal telluride layer 120 may preferably be formed on the source line 105 that is exposed to reduce the resistance of the source line 105. After forming the tandem selection transistor 222, it is preferred to be in the active region 101a and the periphery. A planarized interlayer dielectric layer 123 is formed on the sidewall region 101b, and a plurality of contact plugs 124 are formed in the interlayer dielectric layer 123 for planar metal-oxide-semiconductor field effect transistor elements 114a, 114b and 114c. Connected to external components or circuits (not shown). Moreover, a plurality of contact plugs 125 are formed in the interlayer dielectric layer 123 for connecting the serial selection transistor 222 to a plurality of serially connected memory cells 126 formed subsequently over the active region 101a.

Referring to FIG. 2G, FIG. 2G is a perspective view showing a structure of a three-dimensional memory device 200 according to another embodiment of the present invention. A plurality of serially connected memory cells 126 are formed in the three-dimensional memory cell array 127 above the structure depicted in Figures 2F1 to 2F4. And each of the serial memory cells 126 is connected in series with the drain 121 of the top of the columnar channel structure 111 of one of the tandem selection transistors 222.

In this embodiment, the memory cell array 127 includes a plurality of conductive planar layers 127a stacked in parallel and electrically isolated from each other, a plurality of conductive pillars 127b penetrating through the plurality of conductive planar layers, and a conductive planar layer. The memory layer 127c between the 127a and the conductive column 127b. Each of the series memory cells 126 is formed at the intersection of each of the conductive pillars 127b, the memory layer 127c, and the different conductive plane layers 127a. The serially connected memory cells 126 are connected in series with the drain electrodes 121 of the tandem selection transistors 122 located under the three-dimensional memory cell array 127 by the conductive columns 127b.

A method of making a stereoscopic memory element 300 is further provided in accordance with yet another embodiment of the present invention. It includes the steps of first providing a semiconductor substrate 301 and forming a plurality of shallow trench isolation structures 302 in the semiconductor substrate 301. Please refer to section 3A1 3A2, FIG. 3A1 is a plan view showing a structure of a semiconductor substrate 301 according to an embodiment of the present invention; and FIG. 3A2 is a structural cross-sectional view taken along a line S3a shown in FIG. 3A1. .

In some embodiments of the present invention, as shown in FIG. 3A2, after forming the shallow trench isolation structure 302, a padded germanium layer 303 and nitrogen are preferably formed on the surface of the semiconductor substrate 301 and the shallow trench isolation structure 302. The ruthenium layer 304 is formed and the ruthenium nitride layer 304 is used as a stop layer to planarize the shallow trench isolation structure 302, such as chemical mechanical polishing.

Next, the tantalum nitride layer 304 is removed, and the semiconductor substrate 301 is subjected to at least one ion implantation process. Referring to FIGS. 3B1 to 3B2, FIG. 3B1 is a plan view showing the structure after the ion implantation process of the structure of FIG. 3A1; and FIG. 3B2 is performed along the tangential line S3b shown in FIG. 3B1. Structural profile. A P-type well region PW and an N-type doped layer in the P-type well region PW can be formed in the semiconductor substrate 301 by an ion implantation process. In the present embodiment, since the shallow trench isolation structure 302 is strip-shaped, the N-type doped layer in the semiconductor substrate 301 can be divided into regions of a plurality of parallel shallow trench isolation structures 302, which can be used as the stereo memory device 300. Source line 305.

Then, a gate dielectric layer 306 and a plurality of gate lines 307 are sequentially stacked over the semiconductor substrate 301. Referring to FIGS. 3C1 to 3C3, FIG. 3C1 is a plan view showing the structure after forming the gate dielectric layer 306 and the gate line 307 on the structure of the 3B1; the 3C2 drawing is along the 3C1 drawing. A cross-sectional view of the structure taken by the tangent S3c1; and a third C3 figure is shown along the 3C1 A cross-sectional view of the structure made by the tangent S3c2.

In this embodiment, the formation of the gate dielectric layer 306 and the gate line 307 includes: sequentially forming a dielectric layer and a conductive layer over the semiconductor substrate 301, and then patterning the dielectric layer and the conductive layer. The gate dielectric layer 306 and the gate line 307 crossing the source line 305 are defined on the semiconductor substrate 301, and the gate line 307 and the source line 305 are electrically isolated from each other by the gate dielectric layer 306.

After forming the gate dielectric layer 306 and the gate line 307, it is preferable to form the spacer 308 around the gate line 307, and use the gate line 307 and the spacer 308 as a mask to perform another ion implantation process. A plurality of heavily doped regions 305a are formed in a portion where the source line 305 does not overlap the gate line 307 and the spacer 308. In the present embodiment, the heavily doped region 305a is an N-type heavily doped region having a doping concentration substantially greater than the source line 305.

Thereafter, the base material 101 is covered with a tantalum oxide layer 309 and a tantalum nitride hard mask layer 310. Please refer to FIGS. 3D1 to 3D3. FIG. 3D1 is a diagram showing the structure of the 3C1 layer covered with tantalum oxide. A top view of the structure after the layer 309 and the tantalum nitride hard mask layer 310; the 3D2 figure is a structural cross-sectional view taken along the tangent line S3d1 shown in FIG. 3D1; and the 3D3 figure is shown along the 3D1 figure. A cross-sectional view of the structure made by the tangent S3d2.

After forming the tantalum oxide layer 309 and the tantalum nitride hard mask layer 310, an interlayer dielectric layer 311 is preferably covered on the tantalum nitride hard mask layer 310, and a planarization process is performed; The interlayer dielectric layer 311 is covered with an oxide coating layer 312. By oxidizing the cap layer 312, the interlayer dielectric layer 311, and the tantalum oxide layer The protection of 309 and the tantalum nitride hard mask layer 310 ensures that the gate line 307 and the source line 305 are not affected by subsequent processing in the peripheral region (not shown). Among other processes performed in the peripheral region (not shown), for example, a process for forming a plurality of planar metal-oxide-semiconductor field effect transistor elements (not shown) can be used.

Thereafter, at least one through hole 313 is formed in each of the gate lines 307, and a spacer 314 is formed in each of the through holes 313. Referring to FIGS. 3E1 to 3E3, FIG. 3E1 is a plan view showing a structure after forming the conventional perforation 313 and the spacer 314 on the structure of the 3D1; and the 3E2 is a tangent shown along the 3E1. A structural sectional view made by S3e1; and a 3E3 drawing is a structural sectional view taken along the tangential line S3e2 shown in Fig. 3E1.

In some embodiments of the present invention, a dry etching, such as a reactive ion etching (RIE) process, is preferably used to form an opening at each intersection of the gate line 307 and the source line 305 (through holes). 313), extending through the oxide cap layer 312, the interlayer dielectric layer 311, the tantalum nitride hard mask layer 310, the tantalum oxide layer 309, and the gate line 307, exposing a portion of the corresponding source line 305 to the outside. A spacer 314 made of tantalum oxide is formed on the sidewall of each of the through holes 313 by a thermal oxidation process or a deposition process.

Next, a selective 矽 or 矽锗 epitaxial growth process is performed, and a columnar channel structure 315 is formed in each of the through holes 313. Referring to FIGS. 3F1 to 3F3, FIG. 3F1 is a plan view showing the structure after forming the columnar channel structure 315 in the structure of FIG. 3E1; and FIG. 3F2 is taken along the tangential line S3f1 shown in FIG. 3F1. a structural section view; and a 3F3 diagram along the 3F1 map A cross-sectional view of the structure taken by the tangent S3f2. In the present embodiment, the selective epitaxial growth process deposits polysilicon in each of the through holes 313, thereby forming a columnar channel structure 315 in each of the through holes 313, and the bottom of each of the columnar channel structures 315 is The source lines 305 are connected. In the present embodiment, the germanium or germanium epitaxial growth process is performed on the surface of the oxide cap layer 312, and after the germanium or germanium epitaxial growth process, the oxide cap layer 312 is removed by chemical mechanical polishing. The epitaxial growth on the surface is 矽 or 矽锗, leaving only the epitaxial growth 矽 or 位于 in the through hole 313.

Thereafter, a drain 316 is formed at the top end of each of the columnar channel structures 315, thereby forming a plurality of tandem selection transistors 317 having a vertical channel structure on the semiconductor substrate 301. Referring to FIGS. 3G1 to 3G3, the 3G1 is a top view of the structure after forming the tandem selection transistor 317 in the structure of the 3F1; the 3G2 is a tangent S3g1 along the 3G1 diagram. The structural sectional view made; and the 3G3 figure is a structural sectional view taken along the tangential line S3g2 shown in Fig. 3G1.

After the tandem selection transistor 317 is formed, a planarized interlayer dielectric layer 318 is preferably formed on the substrate 301, and a plurality of contact plugs 319 are formed in the interlayer dielectric layer 318 for aligning the strings. The selection transistor 317 is connected to a plurality of serially connected memory cells 320 that are subsequently formed over the semiconductor substrate 301. Referring to FIG. 3H, FIG. 3H is a perspective view showing the structure of a three-dimensional memory device 300 according to still another embodiment of the present invention. A plurality of tandem memory cells 320 are formed in the three-dimensional memory cell array 321 above the structures illustrated in the third G1 to the third G3. And every A serial memory cell 320 is coupled in series with the drain 316 at the top of the columnar channel structure of the corresponding tandem selection transistor 317.

In this embodiment, the memory cell array 321 includes a plurality of conductive planar layers 321a stacked in parallel and electrically isolated from each other, a plurality of conductive pillars 321b penetrating through the plurality of conductive planar layers, and a conductive planar layer 321a. And a memory layer 321c between the conductive pillars 321b. Each of the series memory cells 320 is formed at the intersection of each of the conductive pillars 321b, the memory layer 321c, and the different conductive plane layers 321a. Each of the tandem memory cells 320 is connected in series with the drain 316 of the tandem selection transistor 317 located under the three-dimensional memory cell array 321 by the conductive pillars 321b.

A method of making a stereo memory component 400 is provided in accordance with yet another embodiment of the present invention. It includes the steps of first providing a semiconductor substrate 401 and forming a plurality of shallow trench isolation structures 402 in the semiconductor substrate 401. Referring to FIGS. 4A1 to 4A2, FIG. 4A1 is a plan view showing a structure of a semiconductor substrate 401 according to an embodiment of the present invention; and FIG. 4A2 is a tangent S4a shown in FIG. 4A1. Structural section view.

In some embodiments of the present invention, as shown in FIG. 4A2, after forming the shallow trench isolation structure 402, a padded germanium layer 403 and nitrogen are preferably formed on the surface of the semiconductor substrate 401 and the shallow trench isolation structure 402. The ruthenium layer 404 is formed and the ruthenium nitride layer 404 is used as a stop layer to planarize the shallow trench isolation structure 402, such as chemical mechanical polishing.

Next, an etching process is performed to remove a portion of the shallow trench isolation Structure 403. Referring to FIGS. 4B1 to 4B2, FIG. 4B1 is a plan view showing the structure after the etching process is performed on the structure of FIG. 4A1, and a part of the shallow trench isolation structure 403 is removed; and the 4B2 diagram is along the 4B1 diagram. A cross-sectional view of the structure taken by the tangent S4b. In this embodiment, the etching process removes the upper portion of each shallow trench isolation structure 403, leaving a lower portion of the shallow trench isolation structure 403, thereby forming a plurality of ridges 405 in the semiconductor substrate 401. Parallel to the remaining shallow trench isolation structures 402.

Another etching process is performed to remove a portion of the ridges 405. Referring to FIGS. 4C1 to 4C4, FIG. 4C1 is a plan view showing a structure in which another etching process is performed on the structure of FIG. 4B1, and a part of the ridges 405 is removed; and the 4C2 is along the 4C1. A cross-sectional view of the structure taken by the tangent S4c1; the fourth C3 is a cross-sectional view taken along the tangent S4c2 shown in FIG. 4C1; and the fourth C4 is taken along the tangent S4c3 shown in FIG. 4C1. Structural section view.

In this embodiment, the etching process includes the steps of first filling a recess formed by removing a portion of the shallow trench isolation structure 402 by using a planarized organic dielectric layer (not shown). The remaining shallow trench isolation structure 402 is an etch stop layer, which is etched by a patterned photoresist layer (not shown) to remove a portion of the ridges 405, thereby forming a plurality of protrusions 406 on the surface of the semiconductor substrate 401.

Next, at least one undercut 407 is formed under each of the projections 406. Please refer to the 4D1 to 4D4 drawings, and the 4D1 drawing A top view of the structure after the undercut opening 407 is formed on the structure of the 4C1; the 4D2 is a structural cross-sectional view taken along the tangent S4d1 shown in FIG. 4D1; and the 4D3 is drawn along the 4D1 A cross-sectional view of the structure taken by the tangent line S4d2; and a cross-sectional view of the fourth line D4 shown along the tangent line S4d3 shown in Fig. 4D1.

In the present embodiment, the formation of the undercut opening 407 includes the following steps: first, an in-situ steam generation (ISSG) oxidation process is performed on the surface of the semiconductor substrate 401 to form a tantalum oxide film (not drawn). a blanket covering the flat surface of the semiconductor substrate 401, the sidewall of each of the protrusions 406, and the surface of the tantalum nitride layer 404 at the top end of the protrusion 406; and removing the horizontal surface of the semiconductor substrate 401 by dry etching And an oxide film on the tantalum nitride layer 404, and a spacer 408 is formed on the sidewall of the protrusion 406. Next, a wet etching process is performed to form at least one opening (side etching opening 407) on the surface of the semiconductor substrate 401 and extending below the protruding portion 406.

A source line 409 is then formed in the semiconductor substrate 401 and partially extends into the undercut opening 407 below each of the protrusions 406. Referring to FIGS. 4E1 to 4E4, FIG. 4E1 is a plan view showing the structure after forming the source line 409 on the structure of FIG. 4D1; FIG. 4E2 is a view taken along the tangent S4e1 shown in FIG. 4E1. FIG. 4E3 is a structural sectional view taken along a tangent line S4e2 shown in FIG. 4E1; and FIG. 4E4 is a structural sectional view taken along a tangent line S4e3 shown in FIG. 4E1.

In the present embodiment, the formation of the source line 409 includes the following steps. Step: a selective N-type (N+) high-doped germanium or N-type high-doped germanium epitaxial growth process is first performed to form a polysilicon layer on the semiconductor substrate 401 and partially extend into the undercut opening 407. . After removing the padding layer 403 and the tantalum nitride layer 404 over the protrusions 406, an ion implantation process is performed to make the polycrystalline germanium layer formed by the selective epitaxial growth process have a high concentration of N-type doping. quality.

Next, a plurality of gate lines 410 are formed to surround each of the protrusions 406 and electrically isolate the gate lines 410 from the source lines 409 and the protrusions 406. Referring to FIGS. 4F1 to 4F4, FIG. 4F1 is a plan view showing a structure after forming the gate line 410 on the structure of FIG. 4E1; and FIG. 4F2 is a line S4f1 taken along the 4F1 diagram. FIG. 4F3 is a structural cross-sectional view taken along line S4f2 shown in FIG. 4F1; and FIG. 4F4 is a cross-sectional view taken along line S4f3 shown in FIG. 4F1.

In the present embodiment, before forming the gate line 410, the surface of each of the protrusions 406 is formed to form the gate dielectric layer 411 by a thermal oxidation process. After the gate line 410 is formed on the gate dielectric layer 411, a spacer 412 is formed on the sidewall of the gate line 410 by another thermal oxidation process. Wherein, the thermal process for forming the gate dielectric layer 411 and the spacer 412 can diffuse the N-type dopant in the source line 409 below each of the protrusions 406 and form below the protrusions 406. A diffusion region 409a is connected to the source line 409.

In detail, in the present embodiment, each of the projections 406 has two undercut openings 407, one on the side below the projections 406 and the other on the opposite side below the projections 406. . Located under each of the projections 406 The source lines 409 also have two source regions, for example, the first source region 409c and the second source region 409d respectively extend into two corresponding undercut openings 407. Wherein, the diffusion region 409a is located between the source regions 409b and 409c, and the three are connected to each other. The doping concentration of the first source region 409b and the second source region 409c is substantially higher than the doping concentration of the diffusion region 409a.

Subsequently, a drain 413 is formed at the top end of each of the projections 406, thereby forming a plurality of tandem selection transistors 414 having a vertical channel structure on the semiconductor substrate 410. Referring to FIGS. 4G1 to 4G4, FIG. 4G1 is a plan view showing a structure after forming a plurality of serial selection transistors 414 in the structure of FIG. 4F1; FIG. 4G2 is shown along the 4G1 diagram. A cross-sectional view of the structure taken by the tangent line S4g1; a cross-sectional view of the structure taken along the tangent line S4g2 shown in Fig. 4G1; and a cross-sectional view of the fourth line G4 taken along the tangent line S4g3 shown in Fig. 4G1. .

In some embodiments of the present invention, before forming the drain 413, a metal telluride layer 415 may be formed over the top end of each of the protrusions 406 and the first source region 409b and the second source region 409c. The bump 406 is covered by a tantalum nitride hard mask layer 416 and an interlayer dielectric layer 417. The fabrication of the drain 413 includes the steps of forming a plurality of through vias 418 through the interlayer dielectric layer 417, the tantalum nitride hard mask layer 416, the metal telluride layer 415, the gate line 410, and the gate dielectric layer 411. A portion of the projection 406 is exposed. Another ion implantation process is performed to form an N-type doped region at the top end of each of the projections 406.

After forming the tandem selection transistor 414, the hole in the through hole 418 A plurality of contact plugs 419 are formed to connect the series tandem selection transistor 414 with a plurality of serially connected memory cells 422 formed over the semiconductor substrate 401. Referring to FIGS. 4H1 to 4H4, FIG. 4H1 is a plan view showing a structure after forming a plurality of contact plugs 419 in the structure of FIG. 4G1; and FIG. 4H2 is a tangent S4h1 shown along FIG. 4H1. A cross-sectional view of the structure is made; a 4H3 diagram is a cross-sectional view taken along a tangential line S4h2 shown in FIG. 4H1; and a cross-sectional view taken along a tangential line S4h3 shown in FIG. 4H1.

In the present embodiment, before the contact plug 419 is formed, the spacer 420 must be formed on the sidewall of the through hole 418 to ensure that the contact plug 419 is electrically isolated from the gate line 410.

Subsequently, a plurality of serially connected memory cells 422 are formed over the substrate 401 in series with the drain 413 at the top end of the protruding portion 406 of the tandem selection transistor 414. Referring to FIG. 4I, FIG. 4I is a perspective view showing the structure of a three-dimensional memory device 400 according to still another embodiment of the present invention.

In the present embodiment, the tandem memory cells 422 are formed in the three-dimensional memory cell array 421 above the structures illustrated in FIGS. 4H1 to 4H4. The memory cell array 421 includes a plurality of conductive planar layers 421a stacked in parallel and electrically isolated from each other, a plurality of conductive pillars 421b penetrating through the plurality of conductive planar layers, and a conductive planar layer 421a and conductive pillars. The memory layer 421c between 421b. Each of the series memory cells 422 is formed at the intersection of each of the conductive pillars 421b and the memory layer 421c and the different conductive plane layer 421a. Wherein, each of the serially connected memory cells 422 is located in the stereo memory cell array by the gold conductive columnar body 421b. The drain 413 of the tandem selection transistor 414 below column 421 is connected in series.

According to the above embodiment, the present invention provides a three-dimensional memory element and a method of fabricating the same. The three-dimensional memory component uses a field effect transistor having a vertical channel as a tandem selection transistor of a serial memory cell. In some embodiments of the invention, the vertical channel of the field effect transistor can be directly constructed in a projection that is convexly disposed on the surface of the semiconductor substrate. In some embodiments of the invention, a selective epitaxial growth process can be employed to form the vertical channels of the field effect transistor.

Because the vertical channel field effect transistor has a small footprint, and the linear relationship between the current and voltage (I / V) changes, it is easier to control and other technical advantages when performing multi-bit operation. The problem of the density of the conventional lateral channel field effect transistor-limited memory cell array and the difficulty in operation control of the bipolar junction transistor or the diode can be solved at the same time.

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

401‧‧‧Semiconductor substrate

406‧‧‧Protruding

409‧‧‧ source line

409a‧‧‧Diffusion zone

409b‧‧‧First source area

409c‧‧‧Second source area

410‧‧‧ gate line

411‧‧‧gate dielectric layer

412‧‧‧ spacer

413‧‧‧汲polar

414‧‧‧Serial selection transistor

415‧‧‧metal telluride layer

416‧‧‧ Hard mask layer

417‧‧‧Interlayer dielectric layer

419‧‧‧Contacts

420‧‧‧ spacer

Claims (18)

A three-dimensional memory device comprising: a semiconductor substrate having a first protrusion; a first source line located in the semiconductor substrate and extending partially below the first protrusion; a first gate line surrounding and covering the first protrusion and electrically isolated from the first protrusion and the first source line; and a plurality of serially connected memory cells above the substrate And connected in series with a top end of the first protrusion. The three-dimensional memory device of claim 1, wherein the semiconductor substrate has a first undercut on one side of the first protrusion and a second undercut opening The opposite side of the first protruding portion is respectively for accommodating a part of the first source line. The three-dimensional memory device of claim 2, wherein the first source line comprises: a first source region, partially extending in the first spacer opening; and a second source region; a portion extending in the second undercut opening; and a first diffusion region under the first protrusion and connecting the first source region and the second source region. The three-dimensional memory device of claim 1, further comprising: a second protruding portion on the semiconductor substrate adjacent to the first protruding portion; a plurality of serially connected memory cells located at the a substrate above and connected to a top end of the second protrusion; and a second source line parallel to the first source line and extending partially below the second protrusion; The first gate line surrounds and covers the second protrusion and is electrically isolated from the second protrusion and the second source line. The three-dimensional memory device of claim 4, further comprising: a third protruding portion on the semiconductor substrate adjacent to the first protruding portion; a plurality of serially connected memory cells located at the a substrate above and connected to a top end of the third protrusion; and a second gate line parallel to the first gate line, surrounding and covering the third protrusion, and The third protrusion is electrically isolated from the first source line; wherein the first source layer extends partially below the third protrusion. A method of fabricating a three-dimensional memory device, comprising: providing a semiconductor substrate having at least one protrusion; forming at least one source line in the semiconductor substrate, and extending the source line partially a lower portion of the protrusion; forming at least one gate line, surrounding and covering the protrusion, and the gate line Electrically isolating from the source line; and forming a plurality of serially connected memory cells above the substrate to be in series with a top end of the protrusion. The method of fabricating a three-dimensional memory device according to claim 6, wherein the step of providing the semiconductor substrate comprises: forming a plurality of shallow trench isolation structures (STI) in the semiconductor substrate; Each of the shallow trench isolation structures is partially removed, whereby a plurality of ridges are formed on the semiconductor material, parallel to the remaining shallow trench isolation structures; and the remaining shallow trench isolation structures are etch stop layers And removing a portion of the ridges to form the at least one protrusion. The method of fabricating a three-dimensional memory device according to claim 6, wherein the method of forming the source line comprises: etching the semiconductor substrate, thereby forming at least one side of the opening under the protrusion; and performing A selective epitaxial growth process forms a polysilicon layer on the semiconductor substrate and partially extends into the undercut opening. The method for fabricating a three-dimensional memory device according to claim 8, wherein before the forming the gate line, the method further comprises: performing a thermal oxidation process to form a gate dielectric The electric layer covers the protruding portion, and a diffusion region is formed under the protruding portion to be connected to the polysilicon layer. A method of fabricating a memory device, comprising: providing a semiconductor substrate having an active region and a peripheral region; forming at least one source line in the active region; performing a selective epitaxial a Selective Epitaxial Growth (SEG) process, forming at least one columnar channel structure on the source line, connecting a bottom of the columnar channel structure to the source line; forming at least one gate line and the source line Intersecting and surrounding the columnar channel structure, and electrically isolating from the columnar channel structure and the source line; forming a plurality of serially connected memory cells above the active region to make a structure with the columnar channel structure The top is connected in series. The method of fabricating a three-dimensional memory device according to claim 10, wherein the step of forming the source line comprises an ion implantation process. The method for fabricating a three-dimensional memory device according to claim 10, wherein the step of forming the columnar channel structure comprises: sequentially forming a first dielectric layer, a sacrificial layer, and a first layer on the source line. Two dielectric layers; Patterning the first dielectric layer, the sacrificial layer and the second dielectric layer to form at least a uniform via, exposing a portion of the source line to the outside, and exposing the sacrificial layer to the outer portion via the through hole Forming a spacer; performing the selective epitaxial growth process to form the columnar channel structure in the through hole. The method for fabricating a three-dimensional memory device according to claim 10, wherein the step of forming the columnar channel structure comprises: sequentially forming a first dielectric layer, a conductor layer and a layer on the source layer; a second dielectric layer; patterning the first dielectric layer, the conductor layer and the second dielectric layer to form at least a uniform via, exposing a portion of the source line to the outside; and passing through the conductor layer A portion of the hole is exposed to the outer portion to form a spacer. The method for fabricating a three-dimensional memory device according to claim 10, after forming the columnar channel structure, further comprising forming at least one planar metal-oxide-semiconductor field effect current in the peripheral region. Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) component. A method for fabricating a three-dimensional memory device, comprising: providing a semiconductor substrate; forming at least one source line in the semiconductor substrate; forming at least one gate line, crossing the source line, and electrically isolating from each other; Forming at least a uniform via in the gate line, exposing a portion of the gate line and a portion of the source line to the outside; forming a spacer on the sidewall of the through hole; performing a selective epitaxial growth process Forming a columnar channel structure in the through hole; and forming a plurality of serially connected memory cells over the semiconductor substrate to be in series with a top end of the columnar channel structure. The method of fabricating a three-dimensional memory device according to claim 15, wherein the step of forming the source line comprises an ion implantation process. The method for fabricating a three-dimensional memory device according to claim 15, further comprising forming a gate dielectric layer between the source line and the gate line. The method for fabricating a three-dimensional memory device according to claim 15, wherein before the forming the through hole, the method further comprises: performing an ion doping process with the gate line as a mask, and forming at least the source line The diion doped region is adjacent to the gate line.