JP2014241325A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an art of a semiconductor device which supports a circumference of a capacitor lower electrode by an intermediate support film.SOLUTION: A semiconductor device according to the present embodiment comprises: a first support film which is formed on a semiconductor substrate and has a first opening and a second opening which are isolated from each other; a second support film which is formed at a position higher than that of the first support film and has a third opening; and a capacitor lower electrode which extends in a perpendicular direction with respect to the semiconductor substrate and contacts an inner wall of the second opening of the first support film and an inner wall of the third opening of the second support film, in which a width of an upper end is larger than a width of a part contacting the first support film.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

In recent years, semiconductor devices such as DRAM (Dynamic Random Access Memory) have been miniaturized. In the manufacture of semiconductor devices, the processing depth by dry etching tends to decrease while the processing depth tends to increase as the integration of semiconductor devices increases. With the further progress of miniaturization in recent years, it is required to form a pattern with a high aspect ratio in which the ratio of the processing depth to the processing area is large. When using the outer wall of a high aspect ratio electrode as a capacitor, a technique for holding the electrode by providing a support film (beam) is known in order to prevent it from collapsing during the manufacturing process and shorting with the adjacent electrode. It has been.

  For example, a technology of a semiconductor device having a support film that suppresses collapse of a lower electrode of a three-dimensional capacitor is known (see, for example, Patent Document 1). In this technique, the support film is formed in a plurality of layers in the height direction of the lower electrode, and the support film of each layer has a line-shaped pattern connecting the lower electrodes, and the pattern extending direction is different between two adjacent layers. A semiconductor device employing the configuration is disclosed.

JP 2011-166071 A

  In the formation of a cylinder-type capacitor, the capacitor lower electrode collapses due to the force exerted by the chemical on the capacitor lower electrode during etching of the capacitor interlayer film or during cleaning before forming the capacitor insulating film formed on the next capacitor lower electrode. In particular, as the miniaturization progresses, it becomes a problem.

  An object of the present invention is to provide a method for manufacturing a semiconductor device in which the outer periphery of a capacitor lower electrode is supported by a plurality of support films.

  In view of the above problems, according to one embodiment of the present invention, a stopper film, a first capacitor interlayer film, and a first support film are sequentially formed over a semiconductor substrate, and the first support film is partially removed. Forming a first opening, forming a second capacitor interlayer from the first opening to the upper surface of the first support film, and further forming a second capacitor interlayer A second step of forming a second support film on the film, and a stopper film, a first capacitor interlayer, a first support film, and a second capacitor so as to be separated from the first opening A third step of forming a second opening penetrating the interlayer film and the second support film, a fourth step of forming a capacitor lower electrode covering the inner surface of the second opening, and a second step The support film is partially removed to form an upper support film opening that exposes the second capacitor interlayer film. And a sixth step of selectively removing the second capacitor interlayer film and the first capacitor interlayer film to form a capacitor lower electrode with the outer wall surface exposed. It relates to a manufacturing method.

  Another aspect of the present invention is a first support film formed on a semiconductor substrate and having a first opening and a second opening that are separated from each other, and higher than the first support film. A second support film formed at a position and having a third opening, and extending in a direction perpendicular to the semiconductor substrate, the inner wall of the second opening of the first support film and the second A capacitor lower electrode in contact with the inner wall of the third opening of the support film, wherein the width of the upper end is larger than the width of the portion in contact with the first support film. The present invention relates to a semiconductor device.

  According to the present invention, since the capacitor lower electrode is formed by surrounding the outer periphery with the intermediate support film, the strength of supporting the capacitor lower electrode of the intermediate support film is improved. As a result, it is possible to prevent collapse when forming the capacitor lower electrode, and the manufacturing yield is improved.

  Further advantages and embodiments of the present invention are described in detail below using the description and the drawings.

FIG. 2 is a cross-sectional view taken along line A-A ′ parallel to the a direction in FIG. 1Z. It is sectional drawing along the B-B 'line parallel to b direction of FIG. 1Z. FIG. 2 is a cross-sectional view taken along line Y-Y ′ parallel to the y direction in FIG. 1Z. It is a top view which shows the semiconductor device by the 1st Embodiment of this invention in order of a manufacturing process. It is sectional drawing along the A-A 'line of FIG. 2Z. FIG. 1D is a top view illustrating a manufacturing step of the semiconductor device following that of FIG. 1Z. It is sectional drawing along the A-A 'line parallel to the a direction of FIG. 3Z. It is sectional drawing along the B-B 'line parallel to b direction of FIG. 3Z. FIG. 4 is a cross-sectional view taken along line Y-Y ′ parallel to the y direction in FIG. 3Z. FIG. 2D is a top view illustrating a manufacturing step of the semiconductor device following FIG. 2Z; FIG. 3B is a cross-sectional view taken along the line A-A ′ showing the manufacturing process of the semiconductor device following FIG. 3A. It is sectional drawing along the A-A 'line of FIG. 5Z. It is a top view which shows the semiconductor device by the 1st Embodiment of this invention in order of a manufacturing process. FIG. 5B is a cross-sectional view taken along the line A-A ′ showing the manufacturing process of the semiconductor device following FIG. 5A. It is sectional drawing along the A-A 'line of FIG. 7Z. It is a top view which shows the semiconductor device by the 1st Embodiment of this invention in order of a manufacturing process. FIG. 7B is a cross-sectional view taken along line A-A ′ showing the manufacturing process of the semiconductor device following FIG. 7A. It is sectional drawing along the A-A 'line parallel to the a direction of FIG. 9Z. It is sectional drawing along the B-B 'line parallel to b direction of FIG. 9Z. It is sectional drawing along the Y-Y 'line | wire parallel to the y direction of FIG. 9Z. It is a top view which shows the semiconductor device by the 1st Embodiment of this invention in order of a manufacturing process. FIG. 9B is a cross-sectional view taken along line A-A ′ showing the manufacturing process of the semiconductor device following FIG. 9A. It is sectional drawing along the A-A 'line parallel to the a direction of FIG. 11Z. FIG. 11B is a cross-sectional view taken along line B-B ′ parallel to the b direction in FIG. 11Z. FIG. 12 is a cross-sectional view taken along line Y-Y ′ parallel to the y direction in FIG. 11Z. It is a top view which shows the semiconductor device by the 1st Embodiment of this invention in order of a manufacturing process. FIG. 11B is a plan view parallel to the semiconductor device along the cut-out line Z2-Z2 ′ at the position of the intermediate support film shown in FIGS. 11A, 11B, and 11Y. It is sectional drawing along the A-A 'line of FIG. 12Z. 12 is a top view showing a manufacturing process of the semiconductor device following FIG. 11Z; FIG. FIG. 12B is a plan view parallel to the semiconductor device along the cut-out line Z2-Z2 ′ at the position of the intermediate support film shown in FIG. 12A. It is sectional drawing along the A-A 'line of FIG. 13Z. FIG. 12D is a top view showing a manufacturing process of the semiconductor device following FIG. 12Z. FIG. 13B is a cross-sectional view taken along the line A-A ′ showing the manufacturing process of the semiconductor device following FIG. 13A. It is sectional drawing along the A-A 'line of FIG. 15Z. It is a top view which shows the semiconductor device by the 1st Embodiment of this invention in order of a manufacturing process. FIG. 15B is a cross-sectional view taken along the line A-A ′ illustrating the manufacturing process of the semiconductor device following FIG. 15A. FIG. 16B is a cross-sectional view taken along line A-A ′ showing the manufacturing process of the semiconductor device, following FIG. 16A; FIG. 16B is a cross-sectional view taken along line B-B ′ showing the manufacturing process of the semiconductor device following FIG. 16A. FIG. 16B is a cross-sectional view taken along line Y-Y ′ showing the manufacturing process of the semiconductor device following FIG. 16A; 1 is a plan conceptual view of a semiconductor device according to a first embodiment of the present invention. FIG. 18B is a plan view parallel to the semiconductor device along the cut-out line Z2-Z2 ′ at the position of the intermediate support film shown in FIGS. 17A, 17B, and 17Y. It is a top view of the semiconductor device by the 2nd Embodiment of this invention. It is a top view of the semiconductor device by the 2nd Embodiment of this invention.

  An example in which the present invention is applied to a capacitor of a DRAM will be described with reference to the drawings. The present invention is not limited to the application of a DRAM capacitor, but can be applied to other semiconductor compensation capacitance elements.

(First embodiment)
First, a first embodiment of the present invention will be described with reference to FIGS. FIG. 17 is a completed view of the semiconductor device of this embodiment. In each drawing, the extending direction of the word line is the y direction, the x direction of the bit line, the extending direction of the element forming region is the b direction, and the diagonal direction of the rectangular lattice formed by the capacitor lower electrode is the a direction. In each embodiment, for example, the drawings with Z such as FIG. 1Z and FIG. 5Z are top views of the semiconductor device according to the present embodiment, and the drawings with Z2 are cut along the cutting line Z2-Z2 ′ of the position of the intermediate support film. 2 is a plan view parallel to the semiconductor substrate. FIG. Further, for example, drawings with A such as FIG. 1A and FIG. 15A are cross-sectional views taken along a cutting line AA ′ parallel to the a direction, and drawings with B such as FIG. 3B and FIG. Is a cross-sectional view cut along a cutting line BB ′ parallel to the line Y, and a drawing with Y is a cross-sectional view cut along a cutting line YY ′ line parallel to the y direction.

  FIG. 1 is a view for explaining the semiconductor device manufacturing method according to the present embodiment (hereinafter, for the sake of simplification, FIG. 1A, FIG. 1B, FIG. 1Y, and FIG. 1Z are collectively referred to as “FIG. 1”). The same applies to FIGS. 2 to 19).

  First, an element isolation 12 in which an insulating film is embedded on the surface of the semiconductor substrate 11 is formed. When viewed in plan, the region of the semiconductor substrate 11 is partitioned by the element isolation 12 to define the element formation region 13. In this embodiment, a P-type conductivity type is used as the conductivity type of the semiconductor substrate 11. The element formation region 13 has an elongated pattern extending in the b direction when viewed in a plane, and is repeatedly arranged in each of the x direction and the y direction.

  For example, as apparent from FIG. 1Y which is a cross-sectional view along the Y-Y ′ line parallel to the y direction, the element formation regions 13 and the element isolations 12 are alternately formed. The gate groove 14 extending in the y direction is dug into the element forming region 13 and the element isolation 12 to form the gate groove 14 penetrating in the y direction. Two gate trenches 14 are arranged in each element formation region 13 so as to be parallel to each other.

  Referring to FIG. 1A, which is a cross-sectional view taken along line A-A ′ parallel to the a direction, a gate insulating film 15 is formed on the surface of the semiconductor substrate 11 exposed in the element formation region 13 in the gate groove 14. A gate electrode 16 is formed by burying a conductive film in the gate trench 14. As a material for the conductive film, a titanium nitride film can be used. The material is not limited to this, and a laminated film of a titanium nitride film and a tungsten film, an impurity-doped silicon film, or the like may be used. The gate electrode 16 functions as a word line of the DRAM.

  A gate cap film 17 is formed on the gate electrode 16 formed in the gate trench 14. A silicon nitride film can be used as the gate cap film 17. Impurity ions are introduced into the surface of the semiconductor substrate 11 in each element formation region 13, that is, the surfaces of the three semiconductor substrates 11 separated by the two gate grooves 14 to form source / drain regions. This is apparent with reference to FIG. 1B, which is a cross-sectional view along the line B-B ′ parallel to the b direction. Of the source / drain regions, the portion sandwiched between the two gate 14 grooves is the bit line side source / drain region 18b, and the portion formed on both outer sides of the two gate grooves 14 is the capacitor side source / drain region 18c. Called. In this embodiment, the N type is used as the conductivity type of the source / drain region.

  In each element formation region 13, the bit line side source / drain region 18 b is a common source / drain, the buried gate electrode 23 is the gate on the left and right sides thereof, and the capacitor side source / drain region 18 c provided on both outer sides of the gate. Are formed as two source / drains.

  Next, a semiconductor device manufacturing process following FIG. 1 will be described with reference to FIG. As can be seen from FIG. 2A, a first interlayer film 21 is formed on the semiconductor substrate 11 on which the cell transistor 19 is formed. For example, a silicon oxide film or the like can be used as the first interlayer film 21. A bit line contactor 22 connected to the bit line side source / drain region 18 b is formed in the first interlayer film 21. A bit line 23 connected to the bit line contact 22 and extending in the x direction is formed. A tungsten film can be used as the material of the bit line 23. As can be seen from FIG. 2Z, a plurality of bit lines are juxtaposed in the y direction.

  A bit line hard mask 24 is formed on the bit line 23, and a bit line sidewall film 25 is formed on the side wall of the bit line 23. A silicon nitride film can be used for the bit line hard mask 24 and the bit line sidewall film 25. In the top view of the semiconductor device shown in FIG. 2Z, the element formation region 13 and the gate electrode 16 are overlapped for easy understanding of the configuration of the semiconductor device according to the present embodiment.

  FIG. 3 shows the manufacturing process of the semiconductor device according to the present embodiment following FIG. A second interlayer film 31 such as a silicon nitride film is formed on the semiconductor substrate 11 processed in the manufacturing process in FIG. A first capacitor contact 32 connected to the capacitor side source / drain region 18 c is formed in the second interlayer film 31. The first capacitor contact 32 is disposed between the bit lines 23 adjacent in the y direction so as not to be short-circuited with the bit line 23.

  Subsequently, a third interlayer film 33 is formed on the second interlayer film 31 and the first capacitor contact 32. A second capacitor contact 34 connected to the first capacitor contact 32 is formed in the third interlayer film 33. FIG. 3Z is a top view showing the configuration of the semiconductor device at the stage where the second capacitor contact 34 is formed. In the figure, the element formation region 13, the gate electrode 16, the bit line contact 22, the bit line 23, and the first capacitor contact 27 are displayed in an overlapping manner.

  FIG. 4A shows the manufacturing process of the semiconductor device according to the present embodiment subsequent to FIG. A stopper film 141 is formed on the semiconductor substrate 11 on which the second capacitor contact 34 is formed. As a material of the stopper film 141, for example, a silicon nitride film can be used. For example, 100 nm is used as the film thickness. A first capacitor interlayer 142 is formed on the stopper film 141. As a material of the first capacitor interlayer 142, for example, a silicon oxide film can be used. For example, 500 nm is used as the film thickness. An intermediate support film 143 is formed on the first capacitor interlayer 142. As the material of the intermediate support film 143, for example, a silicon nitride film can be used. For example, 100 nm is used as the film thickness.

  FIG. 5 shows the manufacturing process of the semiconductor device according to the present embodiment subsequent to FIG. A first resist film 151 is formed on the intermediate support film 143. A first resist film opening 152 is formed in the first resist film 151 by using a lithography technique. The first resist film opening 152 is formed in a region where a first intermediate support film opening is to be formed, which is formed in the next step of FIG. Further, the interval between the first resist film openings 152 adjacent in the x direction is represented as S5X, and the interval between the first resist film openings 152 adjacent in the y direction is represented as S5Y. The pitch of the first resist film openings 152 in the x direction is P5X, and the pitch in the y direction is P5Y. As specific dimensions of the first resist film opening 152 of this embodiment, P5Y uses a minimum wiring pitch of 90 nm, and P5X uses 95 nm which is slightly larger than the minimum wiring pitch. The opening diameter W5 of the first resist film opening 152 may be 40 nm, the spacing S5X in the x direction of the first resist film opening 152 may be 55 nm, and the spacing S5Y in the y direction may be 50 nm.

  FIG. 6A shows the manufacturing process of the semiconductor device according to the present embodiment subsequent to FIG. Using the first resist film 151 as a mask, the exposed intermediate support film 143 is etched to form an intermediate support film opening 161 in the intermediate support 143. The intermediate support opening 161 serves to distribute an etching agent for etching the first capacitor interlayer 142 in the subsequent capacitor interlayer etching, and forms a capacitor insulating film and a capacitor upper electrode. It has a function of distributing a film agent.

  FIG. 7 shows the manufacturing process of the semiconductor device according to the present embodiment following FIG. First, the first resist film 151 on the intermediate support film 143 is removed. In the present embodiment, as shown in FIG. 7Z, the arrangement of the intermediate support film openings 161 uses a rectangular lattice layout that is repeatedly arranged at a predetermined pitch in the x direction and the y direction. As a pattern shape of the intermediate support film opening 161, a circular pattern is used as an example, and the opening diameter is expressed as W7. The pattern is not limited to this, and a rectangular pattern or the like may be used.

  In addition, an interval between the intermediate support film openings 161 adjacent in the x direction is represented as S7X, and an interval between the intermediate support film openings 161 adjacent in the y direction is expressed as S7Y. The pitch of the intermediate support film openings 161 in the x direction is P7X, and the pitch in the y direction is P7Y. As specific dimensions of the intermediate support film opening of the present embodiment, P7Y uses a minimum wiring pitch of 90 nm, and P7X uses 95 nm that is slightly larger than the minimum wiring pitch. The opening diameter W7 of the intermediate support film opening 161 can be 40 nm, the distance S7X in the x direction of the intermediate support film opening 161 can be 55 nm, and the distance S7Y in the y direction can be 50 nm.

  In the present embodiment, for example, an ArF exposure technology process, which is the most advanced technology, is used as the lithography technology. In this embodiment, this process is used, and the minimum wiring pitch (P) can be 90 nm. Here, the wiring pitch is the total length of the wiring width and interval. A value half the minimum wiring pitch (P) is called a technology node, and is used as an index representing the minimum processing dimension of the process. When the minimum wiring pitch is 90 nm, the technology node is 45 nm.

  FIG. 8A shows the manufacturing process of the semiconductor device according to the present embodiment subsequent to FIG. A second capacitor interlayer 181 is formed on the first capacitor interlayer 142 and the intermediate support film 143. As a material of the second capacitor interlayer 181, for example, a silicon oxide film can be used. For example, 700 nm is used as the film thickness. Next, the upper support film 182 is formed on the second capacitor interlayer 181. As a material of the upper support film 182, for example, a silicon nitride film can be used. The film thickness is assumed to be 100 nm, for example. In the present embodiment, the total thickness from the stopper film 141 to the upper support film 182 is 1.5 μm.

  FIG. 9 shows the manufacturing process of the semiconductor device according to the present embodiment subsequent to FIG. A second resist film 191 is formed on the upper support film 182. Then, a second resist film opening 192 is formed in the second resist film 191 by using a lithography technique. The second resist film opening 192 is formed in a capacitor hole formation scheduled region formed in the next step of FIG. The planar shape of the second resist film opening 192 is circular in this embodiment. The shape is not limited to this, and a rectangular shape or the like may be used.

  In the present embodiment, the second resist film openings 192 are arranged in a rectangular lattice arrangement with a predetermined pitch in the x direction and the y direction. The diameter of the second resist film opening 192 is D9, the pitch in the x direction is P9X, the pitch in the y direction is P9Y, and the interval between the second resist film openings 192 adjacent in the x direction is adjacent in the S9X, y direction. The interval between the second resist film openings 192 is represented as S9Y.

  In the top view of the semiconductor device shown in FIG. 9Z, the second resist film opening 192 and the intermediate support film opening 161 are displayed in an overlapping manner in order to clarify the feature according to the present embodiment. As an example of specific dimensions of this embodiment, the pitch P9Y in the y direction is formed using 90 nm which is the minimum wiring pitch (P), and the pitch PX9 in the x direction is 95 nm which is slightly larger than the minimum wiring pitch. be able to. The diameter D9 of the second resist film opening 192 may be 50 nm, the x-direction interval S9X may be 45 nm, and the y-direction interval S9Y may be 40 nm.

  FIG. 10A shows the manufacturing process of the semiconductor device according to the present embodiment subsequent to FIG. Using the second resist film 191 as a mask, the exposed upper layer support film 182 is etched to form capacitor openings A201A in the upper layer support 182. Subsequently, the second capacitor interlayer 181 is etched to form a capacitor opening B201B in the second capacitor interlayer 181. Subsequently, the intermediate support film 143 is etched to form a capacitor opening C201C in the intermediate support film 143. Subsequently, the first capacitor interlayer 142 is etched to form a capacitor opening D201D in the first capacitor interlayer 142. Subsequently, the stopper film 141 is etched to form a capacitor opening E201E in the stopper film 141.

  As a result, the upper surface of the second capacitor contact 34 is exposed, and a capacitor opening 201 penetrating the upper support film 182, the second capacitor interlayer 181, the intermediate support film 143, the first capacitor interlayer 142, and the stopper film 141 is formed. It is formed. The capacitor opening 201 includes a capacitor opening A201A, a capacitor opening B201B, a capacitor opening C201C, a capacitor opening D201D, and a capacitor opening E201E from the top.

  FIG. 11 shows the manufacturing process of the semiconductor device according to the present embodiment subsequent to FIG. The second resist film 191 on the upper support film 182 is removed. FIG. 11Z is a top view of the semiconductor device as viewed from above. In FIG. 11Z, the side surfaces of the upper support film 182, the second capacitor interlayer film 181, the intermediate support film 143, the first capacitor interlayer film 142, the stopper film 141 and the upper surface of the second capacitor contact 34 are formed in the capacitor opening 201. Is seen. In FIG. 11Z, for the sake of explanation, the intermediate support film opening 161 is overlapped with a dotted line. The capacitor opening 201 is disposed at the center position of a rectangular region formed by the four intermediate support film openings 161 adjacent to each other in the x and y directions.

  FIG. 11Z2 is a plan view taken along a plane along the line Z2-Z2 'parallel to the substrate main plane at the position of the intermediate support film 143. FIG. In the intermediate support film 143, an intermediate support film opening 161 and a capacitor opening C201C are formed. In the present invention, the capacitor opening C201C and the intermediate support film opening 161 are formed so as to be separated. That is, the intermediate support film 143 is formed between the capacitor opening C (second opening) 201C and the intermediate support film opening (first opening) 161. The capacitor opening C201C is disposed in the vicinity of the center of the rectangular area formed by the four intermediate support film openings 161 adjacent to each other in the x and y directions. The intermediate support film opening 161 and the capacitor opening C201C are arranged in a checkered pattern.

  The capacitor formed by the present invention uses a three-dimensional structure capacitor in which the capacitor electrode extends in the vertical direction of the substrate and uses the inner wall surface, the outer wall surface, or the inner and outer wall surfaces of the electrode. The shape of the side surface of the capacitor opening 201 formed in this step corresponds to the shape of the outer wall surface of the capacitor electrode formed in the subsequent step. In this three-dimensional structure capacitor, the capacitance value of the capacitor can be increased by increasing the diameter of the outer wall surface.

  By the way, with the high integration of semiconductor elements, the area where capacitors are formed is also reduced. Therefore, it is necessary to form a capacitor in a small area. On the other hand, for the reliability of the semiconductor element, the capacitance value of the capacitor needs to be formed so as to satisfy a predetermined capacitance value or more. Therefore, it is required to form a capacitor in a predetermined region with a large diameter and a small separation. Therefore, a capacitor is formed with a large diameter above the capacitor opening 201 in the semiconductor device.

  On the other hand, in the intermediate support film 143, the capacitor opening 201 and the intermediate support film opening 161 are formed so as to be separated. However, if the capacitor opening 201 is large, it will be easy to come into contact with the intermediate support film opening 161. Therefore, as can be seen in the cross section of the capacitor opening 201 shown in FIGS. 11A, 11B, and 11Y cut perpendicularly to the substrate, the diameter is formed larger above the capacitor opening 201, and the intermediate support film of the capacitor opening is formed. In the vicinity of the portion 143, a structure in which the opening diameter is reduced is used. That is, the capacitor opening C (second opening) 201C is formed to have a smaller opening diameter than the capacitor opening A (third opening) 201A. Thereby, the distance between the capacitor opening 201 and the intermediate support film opening 161 can be secured.

  In order to reduce the opening diameter below the capacitor opening 201, a method of etching while adding a reactive organism to the side wall by adding a fluorocarbon-based gas such as C5F8 or CHF3 to the etching gas can be used. By forming in this way, a taper shape is obtained particularly under the capacitor opening 201.

  FIG. 11 shows an example in which the opening diameter becomes smaller in order of the capacitor opening A201A, the capacitor opening B201B, and the capacitor opening C201C. However, the opening diameter partially increases in the middle portion of the second capacitor interlayer 181. It may be formed in a bowing shape. Even in the case of being formed in such a bowing shape, the opening diameter of the capacitor opening C (second opening) 201C is smaller than that of the capacitor opening A (third opening) 201A. If formed, there is no problem.

  Further, in order to dispose the two elements called the capacitor opening 201 and the intermediate support film opening 161 in the intermediate support film 143 so as to be separated, the capacitor opening 201 is arranged in a rectangular lattice shape, A layout in which the intermediate support film opening 161 is arranged in the gap portion of the capacitor opening arrangement arranged in a rectangular lattice is effective. At this time, the intermediate support film openings 161 are arranged in a rectangular lattice shape, and the capacitor openings 201 and the intermediate support film openings 161 have a checkered pattern. When this arrangement is used, the capacitor openings 201 can be arranged at high density, and the distance between the four pairs of the adjacent capacitor openings 201 and the intermediate support film openings 161 is increased equally. The separation margin can be secured.

  In this embodiment, the planar shape of the capacitor opening 201 is circular. The shape is not limited to this, and a rectangular shape or the like may be used. Here, the diameter of the upper part of the capacitor opening 201 (capacitor opening A201A) is represented as DU11, and the diameter of the capacitor opening C201C at the position of the intermediate support film 143 is represented as DM11. In the upper part, the interval between the capacitor openings 201 adjacent in the x direction is expressed as SU11X, and the interval between the capacitor openings 201 adjacent in the y direction is expressed as SU11Y. In the intermediate support film 143, the interval between the capacitor openings C201C adjacent in the x direction is expressed as SM11X, and the interval between the capacitor openings C201C adjacent in the y direction is expressed as SM11Y. Note that the pitch in the x direction and the pitch in the y direction of the capacitor opening 201 are the same as those of the second resist film opening 192, and are indicated as P9X and P9Y, respectively.

  As an example of specific dimensions of the present embodiment, the pitch S9Y in the y direction is formed using 90 nm which is the minimum wiring pitch (P), and the pitch PX9 in the x direction is 95 nm which is slightly larger than the minimum wiring pitch. . In the upper part, the diameter DU11 can be 50 nm, the x-direction interval SU11X can be 45 nm, and the y-direction interval SU11Y can be 40 nm. In the intermediate support film 143, the diameter DM11 can be 40 nm, the x-direction interval SM11X can be 55 nm, and the y-direction interval SM11Y can be 50 nm.

  Here, W7 which is the diameter of the intermediate support film opening 161 formed in the steps of FIGS. 6 and 7 is formed to 40 nm, and the gap between the capacitor opening C201C and the intermediate support film opening 161 is In design, a length of 25 nm is ensured. In the process of the technology node 45 nm, manufacturing variations such as dimensional variation and position variation that occur at the time of processing using the lithography technique and the etching technique are managed to about 5 nm, and between the capacitor opening C201C and the intermediate support film opening 161, A sufficient separation margin can be secured.

  FIG. 12 shows the manufacturing process of the semiconductor device according to the present embodiment subsequent to FIG. A capacitor lower electrode material made of a conductive film is formed to cover the inner surface of the capacitor opening 201 and the upper surface of the upper support film 182. As a material for the capacitor lower electrode material, for example, a titanium nitride film can be used. The material is not limited to this, and a laminated film of a titanium film and a titanium nitride film, a tungsten nitride film, another refractory metal film, an impurity-doped silicon film, or the like may be used. When a thin film thickness that does not fill the capacitor opening 201 is used, the inside of the capacitor opening 201 can be used as a capacitor. When the capacitor lower electrode material is formed so as to fill the capacitor opening 201, the capacitor opening 201 can be formed in a structure that is not used as a capacitor.

  Using the CMP method, the capacitor lower electrode material on the upper surface of the upper support film 182 is removed, leaving the capacitor lower electrode material in the capacitor opening 201, and forming the capacitor lower electrode 221 in the capacitor opening 201. Thereby, the capacitor lower electrode 221 is formed so as to cover the inner surface of the capacitor opening 201. In this electrode processing, an etching method may be used instead of the CMP method.

  Thereby, a prototype of the capacitor lower electrode 221 is formed. The outer wall of the capacitor lower electrode 221 has a shape that substantially reflects the shape of the inner wall of the capacitor opening 201 formed in the steps of FIGS. Therefore, the inner diameter of the capacitor opening 201 and the outer diameter of the capacitor lower electrode 221 are approximately the same size. The capacitor lower electrode 221 is formed separately from the intermediate support film opening 161 in the intermediate support film. As a result, the capacitor lower electrode 221 can be formed by surrounding the outer periphery with the intermediate support film 143.

  In this embodiment, the planar shape of the capacitor lower electrode 221 is circular, the outer diameter of the top portion is DU12, and the outer diameter of the intermediate support film 143 is DM12. In the upper part, the interval between the capacitor lower electrodes 221 adjacent in the x direction is expressed as SU12X, and the interval between the capacitor lower electrodes 221 adjacent in the y direction is expressed as SU12Y. In the intermediate support film 143, the interval between the capacitor lower electrodes 221 adjacent in the x direction is expressed as SM12X, and the interval between the capacitor lower electrodes 221 adjacent in the y direction is expressed as SM12Y. The pitch of the capacitor lower electrode 221 in the x and y directions is the same as that of the second resist film opening 192, and is P9X and P9Y, respectively.

  As an example of specific dimensions of the present embodiment, 50 nm can be used for the diameter DU12, 45 nm for the X-direction interval SU12X, and 40 nm for the Y-direction interval SU12Y. In the intermediate support film 143, the diameter DM12 may be 40 nm, the X-direction interval SM12X may be 55 nm, and the Y-direction interval SM12Y may be 50 nm. The outer diameter of the capacitor lower electrode 221 is formed to be smaller at the intermediate support film 143 than the outer diameter near the top near the upper support film 182. FIG. 12Z is a top view of this stage of the process, in which the intermediate support film opening 161 is formed together.

  FIG. 13 shows the manufacturing process of the semiconductor device according to the present embodiment subsequent to FIG. A third resist film 231 is formed on the capacitor lower electrode 221 and the upper support film 182. Subsequently, a third resist film opening 232 is formed in the third resist film 231 by using a lithography technique. The third resist film opening 232 is formed in a region where the upper support film opening 241 is to be formed in the next step of FIG. As a pattern of the third resist film opening 232, as shown in FIG. 12Z which is a top view, an opening including a part of the annular upper surface of the capacitor lower electrode 221 and a part of the upper support film 182 is provided. A pattern can be used.

  FIG. 14A shows the manufacturing process of the semiconductor device according to the present embodiment following FIG. Using the third resist film 231 as a mask, the upper support film 182 exposed in the third resist film opening 232 is removed by etching to expose the upper portion of the second capacitor interlayer 181. As a result, the upper support film opening 241 is formed in the upper support film 182. As a result, the capacitor lower electrode 221a is connected to the upper support film 182 at a portion not opened by the third resist film opening 232. In this etching, the upper surface of the capacitor lower electrode 221a may be etched away at the portion where the third resist film opening 232 is opened, thereby generating 242 in some cases. In the cross-sectional view shown in FIG. 14A, for example, the cut-out 242 is about 50 nm. The size of the capacitor lower electrode 221a is the same as that in FIG. 12, and in this embodiment, the planar shape of the capacitor lower electrode 221a is circular, and the outer diameter of the top portion is approximately DU12 and the intermediate support film 143. The outer diameter of this is DM12.

  FIG. 15 shows the manufacturing process of the semiconductor device according to the present embodiment following FIG. The third resist film 231 on the capacitor lower electrode 221a is removed. As shown in the top view of FIG. 15Z, in the third resist film opening 232, the upper support film 182 is removed and the surface of the second capacitor interlayer 181 is exposed. In a portion not included in the third resist film opening 232, the upper capacitor support film 182 supports the adjacent capacitor lower electrode 221 a.

  FIG. 16A shows the manufacturing process of the semiconductor device according to the present embodiment subsequent to FIG. The second capacitor interlayer 181 and the first capacitor interlayer 142 are selectively removed by etching to form a capacitor lower electrode 221b with the outer wall surface exposed (referred to as capacitor interlayer etching). At this time, the upper support film (second support film) 182, the intermediate support film (first support film) 143, the stopper film 141, and the capacitor lower electrode 221b are left. In the case of the material used in this embodiment, etching using a chemical solution containing hydrofluoric acid (HF) can be used for capacitor interlayer film etching.

  In the capacitor interlayer etching in which the second capacitor interlayer 181 and the first capacitor interlayer 142 are selectively removed to leave the upper support film 182, the intermediate support film 143, the stopper film 141, and the capacitor lower electrode 221b, The material and the etching method shown in this embodiment are not limited. The etching rates for the second capacitor interlayer 181 and the first capacitor interlayer 142 are relatively high, and the etching rates for the second support film 182, the first support film 143, the stopper film 141, and the capacitor lower electrode 221b are relatively high. A combination of materials and etching conditions that are small can be used. For example, the first capacitor interlayer 142 and the second capacitor interlayer 181 may be SOG films, BPSG films, PSG films, etc. in addition to pure silicon oxide films. As etching conditions, dry etching using a gas containing hydrofluoric acid may be used.

  Through this capacitor interlayer film etching, a capacitor lower electrode 221b having a three-dimensional structure is formed. In the capacitor of the present invention, the outer wall surface of the capacitor lower electrode 221b can be used, and the capacitance of the capacitor can be increased. In this embodiment, the planar shape of the capacitor lower electrode 221b is circular, the outer diameter of the top portion is DU16, and the outer diameter of the intermediate support film 143 is DM16. These values are substantially the same as DU12 and DM12 in the process of FIG.

  By the way, in the formation of the cylinder type capacitor, the force exerted by the chemical on the capacitor lower electrode 221b during the etching of the capacitor interlayer film or during the cleaning before the formation of the capacitor insulating film 271 formed on the next capacitor lower electrode 221b. The collapse or peeling of the lower electrode 221b becomes a problem particularly as miniaturization progresses. In the present invention, the capacitor lower electrode 221b is formed in the intermediate support film 143 separately from the intermediate support film opening 161. That is, since the capacitor lower electrode 221b can be formed by surrounding the outer periphery with the intermediate support film 143, the strength of the intermediate support film 143 for supporting the capacitor lower electrode 221b is improved. As a result, it is possible to prevent collapse when the capacitor lower electrode 221b is formed, and the manufacturing yield is improved.

  FIG. 17 shows the manufacturing process of the semiconductor device according to the present embodiment subsequent to FIG. A capacitor insulating film 271 is formed covering the surface of the capacitor lower electrode 221c. The material is an insulating film including a zirconium oxide film, for example, and the film thickness can be 8 nm, for example. A capacitor upper electrode film is formed on the capacitor insulating film 271 and then patterned to form the capacitor upper electrode 272. As the capacitor upper electrode 272, a laminated film of a titanium nitride layer 272a and an impurity-doped silicon layer 272b can be used. Note that the structure of the capacitor upper electrode 272 is not necessarily limited to this, and a single layer structure of a titanium nitride film, a laminated structure in which an impurity-doped silicon film, a tungsten film, or the like can be used.

  Subsequently, an upper interlayer film 273 is formed on the impurity-doped silicon layer 272b. In the peripheral circuit region, a peripheral contact that penetrates the upper interlayer film 273 and is connected to the bit line 23 is formed (not shown). An upper wiring 274 connected to the peripheral contact is formed. Thereafter, an interlayer film, a via hole, a wiring, a cap film, an interlayer film, a pad electrode, and a passivation film are formed as necessary to complete the device. Through the above, a semiconductor device including a cylinder type capacitor including a support film is formed.

  In this embodiment, the planar shape of the capacitor lower electrode 221c is circular, the outer diameter of the top portion is represented as DU17, and the outer diameter of the intermediate support film 143 is represented as DM17. These values are approximately the same size as DU12 and DM12 in the step of FIG. FIG. 17Z3 is a conceptual plan view of the semiconductor device. The element formation region 13, the gate electrode 16, the bit line 23, the second capacitor contact 34, the intermediate support film opening 161, the upper contour of the capacitor lower electrode 221, and the second support film opening 241 are shown in an overlapping manner. It is.

  A semiconductor device according to an embodiment of the present invention includes a first support film formed on a substrate and having a first opening and a second opening separated from each other, and extending in a direction perpendicular to the substrate. A structure having a capacitor lower electrode that is in contact with the inner wall of the first opening of the first support film and whose width at the upper end is larger than the width of the portion in contact with the first support film. As a result of such a structure, the capacitor lower electrode can have a structure in which its outer wall is surrounded by an intermediate support film (first support film), and a capacitor lower electrode having high mechanical strength can be formed. Can do. As a result, the manufacturing yield of capacitors can be improved.

  Further, the second support film having a third opening is formed at a position higher than the first support film, and the capacitor electrode is formed in contact with the third opening of the second support film. The structure can be taken. As a result, the upper part of the capacitor lower electrode can be supported by the upper support film (second support film), and the mechanical strength can be further increased.

  In the present invention, a layout in which the capacitor openings are arranged in a rectangular lattice shape and the intermediate support film openings are arranged in the gap portions of the capacitor opening array arranged in the rectangular lattice shape can be used. As a result of using such an arrangement, the intermediate support film openings are arranged in a rectangular lattice shape, and the capacitor openings and the intermediate support film openings have a checkered pattern. In addition, the capacitor openings can be arranged at high density, and in the four pairs of the adjacent capacitor openings and the intermediate support film openings, the distances can be ensured equally large by design. Even if misalignment or the like occurs sometimes, a sufficient separation margin can be secured.

(Second Embodiment)
Subsequently, a second embodiment of the present invention will be described. The second embodiment of the present invention is a modification of the above-described first embodiment. Hereinafter, in the present embodiment, parts having the same functions as those already described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  18Z2 and FIG. 19Z2 show a schematic configuration of the semiconductor device according to the second embodiment of the present invention. Also in this embodiment, the intermediate support film opening 282 as shown in the first embodiment is arranged at the center position of each grid in the rectangular grid array formed by the four adjacent capacitor lower electrodes 292. The structure is taken.

  The intermediate support film opening 282 may be disposed only at a required position in the rectangular lattice array formed by the center position of the rectangular lattice array formed by the four adjacent capacitor lower electrodes 292. In the second embodiment, as such an example, an example is shown in which every other rectangular lattice array formed by the center position of the rectangular lattice array formed by four adjacent capacitor lower electrodes 292 is arranged. In this case, the intermediate support film openings 282 are arranged in a staggered pattern. The manufacturing method of the semiconductor device according to the present embodiment can use the same manufacturing method as that of the first embodiment.

  Referring to the top view of the semiconductor device shown in FIG. 18Z2, one pattern of the intermediate support film opening 282 formed in the intermediate support film 281 is formed in the intermediate support film opening forming process of FIGS. Arrange them in a staggered manner so that they are arranged at intervals.

  Next, referring to the top view of the semiconductor device shown in FIG. 19Z2, FIG. 19Z2 shows a diagram corresponding to the capacitor lower electrode forming step of FIG. 12Z2. The capacitor openings 291 are arranged in the same planar layout and pattern as the capacitor openings 201 of the first embodiment. The capacitor lower electrode 292 is also arranged in the same planar layout and pattern as the capacitor lower electrode 221 of the first embodiment. The support of the capacitor lower electrode 292 from the intermediate support film 281 in the a direction becomes stronger, and the effect of suppressing the collapse and peeling of the capacitor lower electrode is improved.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on each embodiment, it cannot be overemphasized that this invention is not limited to the said embodiment, and can be variously changed in the range which does not deviate from the summary.

  For example, in the above-described embodiment, the example in which the first support film and the second support film are formed on the middle part and the upper part of the capacitor lower electrode has been described. However, depending on the desired length and width of the capacitor, The lower electrode may be modified so as to further provide a plurality of layers such as three layers or four layers.

The materials, dimensions, film forming methods, film forming conditions, etching methods, etching conditions, and the like of each film described above are merely examples, and other materials, other methods, and different dimensions or conditions may be adopted. it can.

11 Semiconductor substrate 12 Element isolation 13 Element formation region 14 Gate groove 15 Gate insulating film 16 Gate electrode 17 Gate cap film 18b Bit line side source / drain region 18c Capacitor side source / drain region 19 Cell transistor 21 First interlayer film 22 Bit line Contact 23 Bit line 24 Bit line hard mask 25 Bit line sidewall 31 Second interlayer film 32 First capacitor contact 33 Third interlayer film 34 Second capacitor contact 141 Stopper film 142 First capacitor interlayer 143 Intermediate support film (first 1 support membrane)
151 First resist film 152 First resist film opening 161 Intermediate support film opening (first opening)
181 Second capacitor interlayer 182 Upper support film (upper support film, second support film)
191 Second resist film 192 Second resist film opening 201 Capacitor opening (second opening)
201A Capacitor opening A (third opening)
201B Capacitor opening B
201C Capacitor opening C (second opening)
201D Capacitor opening D
201E Capacitor opening E
221 capacitor lower electrode 221a capacitor lower electrode 221b capacitor lower electrode 221c capacitor lower electrode 231 third resist film 232 third resist film opening 241 upper support film opening (second support film opening)
242 Cutting 271 Capacitor insulating film 272 Capacitor upper electrode 272a Titanium nitride layer 272b Impurity doped silicon layer 273 Upper interlayer film 274 Upper wiring 281 Intermediate support film 282 Intermediate support film opening 291 Capacitor opening 292 Capacitor lower electrode

Claims (9)

A stopper film, a first capacitor interlayer film, and a first support film are sequentially formed on a semiconductor substrate, and a part of the first support film is removed to form a first opening. Process,
A second step of forming a second capacitor interlayer film from the first opening to the upper surface of the first support film, and further forming a second support film on the second capacitor interlayer film When,
A second opening that penetrates the stopper film, the first capacitor interlayer, the first support film, the second capacitor interlayer, and the second support film so as to be separated from the first opening A third step of forming
A fourth step of forming a capacitor lower electrode covering the inner surface of the second opening;
A fifth step of partially removing the second support film to form an upper support film opening that partially exposes the second capacitor interlayer;
And a sixth step of selectively removing the second capacitor interlayer and the first capacitor interlayer to form a capacitor lower electrode with an exposed outer wall surface.   The second opening is formed in the third step so that the second opening is arranged at the center position of the rectangular region formed by the first opening. A method for manufacturing a semiconductor device.   2. The semiconductor device manufacturing method according to claim 1, wherein in the third step, the second opening is formed so that the second opening and the first opening are separated in a checkered pattern. Method.   4. The method of manufacturing a semiconductor device according to claim 1, wherein, in the third step, the second opening is formed in a tapered shape from above to below. 5.   Forming a capacitor insulating film covering the capacitor lower electrode surface, forming a capacitor upper electrode film and an upper interlayer film on the capacitor insulating film, and further forming an upper wiring connected to the peripheral contact; The method for manufacturing a semiconductor device according to claim 1, further comprising: A first support film formed on a semiconductor substrate and having a first opening and a second opening separated from each other;
A second support film formed at a position higher than the first support film and having a third opening;
A capacitor lower electrode extending in a direction perpendicular to the semiconductor substrate and in contact with the second opening inner wall of the first support film and the third opening inner wall of the second support film, A capacitor lower electrode having a width of an upper end portion larger than a width of a portion in contact with the first support film.   The semiconductor device according to claim 6, wherein an intermediate support film exists between the first opening and the second opening.   The semiconductor device according to claim 6, wherein the second opening is arranged at a center position of a rectangular region formed by the first opening.   The semiconductor device according to claim 6, wherein the first opening and the second opening are separated in a checkered pattern.

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