CN106033682B - Three-dimensional memory structure and its manufacturing method - Google Patents
Three-dimensional memory structure and its manufacturing method Download PDFInfo
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- CN106033682B CN106033682B CN201510104701.4A CN201510104701A CN106033682B CN 106033682 B CN106033682 B CN 106033682B CN 201510104701 A CN201510104701 A CN 201510104701A CN 106033682 B CN106033682 B CN 106033682B
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Abstract
The invention discloses a kind of three-dimensional memory structure and its manufacturing methods.Such three-dimensional memory structure includes multiple serial, a plurality of first conducting wires, a plurality of second conducting wire and a plurality of privates.Serial configured in parallel.First conductor configurations are on serially.The center portion of first conducting wire is perpendicular to serial.Second conductor configurations are on the first conducting wire.Second conducting wire connects the end section of the wherein half of the first conducting wire.Privates is configured on the second conducting wire.Privates connects the other half end section of the first conducting wire.
Description
Technical field
This specification is about a kind of semiconductor structure and its manufacturing method, especially with regard to a kind of three-dimensional (3D) memory
Structure and its manufacturing method.
Background technique
In typical three-dimensional storage device, wordline is mainly connected to outside decoding by polysilicon and silicide path
Device, these paths are not the path of high conductance for signal.In order to improve the operation efficiency of memory, often through in depositing
The two sides memory device for storing up array area is placed in two identical X-decoders, in the storage unit that selection need to operate, secondly a
X-decoder transmits same signal to storage array area simultaneously, can reduce the path length that the signal must transmit, can reduce wordline capacitance-resistance
Sluggish influence.
With the size reduction of memory device, the efficiency in storage array area is made using the method for two X-decoders
At detrimental effect.The occupied space of X-decoder is reduced to increase the purpose of array area, the capacitance-resistance for reducing its wordline causes late
Gesture is trend.One of method is using metallization wordline technique.However, the technique is because for vertical gate structure,
Its manufacturing process and yield control are extremely complex, and are difficult to carry out.
Summary of the invention
In the present specification, a kind of three-dimensional memory structure and its manufacturing method are provided.In this three-dimensional memory structure
In, reduce space shared by an X-decoder and improves the efficiency of array area.
According to some embodiments, a kind of three-dimensional memory structure includes multiple serial (string), a plurality of first conducting wire, more
The second conducting wire of item and a plurality of privates.Serial configured in parallel.First conductor configurations are on serially.The central portion of first conducting wire
Divide perpendicular to serial.Second conductor configurations are on the first conducting wire.Second conducting wire connects the end of the wherein half of the first conducting wire
Part.Privates is configured on the second conducting wire.Privates connects the other half end section of the first conducting wire.
According to some embodiments, a kind of three-dimensional memory structure includes multiple serial, a plurality of first conducting wires, one first metal
Layer and a second metal layer.Serial configured in parallel.First conductor configurations are on serially.The center portion of first conducting wire perpendicular to
Serially.The first metal layer is configured on the first conducting wire.The first metal layer includes a plurality of second conducting wire, the second conducting wire connection first
The end section of the wherein half of conducting wire.Second metal layer is configured on the first metal layer.Second metal layer includes a plurality of
Three wires, privates connect the other half end section of the first conducting wire.
According to some embodiments, a kind of manufacturing method of three-dimensional memory structure includes the following steps.Firstly, being formed multiple
Serially.Serial configured in parallel.A plurality of first conducting wire is formed on serial.The center portion of first conducting wire is perpendicular to serial.It connects
, a plurality of second conducting wire is formed on the first conducting wire.Second conducting wire connects the end section of the wherein half of the first conducting wire.?
A plurality of privates is formed on second conducting wire.Privates connects the other half end section of the first conducting wire.
More preferably understand to have to above-mentioned and other aspect of the invention, preferred embodiment is cited below particularly, and cooperates institute
Accompanying drawings are described in detail below:
Detailed description of the invention
Fig. 1 to Fig. 4 is painted three-dimensional memory structure manufacturing method according to the embodiment.
Fig. 5 is painted the three-dimensional memory structure according to an embodiment.
[symbol description]
102: serial
104: the first conducting wires
The wherein half of 104-1: the first conducting wire
104-2: the first conducting wire the other half
106: bit line connection pad
108: source electrode connection pad
110-1,110-2: string row selecting switch
112: ground connection selection line
114: the second conducting wires
116: privates
118: privates
120:X decoder
202,204: conductor
M1, M2, M3: metal layer
Specific embodiment
Now illustrate three-dimensional memory structure manufacturing method according to the embodiment.Fig. 1 is please referred to, forms multiple serial 102.
Serial 102 configured in parallel.Then, a plurality of first conducting wire 104 is formed on serial 102.The center portion of first conducting wire 104 hangs down
Directly in serial 102.The wherein half 104-1 of first conducting wire and the other half 104-2 of the first conducting wire can be the U towards opposite direction
Shape shape.In one embodiment, the first conducting wire 104 is wordline.
Bit line connection pad 106 and source electrode connection pad (source pad) 108 can be formed, bit line connection pad 106 and source electrode connection pad 108 exist
Serial 102 opposite two end terminates serial 102.Can be formed string row selecting switch (string select switch) 110-1 and
110-2, string row selecting switch 110-1 and 110-2 are connecting serial 102 close at bit line connection pad 106.In one embodiment, it goes here and there
Row 102 be by and string the row selecting switch 110-1 and 110-2 of (AND) type controlled.Also that is, one serial 102 will be gone here and there by a pair
Row selecting switch 110-1 and 110-2 are controlled.Only going here and there both row selecting switch 110-1 and string row selecting switch 110-2 all
When opening, controlled by it serial 102 are selected.Ground connection selection line (ground select line) 112, ground connection choosing can be formed
Select line 112 close at source electrode connection pad 108 across serial 102.
Referring to figure 2., a plurality of second conducting wire 114 is formed on the first conducting wire 104.Second conducting wire 114 connection first is led
The end section of the wherein half 104-1 of line.Second conducting wire 114 can be formed by metal.More specifically, the second conducting wire 114
It can be formed by the first metal layer M1.
Referring to figure 3., a plurality of privates 116 is formed on the second conducting wire 114.The connection of privates 116 first is led
The end section of the other half 104-2 of line.Privates 116 can be formed by metal.More specifically, privates 116 can
It is formed by second metal layer M2.Second conducting wire 114 and privates 116 can be the U-shape towards opposite direction.Second leads
Line 114 and privates 116 can be the other half 104-2 for respectively corresponding the wherein half 104-1 and the first conducting wire of the first conducting wire
U-shape.
Referring to figure 4., a plurality of privates 118 are formed, privates 118 connect second and third conducting wire 114 and 116
To X-decoder 120.Privates 118 can be formed by metal.More specifically, privates 118 can be by third metal layer M3
It is formed, and can be formed on or below second and third conducting wire 114 and 116.In one embodiment, third metal layer M3 is more
It (is not painted) including the 5th conducting wire, the 5th conducting wire is located at array area, the connection for bit line.
In the methods described above, the first conducting wire 104 is by respectively by first, second and third metal layer M1, M2 and M3 institute shape
At second, third and privates 114,116 and 118 be connected to X-decoder 120.Such technique is deposited with typical three-dimensional
Reservoir process compatible does not need additional step.Since second, third and privates 114,116 and 118 are by back segment
(back-end-of-line) technique is formed, therefore does not need the design of change array.In addition, second, third and the 4th lead
Line 114,116 and 118 does not need to be formed with pitch technique.This is conducive to the progress of technique.
The three-dimensional memory structure as manufactured by the above method may be, for example, three-dimensional anti-and (NAND) flash memory structure.It is this
Three-dimensional memory structure includes multiple serial 102, a plurality of first conducting wire 104, a plurality of second conducting wire 114 and a plurality of privates
116.Serial 102 configured in parallel.First conducting wire 104 is configured on serial 102.The center portion of first conducting wire 104 perpendicular to
Serial 102.First conducting wire 104 can be wordline.Second conducting wire 114 is configured on the first conducting wire 104.The connection of second conducting wire 114
The end section of the wherein half 104-1 of first conducting wire.Privates 116 is configured on the second conducting wire 114.Privates
The end section of the other half 104-2 of 116 the first conducting wires of connection.Second conducting wire 114 and privates 116 can be towards phase negative side
To U-shape.The wherein half 104-1 of first conducting wire and the other half 104-2 of the first conducting wire can be respectively correspond second and
The U-shape of privates 114 and 116.Three-dimensional memory structure may also include a plurality of privates 118, and privates 118 will
Second and third conducting wire 114 and 116 is connected to X-decoder 120.Privates 118 be configured in second and third conducting wire 114 and
On 116.Second, third and privates 114,116 and 118 can be formed by metal.Second, third and privates 114,
116 and 118 can be formed by metal layer M1, M2 and M3 respectively.
From the point of view of another angle, the three-dimensional memory structure as manufactured by the above method includes multiple serial 102, more
Item the first conducting wire 104, a first metal layer M1 and a second metal layer M2.Serial 102 configured in parallel.The configuration of first conducting wire 104
On serial 102.The center portion of first conducting wire 104 is perpendicular to serial 102.First conducting wire 104 can be wordline.First metal
Layer M1 is configured on the first conducting wire 104.The first metal layer M1 includes a plurality of second conducting wire 114, the second conducting wire 114 connection first
The end section of the wherein half 104-1 of conducting wire.Second metal layer M2 is configured on the first metal layer M1.Second metal layer M2
Including a plurality of privates 116, privates 116 connects the end section of the other half 104-2 of the first conducting wire.Three-dimensional storage
Structure may also include a third metal layer M3, be configured on second metal layer M2.Third metal layer M3 includes a plurality of 4th leading
Second and third conducting wire 114 and 116 is connected to X-decoder 120 by line 118, privates 118.
In one embodiment, for go here and there row selecting switch 110-1 and 110-2 wiring (routing) can as shown in Figure 5 as
Ground configuration.Conductor 202 and 204 is for connecting string row selecting switch 110-1 and 110-2 and providing switch signal to serial choosing
Select switch 110-1 and 110-2.Conductor 202 can be formed by the first metal layer M1, and conductor 204 can be by second metal layer M2 institute
It is formed, or in contrast.Serial 102 selection be by two groups of string row selecting switch 110-1 and 110-2 collective effects come into
Row.Design in this way can reduce the number of conductor 202 and 204, thus first and second metal layer M1 and M2 can be used in
Form second and third conducting wire 114 and 116.
According to this specification, the first conducting wire (such as wordline) can be connected to by the route (such as metal wire) of high conductance
X-decoder.In this way, which an X-decoder is just enough to control array area.Therefore, the occupied space of X-decoder can drop
It is low, and the size of three-dimensional storage device can further reduce.
Although however, it is not to limit the invention in conclusion the present invention has been disclosed as a preferred embodiment.This hair
Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when various changes can be made
With retouching.Therefore, subject to protection scope of the present invention ought be defined depending on appended claims range.
Claims (8)
1. a kind of three-dimensional memory structure, comprising:
It is multiple serial, these serial configured in parallel；
A plurality of first conducting wire, be configured at these it is serial on, the center portions of these the first conducting wires is serial perpendicular to these, these
The other half of the wherein half of first conducting wire and these the first conducting wires are the U-shape towards opposite direction；
A plurality of second conducting wire is configured on these first conducting wires, these second conducting wires connect wherein the one of these the first conducting wires
Half end section；And
A plurality of privates is configured on these second conducting wires, these privates connect the other half of these the first conducting wires
End section；
Wherein, these second conducting wires and these privates are the U-shape towards opposite direction, these the first conducting wires this one
Half and these the first conducting wires this other half be the U-shape for respectively corresponding these the second conducting wires and these privates.
2. three-dimensional memory structure according to claim 1, further includes:
These second conducting wires and these privates are connected to X-decoder by a plurality of privates.
3. three-dimensional memory structure according to claim 2, wherein these privates be configured at these second conducting wires and
On these privates.
4. three-dimensional memory structure according to claim 2, wherein these second conducting wires, these privates and these
Four conducting wires are formed by metal.
5. three-dimensional memory structure according to claim 2, wherein these second conducting wires, these privates and these
Four conducting wires are to be formed respectively by metal layer.
6. three-dimensional memory structure according to claim 1, wherein these first conducting wires are wordline.
7. a kind of three-dimensional memory structure, comprising:
It is multiple serial, these serial configured in parallel；
A plurality of first conducting wire, be configured at these it is serial on, the center portions of these the first conducting wires is serial perpendicular to these, these
The other half of the wherein half of first conducting wire and these the first conducting wires are the U-shape towards opposite direction；
One the first metal layer is configured on these first conducting wires, which includes a plurality of second conducting wire, these second
Conducting wire connects the end section of the wherein half of these the first conducting wires；And
One second metal layer is configured on the first metal layer, which includes a plurality of privates, these thirds
Conducting wire connects the other half end section of these the first conducting wires；
Wherein, these second conducting wires and these privates are the U-shape towards opposite direction, these the first conducting wires this one
Half and these the first conducting wires this other half be the U-shape for respectively corresponding these the second conducting wires and these privates.
8. a kind of manufacturing method of three-dimensional memory structure, comprising:
Form multiple serial, these serial configured in parallel；
A plurality of first conducting wire is formed on these are serial, the center portion of these the first conducting wires is serial perpendicular to these, these
The other half of the wherein half of first conducting wire and these the first conducting wires are the U-shape towards opposite direction；
A plurality of second conducting wire is formed on these first conducting wires, these second conducting wires connect the wherein half of these the first conducting wires
End section；And
A plurality of privates is formed on these second conducting wires, these privates connect the other half of these the first conducting wires
End section；
Wherein, these second conducting wires and these privates are the U-shape towards opposite direction, these the first conducting wires this one
Half and these the first conducting wires this other half be the U-shape for respectively corresponding these the second conducting wires and these privates.
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| CN106033682B true CN106033682B (en) | 2019-09-24 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005456A (en) * | 2009-08-26 | 2011-04-06 | 三星电子株式会社 | Semiconductor memory device comprising three-dimensional memory cell array |
| CN104051467A (en) * | 2013-03-13 | 2014-09-17 | 旺宏电子股份有限公司 | 3-D IC Device with Enhanced Contact Area |
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| KR101778287B1 (en) * | 2010-08-30 | 2017-09-14 | 삼성전자주식회사 | Semiconductor memory devices and methods for fabricating the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005456A (en) * | 2009-08-26 | 2011-04-06 | 三星电子株式会社 | Semiconductor memory device comprising three-dimensional memory cell array |
| CN104051467A (en) * | 2013-03-13 | 2014-09-17 | 旺宏电子股份有限公司 | 3-D IC Device with Enhanced Contact Area |
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