TWI550774B - 3d memory structure and method for manufacturing the same - Google Patents

Description

Three-dimensional memory structure and manufacturing method thereof 【0001】

The present specification relates to a semiconductor structure and a method of fabricating the same, and more particularly to a three-dimensional (3D) memory structure and a method of fabricating the same.

【0002】

In a typical three-dimensional memory device, the word lines are primarily connected by polysilicon and germanium paths to the outer decoder, which paths are not highly conductive paths for signals. In order to improve the operational efficiency of the memory, two identical X decoders are often placed in the memory device on both sides of the memory array area. When selecting the memory cell to be operated, the two X decoders simultaneously transmit the same signal to The memory array area can reduce the path length of the signal to be transmitted, and can reduce the influence of the delay of the word line resistance.

[0003]

As the size of the memory device shrinks, the method of using two X decoders adversely affects the efficiency of the memory array region. The space occupied by the X decoder is reduced to increase the array area, and the delay potential of the word line is reduced. One such method is to use a metallized word line process. However, this process is extremely difficult to implement due to the complexity of the manufacturing process and yield control for the vertical gate structure.

[0004]

In the present specification, a three-dimensional memory structure and a method of fabricating the same are provided. In this three-dimensional memory structure, the space occupied by one X decoder is reduced to improve the efficiency of the array area.

[0005]

According to some embodiments, a three-dimensional memory structure includes a plurality of strings, a plurality of first wires, a plurality of second wires, and a plurality of third wires. Tandem parallel configuration. The first wire is disposed above the string. The central portion of the first wire is perpendicular to the string. The second wire is disposed above the first wire. The second wire connects the end portion of one half of the first wire. The third wire is disposed above the second wire. The third wire connects the end portion of the other half of the first wire.

[0006]

According to some embodiments, a three-dimensional memory structure includes a plurality of strings, a plurality of first wires, a first metal layer, and a second metal layer. Tandem parallel configuration. The first wire is disposed above the string. The central portion of the first wire is perpendicular to the string. The first metal layer is disposed on the first wire. The first metal layer includes a plurality of second wires, and the second wires connect the end portions of one half of the first wires. The second metal layer is disposed on the first metal layer. The second metal layer includes a plurality of third wires, and the third wire connects the end portions of the other half of the first wires.

【0007】

According to some embodiments, a method of fabricating a three-dimensional memory structure includes the following steps. First, a complex series is formed. Tandem parallel configuration. A plurality of first wires are formed over the series. The central portion of the first wire is perpendicular to the string. Next, a plurality of second wires are formed over the first wires. The second wire connects the end portion of one half of the first wire. A plurality of third wires are formed over the second wire. The third wire connects the end portion of the other half of the first wire.

[0008]

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

[0021]

102: Serial
104: first wire
104-1: Half of the first wire
104-2: The other half of the first wire
106: bit line pad
108: source pad
110-1, 110-2: Serial selection switch
112: Ground selection line
114: second wire
116: third wire
118: fourth wire
120: X decoder
202, 204: conductor
M1, M2, M3: metal layer

【0009】

1 to 4 illustrate a method of fabricating a three-dimensional memory structure according to an embodiment.
FIG. 5 illustrates a three-dimensional memory structure in accordance with an embodiment.

[0010]

A method of manufacturing a three-dimensional memory structure according to an embodiment will now be described. Referring to Fig. 1, a complex series 102 is formed. The series 102 are arranged in parallel. Next, a plurality of first wires 104 are formed over the series 102. The central portion of the first wire 104 is perpendicular to the string 102. One half of the first wire 104-1 and the other half of the first wire 104-2 may be U-shaped in opposite directions. In an embodiment, the first wire 104 is a word line.

[0011]

A bit line pad 106 and a source pad 108 may be formed. The bit line pad 106 and the source pad 108 terminate the string 102 at opposite ends of the string 102. String select switches 110-1 and 110-2 may be formed, and tandem select switches 110-1 and 110-2 are coupled to series 102 at near bit line pads 106. In one embodiment, the series 102 is controlled by AND-type serial selection switches 110-1 and 110-2. That is, a string 102 will be controlled by a pair of string select switches 110-1 and 110-2. Only when both the serial selection switch 110-1 and the serial selection switch 110-2 are turned on, the string 102 controlled by it is selected. A ground select line 112 may be formed that traverses the string 102 proximate to the source pads 108.

[0012]

Referring to FIG. 2, a plurality of second wires 114 are formed on the first wires 104. The second wire 114 connects the end portion of one half 104-1 of the first wire. The second wire 114 may be formed of a metal. More specifically, the second wire 114 may be formed of the first metal layer M1.

[0013]

Referring to FIG. 3, a plurality of third wires 116 are formed on the second wires 114. The third wire 116 connects the end portion of the other half 104-2 of the first wire. The third wire 116 may be formed of a metal. More specifically, the third wire 116 may be formed of the second metal layer M2. The second wire 114 and the third wire 116 may be U-shaped in opposite directions. The second wire 114 and the third wire 116 may have a U shape corresponding to one half of the first wire 104-1 and the other half of the first wire 104-2.

[0014]

Referring to FIG. 4, a plurality of fourth wires 118 are formed, and the fourth wires 118 connect the second and third wires 114 and 116 to the X decoder 120. The fourth wire 118 can be formed of metal. More specifically, the fourth wire 118 may be formed of the third metal layer M3 and may be formed above or below the second and third wires 114 and 116. In an embodiment, the third metal layer M3 further includes a fifth wire (not shown), and the fifth wire is located in the array region for connection of the bit lines.

[0015]

In the above method, the first wire 104 is connected to the X decoder by the second, third, and fourth wires 114, 116, and 118 formed by the first, second, and third metal layers M1, M2, and M3, respectively. 120. Such a process is compatible with typical three-dimensional memory processes and does not require additional steps. Since the second, third, and fourth wires 114, 116, and 118 are formed by a back-end-of-line process, there is no need to change the design of the array. Additionally, the second, third, and fourth conductors 114, 116, and 118 need not be formed in a fine pitch process. This is good for the process.

[0016]

The three-dimensional memory structure manufactured by the above method can be, for example, a three-dimensional inverse (NAND) flash memory structure. The three-dimensional memory structure includes a plurality of strings 102, a plurality of first wires 104, a plurality of second wires 114, and a plurality of third wires 116. The series 102 are arranged in parallel. The first wire 104 is disposed above the string 102. The central portion of the first wire 104 is perpendicular to the string 102. The first wire 104 can be a word line. The second wire 114 is disposed above the first wire 104. The second wire 114 connects the end portion of one half 104-1 of the first wire. The third wire 116 is disposed on the second wire 114. The third wire 116 connects the end portion of the other half 104-2 of the first wire. The second wire 114 and the third wire 116 may be U-shaped in opposite directions. One half of the first wire 104-1 and the other half of the first wire 104-2 may be U-shaped corresponding to the second and third wires 114 and 116, respectively. The three-dimensional memory structure can also include a plurality of fourth conductors 118 that connect the second and third conductors 114 and 116 to the X decoder 120. The fourth wire 118 can be disposed over the second and third wires 114 and 116. The second, third and fourth conductors 114, 116 and 118 may be formed from metal. The second, third, and fourth wires 114, 116, and 118 may be formed of metal layers M1, M2, and M3, respectively.

[0017]

In another aspect, the three-dimensional memory structure fabricated by the above method includes a plurality of strings 102, a plurality of first wires 104, a first metal layer M1, and a second metal layer M2. The series 102 are arranged in parallel. The first wire 104 is disposed above the string 102. The central portion of the first wire 104 is perpendicular to the string 102. The first wire 104 can be a word line. The first metal layer M1 is disposed on the first wire 104. The first metal layer M1 includes a plurality of second wires 114 connected to the end portions of one half 104-1 of the first wires. The second metal layer M2 is disposed on the first metal layer M1. The second metal layer M2 includes a plurality of third wires 116 that connect the end portions of the other half 104-2 of the first wires. The three-dimensional memory structure may further include a third metal layer M3 disposed on the second metal layer M2. The third metal layer M3 includes a plurality of fourth wires 118 that connect the second and third wires 114 and 116 to the X decoder 120.

[0018]

In an embodiment, the routing for the serial selection switches 110-1 and 110-2 can be configured as shown in FIG. Conductors 202 and 204 are used to connect series select switches 110-1 and 110-2 and to provide switching signals to series select switches 110-1 and 110-2. The conductor 202 may be formed of a first metal layer M1, and the conductor 204 may be formed of a second metal layer M2, or vice versa. The selection of the series 102 is performed by the two sets of serial selection switches 110-1 and 110-2. With such a design, the number of conductors 202 and 204 can be reduced, and thus the first and second metal layers M1 and M2 can be used to form the second and third conductors 114 and 116.

[0019]

According to the present specification, the first wire (e.g., word line) can be connected to the X decoder by a highly conductive line (e.g., a metal line). As a result, an X decoder is sufficient to control the array area. Therefore, the space occupied by the X decoder can be reduced, and the size of the three-dimensional memory device can be further reduced.

[0020]

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102: Serial

104: first wire

104-1: Half of the first wire

104-2: The other half of the first wire

106: bit line pad

108: source pad

110-1, 110-2: Serial selection switch

112: Ground selection line

114: second wire

116: third wire

118: fourth wire

120: X decoder

M3: metal layer

Claims (10)

[Item 1] A three-dimensional memory structure comprising:
a plurality of strings arranged in parallel;
a plurality of first wires disposed on the series, the central portions of the first wires being perpendicular to the series;
a plurality of second wires disposed on the first wires, the second wires connecting end portions of the first wires, and a plurality of third wires disposed on the second wires, The third wires connect the end portions of the other half of the first wires. [Item 2] The three-dimensional memory structure of claim 1, wherein the second wires and the third wires are U-shaped shapes facing in opposite directions. [Item 3] The three-dimensional memory structure of claim 2, wherein the half of the first wires and the other half of the first wires are respectively U-shaped corresponding to the second wires and the third wires. [Item 4] The three-dimensional memory structure of claim 1 further includes:
And a plurality of fourth wires connecting the second wires and the third wires to the X decoder. [Item 5] The three-dimensional memory structure of claim 4, wherein the fourth wires are disposed on the second wires and the third wires. [Item 6] The three-dimensional memory structure of claim 4, wherein the second wires, the third wires, and the fourth wires are formed of metal. [Item 7] The three-dimensional memory structure of claim 4, wherein the second wires, the third wires, and the fourth wires are respectively formed of a metal layer. [Item 8] The three-dimensional memory structure of claim 1, wherein the first wires are word lines. [Item 9] A three-dimensional memory structure comprising:
a plurality of strings arranged in parallel;
a plurality of first wires disposed on the series, the central portions of the first wires being perpendicular to the series;
a first metal layer disposed on the first wires, the first metal layer includes a plurality of second wires, the second wires connecting end portions of one half of the first wires; and a second metal And a layer disposed on the first metal layer, the second metal layer includes a plurality of third wires, and the third wires are connected to end portions of the other half of the first wires. [Item 10] A method of fabricating a three-dimensional memory structure, comprising:
Forming a plurality of strings arranged in parallel;
Forming a plurality of first wires on the series, the central portions of the first wires being perpendicular to the series;
Forming a plurality of second wires on the first wires, the second wires connecting end portions of one half of the first wires; and forming a plurality of third wires on the second wires, the A three wire connects the end portions of the other half of the first wires.