TWI570849B - Memory structure - Google Patents

Description

Memory structure

This invention relates to a semiconductor structure, and more particularly to a memory structure.

Semiconductor components are gradually becoming denser and smaller. Along with this trend, various three-dimensional (3D) memory structures have been developed. For many memory structures, some improvements are still possible to achieve lower RC delay, less overhead time, simpler process, and lower cost.

The present invention relates to a memory structure. According to some embodiments, such a memory structure includes M array regions and N contact regions. M is an integer equal to or greater than 2. N is an integer equal to or greater than M. The M array regions are respectively coupled to at least one of the N contact regions. The N contact regions each include a stepped structure and a plurality of contact elements. The stepped structure includes a plurality of electrically conductive layers and a plurality of insulating layers that are alternately stacked. The contact elements are each connected to one of the conductive layers of the stepped structure. Two array regions adjacent to each other in the M array regions are separated in space by two of the N contact regions, and the two contact regions are respectively coupled to the two array regions.

In order to better understand the above and other aspects of the present invention, The preferred embodiment is described in detail with reference to the accompanying drawings.

102‧‧‧Substrate

104(1)~104(8)‧‧‧Array area

106(1)~106(16)‧‧‧Contact area

108‧‧‧Stacking

110‧‧‧ Conductive layer

112‧‧‧Insulation

114‧‧‧Listing

116‧‧‧ step structure

118‧‧‧ Conductive layer

120‧‧‧Insulation

122, 122 (B), 122 (T) ‧ ‧ contact elements

124‧‧‧Wire

126‧‧‧Decoder

206‧‧‧Contact zone

A‧‧‧ area

d ₁₂ , d ₂₃ ‧ ‧ distance

P(1), P(2)‧‧‧ plane

Figure 1 is a schematic illustration of a memory structure in accordance with an embodiment.

2 and 3 are schematic perspective views showing elements in the area A of Fig. 1.

Figure 4 is a schematic illustration of a memory structure in accordance with another embodiment.

Figure 5 is a schematic illustration of a memory structure in accordance with yet another embodiment.

Various embodiments will be described in more detail below with reference to the drawings. It should be noted that, for the sake of clarity, the relative proportions of the various elements shown in the drawings may differ from their actual relative proportions.

A memory structure according to an embodiment of the invention includes M array regions and N contact regions. M is an integer equal to or greater than 2. N is an integer equal to or greater than M, and N is preferably greater than 3, more preferably greater than 7. The M array regions are respectively coupled to at least one of the N contact regions. The N contact regions each include a stepped structure and a plurality of contact elements. The stepped structure includes a plurality of electrically conductive layers and a plurality of insulating layers that are alternately stacked. The contact elements are each connected to one of the conductive layers of the stepped structure. Two array regions adjacent to each other in the M array regions are separated in space by two of the N contact regions, and the two contact regions are respectively coupled to the two array regions.

Please refer to FIG. 1, which illustrates a memory structure in accordance with an embodiment. In this embodiment, M=4 and N=8. As shown in FIG. 1, the array regions 104(1) to 104(4) and the contact regions 106(1) to 106(8) may be disposed on one substrate 102 of the memory structure. Here, N=2M, and each of the contact areas 106(1)~106(8) The contact regions are disposed on two sides of a corresponding one of the array regions 104(1) to 104(4). For example, the two contact regions 106(1), 106(2) coupled to the array region 104(1) are disposed on both sides of the array region 104(1). Two contact regions 106(3), 106(4) coupled to the array region 104(2) are disposed on both sides of the array region 104(2). Two contact regions 106 (5), 106 (6) coupled to the array region 104 (3) are disposed on both sides of the array region 104 (3). Similarly, the two contact regions 106 (7), 106 (8) coupled to the array region 104 (4) are disposed on both sides of the array region 104 (4). Two array regions adjacent to each other are separated in space by two contact regions respectively coupled to the two array regions, in particular, as shown in FIG. 2, one of the stepped structures in the contact region in space The stepwise arrangement direction is separated. For example, array regions 104(1) and 104(2) are separated in space by contact regions 106(2), 106(3). Array regions 104(2) and 104(3) are separated in space by contact regions 106(4), 106(5). Array regions 104(3) and 104(4) are separated in space by contact regions 106(6), 106(7). The memory structure may also include two decoders 126, such as an X decoder, wherein array regions 104(1)-104(4) and contact regions 106(1)-106(8) are disposed in the two decoders 126. between.

Exemplary structural details of the array regions and contact regions are shown in FIG. Only the partial array area 104(1) and the contact areas 106(1) to 106(3) in the area A of Fig. 1 are shown in Fig. 2, and the description will mainly focus on the array area 104(1). And contact area 106 (1). Nonetheless, other array regions and contact regions may have similar structural types. According to Fig. 2, the memory structure can be applied to a 3D vertical channel NAND memory, but the present invention is not limited thereto.

Referring to FIG. 2, the array area 104(1) may include a stack 108 and a plurality of strings 114. The stack 108 includes a plurality of conductive layers 110 and a plurality of insulating layers 112 that are alternately stacked and may be disposed on the substrate 102. The conductive layer 110 may be fabricated from a metal, heavily doped germanium or the like, wherein the heavily doped germanium comprises an n-type or p-type dopant and has a doping concentration higher than 10 ²⁰ cm ^-3 . The stack 108 can extend in the X direction and the conductive layer 110 in the stack 108 can function as a word line. Array area 104(1) may include a plurality of blocks defined by a word line layer. The string 114 passes through the stack 108. As such, a plurality of memory cells can be formed at the intersection of the string 114 and the conductive layer 110. In addition, a plurality of string selection lines (not shown) and a plurality of bit lines (not shown) may be disposed on the string 114 and connected to the string 114, wherein the string selection line may extend in the X direction The bit line may extend in the Y direction.

Contact region 106(1) includes a stepped structure 116 and a plurality of contact elements 122. The stepped structure 116 includes a plurality of conductive layers 118 and a plurality of insulating layers 120 that are alternately stacked and may be disposed on the substrate 102. Conductive layer 118 may be fabricated from a metal, heavily doped germanium or similar material, wherein the heavily doped germanium comprises an n-type or p-type dopant and has a doping concentration greater than 10 ²⁰ cm ^-3 . A stack 108 of each of the contact regions 106(1)-106(8) and a corresponding one of the array regions 104(1)-104(4) may be formed continuously. More specifically, stack 108 and stepped structure 116 can be fabricated from the same process from the same process. Contact elements 122 are each coupled to one of conductive layers 118.

The two contact regions separating the two adjacent array regions are electrically connected to each other but are at least partially separated in space. For example, as shown in FIG. 3, the contact elements 122 of different contact regions (only the contact regions 106(1) to 106(3) are shown in FIG. 3) may be provided by wires disposed above the array region and the contact region. 124 connected. More specifically, the contact elements 122 connected to the conductive layer 118 of the same layer are connected by the same wires 124. The wire 124 may be fabricated from a material having high electrical conductivity, such as made of metal. In the embodiment shown in Figures 2 and 3, the contact area 106 (2) And 106(3) are completely separated in space. In an alternative embodiment, contact regions 106(2) and 106(3) may be partially separated in space. For example, the conductive layers 118 at the lower layers may not be separated.

Referring now to FIG. 1 and FIG. 2 simultaneously, in particular, the N contact regions may include an ith contact region, an (i+1)th contact region, a jth contact region, and a first (j) +1) contact area, where i is an odd number of 1~(N-1) and j is an even number of 2~(N-2). The ith contact region and the (i+1)th contact region may be disposed in a mirror symmetrical manner, and the jth contact region and the (j+1)th contact region may be disposed in a mirror symmetrical manner. For example, the first contact region 106(1) and the second contact region 106(2) are disposed in a mirror symmetrical manner, and the second contact region 106(2) and the third contact region 106(3) are mirror symmetrical. Way to set. The N contact regions may have a distance d _i(i+1) between the ith contact region and the (i+1)th contact region, between the jth contact region and the (j+1) contact region Has a distance d _j(j+1) . The distance between two adjacent contact regions is defined as the distance between the closest pair of contact elements 122. For example, as shown in FIG. 2, the distance d ₁₂ between the first contact region 106 (1) and the second contact region 106 (2) is defined as the highest of the contact regions 106 (1), 106 (2). The distance between the upper contact elements 122 (T), the distance d ₂₃ between the second contact region 106 (2) and the third contact region 106 (3) is defined as the contact regions 106 (2) and 106 (3) The distance between the lowermost contact elements 122 (B). In some embodiments, as shown in FIG. 1, d _i(i+1) >d _j(j+1) , in particular d _i(i+1) /d _j(j+1) >100, wherein d _{j(j+1) is} less than 10 microns. That is, d ₁₂ , d ₃₄ , d ₅₆ , and d _{78 are} larger than d ₂₃ , d ₄₅ , and d ₆₇ (d ₃₄ , d ₄₅ , d ₅₆ , d ₆₇ , d ₇₈ are not indicated in the drawings). In particular, larger distances can exceed 100 times the smaller distance, with smaller distances being less than 10 microns.

Here, due to the shortening of the length of the word line layer, and the plurality of contact areas The setting, the resistance and capacitance of the word line can be reduced. Therefore, the resistance-capacitance delay and power consumption of the memory structure can be reduced. This is particularly advantageous for the case where the word line layer is made of doped polysilicon. Furthermore, a plurality of array regions are disposed between a pair of decoders and are controlled by the pair of decoders. Compared to the case where a pair of decoders is provided for each array area, the number of decoders can be reduced, thereby reducing the cost.

In addition, because the contact regions are disposed in a symmetrical manner relative to the array region, some simpler and less expensive processes can be used to form the contact regions. For example, a trimming process can be applied, which is an isotropic etching process, typically used in a symmetrical structure. The trimming process is particularly advantageous for process costs.

Please refer to FIG. 4, which illustrates a memory structure in accordance with another embodiment. This embodiment differs from the embodiment of Figure 1 in that each of the array regions 104(1)-104(4) is completely surrounded by a contact region 206. From another perspective, each of the two contact zones are connected to each other to surround the corresponding array zone. For example, contact regions 106(1) and 106(2) shown in FIG. 1 are connected to each other and form a contact region 206 surrounding array region 104(1). The contact regions 106(3) and 106(4) shown in Fig. 1 are connected to each other and form a contact region 206 surrounding the array region 104(2). The contact regions 106 (5) and 106 (6) shown in Fig. 1 are connected to each other and form a contact region 206 surrounding the array region 104 (3). Similarly, the contact regions 106 (7) and 106 (8) shown in Figure 1 are connected to each other and form a contact region 206 surrounding the array region 104 (4). This type of structure is more conducive to the application of the trimming process.

Moreover, according to some embodiments, the memory structure can have a multi-plane design, such as shown in the embodiment of FIG. Here, the term "flat" "face" should not be understood from a spatial perspective, but should be understood from an electrical perspective. The multi-planar design allows for extra time reduction. For example, a first instruction address can be sent first and a first data will be read. While waiting for the first data, a second instruction address can be sent. As a result, time is saved. The memory structure can include a plurality of planes, wherein the planes respectively include at least two array regions and at least two contact regions, the at least two array regions and the at least two contact regions are disposed in two decodings of the memory structure Between the two, and the two adjacent to each other in the at least two array regions are separated in space by the two of the at least two contact regions. For example, in the embodiment shown in FIG. 5, the memory structure includes two planes P(1) and P(2). The plane P(1) includes four array regions 104(1) to 104(4) and eight contact regions 106(1) to 106(8), and the plane P(2) includes four array regions 104(5) to 104. (8) and eight contact areas 106(9)~106(16). The planes P(1) and P(2) have the structural forms as described above, respectively. That is, in each of the planes P(1), P(2), two adjacent array regions are separated in space by two contact regions respectively coupled to the two array regions.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102‧‧‧Substrate

104(1)~104(4)‧‧‧Array area

106(1)~106(8)‧‧‧Contact zone

126‧‧‧Decoder

A‧‧‧ area

P(1)‧‧‧ plane

Claims (10)

A memory structure comprising: M array regions, wherein M is an integer equal to or greater than 2; and N contact regions, wherein N is an integer equal to or greater than M, and the M array regions are respectively coupled to the N At least one of the contact regions, the N contact regions respectively include: a stepped structure including a plurality of electrically conductive layers and a plurality of insulating layers alternately stacked; and a plurality of contact elements respectively connected to the stepped structure One of the conductive layers; wherein the two array regions adjacent to each other in the M array regions are in the space of the N contact regions by the two contact regions of the N contact regions A stepwise arrangement of the structures is separated, and the two contact regions are respectively coupled to the two array regions. The memory structure of claim 1, wherein the two contact regions are electrically connected to each other but are at least partially separated in space. The memory structure of claim 1, wherein N=2M, and each of the two contact regions is disposed on two sides of a corresponding one of the M array regions. The memory structure of claim 3, wherein the N contact regions have a distance d _i(i+1) between an ith contact region and an (i+1)th contact region, in a jth contact region And a (j+1) contact zone having a distance d _j(j+1) , i is an odd number of 1~(N-1), and j is an even number of 2~(N-2), and wherein d _i(i+1) >d _j(j+1) , and d _i(i+1) /d _j(j+1) >100. The memory structure of claim 4, wherein d _{j(j+1) is} less than 10 microns. The memory structure of claim 3, wherein the N contact regions comprise an ith contact region, an (i+1)th contact region, a jth contact region, and a (j+1)th contact region, i is An odd number of 1~(N-1), j is an even number of 2~(N-2), and wherein the ith contact region and the (i+1)th contact region are arranged in a mirror symmetrical manner, the jth The contact zone and the (j+1)th contact zone are arranged in a mirror symmetrical manner. The memory structure of claim 3, wherein each of the two contact regions are connected to each other to surround the corresponding array region. The memory structure of claim 1, further comprising: two decoders, wherein the M array regions and the N contact regions are disposed between the two decoders. The memory structure of claim 1, comprising a plurality of planes, each of the planes comprising: at least two of the M array regions and at least two of the N contact regions, wherein the at least two The array area and the at least two contact areas are disposed between two decoders of the memory structure, and two of the at least two array areas adjacent to each other are two of the at least two contact areas Separated in space. The memory structure of claim 1, wherein the M array regions respectively comprise: a stack comprising a plurality of electrically conductive layers and a plurality of insulating layers stacked alternately; and a plurality of strings passing through the stack; wherein the N The stepped structure of each of the contact regions and the stack of the corresponding one of the M array regions are continuously formed.