CN106505068B - Memory construction - Google Patents
Memory construction Download PDFInfo
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- CN106505068B CN106505068B CN201510558132.0A CN201510558132A CN106505068B CN 106505068 B CN106505068 B CN 106505068B CN 201510558132 A CN201510558132 A CN 201510558132A CN 106505068 B CN106505068 B CN 106505068B
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Abstract
The invention discloses a kind of memory constructions.Such memory construction includes M array area and N number of contact zone.M is the integer equal to or more than 2.N is the integer equal to or more than M.Array area is respectively coupled at least one of contact zone.Contact zone respectively includes a stepped structure and multiple contact elements.The stepped structure includes the multiple conductive layers and multiple insulating layers of alternative stacked.These contact elements are respectively connected to one of conductive layer of the stepped structure.Two array areas adjacent to each other are separated in space by two contact zones, which is to be respectively coupled to two array areas.
Description
Technical field
The present invention relates to a kind of semiconductor structures, especially with regard to a kind of memory construction.
Background technique
Semiconductor element is just gradually becoming more dense and smaller.With this burst of trend, various three-dimensional (3D) memory knots
Structure is developed.For many kinds of memory constructions, it would still be possible to make some improvement, be prolonged with reaching lower resistance capacitance
The benefits such as (RC delay), less extra time (overhead time), better simply technique and lower cost late.
Summary of the invention
The present invention relates to a kind of memory constructions.According to some embodiments, such memory construction includes M array area
And N number of contact zone.M is the integer equal to or more than 2.N is the integer equal to or more than M.M array area is respectively coupled to N number of
At least one of contact zone.N number of contact zone respectively includes a stepped structure and multiple contact elements.Stepped structure includes handing over
For the multiple conductive layers and multiple insulating layers of lamination.Contact element is respectively connected to one of conductive layer of stepped structure.M
Two array areas adjacent to each other are separated in space by two contact zones in N number of contact zone in array area, this two connect
Touching area is to be respectively coupled to two array areas.
More preferably understand to have to above-mentioned and other aspect of the invention, preferred embodiment is cited below particularly, and cooperates institute
Accompanying drawings are described in detail below:
Detailed description of the invention
Fig. 1 is the schematic diagram according to the memory construction of an embodiment.
Fig. 2 and Fig. 3 is the perspective diagram for the element being painted in the region A of Fig. 1.
Fig. 4 is the schematic diagram according to the memory construction of another embodiment.
Fig. 5 is the schematic diagram according to the memory construction of another embodiment.
[symbol description]
102: substrate
104 (1)~104 (8): array area
106 (1)~106 (16): contact zone
108: lamination
110: conductive layer
112: insulating layer
114: serial
116: stepped structure
118: conductive layer
120: insulating layer
122,122 (B), 122 (T): contact element
124: conducting wire
126: decoder
206: contact zone
A: region
d12、d23: distance
P (1), P (2): plane
Specific embodiment
Hereinafter with reference to institute's accompanying drawings, a variety of different embodiments are described in detail.It is noted that being
For the sake of clear, the relative scale of each element shown in schema may be different from its actual relative scale.
Memory construction according to an embodiment of the present invention, including M array area and N number of contact zone.M is equal to or more than 2
Integer.N is the integer equal to or more than M, and N is preferably greater than 3, even more preferably greater than 7.M array area is respectively coupled to N number of connect
Touch at least one of area.N number of contact zone respectively includes a stepped structure and multiple contact elements.Stepped structure includes alternating
The multiple conductive layers and multiple insulating layers of lamination.Contact element is respectively connected to one of conductive layer of stepped structure.M battle array
Arranging two array areas adjacent to each other in area is separated in space by two contact zones in N number of contact zone, this two contacts
Area is to be respectively coupled to two array areas.
Fig. 1 is please referred to, the memory construction according to an embodiment is shown.In this embodiment, M=4 and N=8.Such as
Shown in Fig. 1, array area 104 (1)~104 (4) and contact zone 106 (1)~106 (8) may be provided at a base of memory construction
On plate 102.Here, N=2M, and every two contact zones in contact zone 106 (1)~106 (8) are arranged in array area 104 (1)
Two sides of a corresponding array area in~104 (4).For example, two contact zones 106 of array area 104 (1) are coupled to
(1), 106 (2) are two sides of the setting in array area 104 (1).It is coupled to two contact zones 106 (3), 106 of array area 104 (2)
It (4) is two sides of the setting in array area 104 (2).It is coupled to two contact zones 106 (5) of array area 104 (3), 106 (6) are to set
It sets in two sides of array area 104 (3).Similarly, two contact zones 106 (7) of array area 104 (4) are coupled to, 106 (8) are to set
It sets in two sides of array area 104 (4).Two array areas adjacent to each other are connect by being respectively coupled to the two of two array areas
Touching area separates in space.For example, array area 104 (1) and 104 (2) be by contact zone 106 (2), 106 (3) in space
Separation.Array area 104 (2) and 104 (3) are separated in space by contact zone 106 (4), 106 (5).Array area 104 (3) and
104 (4) are separated in space by contact zone 106 (6), 106 (7).Memory construction may also include two decoders 126, example
Such as X-decoder, wherein array area 104 (1)~104 (4) and contact zone 106 (1)~106 (8) are arranged in two decoders
Between 126.
The illustrative CONSTRUCTED SPECIFICATION in array area and contact zone is illustrated in Fig. 2.It is only shown in Fig. 2 in the region A of Fig. 1
Partial array area 104 (1) and contact zone 106 (1)~106 (3), and describe content and will concentrate mainly on array area 104 (1) and connect
It touches area 106 (1).Even so, other array areas and contact zone can have similar structure kenel.According to fig. 2, memory knot
Structure can be applicable to 3D vertical channel nand memory, but the present invention is not limited to this.
Referring to figure 2., array area 104 (1) may include a lamination 108 and multiple serial 114.Lamination 108 includes alternating
The multiple conductive layers 110 and multiple insulating layers 112 of lamination, and it is settable on substrate 102.Conductive layer 110 can be by metal, heavily doped
Miscellaneous silicon or similar material is fabricated, wherein the silicon of the heavy doping includes the dopant of N-shaped or p-type, and doping concentration is high
In 1020cm-3.Lamination 108 can extend in the X direction, and the conductive layer 110 in lamination 108 can be used as wordline.Array area 104
(1) it may include multiple blocks, defined by word line layer.Serial 114 pass through lamination 108.In this way, which multiple storage units can
It is formed in the intersection point of serial 114 and conductive layer 110.In addition, a plurality of serial selection line (not being painted) and multiple bit lines (not being painted)
It may be provided on serial 114 and be connected to serial 114, wherein serial selection line can extend in the X direction, and bit line can be in the side Y
It is upwardly extended to side.
Contact zone 106 (1) includes a stepped structure 116 and multiple contact elements 122.Stepped structure 116 includes alternating
The multiple conductive layers 118 and multiple insulating layers 120 of lamination, and it is settable on substrate 102.Conductive layer 118 can be by metal, heavily doped
Miscellaneous silicon or similar material is fabricated, wherein the silicon of the heavy doping includes the dopant of N-shaped or p-type, and doping concentration is high
In 1020cm-3.Corresponding one in contact zone 106 (1)~106 (8) each stepped structure 116 and array area 104 (1)~104 (4)
The lamination 108 of person can be formed to continuity.More specifically, lamination 108 and stepped structure 116 can be with identical materials by phase
Same technique is fabricated.Contact element 122 is respectively connected to one of conductive layer 118.
Two contact zones for separating two adjacent array areas are to be electrically connected to each other, but at least partly divide in space
From.For example, as shown in figure 3, the contact element of different contact zone (only showing contact zone 106 (1)~106 (3) in Fig. 3)
122 can be connected by array area is arranged in the conducting wire 124 on contact zone.More specifically, it is connected to the conduction of same layer
The contact element 122 of layer 118, is connected by identical conducting wire 124.Conducting wire 124 can by the material with high conductivity manufacture and
At, such as be fabricated by metal.In Fig. 2 and embodiment shown in Fig. 3, contact zone 106 (2) and 106 (3) are complete in space
It is fully separating.In alternative embodiment, contact zone 106 (2) and 106 (3) can be partially separated in space.For example,
It can not be separated to come in lower several layers of conductive layer 118.
Now referring to Fig. 1 and Fig. 2, specifically, N number of contact zone may include i-th contact zone, one
The contact zone (i+1), a jth contact zone and the contact zone (j+1), wherein i be the odd number of 1~(N-1), j be 2~
(N-2) even number.I-th contact zone and the contact zone (i+1) can be arranged in a manner of mirror symmetry, jth contact zone and (j+
1) contact zone can be arranged in a manner of mirror symmetry.For example, the first contact zone 106 (1) and the second contact zone 106 (2)
It is to be arranged in a manner of mirror symmetry, the second contact zone 106 (2) and third contact zone 106 (3) are to set in a manner of mirror symmetry
It sets.N number of contact zone can have a distance d between the i-th contact zone and the contact zone (i+1)i(i+1), in jth contact zone and
There is a distance d between the contact zone (j+1)j(j+1).The distance between two adjacent contact areas are defined as immediate one
To the distance between contact element 122.For example, as shown in Fig. 2, the first contact zone 106 (1) and the second contact zone 106 (2)
The distance between d12It is defined as the distance between the contact element 122 (T) of the top of contact zone 106 (1), 106 (2), the
The distance between two contact zones 106 (2) and third contact zone 106 (3) d23It is defined as contact zone 106 (2) and 106 (3) most
The distance between contact element 122 (B) of lower section.In some embodiments, as shown in Figure 1, di(i+1)> dj(j+1), especially
di(i+1)/dj(j+1)> 100, wherein dj(j+1)Less than 10 microns.Also that is, d12、d34、d56、d78Greater than d23、d45、d67(in schema simultaneously
D is not indicated34、d45、d56、d67、d78).In particular, biggish distance can be more than 100 times of lesser distance, wherein lesser
Distance is less than 10 microns.
Here, due to the shortening of the length of word line layer and the setting of multiple contact zones, the resistance and capacitor of wordline can subtract
It is low.Therefore, RC delays and the power consumption (power consumption) of memory construction be can reduce.This is right
Case made of being as manufactured by DOPOS doped polycrystalline silicon in word line layer is particularly advantageous.Furthermore multiple array areas are arranged in a pair
Between decoder, and decoder is controlled by this.For the case to a pair of of decoder of each array area offer,
The number of decoder can be reduced, to reduce cost.
In addition, because contact zone is to be arranged in a symmetrical manner for array area, some simpler and cheap
Technique can be in the formation of contact zone.For example, trimming technique (trimming process) can be applied, for one kind
Isotropic etch process is typically used in symmetrical structure.Trimming technique is particularly conducive to process costs.
Referring to figure 4., memory construction according to another embodiment is shown.This embodiment and the embodiment of Fig. 1
Difference is that each array area 104 (1)~104 (4) are fully to be surround by a contact zone 206.From another angle
From the point of view of degree, every two contact zones are connected to each other to surround corresponding array area.For example, contact zone 106 shown in FIG. 1
(1) it is connected to each other, and is formed around a contact zone 206 of array area 104 (1) with 106 (2).Contact zone 106 shown in FIG. 1
(3) it is connected to each other, and is formed around a contact zone 206 of array area 104 (2) with 106 (4).Contact zone 106 shown in FIG. 1
(5) it is connected to each other, and is formed around a contact zone 206 of array area 104 (3) with 106 (6).Similarly, shown in FIG. 1 to connect
Touching area 106 (7) and 106 (8) are connected to each other, and are formed around a contact zone 206 of array area 104 (4).Such structural type
State is more advantageous to the application of trimming technique.
In addition, memory construction can have the design of more planes (multi-plane), such as Fig. 5 according to some embodiments
Embodiment shown in.Here, term " plane " should not be understood with angle spatially, and should be managed with the angle in electrical property
Solution.Multilevel design allows the reduction of extra time.For example, one first IA transmittable first, and will read
One first data.While waiting the first data, one second IA can be transmitted.In this way, which the time is just saved down
Come.Memory construction may include multiple planes, and wherein these planes respectively include at least two array areas and at least two contacts
Area, at least two array areas and at least two contact zones are to be arranged between two decoders of memory construction, and be somebody's turn to do
The two adjacent to each other is that at least both of two contact zones separate in space by this at least two array areas.Citing comes
It says, in the embodiment shown in fig. 5, memory construction includes two plane P (1) and P (2).Plane P (1) includes four arrays
Area 104 (1)~104 (4) and eight contact zones 106 (1)~106 (8), plane P (2) include four array area 104 (5)~104
(8) and eight contact zones 106 (9)~106 (16).Plane P (1), P (2) are respectively provided with structure kenel as described above.Also that is,
In plane P (1), P (2) each, two adjacent array areas are by being respectively coupled to the two of two array areas contact zones
It separates in space.
Although however, it is not to limit the invention in conclusion the present invention has been disclosed as a preferred embodiment.This hair
Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when various changes can be made
With retouching.Therefore, subject to protection scope of the present invention ought be defined depending on appended claims range.
Claims (8)
1. a kind of memory construction, comprising:
M array area, wherein M is the integer equal to or more than 2；
N number of contact zone, wherein N is the integer equal to or more than M, which is respectively coupled in N number of contact zone extremely
Few one, N number of contact zone respectively include:
One stepped structure, multiple conductive layers and multiple insulating layers including alternative stacked；And
Multiple contact elements, are respectively connected to one of these conductive layers of the stepped structure；And
Two decoders, the M array area and N number of contact zone are arranged between two decoders；
Wherein two array areas adjacent to each other in the M array area are by two contact zones in N number of contact zone in space
Middle separation, two contact zones are to be respectively coupled to two array areas；
The memory construction further includes multiple planes not overlapped each other, these planes respectively include: in the M array area extremely
At least two contact zones in few two array areas and N number of contact zone, wherein at least two array areas and this at least two
Contact zone is the two being arranged between two decoders of the memory construction, and adjacent to each other at least two array areas
It is that at least both of two contact zones separate in space by this, wherein without any decoder the M in these planes
Between array area.
2. memory construction according to claim 1, wherein two contact zones are to be electrically connected to each other, but in space
At least partly separate.
3. memory construction according to claim 1, wherein N=2M, and every two contact zones in N number of contact zone are
Two sides of a corresponding array area in the M array area are set.
4. memory construction according to claim 3, wherein N number of contact zone is in i-th contact zone and (an i+
1) there is a distance d between contact zonei(i+1), between a jth contact zone and the contact zone (j+1) have a distance
dj(j+1), i is the odd number of 1~(N-1), and j is the even number of 2~(N-2), and
Wherein di(i+1)> dj(j+1), and di(i+1)/dj(j+1)> 100.
5. memory construction according to claim 4, wherein dj(j+1)Less than 10 microns.
6. memory construction according to claim 3, wherein N number of contact zone includes i-th contact zone, (an i
+ 1) contact zone, a jth contact zone and the contact zone (j+1), i are the odd number of 1~(N-1), and j is the idol of 2~(N-2)
Number, and
Wherein i-th contact zone and the contact zone (i+1) are to be arranged in a manner of mirror symmetry, the jth contact zone and this
(j+1) contact zone is to be arranged in a manner of mirror symmetry.
7. memory construction according to claim 3, wherein every two contact zones are connected to each other with circular corresponding
The array area.
8. memory construction according to claim 1, the wherein M array area respectively include:
One lamination, multiple conductive layers and multiple insulating layers including alternative stacked；And
It is multiple serial, pass through the lamination；
The lamination that one is wherein corresponded in the stepped structure of N number of contact zone each and the M array area is continuity
It is formed.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510558132.0A CN106505068B (en) | 2015-09-06 | 2015-09-06 | Memory construction |
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|---|---|---|---|
| CN201510558132.0A CN106505068B (en) | 2015-09-06 | 2015-09-06 | Memory construction |
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| CN106505068A CN106505068A (en) | 2017-03-15 |
| CN106505068B true CN106505068B (en) | 2019-09-24 |
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| CN108364954B (en) * | 2018-03-14 | 2020-10-27 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of forming epitaxial structure in channel hole thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201021201A (en) * | 2008-11-04 | 2010-06-01 | Toshiba Kk | Semiconductor memory device |
| CN104051326A (en) * | 2013-03-12 | 2014-09-17 | 旺宏电子股份有限公司 | Forming method of device with contact landing areas at different depths of substrate and 3-D structure |
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| JP4427847B2 (en) * | 1999-11-04 | 2010-03-10 | エルピーダメモリ株式会社 | Dynamic RAM and semiconductor device |
| KR101624975B1 (en) * | 2009-11-17 | 2016-05-30 | 삼성전자주식회사 | Three dimensional semiconductor memory devices |
| KR102024723B1 (en) * | 2013-01-02 | 2019-09-24 | 삼성전자주식회사 | Three dimensional semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201021201A (en) * | 2008-11-04 | 2010-06-01 | Toshiba Kk | Semiconductor memory device |
| CN104051326A (en) * | 2013-03-12 | 2014-09-17 | 旺宏电子股份有限公司 | Forming method of device with contact landing areas at different depths of substrate and 3-D structure |
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