TWI572014B - Non-volatile memory - Google Patents

Description

Non-volatile memory

This invention relates to a memory, and more particularly to a non-volatile memory.

Since the non-volatile memory element has the advantage that the stored data does not disappear after the power is turned off, it is a memory element widely used in personal computers and electronic devices.

The flash memory arrays currently used in the industry include an inverted OR gate (NOR) type array structure and a NAND type array structure. Since the non-volatile memory structure of the NAND type array is such that the memory cells are connected in series, the degree of integration and area utilization is better than that of the non-volatile memory of the gate (NOR) type array. , has been widely used in a variety of electronic products.

However, under the current trend of miniaturization of components, how to further enhance the accumulation of memory components in a limited space is an active goal of the industry.

The invention provides a non-volatile memory, which can effectively reduce the memory cell area in the three-dimensional memory, thereby improving the integration of the memory elements.

The invention provides a non-volatile memory comprising a substrate, a stacked structure, two channel structures and two layers of charge storage layers. The stacked structure is disposed on the substrate and includes a plurality of first conductor layers, a plurality of dielectric layers, and two second conductor layers. The dielectric layer and the first conductor layer are alternately stacked. The second conductor layer is separately disposed on the uppermost one of the dielectric layers. The channel structure is disposed on the substrate on both sides of the stack structure. The charge storage layer is disposed between the stacked structure and the channel structure.

According to an embodiment of the present invention, in the non-volatile memory described above, the stacked structure further includes a first isolation structure. The first isolation structure is disposed between the second conductor layers.

According to an embodiment of the present invention, in the non-volatile memory, the width of each of the second conductor layers is, for example, smaller than the width of each of the first conductor layers.

According to an embodiment of the invention, in the non-volatile memory described above, the channel structures are coupled to each other. The manner in which the channel structures are coupled to each other can be coupled by forming a connection portion of the channel structure and the connection channel structure by integral molding or can be coupled by the interconnection structure.

According to an embodiment of the invention, in the non-volatile memory, the second isolation structure is further included. The second isolation structure is disposed in the channel structure.

According to an embodiment of the present invention, in the non-volatile memory, the bottom height of each isolation structure is, for example, lower than or equal to the lowest of the first conductor layers. The lower surface height of one of the sides, and the top height of each of the isolation structures is, for example, higher than or equal to the upper surface height of the second conductor layer.

According to an embodiment of the present invention, in the non-volatile memory, when the non-volatile memory includes a plurality of stacked structures, each of the channel structures includes a two-layer main channel portion and two spacer channel portions. The main channel portion is disposed on the bases on both sides of each of the second isolation structures, and the bottoms of the main channel portions are connected to each other or are not connected to each other. The spacer channel portion is disposed between the charge storage layer and the main channel portion between the adjacent two stacked structures.

According to an embodiment of the invention, in the non-volatile memory, the first doped region is further included. The first doped region is disposed in the substrate.

According to an embodiment of the invention, in the non-volatile memory, the second doping region is further included. The second doped region is disposed in the first doped region below the channel structure.

According to an embodiment of the invention, in the non-volatile memory described above, a wire is further included. The wire is coupled to the channel structure.

Based on the above, in the non-volatile memory proposed by the present invention, since the stacked structure includes the stacked first conductor layer, the dielectric layer, and the separated two second conductor layers, a single stacked structure can be used. Two strings of NAND memory cells are formed. The second conductor layer can serve as a selection gate to select which side of the stacked structure is to operate the charge storage layer in the NAND memory cell string, and each of the first conductor layers can operate on the charge storage layer on both sides thereof. Further, a single memory cell of two bits per cell is formed. Therefore, the above non-volatile memory It can effectively reduce the memory cell area in the three-dimensional memory, thereby improving the accumulation of memory components.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Non-volatile memory

102‧‧‧Base

104‧‧‧Stack structure

106‧‧‧Channel structure

108‧‧‧Charge storage layer

110, 114‧‧‧ conductor layer

112, 118‧‧‧ dielectric layer

116, 124‧‧‧Isolation structure

120, 134‧‧‧ hard mask layer

122‧‧‧Connecting Department

126‧‧‧Main Channel Department

127‧‧‧Channel material layer

128‧‧‧clear channel section

130, 132‧‧‧Doped area

136‧‧‧ wire

138‧‧‧Contact window

140‧‧‧ memory cells

BL1~BL3‧‧‧ bit line

CG‧‧‧Control gate

CSL‧‧‧ source line

WL1~WL6‧‧‧ character line

SGL1-1~SGL1-3, SGL2-1~SGL2-6‧‧‧Select gate line

SGD, SGS‧‧‧ select gate

1 is a cross-sectional view showing a non-volatile memory according to an embodiment of the present invention.

2 is a perspective view of a portion of the non-volatile memory of FIG. 1.

3 is a cross-sectional view showing a non-volatile memory according to another embodiment of the present invention.

4 is a perspective view of a portion of the non-volatile memory of FIG. 3.

FIG. 5 is a schematic circuit diagram of the non-volatile memory of FIGS. 1 and 3.

Figure 6 is a schematic diagram of another circuit of the non-volatile memory of Figures 1 and 3.

1 is a cross-sectional view showing a non-volatile memory according to an embodiment of the present invention. 2 is a perspective view of a portion of the non-volatile memory of FIG. 1. In FIG. 2, for the sake of clarity, only the charge storage layer on the sidewall of the conductor layer is illustrated, and the isolation structure in the dielectric layer, the hard mask layer, and the stacked structure is omitted.

Referring to FIG. 1 and FIG. 2 simultaneously, the non-volatile memory 100 includes a substrate 102, a stacked structure 104, a channel structure 106, and a charge storage layer 108. The substrate 102 is, for example, a crucible substrate. In this embodiment, the stack structure 104 and the pass in FIG. 1 and FIG. The number of the track structure 106 and the charge storage layer 108 is merely illustrative, and the invention is not limited thereto. As long as the non-volatile memory 100 comprises a stacked structure 104, two channel structures 106 and two layers of charge storage layer 108, it is within the scope of the present invention.

The stacked structure 104 is disposed on the substrate 102. Each of the stacked structures 104 includes a plurality of conductor layers 110, a plurality of dielectric layers 112, and two conductor layers 114. In this embodiment, the number of the conductor layer 110 and the dielectric layer 112 in FIG. 1 and FIG. 2 is merely illustrative, and the invention is not limited thereto. Those skilled in the art can adjust the number of conductor layers 110 and dielectric layers 112 in accordance with product design requirements.

The dielectric layer 112 and the conductor layer 110 are alternately stacked. In this embodiment, the dielectric layer 112 is taken as the lowermost layer of the stacked structure 104 as an example, so that the conductor layer 110 can be isolated from the substrate 102 by the dielectric layer 112. The conductor layer 110 can be used as a control gate or a select gate in accordance with product design requirements. The material of the dielectric layer 112 is, for example, a dielectric material such as ruthenium oxide. The material of the conductor layer 110 is, for example, a conductor material such as doped polysilicon. The method of forming the dielectric layer 112 and the conductor layer 110 is formed, for example, by using a deposition process, a lithography process, and an etching process in combination.

The conductor layer 114 is separately disposed on the uppermost one of the dielectric layers 112. Conductor layer 114 can be used as a select gate, so that charge storage layer 108 on the left or right side of stack structure 104 can be selected to be operated by conductor layer 114. The width of each conductor layer 114 is, for example, smaller than the width of each conductor layer 110. The material of the conductor layer 114 is, for example, a conductor material such as doped polysilicon. The method of forming the conductor layer 114 is formed, for example, by using a deposition process, a lithography process, and an etching process in combination.

In addition, each stack structure 104 can further include an isolation structure 116, At least one of the dielectric layer 118 and the hard mask layer 120. The isolation structure 116 is disposed between the conductor layers 114 so that the two conductor layers 114 in the stacked structure 104 can be isolated by the isolation structure 116. The material of the isolation structure 116 is, for example, a dielectric material such as ruthenium oxide. The formation method of the isolation structure 116 is formed, for example, by using a deposition process and a chemical mechanical polishing process in combination.

The material of the dielectric layer 118 is, for example, a dielectric material such as ruthenium oxide. The method of forming the dielectric layer 118 is formed, for example, by using a deposition process, a lithography process, and an etching process in combination. In another embodiment, the dielectric layer 118 may not be formed.

The material of the hard mask layer 120 is, for example, a hard mask material such as tantalum nitride. The hard mask layer 120 can serve as a polish stop layer when the isolation structure 116 is formed. The method of forming the hard mask layer 120 is formed, for example, by using a deposition process, a lithography process, and an etching process in combination.

The channel structures 106 are disposed on the substrate 102 on both sides of the stacked structure 104. Channel structure 106 can be coupled to substrate 102, such as doped region 132 that is coupled to substrate 102. The channel structures 106 can be coupled to each other. In this embodiment, the channel structures 106 are coupled to each other by, for example, forming the channel structure 106 and the connecting portion 122 connecting the channel structures 106 to be coupled by integral molding. In another embodiment, the channel structure 106 can also be coupled by an interconnect structure.

In addition, the non-volatile memory 100 further includes at least two isolation structures 124. The isolation structure 124 is disposed in the channel structure 106. The bottom height of each isolation structure 124 is, for example, lower than or equal to the lower surface height of the lowermost one of the conductor layers 110, and the top height of each isolation structure 124 is, for example, higher than or equal to the conductor layer 114. The height of the upper surface. The isolation structure 124 is, for example, a ruthenium oxide layer or an air gap. In this embodiment, the isolation structure 124 is illustrated by taking an air gap as an example.

For example, each channel structure 106 can include a two-layer main channel portion 126 and two spacer channel portions 128. The main channel portion 126 is disposed on the substrate 102 on both sides of each of the isolation structures 124, and the bottoms of the main channel portions 126 are connectable to each other. The spacer channel portion 128 is disposed between the charge storage layer 108 and the main channel portion 126 between the adjacent two stacked structures 104. The material of the spacer passage portion 128 and the main passage portion 126 is, for example, polysilicon. The method for forming the spacer channel portion 128 is formed by first forming a conformal spacer channel material layer (not shown) on the stacked structure 104, and then performing an etch back process on the spacer channel material layer. The method of forming the main channel portion 126 is formed, for example, by conformally depositing a channel material layer 127 on the stacked structure 104 and the spacer channel portion 128, wherein the main channel portion 126 and the connecting portion 122 are respectively part of the channel material layer 127. That is, the main passage portion 126 and the connecting portion 122 in this embodiment may be integrally formed.

The charge storage layer 108 is disposed between the stacked structure 104 and the channel structure 106. The charge storage layer 108 may be a single layer structure or a multilayer structure. When the charge storage layer 108 is a single layer structure, the charge storage layer 108 is, for example, a charge trap layer such as a tantalum nitride layer. When the charge storage layer 108 is of a multilayer structure, the charge storage layer 108 is, for example, a combined layer of a dielectric layer and a charge trap layer, such as a tantalum oxide/tantalum nitride/yttria composite layer. The method of forming the charge storage layer 108 is formed by first forming a charge storage material layer (not shown) on the stacked structure 104 and then removing the charge storage material layer not covered by the spacer channel portion 128.

In addition, the non-volatile memory 100 more preferably includes at least one of the doped region 130, the at least two doped regions 132, the hard mask layer 134, and the wires 136.

The doped region 130 is disposed in the substrate 102. Doped region 130 can be used as a source line. The doped region 130 is, for example, an N-type doped region or a P-type doped region. In this embodiment, the doping region 130 is exemplified by an N-type doping region. The method of forming the doping region 130 is, for example, an ion implantation method.

The doped region 132 is disposed in the doped region 130 below the channel structure 106. Doped region 132 can be used to reduce the resistance between channel structure 106 and substrate 102. The doping concentration of the doping region 132 is, for example, greater than the doping concentration of the doping region 130. The doping region 132 is, for example, an N-type doped region or a P-type doped region. In this embodiment, the doping region 132 is exemplified by an N-type doping region. The method of forming the doping region 132 is, for example, an ion implantation method.

The material of the hard mask layer 134 is, for example, a hard mask material such as tantalum oxide or tantalum nitride. The hard mask layer 134 can be used to define the pattern of the channel structure 106. The method of forming the hard mask layer 134 is formed, for example, by using a deposition process, a lithography process, and an etching process in combination.

The wire 136 is coupled to the channel structure 106. For example, the wire 136 can be coupled to the channel structure 106 by the contact window 138 and the connection portion 122. Wire 136 can be used as a word line. The material of the wire 136 is, for example, a conductor material such as a metal or doped polysilicon. The method of forming the wire 136 is, for example, a physical vapor deposition method or a chemical vapor deposition method.

Based on the above embodiments, since each of the stacked structures 104 includes a stacked conductor layer 110, a dielectric layer 112, and a separately disposed two-layer conductor layer 114, two strings of NAND memory cells can be formed by a single stacked structure 104. The conductor layer 114 can serve as a select gate to selectively operate the charge storage layer 108 in the NAND memory cell string on the left or right side of the stacked structure 104, and each conductor layer 110 can operate on the charge storage layer 108 on both sides thereof. In turn, a single memory cell 140 of two bits per cell is formed. Therefore, the non-volatile memory 100 can effectively reduce the memory cell area in the three-dimensional memory, thereby improving the integration of the memory elements.

3 is a cross-sectional view showing a non-volatile memory according to another embodiment of the present invention. 4 is a perspective view of a portion of the non-volatile memory of FIG. 3. In FIG. 4, for the sake of clarity, only the charge storage layer on the sidewall of the conductor layer is illustrated, and the isolation structure in the dielectric layer, the hard mask layer, and the stacked structure is omitted.

Referring to FIG. 1 to FIG. 4 simultaneously, the difference between the non-volatile memory 100a of FIGS. 3 and 4 and the non-volatile memory 100 of FIGS. 1 and 2 is as follows. In the non-volatile memory 100a, the bottoms of the main channel portions 126a are not connected to each other, for example, by isolating the adjacent main channel portions 126a by the isolation structures 124a extending to the doping regions 132. In addition, in the non-volatile memory 100a, the channel structures 106 are coupled to each other by, for example, an interconnect structure formed by the contact window 138 and the wires 136, rather than the channels in the non-volatile memory 100. The structure 106 is coupled by the connection portion 122. In addition, members similar to the non-volatile memory 100a and the non-volatile memory 100 are denoted by the same reference numerals and their description will be omitted.

FIG. 5 is a schematic circuit diagram of the non-volatile memory of FIGS. 1 and 3.

Referring to FIG. 1 , FIG. 3 and FIG. 5 simultaneously, the conductor layer 110 is set as the word lines WL1 WL WL6 , and the portion in which the word lines WL1 WL WL6 are located in the stacked structure 104 is set as the control gate CG. The lowermost conductor layer 110 in the stacked structure 104 is set as the selection gate lines SGL1-1 to SGL1-3, and the portion in which the selection gate lines SGL1-1 to SGL1-3 are located in the stacked structure 104 is set as the selection gate. SGS. The doping region 134 is set as the source line CSL. The wire 136 is set to the bit lines BL1 to BL3. The conductor layer 114 is set as the selection gate lines SGL2-1 to SGL2-6, and the portion where the selection gate lines SGL2-1 to SGL2-6 are located above the stacked structure 104 is set as the selection gate SGD.

In this embodiment, the three bit lines BL1 BLBL3 are taken as an example for description, but the invention is not limited thereto. The bit lines BL1 BLBL3 are respectively connected to six strings of NAND memory cells formed by three stacked structures 104, that is, the bit lines BL1 BLBL3 are respectively connected to six strings of NAND memory cells in the same row. Therefore, there are a total of eighteen strings of NAND memory cells in FIG. 5, and eighteen strings of NAND memory cells share the source line CSL.

Select gate lines SGL2-1~SGL2-6 are connected to the select gate SGD in the same column, and one select gate SGD controls a string of NAND memory cells. The word lines WL1 WL WL6 are connected to the control gate CG in the same column, and the two strings of NAND memory cells share one control gate CG. The word lines WL1 WL WL3 are coupled to each other, and the word lines WL4 WL WL6 are coupled to each other. The selection gate lines SGL1-1~SGL1-3 are connected to the selection gate SGS in the same column, and the two strings of NAND memory cells share one selection gate SGS. The gate lines SGL1-1~SGL1-3 are coupled to each other.

In the operation, after selecting the gate line SGL2-1~SGL2-6 to select the memory cell string to be operated, the bit line BL1~BL3, the word line WL1~WL6, and the select gate line SGL1-1 can be matched. ~SGL1-3 and source line CSL operate on selected memory cells.

Figure 6 is a schematic diagram of another circuit of the non-volatile memory of Figures 1 and 3.

The difference between the embodiment of FIG. 6 and the embodiment of FIG. 5 is that in FIG. 6, the odd-numbered word lines in the same layer are coupled, and the even-numbered word lines of the same layer are coupled. As shown in FIG. 6, the word lines WL1, WL3 of the same layer are coupled to each other without being coupled to the word line WL2 of the same layer. The word lines WL4, WL6 of the same layer are coupled to each other without being coupled to the word line WL5 of the same layer. In addition, the wires similar to those in FIG. 5 in FIG. 6 are denoted by the same reference numerals and the description thereof will be omitted.

In summary, the above embodiment has at least the following features. Since there are two select gates that are separately disposed in a single stacked structure, two strings of NAND memory cells can be formed by a single stacked structure. Therefore, the non-volatile memory of the above embodiment can effectively reduce the memory cell area in the three-dimensional memory, thereby improving the integration of the memory elements.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Non-volatile memory

102‧‧‧Base

104‧‧‧Stack structure

106‧‧‧Channel structure

108‧‧‧Charge storage layer

110, 114‧‧‧ conductor layer

112, 118‧‧‧ dielectric layer

116, 124‧‧‧Isolation structure

120, 134‧‧‧ hard mask layer

122‧‧‧Connecting Department

126‧‧‧Main Channel Department

127‧‧‧Channel material layer

128‧‧‧clear channel section

130, 132‧‧‧Doped area

136‧‧‧ wire

138‧‧‧Contact window

140‧‧‧ memory cells

Claims (10)

A non-volatile memory comprising: a substrate; a stacked structure disposed on the substrate, and comprising: a plurality of first conductor layers; a plurality of dielectric layers, wherein the dielectric layers alternate with the first conductor layers And two second conductor layers are disposed on the same one of the uppermost ones of the plurality of dielectric layers; two channel structures are disposed on the substrate on both sides of the stacked structure; and two charge storage layers are disposed on The stack structure is between the channel structures. The non-volatile memory of claim 1, wherein the stacked structure further comprises a first isolation structure disposed between the second conductor layers. The non-volatile memory of claim 1, wherein each of the second conductor layers has a width smaller than a width of each of the first conductor layers. The non-volatile memory of claim 1, wherein the channel structures are coupled to each other, and the manner in which the channel structures are coupled to each other comprises forming the channel structures and connecting them by integral molding. The connection portions of the channel structures are coupled or coupled by an interconnect structure. The non-volatile memory of claim 1, further comprising two second isolation structures disposed in the channel structures. Non-volatile memory as described in claim 5, wherein each The bottom height of the isolation structure is lower than or equal to the lower surface height of the lowermost one of the first conductor layers, and the top height of each of the isolation structures is higher than or equal to the upper surface height of the second conductor layers. The non-volatile memory of claim 5, wherein when the non-volatile memory comprises a plurality of stacked structures, each of the channel structures comprises: two main channel portions disposed in each of the second isolation structures On the side of the substrate, and the bottoms of the main channel portions are connected to each other or not connected to each other; and the two gap wall channel portions are disposed between the adjacent two stacked structures and the main channel portions between. The non-volatile memory of claim 1, further comprising a first doped region disposed in the substrate. The non-volatile memory according to claim 8 further includes two second doped regions disposed in the first doped region below the channel structures. The non-volatile memory of claim 1, further comprising a wire coupled to the channel structures.