TWI538168B - Three-dimensional semiconductor device and method of manufacturing the same - Google Patents

Description

Three-dimensional semiconductor component and method of manufacturing same

The present invention relates to a three-dimensional (3D) semiconductor device and a method of fabricating the same, and more particularly to a three-dimensional semiconductor device having bottom contacts and a method of fabricating the same.

A very important feature of non-volatile memory components is the ability to preserve the integrity of the data state when the memory component loses or removes power. Many different types of non-volatile memory components have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory cells with memory cells to achieve a memory structure with higher storage capacity. For example, some NAND type flash memory structures have been proposed for multilayer thin film transistor stacks. Related companies have proposed three-dimensional memory components of various structures, such as memory cells with single-gate, double-gate memory cells, and memory cells of a surrounding gate. And other three-dimensional memory components.

It is hoped by the relevant designers that a three-dimensional memory structure can be constructed, which not only has many layer stacking planes (memory layers) but also achieves higher storage capacity and superior electronic characteristics (for example, good data storage reliability and operation). The speed of the memory structure allows the memory structure to be stable and fast, such as erasing and programming. In general, the page size of a NAND type flash memory is proportional to the number of bit lines. Therefore, when the component size is reduced, not only the cost is reduced, but the parallel operation increases the read/write speed of the component, thereby achieving a higher data transmission speed. However, there are still many other issues to consider when reducing the size of components.

Taking a general three-dimensional vertical channel type memory element (ex: NAND) as an example, a multi-layered connector (X-pitch) in one direction such as an X-direction can utilize a wide staircase rule. It is relaxed, but the Y-pitch in the other direction, for example, in the Y direction, becomes very dense in order to join the multilayer structure connector to the word line decoder. Although expanding the Y-direction region (block_Y) can relax the Y-direction spacing, the number of string selection lines (SSL) will increase, causing more such as power consumption and signal disturbance. The problem. Considering the severe interference in three-dimensional NAND devices, a less SSL number design would be a better choice for constructing a three-dimensional component, however such a design may result in a high pattern density of the fan-out region of the layer (eg, word line WL). .

The present invention relates to a three-dimensional semiconductor device and a method of fabricating the same. According to the three-dimensional semiconductor component of the embodiment, a step contact is proposed to be connected to the bottom under the multilayer structure, for example, to directly extend the step contact to the bottom, or to form the top conductor to connect the step contact and the bottom contact.

According to an embodiment, a three-dimensional semiconductor element is provided, comprising: a substrate having a staircase region including N steps, wherein N is an integer greater than or equal to 1; and having a multi-layer structure (multi- Layers) Stacked on one of the stacks of the substrate, and the multilayer structure includes an active layer and an insulating layer interleaved on the substrate, and the stack includes a plurality of sub-stacks formed on the substrate, the sub-stacks being disposed corresponding to the N steps of the stepped regions to respectively form contacts And a plurality of connectors respectively located in the corresponding contact regions, and the connectors are extended downwardly to one of the bottom layers below the multilayer structure.

According to an embodiment, a method of fabricating a three-dimensional semiconductor device is provided, comprising: providing a substrate having a stepped region including N steps, wherein N is an integer greater than or equal to 1; forming one of the multilayer structures stacked on the substrate And the multi-layer structure comprises an active layer interlaced with the insulating layer, the stack comprising a plurality of sub-stacks formed on the substrate, the sub-stacks being correspondingly arranged with the N steps of the stepped regions to respectively form contact regions; and forming a plurality of connectors respectively Located in the corresponding contact area, and the connectors are extended downwardly to one of the bottom layers below the multilayer structure.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

10‧‧‧Substrate

101‧‧‧ bottom layer

11‧‧‧ memory layer

12, 13‧‧‧ selection line

15‧‧‧Listing

17‧‧‧ Serial contact

18‧‧‧Wire

21, 22, Ld‧‧‧ dielectric layer

211‧‧‧Insulation

213‧‧‧ active layer

231, 232, 233, 234‧‧‧ multilayer structure connectors

241, 242, 243, 244‧‧‧ bottom connectors

251, 252, 253, 254‧‧‧ top conductor

31, 32, 33, 34‧‧‧ connectors

314, 324, 334, 344‧‧‧ first conductive parts

315, 325, 335, 345‧‧‧ second conductive parts

314h, 324h, 334h, 344h‧‧‧ bottom contact hole

Rs‧‧‧ ladder area

Rc1, Rc2, Rc3, Rc4‧‧‧ contact areas

Tc‧‧‧ trench area

TL1, TL2, TL3, TL4‧‧‧ three-layer structure mask

PR-1, PR-2, PR-3, PR-4‧‧‧ patterned photoresist

Lc‧‧‧ conductor

D‧‧‧ spacing

S‧‧‧ thickness

Figure 1 is a perspective view of a three-dimensional semiconductor component.

Fig. 2A is a top plan view showing a part of the structure of the three-dimensional semiconductor element of the first embodiment.

Figure 2B is a three-dimensional semiconductor depicted along section line 2B-2B of Figure 2A. A schematic cross-sectional view of the component.

2C is a schematic cross-sectional view of the three-dimensional semiconductor device taken along section line 2C-2C of FIG. 2A.

2D is a schematic cross-sectional view of the three-dimensional semiconductor device taken along the section line 2D-2D of FIG. 2A.

3A to 14D illustrate a method of manufacturing the three-dimensional semiconductor element with bottom contact of the first embodiment.

Figure 15 is a cross-sectional view showing a three-dimensional semiconductor device according to a second embodiment of the present invention.

16 to 25 illustrate a method of manufacturing the three-dimensional semiconductor element with bottom contact of the second embodiment.

Embodiments of the present disclosure propose a three-dimensional semiconductor component, particularly a three-dimensional semiconductor component having bottom contacts. According to the embodiment, the bottom contact is constructed in the three-dimensional semiconductor component, so that the applicability of the component in the application range can be further improved. For example, the block selectors can be designed under the staircase contact region, and the three-dimensional semiconductor component with the bottom contact of the embodiment of the present invention is applied to make the multilayer structure of the selector and the contact region at the bottom of the step region. Connections have achieved the problem of saving area and avoiding excessive fan-out density. Furthermore, there are other situations in which the bottom contact of the embodiment can be applied, such as the application of a three-dimensional semiconductor component of a peripheral region under a peripheral-under-array, and/or the application of a step contact requiring an internal array. The bottom contact structure of the embodiment is for a three-dimensional semiconductor element that pursues high electronic properties and characteristics. Pieces can provide more structural possibilities.

The disclosure can be applied to a plurality of three-dimensional semiconductor components having different memory cell array types, such as vertical-channel (VC) three-dimensional semiconductor components and vertical-gate (VG) three-dimensional semiconductor components. There is no particular limitation on the application form of the embodiment. Figure 1 is a perspective view of a three-dimensional semiconductor component. In the first drawing, a vertical channel type three-dimensional semiconductor device is illustrated as an example. A three-dimensional semiconductor component includes a stack having multi-layers stacked on a substrate 10, and a staircase region Rs including N steps, wherein N is greater than or An integer equal to 1. And the multilayer structure includes a plurality of memory layers 11 (ie, the active layer, for example, a control gate is included in the VC element) and the insulating layer is interleaved on the substrate 10. The three-dimensional semiconductor component further includes a plurality of selection lines 12 located above the memory layer 11 in parallel with each other, and a plurality of strings 15 perpendicular to the memory layer 11 and the selection line 12, wherein the series 15 are electrically connected Connect to the corresponding selection line 12. Moreover, the three-dimensional semiconductor component further includes a plurality of wires 18 (eg, bit lines BLs) located above the select lines 12, and the wires 18 are parallel to each other and perpendicular to the select lines 12. A plurality of cells are defined by the series 15, the selection lines 12 and the wires 18, and the memory cells are arranged in a plurality of rows and columns to form a memory. Array. Furthermore, a plurality of string contacts 17 are perpendicular to the memory layer 11 and the selection line 12, and the arrangement of each string of contacts 17 corresponds to each column 15 of the memory cells, wherein the series contacts 17 are electrically The connection is made to the corresponding selection line 12 and the corresponding wire 18. The three-dimensional semiconductor component further includes other components. For example, the select line 12 refers to an upper select line (upper SG), and below the memory layer 11, there is a lower select line (lower select). Lines, lower SG) 13 formation.

In an embodiment, the stack includes a plurality of sub-stacks formed on the substrate 10, and the sub-stacks are disposed corresponding to the N steps of the step region Rs to form contact regions (Rc), respectively. The three-dimensional semiconductor component of the embodiment further includes a plurality of connectors respectively located at corresponding contact regions (Rc), and the connectors are extended downwardly to a bottom layer below the multilayer structure. The following is an example of a three-dimensional semiconductor element in contact with the bottom of two aspects, but the disclosure is not limited thereto.

The following embodiments describe the related structures and processes of the present disclosure with reference to the accompanying drawings, but the disclosure is not limited thereto. The same or similar elements in the embodiments are denoted by the same or similar reference numerals. It should be noted that the disclosure does not show all possible embodiments. Other implementations not presented in this disclosure may also be applicable. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

<First Embodiment>

Please refer to Figure 1 and Figure 2A~2D. Fig. 2A is a top plan view showing a part of the structure of the three-dimensional semiconductor element of the first embodiment. Figure 2B is a schematic cross-sectional view of the three-dimensional semiconductor device taken along section line 2B-2B of Figure 2A. 2C is a schematic cross-sectional view of the three-dimensional semiconductor device taken along section line 2C-2C of FIG. 2A. 2D is a schematic cross-sectional view of the three-dimensional semiconductor device taken along the section line 2D-2D of FIG. 2A. Furthermore, FIG. 2A presents an xy plane of the three-dimensional semiconductor component, FIGS. 2B and 2C represent the xz plane of the three-dimensional semiconductor component, and FIG. 2D presents a yz of the three-dimensional semiconductor component. flat.

In an embodiment, a plurality of sub-stacks included in the stack are formed on the substrate 10, and the sub-stacks are disposed corresponding to the N steps of the step region Rs to form contact regions, respectively. For example, the contact regions Rc1, Rc2, Rc3, and Rc4 shown in FIGS. 2A and 2B. In the first embodiment, the three-dimensional semiconductor component further includes a plurality of connectors, for example, multilayered connectors 231, 232, 233, and 234 are respectively located in the corresponding contact regions Rc1, Rc2, Rc3, and Rc4. According to the first embodiment, the connectors are formed by bottom connectors such as 241, 242, 243 and 244 respectively formed in corresponding contact areas, and the bottom connectors are extended downwardly to the multi-layer structure (ie interlaced setting) The active layer 213 and one of the underlying layers 101 below the insulating layer 211) are as shown in FIG. 2B.

As shown in FIG. 2C, multilayered connectors such as 231, 232, 233, and 234 are formed in the corresponding contact regions Rc1, Rc2, Rc3, and Rc4, respectively, and are connected to the active layers 213 of the respective stacks. Landing area. For example, the multilayer structure connector 231 connects the landing area of the active layer 213 of the fourth step (stepped area) in the contact region Rc1. Similarly, the multilayer structure connector 232 connects the landing area of the active layer 213 of the third step (stepped area) in the contact region Rc2, and the multilayer structure connector 233 connects the active layer 213 of the second step (stepped area) of the contact area Rc3. The landing area, and the multilayer structure connector 234 joins the landing area of the active layer 213 of the first step (stepped area) in the contact area Rc4.

Please refer to Figures 2A and 2D. In the first embodiment, each of the multilayer structure connectors such as 231, 232, 233, and 234 is a top conductor (top The conductors such as 251, 252, 253 and 254 are electrically connected to corresponding bottom connectors such as 241, 242, 243 and 244. As shown in FIG. 2A, the adjacently disposed multilayer structure connector 231 and bottom connector 241 are electrically connected by a top conductor 251. Similarly, the adjacently disposed multi-layer structure connector 232 and the bottom connector 242 are electrically connected by a top conductor 252, and the adjacently disposed multi-layer structure connector 233 and the bottom connector 243 are electrically connected by a top conductor 253. The adjacently disposed multilayer structure connector 234 and bottom connector 244 are electrically connected by a top conductor 254. The top conductors 251, 252, 253, and 254 are spaced apart from one another.

In the first embodiment, the multilayer structure connectors (e.g., 231, 232, 233, and 234) and the bottom connectors (e.g., 241, 242, 243, and 244) extend parallel to each other, while the top conductors (e.g., 251, 252, 253) And 254) one of the extending directions, for example along the y-direction, is substantially perpendicular to one of the bottom connectors (eg, 241, 242, 243, and 244) extending direction, such as along the z-direction, as in Figures 2B through 2D. Show.

Furthermore, adjacently disposed multilayer structure connectors and bottom connectors are spaced apart by insulators such as dielectric layers 21 and 22, as shown in Figure 2D. The dielectric layers 21 and 22 may be of the same or different materials, and the disclosure is not limited thereto. In one embodiment, adjacently disposed multilayer structure connectors and bottom connectors (such as multilayer structure connector 231 and bottom connector 241 shown in FIG. 2D) have a pitch D of less than 5 μm. However, in the practical application of the three-dimensional semiconductor component, the pitch D may be other values, and is not limited to the values exemplified herein.

Furthermore, the dielectric layer 22 surrounds the bottom connectors (e.g., 241, 242, 243, and 244) and covers the multilayer structure. In one embodiment, a portion of the dielectric layer 22 surrounding the bottom connector (such as the bottom connector 241 shown in FIG. 2D) has a thickness S of less than or equal to 1 μm. However, in practical applications of three-dimensional semiconductor components, thickness S Other values are also possible, and are not limited to the numerical values exemplified herein.

Furthermore, as shown in FIG. 2D, top conductors (eg, 251, 252, 253, and 254) are formed on dielectric layers 21 and 22 and connect the multilayer structure connectors (eg, 231, 232, 233, and 234) and the bottom connection. The top surface of the devices (e.g., 241, 242, 243, and 244). In other words, according to the first embodiment, the top conductors (e.g., 251, 252, 253, and 254) for connecting the multilayer structure connector and the bottom connector are connected to the active layer 213 of the multilayer structure by the dielectric layers 21 and 22. Separated and insulated.

According to the three-dimensional semiconductor component of the embodiment, the constructed bottom connectors (e.g., 241, 242, 243, and 244) can be electrically connected to corresponding lines under the multilayer structure. Examples of corresponding wirings include area selectors such as TFTs, and elements that can be electrically connected to three-dimensional semiconductor elements under the array area in the peripheral area, and elements that can be electrically connected to three-dimensional semiconductor elements that require step contact of the internal array. and many more. Thus, the bottom contact of the embodiment, which is coupled to the multilayer structure connector (the landing region that is bonded to the active layers of each stack), provides more possible variations for three-dimensional semiconductor component systems that pursue high electronic performance and characteristics. development of.

The following is a method for manufacturing a three-dimensional semiconductor element having a bottom contact of the first embodiment which can be applied. 3A to 14D illustrate a method of manufacturing the three-dimensional semiconductor element with bottom contact of the first embodiment. Please refer to FIG. 1 for the relevant elements of the three-dimensional semiconductor element of the embodiment.

First, a substrate 10 having a stack including a plurality of layers of multi-layers including an interleaved active layer 213 and an insulating layer 211 on a substrate 10, the stack including a plurality of sub-stacks formed on the substrate 10, and the sub-stack corresponds to N steps of the step region Rs of the substrate 10 to form contact regions (for example, Rc1, Rc2, Rc3, Rc4), wherein N is greater than or equal to 1 The integer. As shown in FIGS. 3A and 3B, a dielectric layer 21 is formed on the stepped region Rs, and a trench area Tc is defined along the steps. Referring to FIG. 3A, a top view (xy plane) of a partial structure of the three-dimensional semiconductor device of the embodiment is shown, and the dielectric layer 21 and the active layer 213 at N steps of the contact regions Rc1 - Rc4 are shown. Fig. 3B is a schematic cross-sectional view (xz plane) of the three-dimensional semiconductor element taken along the section line 3B-3B of Fig. 3A. Fig. 3C is a schematic cross-sectional view (xz plane) of the three-dimensional semiconductor element taken along section line 3C-3C of Fig. 3A.

Thereafter, the multilayer structure in the trench region Tc is removed, for example, using a tri-layer process (a three-layer structure mask including ODL/SHB/PR). In the embodiment, after etching a pair of film layers (ie, one active layer 213 and one insulating layer 211 of one of the N steps), a trim-etch process of masking is performed by etching. Please refer to Figures 4A-4B through 11A-11B. 4A to 11B are schematic diagrams showing an etching-micromodulation process of the multilayer structure of the removed trench region Tc of the three-dimensional semiconductor device of the embodiment. Here, the illustration labeled B, for example, the 4B, 5B, 6B, 7B, ... 11B diagram shows the section line BB along the diagram labeled A (for example, 4B-4B, 5B-5B, ... 11B, respectively). Section -11B). Moreover, since the height of the dielectric layer 21 is generally much larger than the width of the trench region Tc, it is assumed in the process of this example that the etching-fine tuning of the dielectric layer 21 along the y-direction can be ignored.

As shown in FIGS. 4A and 4B, a mask TL1 of three-layer structure (for example, ODL/SHB/PR) is formed, and corresponds to the trench region Tc of the contact region Rc1. As shown in FIGS. 5A and 5B, the first layer pair of the contact region Rc1 (ie, an active layer 213 and an insulating layer 211 of the first of the N steps, N=4) is performed with the mask TL1. Etching, after etching, the trench region Tc located in the contact region Rc1 is violent An active layer 213 of the second layer pair (ie, an active layer 213 of the second of the N steps and an insulating layer 211, N=4) is exposed. Thereafter, the mask TL1 of the three-layer structure is fine-tuned to form a mask TL2 of the three-layer structure, and the active layer 213 of the second step in the trench region Tc of the contact regions Rc1 and Rc2 is exposed, as shown in FIG. 6A and Figure 6B shows.

Next, as shown in FIGS. 7A and 7B, the second layer pair of the contact regions Rc1 and Rc2 is performed with the mask TL2 (ie, an active layer 213 and an insulating layer 211, N of the second of the N steps). =4) etching, the trench region Tc located in the contact regions Rc1 and Rc2 after etching exposes the third layer pair (ie, an active layer 213 and an insulating layer 211 of the third step of the N steps, N=4 Active layer 213). Thereafter, the mask TL2 of the three-layer structure is fine-tuned to form a mask TL3 of a three-layer structure, and the active layer 213 of the third step in the trench region Tc of the contact regions Rc1, Rc2, and Rc3 is exposed, as shown in FIG. 8A. And Figure 8B shows.

Next, as shown in FIGS. 9A and 9B, the third layer pair of the contact regions Rc1, Rc2, and Rc3 is performed with the mask TL3 (ie, an active layer 213 and an insulating layer 211 of the third step of the N steps). , N=4) etching, the trench region Tc located in the contact regions Rc1, Rc2, and Rc3 after etching exposes a fourth layer pair (ie, an active layer 213 and an insulating layer 211 of the fourth step of the N steps) , N = 4) active layer 213. Thereafter, the mask TL3 of the three-layer structure is fine-tuned to form a three-layer structure mask TL4 exposing the active layer 213 of the fourth step in the trench region Tc of the contact regions Rc1, Rc2, Rc3 and Rc4, as described 10A and 10B are shown. Next, as shown in FIGS. 11A and 11B, the fourth layer of the contact regions Rc1, Rc2, Rc3, and Rc4 is etched by the mask TL4 so that the alternating active layer 213 and the insulating layer are included in the trench region Tc. The multilayer structure of layer 211 is completely removed.

After all the etch-micromodulation processes are completed, an insulator is deposited and fills the trench region Tc, and then planarized by a planarization process such as chemical mechanical polishing (CMP) to planarize the upper surface of the insulator to form a 12A. The figure is shown to the dielectric layer 22 shown in Fig. 12D. Fig. 12A is a top view (xy plane) of a partial structure of the three-dimensional semiconductor element of the embodiment, showing the dielectric layer 22 in the contact regions Rc1 - Rc4. Fig. 12B is a schematic cross-sectional view (xz plane) of the three-dimensional semiconductor element taken along the section line 12B-12B of Fig. 12A. Fig. 12C is a schematic cross-sectional view (xz plane) of the three-dimensional semiconductor element taken along the section line 12C-12C of Fig. 12A. Fig. 12D is a schematic cross-sectional view (yz plane) of the three-dimensional semiconductor element taken along the section line 12D-12D of Fig. 12A.

After forming the dielectric layer 22, a contact hole process is performed to simultaneously form a multilayer structure connector (eg, 231, 232, 233, and 234) and a bottom connector (eg, 241, 242, 243, and 244), as shown in FIG. 13A. Figure 13D is shown. According to FIGS. 13B and 13D, the bottom connectors (eg, 241, 242, 243, and 244) formed in the respective contact regions (eg, Rc1, Rc2, Rc3, Rc4) are extended downwardly to the multilayer structure (ie staggered arrangement) The active layer 213 and the underlying layer 101 below the insulating layer 211). The multilayer structure connectors (e.g., 231, 232, 233, and 234) formed in the respective contact regions (e.g., Rc1, Rc2, Rc3, Rc4) connect the landing regions of the active layers 213 of the respective stacks as shown in Fig. 13C. Furthermore, adjacent multilayer connectors (such as 231/232/233/234) and bottom connectors (such as 241/242/243/244) are separated by dielectric layers 21 and 22, such as 13D. The figure shows. Dielectric layers 21 and 22 can be made of the same or different materials.

After the contact hole process is completed, a conductive material (such as metal) is deposited and a patterning step is performed to form top conductors (eg, 251, 252, 253, and 254). Thus the top connection of the adjacent multilayer structure connector (e.g., 231/232/233/234) and the bottom connector (e.g., 241/242/243/244) is completed as shown in Figures 14A through 14D. In the first embodiment, each of the multilayer structure connectors such as 231, 232, 233, and 234 are electrically connected to the bottom connectors such as 241, 242, 243, and 244 by top conductors 251, 252, 253, and 254, respectively. Figure 14D is shown. The structural details of the related elements are as described above, and the detailed description thereof will not be repeated here.

<Second embodiment>

Figure 15 is a cross-sectional view showing a three-dimensional semiconductor device according to a second embodiment of the present invention. According to an embodiment, the connectors respectively forming the contact regions are connected downwardly to one of the bottom layers 101 below the multilayer structure, wherein each connector is electrically connected to the multilayer structure connector connecting the landing regions of the active layers of each of the stacks. In the second embodiment, a stepwise contact is made to the bottom as an example, wherein the connector formed (connected to one of the bottom layers 101 below the multilayer structure) and the multilayer structure connector are an integral piece.

As shown in Fig. 15, the connectors, such as 31, 32, 33 or 34, each include a first conductive portion such as 314, 324, 334 or 344 extending downwardly to the bottom layer 101 below the multilayer structure, and a second A conductive portion such as 315, 325, 335 or 345 connects the first conductive portion. The second conductive portions, such as 315, 325, 335, and 345, are electrically connected to the landing regions of the corresponding sub-stacked active layers 213 (located in the first, second, third, and fourth steps, respectively). In Fig. 15, the first conductive portions such as 314, 324, 334 and 344 and the second conductive portions such as 315, 325, 335 and 345 respectively form four integral pieces.

According to a second embodiment, the second conductive portion of the connector (e.g., 31/32/33/34) (e.g., 315/325/335/345) is in direct contact with the active layer 213 of the corresponding sub-stack. Landing area. Furthermore, the first conductive portion (such as 314/324/334/344) is separated from the active layers 213 of the multilayer structure by a dielectric layer Ld, as shown in FIG.

In one embodiment, one of the first conductive portions (eg, 314/324/334/344) extends in a direction (ie, along the z-direction) substantially perpendicular to the second conductive portion (eg, 315/325/335/345) An extension direction (ie along the x-direction). In one embodiment, the first conductive portion (e.g., 314/324/334/344) passes through the multilayer structure and connects one of the conductors below the multilayer structure (e.g., the line on the bottom layer 101).

The following is a method for manufacturing a three-dimensional semiconductor element having a bottom contact of the second embodiment which can be applied. 16 to 25 illustrate a method of manufacturing the three-dimensional semiconductor element with bottom contact of the second embodiment. Please refer to FIG. 1 for the relevant elements of the three-dimensional semiconductor element of the embodiment. Further, the substrate 10 is provided with a stack including a multilayer structure thereon, and the stack includes a plurality of sub-stacks formed on the substrate 10, which correspond to N steps of the step region Rs of the substrate 10 to respectively form contacts The contents of related elements such as regions (e.g., Rc1 to Rc4) have been described in detail in the first embodiment, and the details thereof will not be repeated here. Please also consider Figures 3A and 3B. Figs. 16 to 25 are, for example, related to the angle of the section along the section line 3B-3B of Fig. 3A. The manufacturing steps illustrated in Figs. 16 to 25 are performed along the groove region Tc defined by the steps as shown in Figs. 3A and 3B.

Please refer to FIG. 16 and FIG. 17, which illustrate a first patterning process of the manufacturing method according to the second embodiment. As shown in Fig. 16, a patterned photoresist PR-1 (or a patterned hard mask) is formed which has two holes corresponding to the active layer 213 of the second step and the fourth step. Thereafter, etching a pair of film layers (ie, one active layer 213 and one insulating layer 211 of one of the N steps), such as As shown in Fig. 17, the step of performing a photoresist removal (PR-strip) is followed. As shown in Fig. 17, at the trench region Tc, the second layer pair in the contact region Rc2 (i.e., an active layer 213 and an insulating layer 211 of the second step of the N steps, N = 4) and the contact are located. The fourth layer pair of the region Rc4 (i.e., an active layer 213 and an insulating layer 211 of the fourth step of the N steps, N = 4) are simultaneously etched according to the patterned photoresist PR-1. In Fig. 17, a fourth bottom contact hole 344h is formed.

Referring to FIGS. 18 and 19, a second patterning process of the manufacturing method according to the second embodiment is illustrated. As shown in Fig. 18, a patterned photoresist PR-2 (or patterned hard mask) is formed which has two holes corresponding to the active layer 213 of the second step. Thereafter, two pairs of film layers (i.e., two active layers 213 and two insulating layers 211 of two steps of N steps) are etched, as shown in Fig. 19, and then subjected to a photoresist removal (PR-strip) step. As shown in Fig. 19, at the trench region Tc, the three layer pairs located in the contact region Rc2 and the two layer pairs located in the contact region Rc3 are removed. In Fig. 19, a second bottom contact hole 324h and a third bottom contact hole 334h are formed.

Referring to FIGS. 20 and 21, a third patterning process of the manufacturing method according to the second embodiment is illustrated. As shown in Fig. 20, a patterned photoresist PR-3 (or patterned hard mask) having a hole corresponding to the active layer 213 of the first step is formed. Then, four pairs of film layers are etched, as shown in Fig. 21, and then the photoresist removal step is performed. As shown in Fig. 21, at the trench region Tc, the four layer pairs located in the contact region Rc1 are removed. In Fig. 21, a first bottom contact hole 314h is formed. At this point, four bottom contact holes (ie, 314h, 324h, 334h, and 344h) have been formed.

After the four bottom contact holes form and remove the photoresist, the system deposits a The electrical material (deposited, for example, in the form of a lining forming a bottom contact hole) is etched to form a dielectric layer Ld as shown in FIG. In Fig. 22, the top conductive layer (i.e., the top active layer 231) is exposed to facilitate electrical connection in subsequent processes.

Thereafter, a conductor Lc such as lightened titanium/tungsten (TiN/W) or doped germanium is deposited, and the first to fourth bottom contact holes 314h-334h are filled as shown in FIG. Then, as shown in FIG. 24, a patterned photoresist PR-4 (or patterned hard mask) is formed; then an isotropic etch is performed to remove the unpatterned photoresist PR- 4 cover the conductor connection part. After the patterned photoresist PR-4 is removed, the structure of the second embodiment is formed as shown in Fig. 25 (the structure of Fig. 15). In Fig. 25 (/fifteenth), each connector (31/32/33/34) includes a first conductive portion (314/324/334/344) extending downwardly to the bottom layer 101 below the multilayer structure. And a second conductive portion (315/325/335/345) is connected to the first conductive portion and contacts the landing region of the corresponding sub-stacked active layer 213.

According to the disclosure of the above embodiments, a three-dimensional semiconductor component having a bottom contact is provided, and an adjacent multilayer structure connector and a bottom connector are disposed, and each of the two is electrically connected by a top conductor (first Embodiment), or a connector (second embodiment) having a step contact portion and a bottom contact portion to form an embodiment. The bottom contact of the embodiment can be widely applied to a plurality of three-dimensional semiconductor components having different types, such as vertical-channel (VC) and vertical-gate (VG) three-dimensional semiconductor components, and multilayer structures. The film layer may be a metal (metal gate), a semiconductor (polysilicon gate or bit line). The present disclosure is not particularly limited to the application form of the three-dimensional semiconductor element of the embodiment. The structure of the memory cell array and the stepped region of the above components is for illustrative purposes only, and the disclosure is not limited to the above structure. Therefore, those skilled in the relevant art will recognize that the above embodiment The proposed construction and design can be appropriately modified and adjusted according to the actual needs of the application. According to the three-dimensional semiconductor element proposed in the above embodiment, the bottom contact structure of the embodiment having a wider range of structures can be applied, and a wide range of variations and developments can be provided for the three-dimensional semiconductor element which pursues high electronic performance and characteristics. Three-dimensional semiconductor components of size, ease of fabrication, or more stable electronic properties provide no more structural possibilities. Furthermore, the three-dimensional semiconductor device of the embodiment is a non-time consuming and non-expensive process, and is still suitable for mass production in production.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

101‧‧‧ bottom layer

21, 22‧‧‧ dielectric layer

211‧‧‧Insulation

213‧‧‧ active layer

241, 242, 243, 244‧‧‧ bottom connectors

251, 252, 253, 254‧‧‧ top conductor

Rs‧‧‧ ladder area

Rc1, Rc2, Rc3, Rc4‧‧‧ contact areas

Claims (4)

A three-dimensional semiconductor component comprising: a substrate having a staircase region comprising N steps, wherein N is an integer greater than or equal to 1; a stack having a multi-layers stack Placed on the substrate, and the multilayer structure includes an active layer and an insulating layer interleaved on the substrate, the stack including a plurality of sub-stacks formed on the substrate, the sub-stacks and the N of the stepped regions Steps are correspondingly arranged to form contact regions respectively; and a plurality of connectors are respectively located in the corresponding contact regions, and the connectors are extended downwardly to one of the bottom layers below the multilayer structure a bottom layer, each of the connectors includes: a first conductive portion extending downwardly to the bottom layer below the multilayer structure; and a second conductive portion connecting the first conductive portion, the second conductive portion electrically a landing area corresponding to the active layer of the stack, wherein one of the first conductive portions extends substantially perpendicular to a direction in which the second conductive portion extends, the second conductive portion Formed above the first conductive portion, and the second conductive portion directly contacts the landing region of the active layer corresponding to the second stack. The three-dimensional semiconductor component of claim 1, wherein at least one of the connectors is electrically connected to one of the lines below the multilayer structure. A method of fabricating a three-dimensional semiconductor device, comprising: providing a substrate having a stepped region including N steps, wherein N is an integer greater than or equal to 1; Forming one of having multi-layers stacked on the substrate, and the multilayer structure includes an active layer interleaved with the insulating layer, the stack including a plurality of sub-stacks formed on the substrate, the sub-stacks and the stepped regions The N steps are correspondingly disposed to form contact regions respectively; and a plurality of connectors are formed respectively corresponding to the contact regions, and the connectors are extended downwardly to the underlying structure a bottom layer, each of the connectors includes: a first conductive portion extending downwardly to the bottom layer below the multilayer structure; and a second conductive portion connecting the first conductive portion, the second The conductive portion is electrically connected to a landing area of the active layer of the corresponding stack, wherein one of the first conductive portions extends substantially perpendicular to a direction in which the second conductive portion extends, and the second conductive portion is formed. Above the first conductive portion, the second conductive portion directly contacts the landing region of the active layer corresponding to the sub-stack. The manufacturing method of claim 3, further comprising electrically connecting at least one of the connectors to one of the conductors below the multilayer structure.