TWI681548B - Three dimensional memory device and method for fabricating the same - Google Patents

Abstract

A three-dimensional memory device includes a substrate, conductive layers and insulating layers, a storage layer, a first channel, a second channel and a first conductive plug. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The storage layer penetrates through the multi-layer stacked structure, and has a first string portion and a second string portion that are spaced from each other. The first channel is located on a lateral side of the first string portion. The second channel is located on a lateral side of the second string portion. The first channel and the second channel have an upper channel portion and a lower channel portion. The first conductive plug is interconnected between the upper channel portion and the lower channel portion.

Description

Three-dimensional memory element and manufacturing method thereof

This disclosure relates to a memory element and a method of manufacturing the same, and particularly to a three-dimensional memory element with a high memory density and a method of manufacturing the same.

Memory components are important data storage components in portable electronic devices, such as MP3 players, digital cameras, notebook computers, smart phones, etc... With the increase of various application programs and the improvement of functions, the demand for memory components also tends to be smaller in size and larger in memory capacity. In response to this demand, current designers have turned to a three-dimensional memory device including multiple stacked memory cell layers, such as a vertical channel three-dimensional NAND flash memory device.

However, as the key dimensions of components shrink to the limit of the general memory cell technology field, how to obtain higher memory storage capacity under the limitation of the process capability of existing equipment has become an important issue facing this technical field. Therefore, there is a need to provide an advanced three-dimensional memory device and its manufacturing method to solve the problems faced by the conventional technology.

An embodiment of the present specification discloses a three-dimensional memory device, which includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a storage layer, an insulating partition wall, a first channel portion, a second channel portion and A first conductive plug. The conductive layers and the insulating layers are alternately stacked on the substrate to form a multilayer stack structure. The storage layer passes through the multilayer stack structure and has a first tandem portion and a second tandem portion separated from each other. The first channel portion is located on one side of the first tandem portion, and the first tandem portion is located between the multilayer stack structure and the first channel portion. The second channel portion is located on one side of the second tandem portion, and the second tandem portion is located between the multilayer stack structure and the second channel portion. The first channel portion and the second channel portion each include an upper channel portion and a lower channel portion. The first conductive plug is connected between the upper channel portion and the lower channel portion.

In other embodiments of the present specification, the three-dimensional memory device further includes an etch stop layer located in the multi-layer stacked structure and located on the side of the first conductive plug.

In other embodiments of the present specification, the three-dimensional memory device further includes a bottom channel, and the first channel portion and the lower channel portion of the two channels are U-shaped channels separated from each other, and are connected to both ends of the bottom channel.

In other embodiments of the present specification, the three-dimensional memory element further includes a dielectric partition wall located between the first and second serial portions of the storage layer. The dielectric partition wall includes an upper portion and a lower portion, and a cross section at the top of the lower portion Section wider than the bottom end of the upper part.

In other embodiments of the present specification, the upper channel portion includes an outer channel layer and an inner channel layer. The outer channel layer is located between the storage layer and the inner channel layer and is separated from the first conductive plug.

In other embodiments of the present specification, the three-dimensional memory device further includes a second conductive plug, which is located above the multilayer stack structure and connected to the upper channel portion.

In other embodiments of the present specification, the 3D memory device further includes an etch stop layer, which is located above the multilayer stack structure and on the side of the second conductive plug.

In other embodiments of the present specification, the materials of the first conductive plug and the second conductive plug are both doped polysilicon.

Another embodiment of the present specification discloses a method for manufacturing a three-dimensional memory device, which includes the following steps: alternately depositing a plurality of first conductive layers and a first insulating layer on a substrate; etching a first through hole through the first A conductive layer and the first insulating layers; depositing a first storage layer in the first through hole; depositing a lower channel part on the first storage layer; depositing a first conductive plug to contact the lower channel part; Alternately depositing a plurality of second channel layers and a second insulating layer on the first conductive plug; etching a second through hole through the second channel layers and the second insulating layers to expose the first conductive plug; Depositing a second storage layer in the second through hole; depositing a second channel layer on the second storage layer; etching the second storage layer and the second channel layer to expose the first conductive plug, and The second channel layer remaining after etching is located on the side wall of the second storage layer; a third channel layer is deposited on the second channel layer remaining after etching to form a second channel portion, which contacts the first conductive plug Plug; and Shen Ji a second conductive plug contacts the top of the second channel portion.

In other embodiments of the present specification, the method of manufacturing the three-dimensional memory device further includes etching a first trench to cut the first conductive plug, the second conductive layer before depositing the second channel layers and the second insulating layers The first storage layer and the lower Channel portion; deposit a first dielectric partition to fill the first trench; etch a second trench to cut the second conductive plug, the second storage layer, and the upper channel portion to expose the first dielectric A partition wall; and a second dielectric partition wall is deposited to fill the second trench and contact the first dielectric partition wall.

The semi-cylindrical semiconductor memory element uses a multi-step etching scheme to increase the total depth width, so that conventional etching tools with normal etching ability can still manufacture higher density semiconductor memory elements.

The above description will be described in detail in the following embodiments, and the technical solutions of the present invention will be further explained.

In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious and understandable, the attached symbols are described as follows:

100‧‧‧Memory component

200‧‧‧Memory component

102‧‧‧ Base material

104‧‧‧Conductor layer

106‧‧‧Insulation

110‧‧‧Etching stop layer

112‧‧‧Storage layer

112’‧‧‧ storage layer

112a‧‧‧Series

112b‧‧‧Series

112c‧‧‧Series

112a’‧‧‧Series

112b’‧‧‧Series

114‧‧‧channel layer

114’‧‧‧Channel

114”‧‧‧channel layer

114a‧‧‧Channel Department

114b‧‧‧Channel Department

114a’‧‧‧Access Department

114b’‧‧‧Access Department

114a”‧‧‧ Channel Department

114b”‧‧‧Channel Department

114c‧‧‧Channel Department

116‧‧‧hole

116’‧‧‧hole

116a‧‧‧recess

116a’‧‧‧recess

118‧‧‧dielectric packed column

120‧‧‧Conductive plug layer

120a‧‧‧Conductive plug

120b‧‧‧Conductive plug

122‧‧‧Groove

122’‧‧‧Trench

124‧‧‧Dielectric partition

124’‧‧‧Dielectric partition

130‧‧‧Etching stop layer

132‧‧‧dielectric packed column

136‧‧‧Conductive plug layer

136a‧‧‧Conductive plug

136b‧‧‧Conductive plug

DWL‧‧‧Dummy character line

WL(0~127)‧‧‧character line

BL‧‧‧bit line

IG‧‧‧Reverse gate

SSL‧‧‧String selection line

CSL‧‧‧Common Source Line

GSL‧‧‧Gate selection line

T1‧‧‧thickness

T2‧‧‧thickness

W1‧‧‧Width

C1‧‧‧Width

C2‧‧‧Width

D1‧‧‧Depth

D2‧‧‧Depth

E1‧‧‧Width

E2‧‧‧Width

In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the drawings are described as follows: FIG. 1 is a cross section of a three-dimensional semiconductor memory device according to an embodiment of the present disclosure Figures 2A~22A are top views of a method for manufacturing a semiconductor memory device according to certain embodiments of the present disclosure in multiple steps; Figures 2B~22B are views of certain embodiments according to the present disclosure A cross-sectional view of the semiconductor memory device manufacturing method in multiple steps; FIG. 23A is a top view of a three-dimensional semiconductor memory device according to another embodiment of the present disclosure; FIG. 23B is a cross-sectional line along FIG. 23A 23B-23B sectional views; and FIG. 24 is a cross-sectional view of a three-dimensional semiconductor memory device according to another embodiment of the present disclosure.

This specification provides a method for manufacturing a three-dimensional memory element, which can obtain a higher memory storage capacity in a smaller element size, and at the same time, it can also take into account the operation stability of the element. In order to make the above embodiment of the present specification and other objects, features and advantages more obvious and understandable, a memory element and its manufacturing method are specifically described below as preferred embodiments, which will be described in detail in conjunction with the accompanying drawings.

However, it must be noted that these specific implementation examples and methods are not intended to limit the present invention. The present invention can still be implemented using other features, components, methods, and parameters. The proposed preferred embodiments are only used to illustrate the technical features of the present invention, and are not intended to limit the patent application scope of the present invention. Those with ordinary knowledge in this technical field will be able to make equivalent modifications and changes based on the description of the following description without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be denoted by the same element symbols.

It should be understood that although "first", "second", etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, and/or sections should not be affected by these Terminology limitations. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.

The terminology used herein is merely for describing specific embodiments of the present invention and is not intended to limit the present invention. For example, this article uses "One", "an", and "the" do not limit the components to singular or plural forms. As used herein, "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the term "comprising" or "including" specifies the features, regions, wholes, steps, operations, presence of elements and/or components, but does not exclude one or more other features , Regions, wholes, steps, operations, elements, components, and/or combinations thereof.

In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship between one element and another element, as shown. It should be understood that relative terms are intended to include different orientations of the device than those shown in the figures. For example, if the device in one drawing is turned over, the element described as being on the "lower" side of the other element will be oriented on the "upper" side of the other element. Thus, the exemplary term "lower" may include "lower" and "upper" orientations, depending on the particular orientation of the drawings. Similarly, if the device in one figure is turned over, elements described as "below" or "beneath" other elements would be oriented "above" the other elements. Thus, the exemplary terms "below" or "below" can include an orientation of above and below.

Please refer to FIG. 1, which illustrates a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. The semiconductor memory device 100 includes a plurality of layers (for example, 64 layers or more) of a lower half-stack structure (that is, a layer stack below the etch stop layer 110) and an upper half-stack structure (that is, a stack layer above the etch stop layer 110) So that the overall stacked structure does not need to face deeper hole/trench etching processes.

In this embodiment, the lower half of the laminated structure includes multiple conductors Layers (eg, reverse gate IG or multiple word lines WL32-WL64) and insulating layers are alternately stacked on the substrate. The lower half-layer structure includes a lower channel portion (114a, 114b, 114c) and a lower storage layer (112a, 112b, 112c). Each segment of the lower storage layer (112a, 112b, 112c) is sandwiched between the corresponding segment of the lower channel portion (114a, 114b, 114c) and the corresponding segment of the conductor layer (eg, WL32-WL64), so as to form a plurality of memory cells.

In this embodiment, the upper half-stack structure includes a plurality of conductor layers (for example, SSL, DWL, or WL0-WL31) and a plurality of insulating layers alternately stacked on the etch stop layer 110. The upper half-stacked structure includes upper channel portions (114a', 114b') and upper storage layers (112a', 112b'). Each segment of the upper storage layer (112a', 112b') is sandwiched between the corresponding segment of the upper channel portion (114a', 114b') and the corresponding segment of the conductor layer (eg WL0~WL31) to form a plurality of memory cells .

In this embodiment, the conductive plugs (120a, 120b) are connected between the upper channel portions (114a', 114b') and the lower channel portions (114a, 114b). Another conductive plug (136a, 136b) is formed above the multilayer stack structure and connected to the upper channel portion (114a', 114b'). Therefore, the upper and lower channel portions may be connected in series by conductive plugs (120a, 120b, 136a, 136b). In this embodiment, the conductive plugs (120a, 120b, 136a, 136b) include semiconductor materials that are preferably doped semiconductor materials, for example made of doped polysilicon, but are not limited thereto.

In this embodiment, the dielectric partition wall (124, 124') is located between the channel portion (114a, 114a') and the channel portion (114b, 114b'). More specifically, the dielectric partition has an upper half (ie 124') and a lower half (ie 124) between the channel part (114a, 114b) and the channel part (114a', 114b'). The upper and lower halves of the dielectric partition have tapered cross-sections. In some embodiments of this specification In the middle, the top cross section of the lower half 124 is wider than the bottom cross section of the upper half 124'. The channel parts (114a, 114a') and channel parts (114b, 114b') may also be referred to as first channel parts (114a, 114a') and second channel parts (114b, 114b'), respectively.

Please refer to FIGS. 2A and 2B. FIG. 2B is a cross-sectional view taken along section line 2B-2B of FIG. 2A. A plurality of conductor layers 104 and insulating layers 106 are alternately deposited on the base material 102 to form a multilayer stack structure, such as the lower half-stack structure in FIG. 1. In some embodiments of the present specification, the insulating layer 106 may be made of a dielectric material, including oxide such as silicon oxide. The conductor layer 104 may be made of metal (for example, gold, copper, aluminum, tungsten, or the above alloy) or semiconductor material (for example, doped or undoped polycrystalline or single crystal silicon/germanium) or other suitable materials. The etch stop layer 110 is further deposited on the multilayer stack structure, and the etch stop layer 110 may be made of a dielectric material different from the insulating layer 106. In the present embodiment, the etch stop layer 110 may be deposited on top of the insulating layer 106 and have a thickness T1 ranging from about 20 nm to about 100 nm. In this embodiment, the total average thickness T2 of the conductor layer 104 and the insulating layer 106 ranges from about 40 nm to about 70 nm.

Please refer to FIGS. 3A and 3B. FIG. 3B is a cross-sectional view taken along section line 3B-3B of FIG. 3A. An etching step is performed to form a plurality of holes 116 on the multilayer stacked structure to form a hole array (ie, rows of holes). Each hole 116 passes through the multilayer stack structure (104, 106) and the etch stop layer 110. In some embodiments of the present specification, the porous hole 116 may have an O-shaped, elliptical, egg-shaped, or rounded rectangular periphery, but is not limited thereto. In some embodiments of the present specification, a patterned hard mask (not shown in the drawing) is used as an etching mask to perform an anisotropic etching process, such as an anisotropic etching process for a multilayer stack structure Etching multiple holes 116. In this embodiment, each hole 116 may have a range Width W1 around the bottom from about 100 nm to about 250 nm.

Then, a storage layer 112 and a channel layer 114 are formed on the bottom and sidewalls of each hole 116 through a deposition process, such as low pressure chemical vapor deposition (LPCVD). In some embodiments of the present specification, the storage layer 112 may be a composite layer (ie, ONO structure) of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, but the structure of the storage layer is not This is limited. In other embodiments of the present specification, the composite layer of the storage layer may also be selected from a silicon oxide-silicon nitride-silicon oxide-silicon nitride-silicon oxide (oxide-nitride-oxide-nitride-oxide , That is, ONONO) structure, a silicon-silicon oxide-silicon nitride-silicon oxide-silicon-silicon (SONOS) structure, a band gap engineering silicon-silicon oxide-nitride Band-gap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS) structure, tantalum nitride-alumina-silicon nitride-silicon oxide-silicon (tantalum nitride, aluminum oxide) , silicon nitride, silicon oxide, silicon, TANOS) structure and a metal high-k dielectric bandgap engineering silicon-silicon oxide-silicon nitride-silicon oxide-silicon (metal-high-k bandgap-engineered silicon-oxide- Nitride-oxide-silicon (MA BE-SONOS) structure. In this embodiment, the storage layer 112 may be an ONO structure. The channel layer 114 includes a doped semiconductor material or an undoped semiconductor material. In this embodiment, the channel layer 114 may be a polysilicon layer.

Please refer to FIGS. 4A and 4B. FIG. 4B is a cross-sectional view taken along section line 4B-4B of FIG. 4A. Next, a dielectric filled pillar 118 is formed in each hole 116 by depositing a dielectric material.

Please refer to FIGS. 5A and 5B. FIG. 5B is a cross-sectional view taken along section line 5B-5B of FIG. 5A. Using the etch stop layer 110 as a stop layer, a planarization process (for example, a CMP process) is performed to remove excess material. In this embodiment, the conductor layer of the lower half-stack structure constitutes a plurality of word lines (WL32-WL63), an inverse gate IG, and a plurality of word lines (WL64-WL95), but it is not limited thereto.

Please refer to FIGS. 6A and 6B. FIG. 6B is a cross-sectional view taken along section line 6B-6B of FIG. 6A. Then, an etch-back process is performed to remove the tops of the dielectric fill pillar 118, the storage layer 112, and the channel layer 114 to form the recess 116a.

Please refer to FIGS. 7A and 7B. FIG. 7B is a cross-sectional view taken along line 7B-7B of FIG. 7A. The conductive plug layer 120 is deposited in the recess 116a. The material constituting the conductive plug layer may include doped or undoped semiconductor materials (such as doped or undoped polycrystalline or single crystal silicon/germanium) or other suitable materials.

Please refer to FIGS. 8A and 8B. FIG. 8B is a cross-sectional view along section line 8B-8B of FIG. 8A. Using the etch stop layer 110 as a stop layer, another planarization process (for example, a CMP process) is performed for removing excess material. In this embodiment, the etch stop layer 110 is located on one side of the conductive plug layer 120 or aligned with the conductive plug layer 120. In some embodiments, the etch stop layer 110 and the conductive plug layer 120 may have a continuously flush top surface.

Please refer to FIGS. 9A and 9B. FIG. 9B is a cross-sectional view taken along line 9B-9B of FIG. 9A. A trench 122 is etched in the holes 116 of each row to cut the conductive plug layer 120, the dielectric fill pillar 118, the storage layer 112, and the channel layer 114. Therefore, the conductive plug layer 120 is divided into two conductive plugs (120a, 120b). Therefore, the storage layer 112 is cut to form a U-shaped tandem portion 112a on the first side of the side wall of each hole 116 and on the opposite second side of the side wall of each hole 116 The U-shaped tandem portion 112b, but the bottom tandem portion 112c is not cut by the groove 122 and is still connected between the bottom ends of the tandem portions (112a, 112b). The channel layer 114 has a U-shaped channel portion 114a and a U-shaped channel portion 114b spaced apart from each other, but the bottom channel portion 114c is not cut by the groove 122 and is still connected between the bottoms of the channel portions (114a, 114b). Each conductive plug (120a, 120b) may be made of the same material as the channel layer 114, but the cross-sectional width of each conductive plug (120a, 120b) is larger than the cross-sectional width of the channel layer 114.

In this embodiment, the width C1 in the bottom of the trench 122 ranges from about 30 nm to about 60 nm, the width E1 in the top ranges from about 50 nm to about 80 nm, and the internal depth D1 ranges from about 1200 nm to about 2400 nm, but not Limited to this. The groove 122 has a tapered cross section tapering from the top to the bottom. Generally speaking, the aspect ratio (ie D1/C1) achievable by the etching capability is less than about 40-60.

Please refer to FIGS. 10A and 10B. FIG. 10B is a cross-sectional view taken along section line 10B-10B of FIG. 10A. Dielectric material is then filled into the trench 122 to form a dielectric layer embedded between the channel portions (114a, 114b) of the channel layer 114 and between the tandem portions (112a, 112b) of the storage layer 112 and the hole 116 The dielectric partition 124 in the column 118 is electrically filled. The dielectric partition 124 also has a tapered cross-section 112 that tapers from its top to the bottom.

Please refer to FIGS. 11A and 11B. FIG. 11B is a cross-sectional view taken along line 11B-11B of FIG. 11A. A plurality of conductor layers 104 and insulating layers 106 are alternately deposited on the etch stop layer 110 and the conductive plugs (120a, 120b) to form another multilayer stacked structure (for example, in FIG. 1, the upper half of the stacked structure is deposited on the lower half Above the laminated structure). In some embodiments of the present specification, the insulating layer 106 may be made of a dielectric material, including oxide such as silicon oxide. The conductor layer 104 may be made of metal (for example For example, gold, copper, aluminum, tungsten or the above alloys) or semiconductor materials (for example, doped or undoped polycrystalline or single crystal silicon/germanium) or other suitable materials. The etch stop layer 130 is further deposited to cover the upper half of the stacked structure, and the etch stop layer 130 may be made of a dielectric material different from the insulating layer 106, including nitride such as silicon nitride. In this embodiment, the etch stop layer 130 may be deposited on the topmost insulating layer 106 of the upper half-stack structure.

Please refer to FIGS. 12A and 12B. FIG. 12B is a cross-sectional view taken along section line 12B-12B of FIG. 12A. An etching step is performed to form a plurality of holes 116' on the upper semi-layered structure to form an array of holes (i.e., multiple rows of holes). Each hole 116' is aligned with a corresponding hole 116 in the lower half-stack structure. Each hole 116' passes through the multilayer stack structure (104, 106) and the etch stop layer 130. In some embodiments of the present specification, the porous hole 116' may have an O-shaped, elliptical, egg-shaped, or rounded rectangular periphery, but is not limited thereto. In some embodiments of the present specification, a patterned hard mask (not shown in the drawing) is used as an etching mask to perform an anisotropic etching process, such as an anisotropic etching process for a multilayer stack structure A plurality of holes 116' are etched.

Then, by a deposition process, such as low pressure chemical vapor deposition (LPCVD), a storage layer 112' and a channel layer 114' are formed on the bottom and side walls of each hole 116'. In some embodiments of the present specification, the storage layer 112 may be a composite layer (ie, ONO structure) of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, but the structure of the storage layer is not This is limited. In other embodiments of the present specification, the composite layer of the storage layer may also be selected from a silicon oxide-silicon nitride-silicon oxide-silicon nitride-silicon oxide (oxide-nitride-oxide-nitride-oxide , That is, ONONO) structure, a silicon-silicon Oxide-silicon nitride-silicon oxide-silicon (silicon-oxide-nitride-oxide-silicon, or SONOS) structure, a band-gap engineered silicon-silicon oxide-silicon nitride-silicon oxide-silicon (bandgap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS) structure, tantalum nitride-alumina-silicon nitride-silicon oxide-silicon (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon, TANOS ) Structure and a metal high dielectric constant energy gap engineering silicon-silicon oxide-silicon nitride-silicon oxide-silicon (metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon, MA BE-SONOS ) An ethnic group composed of structures. In this embodiment, the storage layer 112' may be an ONO structure, and the channel layer 114' may be a polysilicon layer.

Please refer to FIGS. 13A and 13B. FIG. 13B is a cross-sectional view taken along line 13B-13B of FIG. 13A. An etch-back process is then performed to remove excess channel layer 114' material and storage layer 112' to expose the top surfaces of the conductive plugs (120a, 120b) and the dielectric barrier 124. The remaining channel layer 114' remains on the sidewalls of the storage layer 112' as sidewall etching protection. The lowermost surface of the remaining channel layer 114' is higher than the lowermost surface of the storage layer 112', in other words, the channel layer 114' exposes the bottom end of the storage layer 112' and is separated from the conductive plugs (120a, 120b) . In this embodiment, the conductor layer of the upper half-stack structure constitutes a string selection line SSL, a dummy word line DWL and a plurality of word lines (WL0 to WL31), and a gate selection line GSL and a dummy word line DWL on the other side. Multiple character lines (WL96~WL127).

Please refer to FIGS. 14A and 14B. FIG. 14B is a cross-sectional view taken along line 14B-14B of FIG. 14A. Another channel layer 114" is formed by a deposition process such as low pressure chemical vapor deposition (LPCVD) into each hole 116' and the upper half layer Stacked structure. The channel layer 114" is in contact with the bottom of the channel layer 114' and the exposed top surfaces of the conductive plugs (120a, 120b) and the dielectric partition 124. The channel layer 114" and the channel layer 114' together constitute an upper channel portion, and the channel layer The bottom end of 114" contacts the conductive plug (120a, 120b).

Please refer to FIGS. 15A and 15B. FIG. 15B is a cross-sectional view along line 15B-15B of FIG. 15A. Thereafter, a dielectric filled pillar 132 is formed in each hole 116' by depositing a dielectric material.

Please refer to FIGS. 16A and 16B. FIG. 16B is a cross-sectional view taken along section line 16B-16B of FIG. 16A. Use the etch stop layer 130 as a stop layer to perform a planarization process, such as a CMP process, to remove part of the channel layer 114” and part of the dielectric fill pillar 132 on the etch stop layer 130. The channel layer 114” may be referred to as an “inner channel layer ", the channel layer 114' may be called an "outer channel layer", the inner channel layer 114" is in contact with the outer channel layer 114', and together constitutes the upper channel portion, the outer channel layer 114' is located between the storage layer 112' and the inner channel layer 114 "between.

Please refer to FIGS. 17A and 17B. FIG. 17B is a cross-sectional view taken along line 17B-17B of FIG. 17A. An etch-back process is then performed to remove the top of the dielectric fill pillar 132, the storage layer 112', and the channel layer (114', 114") to form the recess 116a'.

Please refer to FIGS. 18A and 18B. FIG. 18B is a cross-sectional view taken along section line 18B-18B of FIG. 18A. The conductive plug layer 136 is deposited in the recess 116a'. The material constituting the conductive plug layer may include doped or undoped semiconductor materials (such as doped or undoped polycrystalline or single crystal silicon/germanium) or other suitable materials.

Please refer to FIGS. 19A and 19B. FIG. 19B is a cross-sectional view taken along line 19B-19B of FIG. 19A. Perform using the etch stop layer 130 as a stop layer Another planarization process (eg CMP process) is used to remove excess material. In this embodiment, the etch stop layer 130 is located on one side of the conductive plug layer 136 or aligned with the conductive plug layer 136. In some embodiments, the etch stop layer 130 and the conductive plug layer 136 may have a continuously flush top surface.

Please refer to FIGS. 1, 20A, and 20B. FIG. 20B is a cross-sectional view taken along section line 20B-20B of FIG. 20A. A trench 122' is etched in each row of holes 116' to cut the conductive plug layer 136, the dielectric fill pillar 132, the storage layer 112' and the channel layer (114', 114"). Therefore, the conductive plug layer 236 is divided into two conductive plugs (136a, 136b). Therefore, the storage layer 112' is cut to form a U-shaped tandem portion 112a' located on the first side of the sidewall of each hole 116' and located at each hole The U-shaped tandem portion 112b' on the opposite second side of the side wall of 116. The inner channel layer 114" is also cut to form an L-shaped channel portion 114a" and an L-shaped channel portion 114b" that are spaced apart from each other. The top of the dielectric barrier 124 is exposed by using the etch stop layer 110 as a stop layer of the etch trench 122'. The tandem portions (112a, 112a') and tandem portions (112b, 112b') of the storage layer may also be referred to as first tandem portions (112a, 112a') and second tandem portions (112b, 112b').

In this embodiment (please refer to FIGS. 9B and 20B), the width C2 in the bottom of the trench 122' ranges from about 30 nm to about 60 nm, the width E2 in the top ranges from about 50 nm to about 80 nm, and the internal depth D2 The range is about 1200 nm to about 2400 nm, but is not limited thereto. The groove 122' has a tapered cross section tapering from the top to the bottom. Using a two-step etching scheme, the overall aspect ratio of high-density memory designs (such as 64-layer or 96-layer vertical memory arrays) can be relaxed, ie (D1+D2)/C1. In other embodiments, a three-step or more-step etching scheme may be used to relax the design of higher density memory (such as a vertical memory array with 128 or more layers) Total aspect ratio.

Please refer to FIGS. 1, 21A, and 21B. FIG. 21B is a cross-sectional view taken along the line 21B-21B of FIG. 21A. The dielectric material is then filled into the trench 122' to form a tandem portion (112a') embedded between the channel portions (114a', 114b') of the channel layer (114', 114") and in the storage layer 112' , 112b') and the dielectric partition 124 in the dielectric packing column 132. The dielectric partition 124' also has a tapered cross section tapering from the top to the bottom. The upper dielectric partition 124' and The lower dielectric partition 124 forms a continuous dielectric partition to divide the channel portion into two opposing U-shaped or semi-cylindrical channel portions (114a, 114a', 114b, 114b'). Conductive plugs (120a, 120b) It is connected between the upper channel part (114a', 114b') and the lower channel part (114a, 114b).

Please refer to FIGS. 1, 22A, and 22B. FIG. 22B is a cross-sectional view taken along line 22B-22B of FIG. 22A. The three-dimensional memory element 100 may include an interconnection layer, that is, a bit line BL and a common source line CSL to connect to the channel portion in the hole (116, 116'). Specifically, two conductive plugs (136a, 136b) are formed at the open end of each hole (116, 116') and are in contact with the channel portions (114a', 114b'), respectively. One of the two conductive plugs (136a, 136b) is connected to the bit line BL, and the other of the two conductive plugs (136a, 136b) is connected to the common source line CSL. Therefore, all memory cells of the memory device 100 can be connected to the interconnect layer.

Please also refer to Figures 1, 23A, 23B, and 24. The difference between the memory device 200 and the memory device 100 is that the bottom serial part 112c of the memory device 100 does not exist in the memory device 200, so that the memory cells on the serial part 112a and the serial part 112b cannot be connected. The same list. For example, the serial string_0 of the storage layer corresponds to the string selection line SSL_0, the dummy word line DWL_e, a plurality of character lines (WL0_e~WL63_e), and the gate selection line GSL, while the serial layer of the storage layer string_1 corresponds to the string selection line SSL_1, the dummy word line DWL_o, the multi-word line s (WL0_o~WL63_o), and the gate selection line GSL. The three-dimensional memory element 200 further includes a bit line BL connected to all conductive plugs (136a, 136b) and a common source line CSL connected to the bottom ends of all channel portions (114a, 114a', 114b, 114b'). Therefore, the configuration of the interconnection layer of the memory device 200 is also different from the configuration of the interconnection layer of the memory device 100.

According to the foregoing embodiment, the semi-cylindrical semiconductor memory device utilizes a multi-step etching scheme to relax the overall depth width of the higher density design, so that conventional etching tools with normal etching capabilities can still manufacture higher density design shaped semiconductor memory devices.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in this technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be deemed as defined by the appended patent application scope.

100‧‧‧Memory component

110‧‧‧Etching stop layer

112a‧‧‧Series

112b‧‧‧Series

112c‧‧‧Series

112a’‧‧‧Series

112b’‧‧‧Series

114’‧‧‧Channel

114”‧‧‧channel layer

114a‧‧‧Channel Department

114b‧‧‧Channel Department

114a’‧‧‧Access Department

114b’‧‧‧Access Department

114c‧‧‧Channel Department

120a‧‧‧Conductive plug

120b‧‧‧Conductive plug

124‧‧‧Dielectric partition

124'‧‧‧Dielectric partition

130‧‧‧Etching stop layer

136a‧‧‧Conductive plug

136b‧‧‧Conductive plug

DWL‧‧‧Dummy character line

WL(0~127)‧‧‧character line

BL‧‧‧bit line

IG‧‧‧Anti-gate layer

SSL‧‧‧String selection line

CSL‧‧‧Common Source Line

GSL‧‧‧Gate selection line

Claims (9)

A three-dimensional memory device includes: a substrate; a plurality of conductive layers and a plurality of insulating layers, stacked alternately on the substrate to form a multilayer stack structure; and a storage layer passing through the multilayer stack structure, And has a first tandem portion and a second tandem portion; a first channel portion is located on one side of the first tandem portion, and the first tandem portion is located in the multilayer stack structure and the first Between the channel portions; a second channel portion is located on one side of the second tandem portion, and the second tandem portion is located between the multilayer stack structure and the second channel portion, the first channel portion is The second channel portion each includes an upper channel portion and a lower channel portion; and a first conductive plug connected between the upper channel portion and the lower channel portion, wherein the upper channel portion includes a An outer channel layer and an inner channel layer, the outer channel layer is located between the storage layer and the inner channel layer, and is separated from the first conductive plug. The three-dimensional memory device described in item 1 of the patent application scope further includes an etch stop layer located in the multilayer stack structure and on the side of the first conductive plug. The three-dimensional memory element described in item 1 of the patent application scope further includes a bottom channel, and the lower channel portions of the first channel portion and the second channel portion are U-shaped channels separated from each other, and are connected to The bottom channel Both ends. The three-dimensional memory device as described in item 1 of the patent application scope further includes a dielectric partition wall between the first and second serial portions of the storage layer, the dielectric partition wall includes an upper portion and a lower portion , The cross section of the top end of the lower part is wider than that of the bottom end of the upper part. The three-dimensional memory device described in item 1 of the patent application scope further includes a second conductive plug located above the multilayer stack structure and connected to the upper channel portion. The three-dimensional memory device described in item 5 of the patent application scope further includes an etch stop layer located above the multilayer stack structure and on the side of the second conductive plug. The three-dimensional memory device as described in item 5 of the patent application range, wherein the material of the first conductive plug and the second conductive plug is doped polysilicon. A method for manufacturing a three-dimensional memory device includes: alternately depositing a plurality of first conductive layers and first insulating layers on a substrate; etching a first through hole to pass through the first conductive layers and the first insulating layers; Depositing a first storage layer in the first through hole; depositing a channel part on the first storage layer; Depositing a first conductive plug to contact the lower channel portion; alternately depositing a plurality of second conductive layers and a second insulating layer on the first conductive plug; etching a second through hole through the second channel layers and the ones A second insulating layer to expose the first conductive plug; deposit a second storage layer in the second through hole; deposit a second channel layer on the second storage layer; etch the second storage layer and the first Two channel layers to expose the first conductive plug, and the second channel layer remaining after etching is located on the sidewall of the second storage layer; a third channel layer is deposited on the second channel layer remaining after etching to form An upper channel portion, which contacts the first conductive plug; and a second conductive plug is deposited, which contacts the top end of the upper channel portion. The manufacturing method as described in item 8 of the patent application scope, wherein before depositing the second channel layers and the second insulating layers, the method further includes: etching a first trench to cut the first conductive plug, the first A storage layer and the lower channel portion; deposit a first dielectric partition to fill the first trench; etch a second trench to cut the second conductive plug, the second storage layer and the upper channel portion Exposing the first dielectric partition wall; and depositing a second dielectric partition wall to fill the second trench and contact the first dielectric partition wall.

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