CN105826324B - 3 D semiconductor element and its manufacturing method - Google Patents
3 D semiconductor element and its manufacturing method Download PDFInfo
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- CN105826324B CN105826324B CN201510004402.3A CN201510004402A CN105826324B CN 105826324 B CN105826324 B CN 105826324B CN 201510004402 A CN201510004402 A CN 201510004402A CN 105826324 B CN105826324 B CN 105826324B
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Abstract
The invention discloses a kind of 3 D semiconductor element and its manufacturing method, which includes: the substrate with the staircase areas including N number of step, and wherein N is the integer more than or equal to 1；A lamination of substrate is stacked and placed on multilayered structure, and multilayered structure includes that active layer and insulating layer crisscross on substrate, lamination includes that multiple secondary laminations are formed on substrate, and N number of step of secondary lamination and staircase areas is correspondingly arranged to be respectively formed contact area；With the multiple connectors for being located at corresponding contact area, and connector is to extend downwardly the bottom being connected to below multilayered structure.
Description
Technical field
The invention relates to a kind of three-dimensional (three-dimensional, 3D) semiconductor element and its manufacturing methods, and
In particular to the 3 D semiconductor element and its manufacturing method of a kind of tool bottom contact (bottom contacts).
Background technique
Non-volatile memory device has a very big characteristic to be in design, when memory component loses or remove electricity
Remain to save the integrality of data mode behind source.There are many non-volatile memory devices of different shaped state to be mentioned for industry at present
Out.But related dealer still constantly researches and develops new design or combines the prior art, carries out the memory plane containing storage unit
Lamination to reach the memory construction with more high storage capacity.Such as have some plural layers transistor stacks with it is non-
Door (NAND) type flash memory structure is suggested.Related dealer has proposed the three-dimensional storage element of various different structures, such as has
Storage unit, the storage unit and circulating type grid of bigrid (double gate) of single grid (Single-Gate)
The three-dimensional storages elements such as the storage unit of (surrounding gate).
Relevant design person can construct a three-dimensional memory structure without undesirable, not only have many stacking layer planes
(memory layer) and reach higher storage volume, (such as can with the preservation of good data with more excellent characteristic electron
By property and service speed), so that memory construction is such as wiped and be programmed operation with quick by stable.It is general and
Speech, page (Page) size of NAND-type flash memory is proportional to number of bit.Therefore when component size diminution, it is not only cost drop
Low, the increase of operation repetitive also improves the read or write speed of element, and then reaches higher data transmission bauds.However,
When reducing component size, still need to consider there are many other problems.
By taking general three-dimensional perpendicular channel-type memory component (ex:NAND) as an example, multilayered structure connector
(multilayered connectors) in one direction the spacing (X-pitch) in such as X-direction using wide staircase rule
(wide staircase rule) and loosen, but spacing (Y-pitch) in such as Y-direction can be for chain in another direction
Connecing multilayered structure connector becomes very intensive to word-line decoder.Although expanding Y-direction region (block_Y) can relax
Y-direction spacing, but the number of serial selection line (string selection line, SSL) will will increase, and cause more such as
The problem of power loss (power consumption) and signal interference (signal disturbance).In view of in three-dimensional
The situation of serious interference in NAND element, the design of less SSL number will be the preferable selections of building three-D elements, however such
Design may cause the high pattern density of the fan-out area of layer (such as wordline WL).
Summary of the invention
The invention relates to a kind of 3 D semiconductor element and its manufacturing methods.3 D semiconductor member according to the embodiment
Part is to propose that ladder contact is connected to the bottom below multilayered structure, such as contact directly to extend ladder to bottom, or formed
Top conductor by connect ladder contact and bottom contact etc. in a manner of implement.
It is to propose a kind of 3 D semiconductor element according to embodiment, comprising: there is one including N number of step (N steps)
One substrate of staircase areas (staircase region), wherein N is the integer more than or equal to 1；With multilayered structure
(multi-layers) it is stacked and placed on a lamination of substrate, and multilayered structure includes that active layer and insulating layer crisscross on substrate, is folded
Layer includes that multiple secondary laminations are formed on substrate, and N number of step of these secondary laminations and staircase areas is correspondingly arranged to be respectively formed
Contact area；With the multiple connectors for being located at corresponding contact area, and these connectors be extend downwardly be connected to it is more
A bottom below layer structure.
It is the manufacturing method for proposing a kind of 3 D semiconductor element according to embodiment, comprising:
A substrate is provided, substrate has the staircase areas including N number of step, and wherein N is the integer more than or equal to 1；
It forms with multi-layer structure one to be stacked on substrate, and multilayered structure includes that active layer interlocks with insulating layer, fold
Layer includes that multiple secondary laminations are formed on substrate, and N number of step of these secondary laminations and staircase areas is correspondingly arranged to be respectively formed
Contact area；With
It forms multiple connectors and is located at corresponding contact area, and these connectors are to extend downwardly to be connected to multilayer
A bottom below structure.
More preferably understand to have to above-mentioned and other aspect of the invention, special embodiment below, and cooperates institute's attached drawing
Formula is described in detail below:
Detailed description of the invention
Fig. 1 is the perspective view of a 3 D semiconductor element.
Fig. 2A is the top view of the part-structure of a 3 D semiconductor element of first embodiment of the invention.
Fig. 2 B is the diagrammatic cross-section of 3 D semiconductor element depicted in hatching 2B-2B along Fig. 2A.
Fig. 2 C is the diagrammatic cross-section of 3 D semiconductor element depicted in hatching 2C-2C along Fig. 2A.
Fig. 2 D is the diagrammatic cross-section of 3 D semiconductor element depicted in hatching 2D-2D along Fig. 2A.
Fig. 3 A to Figure 14 D is painted a kind of manufacturing method of the 3 D semiconductor element of the tool bottom contact of first embodiment.
Figure 15 is the diagrammatic cross-section of a 3 D semiconductor element of second embodiment of the invention.
Figure 16 to Figure 25 is painted a kind of manufacturing method of the 3 D semiconductor element of the tool bottom contact of second embodiment.
[symbol description]
10: substrate
101: bottom
11: memory layer
12,13: selection line
15: serial
17: serial contact
18: conducting wire
21,22, Ld: dielectric layer
211: insulating layer
213: active layer
231,232,233,234: multilayered structure connector
241,242,243,244: base connector
251,252,253,254: top conductor
31,32,33,34: connector
314,324,334,344: the first conductive part
315,325,335,345: the second conductive part
314h, 324h, 334h, 344h: bottom contact hole
Rs: staircase areas
Rc1, Rc2, Rc3, Rc4: contact area
Tc: trench region
TL1, TL2, TL3, TL4: the mask of three-decker
PR-1, PR-2, PR-3, PR-4: patterning photoresist
Lc: conductor
D: spacing
S: thickness
Specific embodiment
The embodiment of the present invention is to propose a kind of 3 D semiconductor element, and especially a kind of tool bottom contacts (bottom
Contacts 3 D semiconductor element).According to embodiment, it is to construct bottom contact in 3 D semiconductor element, makes element
It can more be improved in the applicability of application range.For example, district selector (block selectors) can be designed at rank
Below terraced contact area (staircase contact region), partly led using the three-dimensional that the tool bottom of embodiment of this case contacts
Volume elements part makes to connect in the selector of staircase areas bottom with the multilayered structure of contact area, area and keeps away by having reached to save
Exempt to be fanned out to the excessively high problem of density.Furthermore can be with the contact of the bottom of Application Example there are also other the case where, such as peripheral region
The application of the 3 D semiconductor element of (periphery-under-array) below array region, and/or need local array
Ladder contact application.The bottom contact structure of embodiment, for pursuing the 3 D semiconductor member of high Electronic Performance and characteristic
Part can provide more diverse structure possibility.
Present invention can apply to the 3 D semiconductor elements of the different memory cell array kenels of many tools, such as vertical channel
Formula (vertical-channel, VC) 3 D semiconductor element and vertical gate formula (vertical-gate, VG) 3 D semiconductor
Element, the present invention are not particularly limited the application kenel of embodiment.Fig. 1 is the perspective view of a 3 D semiconductor element.
It is to be explained for being painted a vertical channel formula 3 D semiconductor element in Fig. 1.One 3 D semiconductor element includes a lamination
(stack) there is multilayered structure (multi-layers) to be stacked and placed on a substrate 10, and one including N number of step (N steps)
Staircase areas (staircase region) Rs, wherein N is the integer more than or equal to 1.And multilayered structure includes several layers of storage
Device layer (memory layers) 11 (i.e. active layer e.g. includes control grid in VC element) crisscrosses base with insulating layer
On plate 10.3 D semiconductor element further includes a plurality of selection line (selection lines) 12 and is located at memory in parallel to each other
11 top of layer, a plurality of serial (strings) 15 is perpendicular to memory layer 11 and selection line 12, and wherein these serial 15 are electrically to connect
It is connected to corresponding selection line 12.Furthermore 3 D semiconductor element further includes a plurality of conducting wire 18 (such as bit line BLs) and is located at selection line
12 tops, and these conducting wires 18 are parallel to each other and perpendicular to selection line 12.Multiple storage units (cells) are respectively by these
Serial 15, these selection lines 12 and the definition of these conducting wires 18, and these storage units are arranged as multiple row (rows) and multirow
(columns) to form memory array.Furthermore multiple serial contact (string contacts) 17 are perpendicular to memory
Layer 11 and selection line 12, and every serial the 15 of storage unit are corresponded to per the setting of serial contact 17, wherein serially contact 17
It is electrically connected to corresponding selection line 12 and corresponding conducting wire 18.3 D semiconductor element further includes other elements, such as is selected
It selects line 12 and refers to top selection line (upper select lines, upper SG), and 11 lower section of memory layer more has lower section to select
Select the formation of line (lower select lines, lower SG) 13.
In embodiment, lamination includes that multiple secondary laminations (sub-stacks) are formed on substrate 10, and these secondary laminations with
N number of step of staircase areas Rs is correspondingly arranged to be respectively formed contact area (contact regions) (Rc).The three of embodiment
Dimension semiconductor element further includes multiple connectors (connectors), is located at corresponding contact area (Rc), and these connect
Connecing device is to extend downwardly the bottom (bottom layer) being connected to below multilayered structure.It is with the bottom of two kinds of aspects below
It is explained for the 3 D semiconductor element of contact, but the present invention is not limited to this.
Following embodiment is that dependency structure and technique of the invention are described referring to institute's accompanying drawings, and the right present invention is not limited in
This.Same or similar element is with same or similar label mark in embodiment.It is noted that the present invention and non-display
All possible embodiment out.It may not also can be applied in other state sample implementations proposed by the present invention.Furthermore the ruler in schema
Very little ratio is not drawn according to actual product equal proportion.Therefore, specification and diagramatic content are only described herein the use of embodiment, rather than
It is used as the scope of the present invention is limited.
<first embodiment>
Please refer to Fig. 1 and Fig. 2A~Fig. 2 D.Fig. 2A is the part of a 3 D semiconductor element of first embodiment of the invention
The top view of structure.Fig. 2 B is the diagrammatic cross-section of 3 D semiconductor element depicted in hatching 2B-2B along Fig. 2A.Figure
2C is the diagrammatic cross-section of 3 D semiconductor element depicted in hatching 2C-2C along Fig. 2A.Fig. 2 D is along Fig. 2A's
The diagrammatic cross-section of 3 D semiconductor element depicted in hatching 2D-2D.Furthermore the one of 3 D semiconductor element is presented in Fig. 2A
X/y plane, the yz that the xz plane of 3 D semiconductor element is presented in Fig. 2 B and Fig. 2 C and 3 D semiconductor element is presented in Fig. 2 D are flat
Face.
In embodiment, multiple secondary laminations (sub-stacks) included by lamination are formed on substrate 10, and these times
N number of step of lamination and staircase areas Rs is correspondingly arranged, and to be respectively formed contact area (contact regions), such as is schemed
Contact area Rc1, Rc2, Rc3 and Rc4 shown in 2A and Fig. 2 B.In the first embodiment, 3 D semiconductor element further includes more
A connector (connectors), such as 231,232,233 and of multilayered structure connector (multilayered connectors)
234 are located at corresponding contact area Rc1, Rc2, Rc3 and Rc4.According to first embodiment, these connectors are bottom connection
Device (bottom connectors) such as 241,242,243 and 244 is respectively formed in corresponding contact area, and bottom connects
Device extends downwardly the bottom 101 being connected to below multilayered structure (active layer 213 and insulating layer 211 that i.e. is staggered),
As shown in Figure 2 B.
As shown in Figure 2 C, multilayered structure connector (multilayered connectors) such as 231,232,233 and
234 be to be respectively formed in corresponding contact area Rc1, Rc2, Rc3 and Rc4, and be separately connected the active layer 213 of each secondary lamination
Drop zone.For example, multilayered structure connector 231 links the active layer 213 of the 4th step (staircase areas) in contact area Rc1
Drop zone.Similar, third step (staircase areas) is active in the link of multilayered structure connector 232 contact area Rc2
The drop zone of layer 213, multilayered structure connector 233 link the active layer of the second step (staircase areas) in contact area Rc3
213 drop zone and multilayered structure connector 234 link the active of the first step (staircase areas) in contact area Rc4
The drop zone of layer 213.
A and Fig. 2 D referring to figure 2..In first embodiment, each multilayered structure connector such as 231,232,233 and 234 is
Corresponding base connector such as 251,252,253 and 254 is electrically connected at such as with top conductor (top conductor) respectively
241,242,243 and 244.As shown in Figure 2 A, the multilayered structure connector 231 and base connector 241 being disposed adjacent are with one
Top conductor 251 is electrically connected.Similar, the multilayered structure connector 232 and base connector 242 being disposed adjacent are Yi Yiding
Portion's conductor 252 is electrically connected, and the multilayered structure connector 233 and base connector 243 being disposed adjacent are with a top conductor 253
It is electrically connected, the multilayered structure connector 234 and base connector 244 being disposed adjacent are with a top conductor 254 electric connection.
Top conductor 251,252,253 and 254 is spaced apart.
In first embodiment, multilayered structure connector (such as 231,232,233 and 234) and base connector (such as
241,242,243 and 244) be to extend parallel to each other, an and extension side of top conductor (such as 251,252,253 and 254)
To for example along the direction y-, being an extending direction example substantially perpendicular to base connector (such as 241,242,243 and 244)
Such as along the direction z-, as shown in Fig. 2 B to Fig. 2 D.
Furthermore the multilayered structure connector being disposed adjacent and base connector are between insulant such as dielectric layer 21 and 22
It separates and, as shown in Figure 2 D.Dielectric layer 21 and 22 can be including identical or different material, and the present invention to this and seldom limits
System.In one embodiment, the multilayered structure connector and base connector (the multilayered structure connector as shown in Figure 2 D that are disposed adjacent
231 and base connector 241) be the space D with less than 5 μm.So in the 3 D semiconductor element of practical application, spacing
D also can be other numerical value, be not limited to that the numerical value of illustration.
Furthermore dielectric layer 22 surrounds base connector (such as 241,242,243 and 244) and covering multilayered structure.One is real
It applies in example, a part around the dielectric layer 22 of base connector (base connector 241 as shown in Figure 2 D) is that have to be less than
Or the thickness S equal to 1 μm.So in the 3 D semiconductor element of practical application, thickness S also can be other numerical value, and not only limit
In the numerical value that this is illustrated.
Furthermore as shown in Figure 2 D, top conductor (such as 251,252,253 and 254) is formed on dielectric layer 21 and 22 simultaneously
Connect multilayered structure connector (such as 231,232,233 and 234) and base connector (such as 241,242,243 and 244)
Top surface.In other words, according to first embodiment, for connecting the top conductor (example of multilayered structure connector and base connector
It is to be separated by the active layer 213 of dielectric layer 21 and 22 and multilayered structure and insulation such as 251,252,253 and 254).
3 D semiconductor element according to the embodiment, constructed base connector (such as 241,242,243 and 244) can
The respective lines being electrically connected to below multilayered structure.The example of respective lines includes district selector such as TFTs, and for outer
The element that 3 D semiconductor element of the region below array region can be electrically connected is enclosed, and for needing local array
Ladder contact the element etc. that can be electrically connected of 3 D semiconductor element.Therefore, the bottom contact of embodiment, with
Multilayered structure connector (drop zone for linking to the active layer of each secondary lamination) coupling, for pursuing high Electronic Performance and characteristic
3 D semiconductor element be that can provide more possible change and progress.
It is the 3 D semiconductor element for proposing the tool bottom contact of one of applicable manufacture first embodiment below
Method.Fig. 3 A to Figure 14 D is painted a kind of manufacturing method of the 3 D semiconductor element of the tool bottom contact of first embodiment.Please
Related elements referring concurrently to Fig. 1 about the 3 D semiconductor element of embodiment.
Firstly, providing a substrate 10, there is the lamination including multilayered structure (multi-layers), multilayered structure thereon
Including staggeredly stacked active layer 213 and insulating layer 211 on substrate 10, lamination includes that multiple secondary laminations are formed in substrate 10
On, and secondary lamination it is corresponding with N number of step of staircase areas Rs of substrate 10 be respectively formed contact area (such as Rc1, Rc2,
Rc3, Rc4), wherein N is the integer more than or equal to 1.As shown in Figure 3A and Figure 3B, a dielectric layer 21 is formed in staircase areas Rs
On, and a trench region (trench area) Tc is defined along step.A referring to figure 3. is the 3 D semiconductor of embodiment
The top view (x/y plane) of the part-structure of element shows dielectric layer 21 and having at N number of step of contact area Rc1-Rc4
Active layer 213.Fig. 3 B is that (xz is flat for the diagrammatic cross-section of 3 D semiconductor element depicted in hatching 3B-3B along Fig. 3 A
Face).Fig. 3 C is the diagrammatic cross-section (xz plane) of 3 D semiconductor element depicted in hatching 3C-3C along Fig. 3 A.
Later, such as using three-decker technique (tri-layer process, a kind of mask of three-decker include
ODL/SHB/PR), the multilayered structure in trench region Tc is removed.In embodiment, etching a pair of of film layer, (i.e. N number of step is wherein
One layer of active layer 213 of one step and a layer insulating 211) and then to etch the fine tuning technique (trim- being masked
etch process).A- Fig. 4 B to Figure 11 A- Figure 11 B referring to figure 4..Fig. 4 A to Figure 11 B is illustrated embodiments 3 D semiconductor
Etching-fine tuning process schematic representation of the multilayered structure of the removal trench region Tc of element.Wherein, labeled as the icon of B, such as scheme
4B, Fig. 5 B, Fig. 6 B, Fig. 7 B ... Figure 11 B be painted along labeled as A icon section line B-B (such as be respectively 4B-4B,
5B-5B ... 11B-11B) sectional view.Furthermore since the height of dielectric layer 21 is typically much deeper than the width of trench region Tc,
Thus assume that dielectric layer 21 can be ignored along the etching-fine tuning in the direction y- in this exemplary technique.
As shown in Figure 4 A and 4 B shown in FIG., the mask TL1 (such as ODL/SHB/PR) of three-decker, and corresponding contact area are formed
The trench region Tc of Rc1.As fig. 5 a and fig. 5b, the first layer of contact area Rc1 is carried out to (i.e. N number of step with mask TL1
In first step an active layer 213 and an insulating layer 211, N=4) etching, the ditch of contact area Rc1 is located at after etching
Slot region Tc is to expose the second layer to (an active layer 213 and an insulating layer 211, N=for second step in i.e. N number of step
4) active layer 213.Later, the mask TL1 of three-decker is finely tuned, to form the mask TL2 of three-decker, contact area Rc1
It is exposed with the active layer 213 of second step in the trench region Tc of Rc2, as shown in Figure 6 A and 6 B.
Then, as shown in figures 7 a and 7b, the second layer of contact area Rc1 and Rc2 are carried out to (i.e. N number of ladder with mask TL2
An active layer 213 and an insulating layer 211, N=4 for second step in grade) etching, be located at after etching contact area Rc1 and
The trench region Tc of Rc2 is exposed third layer to (an active layer 213 and an insulating layer for third step in i.e. N number of step
211, N=4) active layer 213.Later, the mask TL2 of three-decker is finely tuned, to form the mask TL3 of three-decker, contact
The active layer 213 of third step is exposed in the trench region Tc of region Rc1, Rc2 and Rc3, such as Fig. 8 A and Fig. 8 B institute
Show.
Then, as shown in fig. 9 a and fig. 9b, the third layer of contact area Rc1, Rc2 and Rc3 are carried out to (i.e. N with mask TL3
An active layer 213 and an insulating layer 211, N=4 for third step in a step) etching, contact area is located at after etching
The trench region Tc of Rc1, Rc2 and Rc3 are to expose the 4th layer to (213 He of an active layer of the 4th step in i.e. N number of step
One insulating layer 211, N=4) active layer 213.Later, the mask TL3 of three-decker is finely tuned, to form the mask of three-decker
TL4 is the active layer 213 of the 4th step in the trench region Tc for expose contact area Rc1, Rc2, Rc3 and Rc4, is such as schemed
Shown in 10A and Figure 10 B.Then, as seen in figs. 11a and 11b, contact area Rc1, Rc2, Rc3 and Rc4 are carried out with mask TL4
Four layer pair of etching, make in trench region Tc include alternate active layer 213 and insulating layer 211 multilayered structure it is complete
It is removed.
After the completion of all etchings-fine tuning technique, it is one insulant of deposition and fills up trench region Tc, later again with flat
Smooth chemical industry skill such as chemical mechanical grinding (CMP) is formed as shown in Figure 12 A to Figure 12 D with planarizing the upper surface of insulant
Dielectric layer 22.Figure 12 A is the top view (x/y plane) of the part-structure of the 3 D semiconductor element of embodiment, and display, which is located at, to be connect
Touch the dielectric layer 22 of region Rc1-Rc4.Figure 12 B is 3 D semiconductor element depicted in the hatching 12B-12B along Figure 12 A
Diagrammatic cross-section (xz plane).Figure 12 C is 3 D semiconductor element depicted in the hatching 12C-12C along Figure 12 A
Diagrammatic cross-section (xz plane).Figure 12 D cuts open for 3 D semiconductor element depicted in the hatching 12D-12D along Figure 12 A
Face schematic diagram (yz plane).
After forming dielectric layer 22, be carry out contact hole technique be formed simultaneously multilayered structure connector (such as 231,
234) and base connector (such as 241,242,243 and 244) 232,233 and, as shown in Figure 13 A to Figure 13 D.According to Figure 13 B
With Figure 13 D, it is formed in base connector (such as 241,242,243 and of each contact area (such as Rc1, Rc2, Rc3, Rc4)
It 244) is to extend downwardly the bottom being connected to below multilayered structure (active layer 213 and insulating layer 211 that i.e. is staggered)
101.It is formed in multilayered structure connector (such as 231,232,233 and of each contact area (such as Rc1, Rc2, Rc3, Rc4)
234) drop zone of the active layer 213 of each secondary lamination is then connected, as shown in fig. 13 c.Furthermore adjacent multilayered structure connector
(such as 231/232/233/234) and base connector (such as 241/242/243/244) are separated with dielectric layer 21 and 22, such as
Shown in Figure 13 D.It is made that dielectric layer 21 and 22 can be identical or different material.
It is deposition one conductive material (such as metal) and progress patterning step, to form top after the completion of contact hole technique
Portion's conductor (such as 251,252,253 and 254), thus complete adjacent multilayered structure connector (such as 231/232/233/234)
It is connected with the top of base connector (such as 241/242/243/244), as shown in Figure 14 A to Figure 14 D.In first embodiment, respectively
Multilayered structure connector such as 231,232,233 and 234 is electrically to be connected by top conductor 251,252,253 and 254 respectively
It is connected to base connector such as 241,242,243 and 244, as shown in fig. 14d.The CONSTRUCTED SPECIFICATION of related elements be as previously mentioned,
It is no longer repeated for this.
<second embodiment>
Figure 15 is the diagrammatic cross-section of a 3 D semiconductor element of second embodiment of the invention.According to embodiment, respectively
Formed contact area connector be extend downwardly the bottom 101 being connected to below multilayered structure, wherein each connector be with
The multilayered structure connector for connecting the drop zone of the active layer of each secondary lamination is electrically connected.It in a second embodiment, is with rank
Ladder contact, which is linked to for bottom, to be explained, wherein the connector (being connected to the bottom 101 below multilayered structure) that is formed and
Multilayered structure connector is integral part (integral piece).
As shown in figure 15, connector, such as 31,32,33 or 34, it respectively include one first conductive part such as 314,324,334
Or 344 extend downwardly the bottom 101 being connected to below multilayered structure and one second conductive part such as 315,325,335 or 345 and connect
Connect the first conductive part.Second conductive part such as 315,325,335 and 345 is the active layer 213 for being electrically connected corresponding secondary lamination
The drop zone of (being located at the first, second, third and fourth step).In Figure 15, the first conductive part such as 314,324,334 and
344 and second conductive part such as 315,325,335 and 345 be to be respectively formed four single pieces (integral pieces).
According to second embodiment, the second conductive part (such as 315/325/335/345) of connector (such as 31/32/33/34) is
Directly contact the drop zone of the active layer 213 of corresponding secondary lamination.Furthermore the first conductive part (such as 314/324/334/344)
It is to be spaced with these active layers 213 of a dielectric layer Ld and multilayered structure, as shown in figure 15.
In one embodiment, an extending direction of the first conductive part (such as 314/324/334/344) is (i.e. along z-
Direction) substantially perpendicular to an extending direction of the second conductive part (such as 315/325/335/345) (i.e. along x-
direction).In one embodiment, the first conductive part (such as 314/324/334/344) is across multilayered structure and connection multilayer knot
A conductor (route as being located at bottom 101) below structure.
It is the 3 D semiconductor element for proposing the tool bottom contact of one of applicable manufacture second embodiment below
Method.Figure 16 to Figure 25 is painted a kind of manufacturing method of the 3 D semiconductor element of the tool bottom contact of second embodiment.Please
Related elements referring concurrently to Fig. 1 about the 3 D semiconductor element of embodiment.Furthermore have thereon about the substrate of offer 10
A lamination and lamination including multilayered structure include the multiple secondary laminations being formed on substrate 10, and the rank with substrate 10
N number of step of terraced region Rs is corresponding, and to be respectively formed contact area, (content of such as Rc1 to Rc4) related elements is in detail
It is described in first embodiment, details is not repeated herein.Please consider Fig. 3 A and Fig. 3 B in light of actual conditions simultaneously.Figure 16 to Figure 25 be, for example, and edge
The hatching 3B-3B of Fig. 3 A profile angle it is related.Manufacturing step depicted in Figure 16 to Figure 25 is in along such as Fig. 3 A, figure
Step shown in 3B and the trench region Tc that defines is carried out.
Figure 16 and Figure 17 are please referred to, the first patterning program of manufacturing method according to the second embodiment is painted.Such as figure
Shown in 16, it is to form a patterning photoresist PR-1 (or patterning hardmask), simultaneously there are two circular cavities to correspond to
The active layer 213 of second step and the 4th step.Later, a pair of of film layer (one layer of one of step of i.e. N number of step is etched
Active layer 213 and a layer insulating 211), as shown in figure 17, photoresist removal (PR-strip) step is carried out later.Such as Figure 17
Shown, at trench region Tc, the second layer positioned at contact area Rc2 is to (an active layer of second step in i.e. N number of step
213 and an insulating layer 211, N=4) and positioned at the 4th layer of contact area Rc4 to (the one of the 4th step in i.e. N number of step
Active layer 213 and an insulating layer 211, N=4), it is to be etched simultaneously according to patterning photoresist PR-1.It is to be formed in Figure 17
One the 4th bottom contact hole 344h.
Figure 18 and Figure 19 are please referred to, the second patterning program of manufacturing method according to the second embodiment is painted.Such as figure
Shown in 18, it is to form a patterning photoresist PR-2 (or patterning hardmask), simultaneously there are two circular cavities to correspond to
The active layer 213 of second step.Later, two pairs of film layers (two layers of active layer 213 and two of two steps of i.e. N number of step is etched
Layer insulating 211), as shown in figure 19, photoresist removal (PR-strip) step is carried out later.As shown in figure 19, trench region
At Tc, three layers pair positioned at contact area Rc2 and two layers positioned at contact area Rc3 are to removed.It is shape in Figure 19
At one second bottom contact hole 324h and a third bottom contact hole 334h.
0 and Figure 21 referring to figure 2. is painted the third patterning program of manufacturing method according to the second embodiment.Such as figure
Shown in 20, it is to form a patterning photoresist PR-3 (or patterning hardmask), there is a hole to correspond to first
The active layer 213 of step.Then, four pairs of film layers are etched, as shown in figure 21, carry out photoresist removing step later.Such as Figure 21 institute
Show, at trench region Tc, four layers positioned at contact area Rc1 are to removed.It is to form one first bottom contact hole in Figure 21
314h.So far, four bottom contact holes (i.e. 314h, 324h, 334h and 344h) have been formed.
It is that (depositional mode is, for example, with shape to one dielectric of deposition after four bottom contact holes are formed and remove photoresist
At the form of the lining of bottom contact hole) and perform etching to form dielectric layer Ld, as shown in figure 22.In Figure 22, top conductive
Layer (i.e. top active layer 231) is exposed, and the electric connection in subsequent technique is conducive to.
Later, a conductor Lc is deposited, titanium/tungsten (TiN/W) or doped silicon are such as desalinated, and fills the contact of first to fourth bottom
Hole 314h-334h, as shown in figure 23.Then, as shown in figure 24, formed one patterning photoresist PR-4 (or patterning hard
Mask)；The tropisms etching (isotropic etch) such as carry out, later to remove the conductor for not being patterned photoresist PR-4 and covering
Linking portion.After removing patterning photoresist PR-4, then the structure of second embodiment is formed, as shown in figure 25 (with the knot of Figure 15
Structure).In Figure 25 (/ Figure 15), each connector (31/32/33/34) include one first conductive part (314/324/334/344) to
Lower extension is connected to the first conduction of bottom 101 and the connection of one second conductive part (315/325/335/345) below multilayered structure
Portion and contact corresponding secondary lamination active layer 213 drop zone.
The content according to disclosed by above-described embodiment is the 3 D semiconductor element for proposing a kind of contact of tool bottom, can lead to
Cross that neighbouring multilayered structure connector and base connector and the two is arranged is each first is that being electrically connected that (first is real with a top conductor
Apply example), or form the connector (second embodiment) with ladder contact portion and bottom contact portion and realize embodiment.It is real
The bottom contact for applying example can be widely applied to the 3 D semiconductor element of the different kenels of many tools, such as vertical channel formula
The 3 D semiconductor element of (vertical-channel, VC) and vertical gate formula (vertical-gate, VG), multilayered structure
Film layer can be metal (metal gates), semiconductor (polysilicon gate or bit line).Three-dimensional half of the present invention for embodiment
The application kenel of conductor element is not particularly limited.And the memory cell array of said elements and the structure of staircase areas are only
Narration is used, and the present invention is not limited to above-mentioned structure.Therefore, the those skilled in the art of related fields is it is found that above-described embodiment institute
The construction and design of proposition can all do appropriate modification and adjustment according to the actual demand of application.It is proposed according to above-described embodiment
3 D semiconductor element, can be high electro for pursuing with the bottom contact structure of the wider array of embodiment of application structure range
Can and characteristic 3 D semiconductor element, the change and progress of wider scope can be provided, for pursue small size, it is easy to manufacture,
Or for the 3 D semiconductor element of more stable characteristic electron, it is no different and provides more structure possibilities.Furthermore implement
The 3 D semiconductor element of example is still suitble to volume production using non-time-consuming also inexpensive technique in production.
In conclusion although the present invention has been disclosed by way of example above, it is not intended to limit the present invention..Institute of the present invention
Belong in technical field and have usually intellectual, without departing from the spirit and scope of the present invention, when various change and profit can be made
Decorations.Therefore, subject to protection scope of the present invention ought be defined depending on appended claims range.
Claims (8)
1. a kind of 3 D semiconductor element, comprising:
One substrate has the staircase areas including N number of step, and wherein N is the integer more than or equal to 1；
There is one lamination multilayered structure to be stacked and placed on the substrate, and the multilayered structure includes that active layer and insulating layer crisscross the base
On plate, which includes that multiple secondary laminations are formed on the substrate, these secondary laminations are corresponding with N number of step of the staircase areas
It is arranged to be respectively formed contact area；With
Multiple connectors are located at these corresponding contact areas, and these connectors are to extend downwardly to be connected to the multilayer
A bottom below structure；
Wherein, respectively the connector includes:
One first conductive part extends downwardly the bottom being connected to below the multilayered structure；With
One second conductive part connects first conductive part, second conductive part be electrically connected the corresponding secondary lamination this is active
The drop zone of layer.
2. 3 D semiconductor element according to claim 1, wherein first conductive part is with a dielectric layer and the multilayer
These active layers of structure are spaced.
3. 3 D semiconductor element according to claim 1, wherein the one of first conductive part extends perpendicularly to this
One extending direction of the second conductive part.
4. 3 D semiconductor element according to claim 1, wherein second conductive part of the connector is directly to contact
The drop zone of the active layer of the corresponding secondary lamination.
5. 3 D semiconductor element according to claim 1, wherein at least one of these connectors are electrically connected to this
A route below multilayered structure.
6. a kind of manufacturing method of 3 D semiconductor element, comprising:
A substrate is provided, which has the staircase areas including N number of step, and wherein N is the integer more than or equal to 1；
It forms with multi-layer structure one to be stacked on the substrate, and the multilayered structure includes that active layer interlocks with insulating layer, it should
Lamination includes that multiple secondary laminations are formed on the substrate, N number of step of these secondary laminations and the staircase areas be correspondingly arranged with
It is respectively formed contact area；With
It forms multiple connectors and is located at these corresponding contact areas, and these connectors are to extend downwardly that be connected to this more
A bottom below layer structure；
Wherein, in the step of forming these connectors, respectively the connector includes:
One first conductive part extends downwardly the bottom being connected to below the multilayered structure；With
One second conductive part connects first conductive part, second conductive part be electrically connected the corresponding secondary lamination this is active
The drop zone of layer.
7. manufacturing method according to claim 6, wherein the one of first conductive part extends perpendicularly to this and second leads
One extending direction in electric portion.
8. manufacturing method according to claim 6, further includes:
A dielectric layer is formed, first conductive part and these active layers of the multilayered structure are separated,
Wherein second conductive part of the connector is formed above first conductive part, and the second conductive part directly contacts correspondence
The secondary lamination the active layer the drop zone.
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