CN203760476U - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN203760476U CN203760476U CN201420083487.XU CN201420083487U CN203760476U CN 203760476 U CN203760476 U CN 203760476U CN 201420083487 U CN201420083487 U CN 201420083487U CN 203760476 U CN203760476 U CN 203760476U
- Authority
- CN
- China
- Prior art keywords
- channel
- vertical
- cell
- semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 100
- 239000004020 conductor Substances 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000011229 interlayer Substances 0.000 claims description 58
- 230000015654 memory Effects 0.000 claims description 38
- 230000004888 barrier function Effects 0.000 claims description 29
- 239000010410 layer Substances 0.000 description 48
- 238000000034 method Methods 0.000 description 16
- 238000000151 deposition Methods 0.000 description 14
- 238000005530 etching Methods 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000011049 filling Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000003475 lamination Methods 0.000 description 7
- 238000003860 storage Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000004380 ashing Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 244000287680 Garcinia dulcis Species 0.000 description 1
- -1 HfSiN Inorganic materials 0.000 description 1
- 229910003217 Ni3Si Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 150000004645 aluminates Chemical class 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007514 turning Methods 0.000 description 1
Abstract
A semiconductor device is disclosed and comprises a plurality of device units that are stacked, wherein each device unit comprises a corresponding grid electrode conductor; the plurality of device units comprise a common intermediate dielectric layer, common vertical channels and a common core part insulating layer; the core part insulating layer is surrounded by the vertical channels, the grid electrode conductors are separated from the vertical channels through the intermediate dielectric layer, the topmost device unit of the plurality of device units also comprises a drain region adjacent to the vertical channels, the bottommost device unit of the plurality of device units also comprises a source region and a horizontal channel that are positioned in a semiconductor substrate, the horizontal channel is connected with the source region and the vertical channels, and the drain region is positioned above the vertical channels and the core part insulating layer. Contact parts between the drain region and electric conduction passageways are large in area, and therefore effects of contact resistors and positioning mismatch can be reduced; device performance improvement and yield rate improvement are realized.
Description
Technical field
The utility model relates to semiconductor technology, more specifically, relates to the semiconductor device of three-dimensional structure.
Background technology
In recent years, owing to can improving exponentially integrated level, reducing chip area footprints and reduce costs, the semiconductor device of three-dimensional structure has caused widely to be paid close attention to.Especially in memory area, the progress of semiconductor fabrication process causes the characteristic size of semiconductor device more and more less, and result is more and more difficult by improving semiconductor fabrication process raising storage density.The memory of three-dimensional structure becomes the key that improves storage density.
Planar semiconductor device can be stacked into many levels, insulating barrier be set between adjacent aspect and provide interconnection to realize simple three-dimensional structure.The storage density of this three-dimensional storage can improve pro rata with aspect number.Or, can further memory cell self also be changed into vertical devices from planar device, this has reduced the chip area footprints of each memory cell, thereby further improves the storage density of memory.
NAND and NOR are two kinds of main non-volatile flash technology in the market.The write operation of flash memory can only be carried out in unit empty or that wiped.It is simple that nand flash memory is carried out erase operation, and NOR flash memory requires first positions all in object block to be all written as to 0 before wiping.Enable nand gate can be realized less memory cell, thereby reaches higher storage density.Nand flash memory and the NOR flash memory of three-dimensional structure are disclosed.
The memory of three-dimensional structure generally includes public vertical-channel.Vertical-channel may be introduced additional contact resistance with being electrically connected to of adjacent part, and this causes the conducting resistance of memory isoparametric deteriorated.Further, if vertical-channel and adjacent part mispairing will cause the memory completely can not normal running.
Still expectation further improves reliability and the performance of the semiconductor device of three-dimensional structure.
Utility model content
The purpose of this utility model is to provide three-dimensional semiconductor device and the manufacture method thereof of a kind of high reliability and performance.
According to one side of the present utility model, a kind of semiconductor device is provided, comprise stacking a plurality of device cells, on stacking direction, the adjacent devices unit of described a plurality of device cells is separated by interlayer insulating film, and each device cell comprises corresponding grid conductor, described a plurality of device cell comprises public interlayer dielectric, public vertical-channel and public core insulating barrier, described vertical-channel is around described core insulating barrier, between described grid conductor and described vertical-channel, by described interlayer dielectric, separated, device cell of top in described a plurality of device cell also comprises the drain region with described vertical-channel adjacency, and device cell of the bottommost in described a plurality of device cell comprises and also comprises source region and the horizontal channel that is arranged in Semiconductor substrate, described horizontal channel connects described source region and described vertical-channel, wherein, described drain region is positioned at the two top of described vertical-channel and described core insulating barrier.
Preferably, in described semiconductor device, the neighboring in described drain region and the neighboring of described vertical-channel are self aligned.
Preferably, in described semiconductor device, described vertical-channel extends in described Semiconductor substrate, and all parts that vertical-channel extends to the upper surface below of described Semiconductor substrate contact described Semiconductor substrate.
Preferably, in described semiconductor device, described a plurality of device cell is divided into stacking many levels, a plurality of device cells of each aspect are pressed row and column and are arranged, and the device cell that is positioned at same row comprises public grid conductor, and by another insulating barrier, is separated between the grid conductor of the device cell of adjacent column.
Preferably, in described semiconductor device, described semiconductor device is nand memory, and at least some device cells in described a plurality of device cell form actual memory cell string, and at least other device cell in described a plurality of device cells forms false memory cell string.
Semiconductor device according to the invention, drain region is positioned at the two top of vertical-channel and core insulating barrier.This drain region is by the conductive channel adjacency with top.The situation that is only positioned at vertical-channel top with drain region is compared, this drain region provide and conductive channel between larger contact area, thereby reduced contact resistance.Even if exist location mispairing to a certain degree between this drain region and conductive channel, also still can guarantee good electrically contacting.
In a preferred embodiment, the neighboring of the vertical-channel of drain region and below is self aligned, thereby semiconductor device of the present invention can further improve process margin.
In a preferred embodiment, vertical-channel extends in this Semiconductor substrate, and this vertical-channel extends to all part contact semiconductor substrates of the upper surface below of Semiconductor substrate.Therefore, horizontal channel will be directly in abutting connection with vertical-channel, forms the shortest channel path.Horizontal channel and vertical-channel itself not only, and both turnings of being connected, all can be subject at work the control of grid conductor, thereby be conducive to reduce threshold voltage and power consumption, improved device performance.
Accompanying drawing explanation
By the description to the utility model embodiment referring to accompanying drawing, above-mentioned and other objects of the present utility model, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1 a and 1b show respectively according to the perspective view of the semiconductor device of an embodiment of the present utility model and vertical view;
Fig. 2-12 show respectively according to the sectional view in each stage of the manufacture method of the semiconductor device of an embodiment of the present utility model, wherein Fig. 2 a-12a illustrates along the vertical cross-section diagram of a direction, and Fig. 2 b-12b illustrates the vertical cross-section diagram along another direction.
Figure 13 shows according to the sectional view in a part of stage of another manufacture method of the semiconductor device of an embodiment of the present utility model, and wherein Figure 13 a illustrates along the vertical cross-section diagram of a direction, and Figure 13 b illustrates the vertical cross-section diagram along another direction.
Embodiment
Hereinafter with reference to accompanying drawing, the utility model is described in more detail.In each accompanying drawing, identical element adopts similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.In addition, may not shown some known part.For brevity, the semiconductor structure obtaining can be described in a width figure after several steps.
Be to be understood that, when the structure of outlines device, when one deck, region are called be positioned at another layer, another region " above " or when " top ", can refer to be located immediately at another layer, another is above region, or its and another layer, also comprise between another region other layer or region.And if by device upset, this one deck, a region will be positioned at another layer, another region " below " or " below ".
If be located immediately at another layer, another situation above region in order to describe, will adopt herein " directly exist ... above " or " ... above and with it in abutting connection with " form of presentation.
In this application, term " semiconductor structure " refers to the general designation of the whole semiconductor structure that forms in manufacturing each step of semiconductor device, comprises all layers or the region that have formed.Described hereinafter many specific details of the present utility model, for example structure of device, material, size, treatment process and technology, to more clearly understand the utility model.But just as the skilled person will understand, can realize the utility model not according to these specific details.
Unless particularly pointed out hereinafter, the various piece of semiconductor device can consist of the known material of those skilled in the art.Semi-conducting material for example comprises III-V family semiconductor, as GaAs, InP, GaN, SiC, and IV family semiconductor, as Si, Ge.Grid conductor can be formed by the various materials that can conduct electricity, for example metal level, doped polysilicon layer or comprise metal level and the stacked gate conductor of doped polysilicon layer or other electric conducting materials, for example, be the combination of TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W and described various electric conducting materials.The material that gate-dielectric can be greater than SiO2 by SiO2 or dielectric constant forms, for example, comprise oxide, nitride, oxynitride, silicate, aluminate, titanate.And gate-dielectric not only can be formed by the known material of those skilled in the art, also can adopt the material for gate-dielectric of exploitation in the future.
The utility model can present by various forms, below will describe some of them example.
With reference to Fig. 1 a and 1b, describe according to the schematic structure of the semiconductor device of an embodiment of the present utility model, wherein, the perspective view of semiconductor device has been shown in Fig. 1 a, the vertical view of semiconductor device has been shown in Fig. 1 b.In Fig. 1 b, also show the interception position of vertical cross-section diagram subsequently, wherein Fig. 2 a-12a is the vertical cross-section diagram along the line A-A intercepting through a line device cell, and Fig. 2 b-12b and 9c are the vertical cross-section diagrams along the line B-B intercepting through a row device cell.In addition, the wave in Fig. 2 b-12b and 9c represents only to illustrate a part for equivalent layer.
As shown in Fig. 1 a and 1b, semiconductor device 1000 comprises the device cell of 8 aspects, and each aspect comprises 3 row * 3 row device cell, altogether 72 device cells.In an example, semiconductor device 1000 is nand memories, and the device cell of top is string select transistor, and the device cell of bottommost is that ground connection is selected transistor, and the device cell of middle 6 aspects is memory cell, altogether 54 memory cell.6 memory cell of each group vertical stacking form a memory cell string, altogether 9 memory cell strings.Between the device cell of adjacent column, by interlayer insulating film 210, separated.Semiconductor device 1000 can comprise more or less aspect, row, column and device cell.For the sake of clarity, interlayer insulating film 130, the grid conductor 140 of the device cell in Fig. 1 a, the leftmost side one being listed as, and public interlayer dielectric 160, interlayer insulating film 210 decomposition of all device cells illustrate.
Particularly, semiconductor device 1000 comprises Semiconductor substrate 110.Semiconductor substrate 110 is for example silicon substrate.In an example, in Semiconductor substrate 110, form the first doped region 120 of N-type or P type.At semiconductor device 1000, be under the situation of nand memory, transistorized source region is selected as ground connection in the first doped region 120.
Interlayer insulating film 130 is positioned at Semiconductor substrate 110 tops, separates the grid conductor 140 in different aspects.In interlayer insulating film 130 and grid conductor 140, form a plurality of openings, hold respectively for example columned vertical-channel 150.Vertical-channel 150 is for example the surperficial semiconductor layer being positioned on core insulating barrier.Above vertical-channel 150 and core insulating barrier, form the second doped region 121.The top of vertical-channel 150 and the second doped region 121 adjacency, bottom extends in Semiconductor substrate 110, and spaced apart with the first doped region 120.Horizontal channel (not shown) in Semiconductor substrate 110 connects the first doped region 120 and vertical-channel 150.Interlayer dielectric 160 is between vertical-channel 150 and grid conductor 140.At semiconductor device 1000, be under the situation of nand memory, the second doped region 121 is as the drain region of string select transistor, interlayer dielectric 160 is the laminations that comprise tunneling medium layer, electric charge capture layer and barrier layer, for storing the electric charge that represents value data, interlayer dielectric 160 is also selected transistorized gate-dielectric as string select transistor and ground connection.Although as shown in the figure, interlayer dielectric 160 conformally covers on the surface of interlayer insulating film 130 and the exposed surface of vertical-channel 150, yet this is also nonessential.In alternative embodiment, interlayer dielectric 160 can partly between grid conductor 140 and vertical-channel 150, for example, not cover the surface of interlayer insulating film 130.
At cell array region 1000a(as shown in Figure 1 b), the second doped region 121 is connected with first group of wire 170 via conductive channel (via) 190.Conductive channel 190 is for example formed in the access opening (via hole) in interlayer insulating film 210.At contact area 1000b(as shown in Figure 1 b), vertical-channel 150 is not connected with external circuit, and instead, the grid conductor 140 of each aspect is connected with in second group of wire 180 one via conductive channel 200 respectively.Conductive channel 200 is for example formed in the access opening in interlayer insulating film 210.Therefore, the vertical-channel 150 in contact area 1000b and core insulating barrier 151 are as just support column.It should be noted that for clarity sake, Fig. 1 a with in 1b, only gone out the wire being connected with the grid conductor 140 of the device cell of three aspects in top, and the wire that the grid conductor 140 of the device cell of not shown bottom five aspects is connected.
In alternative embodiment, in contact area 1000b, do not form vertical-channel 150 and core insulating barrier 151 as support column, but self provide mechanical support by interlayer insulating film 130 and the grid conductor 140 of every aspect.
At semiconductor device 1000, be under the situation of nand memory, first group of wire 170 be as the bit line BL of memory, and second group of wire 180 comprises that the string being connected with the grid conductor 140 of the string select transistor of top selects line SSL, a ground connection selection line GSL who is connected with the grid conductor 140 of the grounding transistor of bottommost and 6 word line WL that are connected respectively with the grid conductor 140 of memory cell.In cell array region 1000a, grid conductor 140, interlayer dielectric 160 have formed memory cell string and have selected transistor together with vertical-channel 150, and in contact area 1000b, grid conductor 140, interlayer dielectric 160 and vertical-channel 150 have formed false memory cell string and the false transistor of selecting, as support column.In alternative embodiment, can adopt independently support column to replace vertical-channel 150 and the core insulating barrier 151 in contact area 1000b.
With reference to Fig. 2-12, describe according to each stage of the manufacture method of the semiconductor device of an embodiment of the present utility model.
As shown in Fig. 2 a and 2b, in Semiconductor substrate 110, form sacrifice layer 111, then form interlayer insulating film 130, further repeat to form the step of sacrifice layer 111 and interlayer insulating film 130, thereby form the lamination of sacrifice layer 111 and interlayer insulating film 130.Sacrifice layer 111 can be comprised of the material with respect to Semiconductor substrate 110 and interlayer insulating film 130 selective removals.For example, Semiconductor substrate 110 is comprised of Si, and interlayer insulating film 130 is comprised of SiO2, and sacrifice layer 111 is comprised of SiGe.
In order to form the device cell of 8 aspects, this lamination should comprise at least 8 sacrifice layers 111.Form sacrifice layer 110 and interlayer insulating film 130 and can adopt known depositing operation, as electron beam evaporation (EBM), chemical vapor deposition (CVD), ald (ALD), sputter etc.
Further, for example, on the surface of semiconductor structure, form photoresist mask, then carry out etching, by the lamination patterning of sacrifice layer 111 and interlayer insulating film 130 to form a plurality of openings 131.This etching can adopt dry etching, as ion beam milling etching, plasma etching, reactive ion etching, laser ablation, or by using the optionally wet etching of etchant solutions, etching that Open Side Down from photoresist mask is through all sacrifice layers 111 and interlayer insulating film 130, and further a part for etching semiconductor substrate 110, stops until reaching the desired depth of Semiconductor substrate 110 upper surface belows.After etching, by dissolving or ashing in solvent, remove photoresist mask, as shown in Fig. 3 a and 3b.
Further, by above-mentioned known depositing operation, in sidewall and the bottom of opening 131, form vertical-channel 150, and further deposit core insulating barrier 151 with complete filling opening, as shown in Figs. 4a and 4b.Vertical-channel 150 extends to all part contact semiconductor substrates 110 of the upper surface below of Semiconductor substrate 110.Form vertical-channel 150 and can comprise that the above-mentioned known depositing operation of employing forms conforma layer in sidewall and the bottom of opening 131, make the remaining space of opening 131 be formed for holding the opening of core insulating barrier 151, or alternatively comprise and adopt the complete filling opening 131 of above-mentioned known depositing operation, be then etched with the opening that is formed for holding core insulating barrier 151.For example, vertical-channel 150 is comprised of Si, and core insulating barrier 151 is comprised of SiO2.
Further, for example, pass through optionally wet etching, etch-back vertical-channel 150 and core insulating barrier 151, form self aligned another opening in neighboring with vertical-channel.By above-mentioned known depositing operation, on the surface of semiconductor structure, form semiconductor layer, and further carry out complanation (for example chemico-mechanical polishing), to remove the part being positioned at outside described another opening, and obtain even curface.A part that retains semiconductor layer 156 in described another opening, as shown in Fig. 5 a and 5b.The neighboring of the neighboring of semiconductor layer 156 and vertical-channel 150 is self aligned, and can be comprised of identical or different semi-conducting material.For example, the semi-conducting material adulterating by Direct precipitation, or deposition unadulterated semi-conducting material after (just as will be described) adopt additional Implantation to adulterate, can form the semiconductor layer 156 of doping.
Further, for example on the surface of semiconductor structure, form photoresist mask, then by above-mentioned etch process, by the lamination patterning of sacrifice layer 111 and interlayer insulating film 130 to be formed for separating the groove 152 of device cell of adjacent column of the semiconductor device 1000 of final formation.Then, via groove 152, further adopt optionally etch process, with respect to vertical-channel 150, interlayer insulating film 152 and Semiconductor substrate 110, remove sacrifice layer 111 completely, to form the opening 153 that extends laterally to vertical-channel 150.After etching, by dissolving or ashing in solvent, remove photoresist mask.Groove 152 exposes the part surface of vertical-channel 150 and interlayer insulating film 130 together with opening 153, as shown in Fig. 6 a and 6b.
In above-mentioned step, after removing sacrifice layer 111, interlayer insulating film 130 is unsettled.At cell array region 1000a, the vertical-channel 150 of column and core insulating barrier 151 are together for interlayer insulating film 130 provides mechanical support.In contact area 1000b, the vertical-channel 150 of column and core insulating barrier 151 are also together for interlayer insulating film 130 provides mechanical support.In alternative embodiment, in contact area 1000b, do not form vertical-channel 150 and core insulating barrier 151 as support column, but self provide mechanical support by the interlayer insulating film 130 of every aspect.
Further, by isotropic depositing operation, via groove 152 and opening 153, on the exposed surface of vertical-channel 150 and interlayer insulating film 130, form conformal interlayer dielectric 160, as shown in Fig. 7 a and 7b.Meanwhile, this interlayer dielectric 160 has covered the top surface of semiconductor structure.Although in the drawings interlayer dielectric 160 is depicted as to individual layer, in fact interlayer dielectric 160 can be the conformal lamination forming through Multiple depositions.As mentioned above, at semiconductor device 1000, be under the situation of nand memory, interlayer dielectric 160 is the laminations that comprise tunneling medium layer, electric charge capture layer and barrier layer, for storing the electric charge that represents value data, interlayer dielectric 160 is also selected transistorized gate-dielectric as string select transistor and ground connection.
Further, by isotropic depositing operation, via groove 152, form the grid conductor 140 of filling opening 153.Form grid conductor 140 and can comprise that the above-mentioned known depositing operation of employing forms conforma layer in sidewall and the bottom of opening 153, the thickness of this conforma layer is enough to filling opening 153, and be not enough to filling groove 152, or alternatively can comprise and adopt the complete filling opening 153 of above-mentioned isotropic depositing operation and groove 152, then adopt anisotropic etch process to be etched with and again form groove 152, as shown in Fig. 8 a and 8b.
Further, via groove 152, carry out Implantation, in Semiconductor substrate 110, form the first doped region 120 of N-type (using N-type dopant, for example P, As) or P type (using P type dopant, for example B).Meanwhile, dopant also enters in semiconductor layer 156 through the top surface of interlayer dielectric 160, semiconductor layer 156 is transformed into second doped region 121 identical with the conduction type of the first doped region 120, as shown in Fig. 9 a and 9b.The top of vertical-channel 150 and the second doped region 121 adjacency, bottom extends in Semiconductor substrate 110, and spaced apart with the first doped region 120 levels.Horizontal channel (not shown) in Semiconductor substrate 110 connects the first doped region 120 and vertical-channel 150.At semiconductor device 1000, be under the situation of nand memory, transistorized source region is selected as ground connection in the first doped region 120, and the second doped region 121 is as the drain region of string select transistor.
Further, for example on the surface of semiconductor structure, form photoresist mask, then in contact area 1000b, carry out etching, for example optionally remove the part that the one deck of top in interlayer insulating film 130 is not blocked by photoresist mask, and the appropriate section of interlayer dielectric 160, thereby the grid conductor 140 below exposing.After etching, by dissolving or ashing in solvent, remove photoresist mask.Then, repeat to form the step of photoresist mask, selective etch and removal photoresist mask, in contact area 1000b, successively expose the grid conductor 140 of each aspect downwards, as shown in Figure 10 a and 10b.When each etching, block all grid conductors 140 on upper strata completely, and expose a part for the grid conductor 140 of next aspect of next-door neighbour, the grid conductor 140 of final structure at all levels is step-like, and the grid conductor 140 of each aspect forms one-level step.In this etching step, not only expose the grid conductor 140 of each layer, also the part that vertical-channel 150 and core insulating barrier 151 are positioned at corresponding grid conductor 140 tops has been removed in etching.
Then, by above-mentioned known depositing operation, on the surface of semiconductor structure, form interlayer insulating film 210, and further carry out complanation (for example chemico-mechanical polishing), to obtain even curface, as shown in Figure 11 a and 11b.Interlayer insulating film 210 filling grooves 152, and separate the device cell of adjacent column of the semiconductor device 1000 of final formation.At cell array region 1000a, interlayer insulating film 210 covers the top surface of interlayer dielectric 160.In contact area 1000b, interlayer insulating film 210 covers the exposed surface of step-like grid conductor 140.
Further, for example on the surface of semiconductor structure, form photoresist mask, by above-mentioned etch process, in cell array region 1000a, interlayer insulating film 210 and interlayer dielectric 160 patternings are arrived to the access opening of the second doped region 121 with formation, in contact area 1000b, insulating barrier 201 patternings are arrived to the access opening of grid conductor 140 with formation.
Then, by above-mentioned known depositing operation, form conductor layer, this conductor layer is filling channel hole at least.Using interlayer insulating film 210 as stop-layer, carry out complanation (for example chemico-mechanical polishing), remove the part that conductor layer is positioned at access opening outside, in cell array region 1000a, form conductive channel 190, in contact area 1000b, form conductive channel 200.
Then, by above-mentioned known depositing operation, on interlayer insulating film 210, again form conductor layer, conductor layer is patterned to first group of wire 170 and second group of wire 180, as shown in Figure 12 a and 12b.First group of wire 170 is arranged in cell array region 1000a, contacts with conductive channel 190.Second group of wire 180 is arranged in contact area 1000b, contacts with conductive channel 200.As previously mentioned, at semiconductor device 1000, be under the situation of nand memory, first group of wire 170 be as the bit line BL of memory, and second group of wire 180 comprises that the string being connected with the grid conductor 140 of the string select transistor of top selects line SSL, a ground connection selection line GSL who is connected with the grid conductor 140 of the grounding transistor of bottommost and 6 word line WL that are connected respectively with the grid conductor 140 of memory cell.
With reference to Figure 13, describe according to the sectional view in a part of stage of another manufacture method of the semiconductor device of an embodiment of the present utility model.
After the step shown in Fig. 2-3, replace the step shown in Fig. 4, in the opening 131 of cell array region 1000a, the pillared vertical-channel 150 of shape and core insulating barrier 151 form additional support column 154, as shown in figure 13 in the opening 131 of contact area 1000b.The later step of the method is identical with the step shown in Fig. 5-12.
In the step shown in Fig. 4, vertical-channel 150 and core insulating barrier 151 are as support column.Different with it, in the step shown in Figure 13, formed independently support column 154, therefore can be for the required mechanical support demand of contact area 1000b, for support column 154 is selected suitable material and layout.
In above description, for ins and outs such as the composition of each layer, etchings, be not described in detail.Can be by various technological means but it will be appreciated by those skilled in the art that, form layer, region of required form etc.In addition, in order to form same structure, those skilled in the art can also design and the not identical method of method described above.In addition, although describing respectively above each embodiment, this and the measure in each embodiment that do not mean that can not advantageously be combined with.
Above embodiment of the present utility model is described.But these embodiment are only used to the object of explanation, and are not intended to limit scope of the present utility model.Scope of the present utility model is limited by claims and equivalent thereof.Do not depart from scope of the present utility model, those skilled in the art can make multiple substituting and modification, within these substitute and revise and all should drop on scope of the present utility model.
Claims (5)
1. a semiconductor device, comprises stacking a plurality of device cells, and on stacking direction, the adjacent devices unit of described a plurality of device cells is separated by interlayer insulating film, and each device cell comprises corresponding grid conductor,
Described a plurality of device cell comprises public interlayer dielectric, public vertical-channel and public core insulating barrier, and described vertical-channel, around described core insulating barrier, is separated by described interlayer dielectric between described grid conductor and described vertical-channel,
Device cell of top in described a plurality of device cell also comprises the drain region with described vertical-channel adjacency, and
Device cell of bottommost in described a plurality of device cell comprises and also comprises source region and the horizontal channel that is arranged in Semiconductor substrate, and described horizontal channel connects described source region and described vertical-channel,
It is characterized in that, described drain region is positioned at the two top of described vertical-channel and described core insulating barrier.
2. semiconductor device according to claim 1, is characterized in that, the neighboring in described drain region and the neighboring of described vertical-channel are self aligned.
3. semiconductor device according to claim 1, is characterized in that, described vertical-channel extends in described Semiconductor substrate, and all parts that vertical-channel extends to the upper surface below of described Semiconductor substrate contact described Semiconductor substrate.
4. according to semiconductor device in any one of the preceding claims wherein, it is characterized in that, described a plurality of device cell is divided into stacking many levels, a plurality of device cells of each aspect are pressed row and column and are arranged, and the device cell that is positioned at same row comprises public grid conductor, and by another insulating barrier, is separated between the grid conductor of the device cell of adjacent column.
5. semiconductor device according to claim 1, it is characterized in that, described semiconductor device is nand memory, and at least some device cells in described a plurality of device cell form actual memory cell string, at least other device cell in described a plurality of device cells forms false memory cell string.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420083487.XU CN203760476U (en) | 2014-02-26 | 2014-02-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420083487.XU CN203760476U (en) | 2014-02-26 | 2014-02-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203760476U true CN203760476U (en) | 2014-08-06 |
Family
ID=51255719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420083487.XU Expired - Lifetime CN203760476U (en) | 2014-02-26 | 2014-02-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203760476U (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015070817A1 (en) * | 2013-11-18 | 2015-05-21 | ZONG, Tang | Semiconductor device and method for manufacturing the same |
| CN105826324A (en) * | 2015-01-06 | 2016-08-03 | 旺宏电子股份有限公司 | Three-dimensional semiconductor component and manufacturing method thereof |
| TWI557849B (en) * | 2014-11-19 | 2016-11-11 | 旺宏電子股份有限公司 | Vertical and 3d memory devices and methods of manufacturing the same |
| CN108140644A (en) * | 2015-11-25 | 2018-06-08 | 桑迪士克科技有限责任公司 | For replacing opening in the array of three dimensional memory device |
| TWI696274B (en) * | 2018-05-22 | 2020-06-11 | 旺宏電子股份有限公司 | Pitch scalable 3d nand memory |
| CN112567516A (en) * | 2018-07-12 | 2021-03-26 | 日升存储公司 | Method for manufacturing three-dimensional NOR memory array |
| US11937424B2 (en) | 2020-08-31 | 2024-03-19 | Sunrise Memory Corporation | Thin-film storage transistors in a 3-dimensional array of nor memory strings and process for fabricating the same |
-
2014
- 2014-02-26 CN CN201420083487.XU patent/CN203760476U/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015070817A1 (en) * | 2013-11-18 | 2015-05-21 | ZONG, Tang | Semiconductor device and method for manufacturing the same |
| TWI557849B (en) * | 2014-11-19 | 2016-11-11 | 旺宏電子股份有限公司 | Vertical and 3d memory devices and methods of manufacturing the same |
| CN105826324A (en) * | 2015-01-06 | 2016-08-03 | 旺宏电子股份有限公司 | Three-dimensional semiconductor component and manufacturing method thereof |
| CN105826324B (en) * | 2015-01-06 | 2019-03-29 | 旺宏电子股份有限公司 | 3 D semiconductor element and its manufacturing method |
| CN108140644A (en) * | 2015-11-25 | 2018-06-08 | 桑迪士克科技有限责任公司 | For replacing opening in the array of three dimensional memory device |
| TWI696274B (en) * | 2018-05-22 | 2020-06-11 | 旺宏電子股份有限公司 | Pitch scalable 3d nand memory |
| US10840254B2 (en) | 2018-05-22 | 2020-11-17 | Macronix International Co., Ltd. | Pitch scalable 3D NAND |
| CN112567516A (en) * | 2018-07-12 | 2021-03-26 | 日升存储公司 | Method for manufacturing three-dimensional NOR memory array |
| US11937424B2 (en) | 2020-08-31 | 2024-03-19 | Sunrise Memory Corporation | Thin-film storage transistors in a 3-dimensional array of nor memory strings and process for fabricating the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203760476U (en) | Semiconductor device | |
| CN103594475A (en) | Semiconductor device and manufacturing method thereof | |
| US10418374B2 (en) | Vertical memory devices | |
| US11121149B2 (en) | Three-dimensional memory device containing direct contact drain-select-level semiconductor channel portions and methods of making the same | |
| CN106024794B (en) | Semiconductor device and method for manufacturing the same | |
| US11309332B2 (en) | Three-dimensional memory device containing ferroelectric memory elements encapsulated by transition metal-containing conductive elements and method of making thereof | |
| KR102298605B1 (en) | Vertical memory devices and methods of manufacturing the same | |
| KR102190350B1 (en) | Semiconductor Memory Device And Method of Fabricating The Same | |
| US10347647B1 (en) | Three-dimensional memory device containing multi-threshold-voltage drain select gates and method of making the same | |
| US10211257B2 (en) | High density resistive random access memory (RRAM) | |
| US20200020715A1 (en) | Three-dimensional memory device having a slimmed aluminum oxide blocking dielectric and method of making same | |
| US9543307B2 (en) | Vertical memory devices and methods of manufacturing the same | |
| CN109192735B (en) | 3D memory device and method of manufacturing the same | |
| CN113224079B (en) | 3D memory device and method of manufacturing the same | |
| CN110289259B (en) | 3D memory device and method of manufacturing the same | |
| CN110379812B (en) | 3D memory device and method of manufacturing the same | |
| CN110808254B (en) | 3D memory device and method of manufacturing the same | |
| CN110943089B (en) | 3D memory device and method of manufacturing the same | |
| US11335790B2 (en) | Ferroelectric memory devices with dual dielectric confinement and methods of forming the same | |
| CN203521410U (en) | Semiconductor device | |
| US20210375917A1 (en) | 3d memory with graphite conductive strips | |
| KR20210118411A (en) | 3D memory device and manufacturing method thereof | |
| CN115884592A (en) | Semiconductor device with a plurality of transistors | |
| CN111370418B (en) | Method for manufacturing 3D memory device | |
| US11393836B2 (en) | Three-dimensional memory device with separated source-side lines and method of making the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140806 |
|
| CX01 | Expiry of patent term |