CN105826324A - Three-dimensional semiconductor component and manufacturing method thereof - Google Patents
Three-dimensional semiconductor component and manufacturing method thereof Download PDFInfo
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- CN105826324A CN105826324A CN201510004402.3A CN201510004402A CN105826324A CN 105826324 A CN105826324 A CN 105826324A CN 201510004402 A CN201510004402 A CN 201510004402A CN 105826324 A CN105826324 A CN 105826324A
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Abstract
The invention discloses a three-dimensional semiconductor component and a manufacturing method thereof. The three-dimensional semiconductor component comprises a substrate, a stack, and multiple connectors. The substrate has a staircase region including N steps, wherein N is an integer greater than or equal to 1. The stack is of a multi-layer structure and is superimposed on the substrate, the multi-layer structure includes active layers and insulating layers which are arranged on the substrate in a staggered manner, the stack includes multiple sub-stacks formed on the substrate, and the sub-stacks correspond to the N steps of the staircase region to form contact regions. The multiple connectors are respectively disposed in the corresponding contact regions, and the connectors extend downward and are connected to a bottom layer under the multi-layer structure.
Description
Technical field
The invention relates to a kind of three-dimensional (three-dimensional, 3D) semiconductor element and manufacture method thereof, and in particular to contacting 3 D semiconductor element and the manufacture method thereof of (bottomcontacts) bottom one tool.
Background technology
Non-volatile memory device has a characteristic the biggest to be to remain to preserve the integrity of data mode after memory component loses or remove power supply in design.The non-volatile memory device of the existing many different kenels of industry is suggested at present.But relevant dealer the most constantly researches and develops new design or combines prior art, carries out the lamination of the memory plane containing memory element to reach the memory construction with more high storage capacity.NAND gate (NAND) the type flash memory structure such as having some plural layers transistor stack is suggested.Relevant dealer has been proposed that the three-dimensional storage element of various different structure, the three-dimensional storage elements such as the such as memory element of tool list grid (Single-Gate), the memory element of bigrid (doublegate), and the memory element of circulating type grid (surroundinggate).
Relevant design person is without undesirably constructing a three-dimensional memory structure, not only there is many layer laminate planes (memory layer) and reach higher storage volume, have more the characteristic electron (such as there are good data and preserve reliability and speed of operation) of excellence, make the memory construction can be by stable and the most such as carry out wiping and the operation such as programming.It is said that in general, the page of NAND-type flash memory (Page) size is proportional to number of bit.Therefore reducing when component size, be not only cost and reduce, the increase of its operation repetitive also improves the read or write speed of element, and then reaches higher data transmission bauds.But, when reducing component size, still there are many other problemses to need to consider.
As a example by general three-dimensional perpendicular channel-type memory component (ex:NAND), spacing (X-pitch) in multiple structure adapter (multilayeredconnectors) the most such as X-direction may utilize wide staircase rule (widestaircaserule) and loosens, but the spacing in such as Y-direction (Y-pitch) can become the most intensive to link multiple structure adapter to word-line decoder on other direction.Although expanding Y-direction region (block_Y) Y-direction spacing can be relaxed, but serial selection line (stringselectionline, SSL) number will increase, and causes more problem disturbing (signaldisturbance) such as power attenuation (powerconsumption) and signal.In view of the situation of serious interference in three dimensional NAND element, the design of less SSL number will be the preferable selection building three-D elements, but this kind of design is likely to result in the high pattern density of fan-out area of layer (such as wordline WL).
Summary of the invention
The invention relates to a kind of 3 D semiconductor element and manufacture method thereof.3 D semiconductor element according to embodiment, is to propose the bottom that ladder contact is connected to below multiple structure, such as, contact to bottom directly extending ladder, or mode is implemented with bottom contacts etc. to connect that ladder contacts to form top conductor.
According to embodiment, it is to propose a kind of 3 D semiconductor element, including: having a substrate of the staircase areas (staircaseregion) including N number of step (Nsteps), wherein N is the integer more than or equal to 1；There is multiple structure (multi-layers) and be stacked and placed on a lamination of substrate, and multiple structure includes active layer and crisscrosses on substrate with insulating barrier, lamination includes that multiple laminations are formed on substrate, and N number of step of these lamination and staircase areas is correspondingly arranged to be formed respectively contact area；With lay respectively at multiple adapters of contact area of correspondence, and these adapters are to downwardly extend the bottom being connected to below multiple structure.
According to embodiment, it is the manufacture method proposing a kind of 3 D semiconductor element, including:
Thering is provided a substrate, substrate has the staircase areas including N number of step, and wherein N is the integer more than or equal to 1；
Formation has the one of multiple structure and is stacked on substrate, and multiple structure includes active layer and interlocks with insulating barrier, and lamination includes that multiple laminations are formed on substrate, and N number of step of these lamination and staircase areas is correspondingly arranged to be formed respectively contact area；With
Form multiple adapter and lay respectively at the contact area of correspondence, and these adapters are to downwardly extend the bottom being connected to below multiple structure.
More preferably understand in order to the above-mentioned and other aspect of the present invention is had, special embodiment below, and coordinate institute's accompanying drawings, be described in detail below:
Accompanying drawing explanation
Fig. 1 is the axonometric chart of a 3 D semiconductor element.
Fig. 2 A is the top view of the part-structure of a 3 D semiconductor element of first embodiment of the invention.
Fig. 2 B is the generalized section along the 3 D semiconductor element depicted in the hatching 2B-2B of Fig. 2 A.
Fig. 2 C is the generalized section along the 3 D semiconductor element depicted in the hatching 2C-2C of Fig. 2 A.
Fig. 2 D is the generalized section along the 3 D semiconductor element depicted in the hatching 2D-2D of Fig. 2 A.
Fig. 3 A to Figure 14 D illustrates a kind of manufacture method of the 3 D semiconductor element of contact bottom the tool of first embodiment.
Figure 15 is the generalized section of a 3 D semiconductor element of second embodiment of the invention.
Figure 16 to Figure 25 illustrates a kind of manufacture method of the 3 D semiconductor element of contact bottom the tool of the second embodiment.
[symbol description]
10: substrate
101: bottom
11: memory layer
12,13: select line
15: serial
17: serial contacts
18: wire
21,22, Ld: dielectric layer
211: insulating barrier
213: active layer
231,232,233,234: multiple structure adapter
241,242,243,244: base connector
251,252,253,254: top conductor
31,32,33,34: adapter
314,324,334,344: the first conductive part
315,325,335,345: the second conductive part
314h, 324h, 334h, 344h: bottom contact hole
Rs: staircase areas
Rc1, Rc2, Rc3, Rc4: contact area
Tc: trench region
The mask of TL1, TL2, TL3, TL4: three-decker
PR-1, PR-2, PR-3, PR-4: patterning photoresist
Lc: conductor
D: spacing
S: thickness
Detailed description of the invention
Embodiments of the invention are to propose a kind of 3 D semiconductor element, contact the 3 D semiconductor element of (bottomcontacts) bottom particularly a kind of tool.According to embodiment, it is to contact bottom building in 3 D semiconductor element, makes element can more improve in the suitability of range of application.Such as, district selector (blockselectors) can be designed at ladder contact area (staircasecontactregion) lower section, the 3 D semiconductor element of contact bottom the tool of application this case embodiment, the multiple structure making the selector bottom staircase areas and contact area connects, and mat has been reached and saved area and avoid the too high problem of fan-out density.Furthermore, also have other situations about can contact with the bottom of Application Example, such as outer peripheral areas application of the 3 D semiconductor element of (periphery-under-array) below array region, and/or need the application that the ladder of local array contacts.The bottom contact structure of embodiment, for pursuing high Electronic Performance and the 3 D semiconductor element of characteristic, it is provided that structure probability with a greater variety.
Present invention can apply to the 3 D semiconductor element of the different memory cell array kenel of many tools, such as vertical channel formula (vertical-channel, VC) 3 D semiconductor element and vertical gate formula (vertical-gate, VG) 3 D semiconductor element, the present invention is not particularly limited for the application kenel of embodiment.Fig. 1 is the axonometric chart of a 3 D semiconductor element.Fig. 1 is illustrate a vertical channel formula 3 D semiconductor element as a example by explain.One 3 D semiconductor element includes that a lamination (stack) has multiple structure (multi-layers) and is stacked and placed on a substrate 10, with include a staircase areas (staircaseregion) Rs of N number of step (Nsteps), wherein N is the integer more than or equal to 1.And multiple structure includes that several layers of memory layer (memorylayers) 11 (i.e. active layer includes control gate in e.g. VC element) and insulating barrier crisscross on substrate 10.3 D semiconductor element further includes a plurality of selection line (selectionlines) 12 and is positioned at above memory layer 11 in parallel to each other, a plurality of serial (strings) 15 is perpendicular to memory layer 11 and selects line 12, and wherein these serials 15 are electrically connected to the selection line 12 of correspondence.Furthermore, 3 D semiconductor element further includes a plurality of wire 18 (such as bit line BLs) and is positioned at above selection line 12, and these wires 18 are to be parallel to each other and be perpendicular to select line 12.Multiple memory element (cells) are to be defined by these serials 15, these selection lines 12 and these wires 18 respectively, and these memory element are arranged as multiple row (rows) and multirow (columns) to form memory array.Furthermore, multiple serials contact (stringcontacts) 17 is perpendicular to memory layer 11 and selects line 12, and the setting of often serial contact 17 corresponds to every serial 15 of memory element, wherein serial contact 17 is electrically connected to the selection line 12 of correspondence and corresponding wires 18.3 D semiconductor element also includes other element, line 12 is such as selected to refer to line (upperselectlines selected over, upperSG), lower section is more had to select the formation of line (lowerselectlines, lowerSG) 13 below memory layer 11.
In embodiment, lamination includes that multiple laminations (sub-stacks) are formed on substrate 10, and N number of step of these lamination and staircase areas Rs is correspondingly arranged to form contact area (contactregions) (Rc) respectively.The 3 D semiconductor element of embodiment further includes multiple adapter (connectors), lay respectively at the contact area (Rc) of correspondence, and these adapters are to downwardly extend the bottom (bottomlayer) being connected to below multiple structure.The following is and explain as a example by the 3 D semiconductor element of the bottom of two kinds of aspects contact, but the present invention is not limited to this.
Following example are the dependency structure with reference to the institute accompanying drawings narration present invention and technique, and so the present invention is not limited to this.In embodiment, same or similar element is to indicate with same or similar label.It is noted that the present invention not demonstrates all possible embodiment.Other enforcement aspects not proposed in the present invention are likely to apply.Furthermore, graphic on dimension scale not according to actual product equal proportion draw.Therefore, description and diagramatic content are only described herein the use of embodiment, rather than are used as limit scope.
<first embodiment>
Refer to Fig. 1 and Fig. 2 A～Fig. 2 D.Fig. 2 A is the top view of the part-structure of a 3 D semiconductor element of first embodiment of the invention.Fig. 2 B is the generalized section along the 3 D semiconductor element depicted in the hatching 2B-2B of Fig. 2 A.Fig. 2 C is the generalized section along the 3 D semiconductor element depicted in the hatching 2C-2C of Fig. 2 A.Fig. 2 D is the generalized section along the 3 D semiconductor element depicted in the hatching 2D-2D of Fig. 2 A.Furthermore, Fig. 2 A presents an x/y plane of 3 D semiconductor element, Fig. 2 B and Fig. 2 C and presents the xz plane of 3 D semiconductor element, and Fig. 2 D presents a yz plane of 3 D semiconductor element.
In embodiment, multiple laminations (sub-stacks) included by lamination are formed on substrate 10, and N number of step of these lamination and staircase areas Rs is correspondingly arranged, to form contact area Rc1, Rc2, Rc3 and the Rc4 shown in contact area (contactregions), such as Fig. 2 A and Fig. 2 B respectively.In the first embodiment, 3 D semiconductor element further includes multiple adapter (connectors), such as multiple structure adapter (multilayeredconnectors) 231,232,233 and 234 and lays respectively at contact area Rc1, Rc2, Rc3 and Rc4 of correspondence.According to first embodiment, these adapters are the contact area that base connector (bottomconnectors) such as 241,242,243 and 244 is respectively formed in correspondence, and base connector downwardly extends the bottom 101 being connected to multiple structure (active layer 213 and insulating barrier 211 that i.e. is crisscross arranged) lower section, as shown in Figure 2 B.
As shown in Figure 2 C, multiple structure adapter (multilayeredconnectors) such as 231,232,233 and 234 is contact area Rc1, Rc2, Rc3 and the Rc4 being respectively formed in correspondence, and connects the drop zone of the active layer 213 of each lamination respectively.Such as, the drop zone of the active layer 213 of the 4th step (staircase areas) during multiple structure adapter 231 links contact area Rc1.It is similar to, multiple structure adapter 232 links the drop zone of the active layer 213 of the 3rd step (staircase areas) in contact area Rc2, multiple structure adapter 233 links the drop zone of the active layer 213 of the second step (staircase areas) in contact area Rc3, and multiple structure adapter 234 links the drop zone of the active layer 213 of the first step (staircase areas) in contact area Rc4.
Refer to Fig. 2 A and Fig. 2 D.In first embodiment, each multiple structure adapter such as 231,232,233 and 234 is the base connector such as 241,242,243 and 244 being electrically connected at correspondence respectively with top conductor (topconductor) such as 251,252,253 and 254.As shown in Figure 2 A, the multiple structure adapter 231 being disposed adjacent and base connector 241 are to be electrically connected with a top conductor 251.It is similar to, the multiple structure adapter 232 being disposed adjacent and base connector 242 are to be electrically connected with a top conductor 252, the multiple structure adapter 233 being disposed adjacent and base connector 243 are to be electrically connected with a top conductor 253, and the multiple structure adapter 234 being disposed adjacent and base connector 244 are to be electrically connected with a top conductor 254.Top conductor 251,252,253 and 254 is spaced apart.
In first embodiment, multiple structure adapter (such as 231,232,233 and 234) and base connector (such as 241,242,243 and 244) are to extend parallel to each other, and a bearing of trend of top conductor (such as 251,252,253 and 254) is such as along y-direction, be the bearing of trend being substantially perpendicular to base connector (such as 241,242,243 and 244) such as along z-direction, as shown in Fig. 2 B to Fig. 2 D.
Furthermore, the multiple structure adapter being disposed adjacent and base connector are spaced apart, as shown in Figure 2 D with insulant such as dielectric layer 21 and 22.Dielectric layer 21 and 22 can be to include identical or different material, and the present invention to this and is seldom restricted.In one embodiment, the multiple structure adapter being disposed adjacent and base connector (multiple structure adapter 231 as shown in Figure 2 D and base connector 241) are to have the space D less than 5 μm.So in the 3 D semiconductor element of reality application, space D can be also other numerical value, is not limited to that the numerical value of illustration.
Furthermore, dielectric layer 22 surrounds base connector (such as 241,242,243 and 244) and covers multiple structure.In one embodiment, the part around the dielectric layer 22 of base connector (base connector 241 as shown in Figure 2 D) is to have the thickness S less than or equal to 1 μm.So in the 3 D semiconductor element of reality application, thickness S can be also other numerical value, is not limited to that the numerical value of illustration.
Furthermore, as shown in Figure 2 D, top conductor (such as 251,252,253 and 254) is formed on dielectric layer 21 and 22 and connects multiple structure adapter (such as 231,232,233 and 234) and the top surface of base connector (such as 241,242,243 and 244).In other words, according to first embodiment, it is used for connecting the top conductor (such as 251,252,253 and 254) of multiple structure adapter and base connector, is that active layer 213 with multiple structure separates and insulate by dielectric layer 21 and 22.
3 D semiconductor element according to embodiment, constructed base connector (such as 241,242,243 and 244) can be electrically connected to the respective lines below multiple structure.The example of respective lines includes district selector such as TFTs, with the element that can carry out being electrically connected with for outer peripheral areas 3 D semiconductor element below array region, and the 3 D semiconductor element for needing the ladder of local array to contact can carry out element of being electrically connected with etc..Therefore, the bottom contact of embodiment, it couples with multiple structure adapter (linking to the drop zone of the active layer of each lamination), is to provide more possible change and progress for pursuing the 3 D semiconductor element of high Electronic Performance and characteristic.
The following is and propose the method for the 3 D semiconductor element of contact bottom the tool of one of which applicable manufacture first embodiment.Fig. 3 A to Figure 14 D illustrates a kind of manufacture method of the 3 D semiconductor element of contact bottom the tool of first embodiment.Referring to Fig. 1 about the related elements of the 3 D semiconductor element of embodiment.
First, one substrate 10 is provided, there is on it lamination including multiple structure (multi-layers), multiple structure includes that staggered stacked active layer 213 and insulating barrier 211 are on substrate 10, lamination includes that multiple laminations are formed on substrate 10, and secondary lamination is corresponding with N number of step of staircase areas Rs of substrate 10 to form contact area (such as Rc1, Rc2, Rc3, Rc4) respectively, wherein N is the integer more than or equal to 1.As shown in Figure 3 A and Figure 3 B, a dielectric layer 21 is formed in staircase areas Rs, and defines a trench region (trencharea) Tc along step.Refer to Fig. 3 A, for the top view (x/y plane) of part-structure of the 3 D semiconductor element of embodiment, display dielectric layer 21 and the active layer at N number of step of contact area Rc1-Rc4 213.Fig. 3 B is the generalized section (xz plane) along the 3 D semiconductor element depicted in the hatching 3B-3B of Fig. 3 A.Fig. 3 C is the generalized section (xz plane) along the 3 D semiconductor element depicted in the hatching 3C-3C of Fig. 3 A.
Afterwards, such as utilize three-decker technique (tri-layerprocess, the mask of a kind of three-decker includes ODL/SHB/PR), remove the multiple structure in trench region Tc.In embodiment, after etching a pair film layer (one layer of active layer 213 of one of them step of the most N number of step and a layer insulating 211), then the fine setting technique (trim-etchprocess) being masked with etching.Refer to Fig. 4 A-Fig. 4 B to Figure 11 A-Figure 11 B.Fig. 4 A to Figure 11 B is the etching-fine setting process schematic representation of the multiple structure removing trench region Tc of illustrated embodiments 3 D semiconductor element.Wherein, being labeled as the icon of B, such as Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B ... Figure 11 B are to illustrate the profile along icon section line B-B (being such as respectively 4B-4B, 5B-5B ... 11B-11B) being labeled as A.Furthermore, owing to the height of dielectric layer 21 is typically much deeper than the width of trench region Tc, thus in the technique of this example, assume that dielectric layer 21 can be left in the basket along the etching-fine setting in y-direction.
As shown in Figure 4 A and 4 B shown in FIG., the mask TL1 (such as ODL/SHB/PR) of three-decker, and the trench region Tc of corresponding contact area Rc1 are formed.As fig. 5 a and fig. 5b, the ground floor of contact area Rc1 is carried out to (active layer 213 and an insulating barrier 211 of first step in the most N number of step with mask TL1, N=4) etching, the trench region Tc being positioned at contact area Rc1 after etching is the active layer 213 exposing the second layer to (active layer 213 and an insulating barrier 211, N=4 of second step in the most N number of step).Afterwards, the mask TL1 of fine setting three-decker, to form the mask TL2 of three-decker, in the trench region Tc of contact area Rc1 and Rc2, the active layer 213 of second step is exposed, as shown in Figure 6 A and 6 B.
Then, as shown in figures 7 a and 7b, the second layer of contact area Rc1 and Rc2 is carried out to (active layer 213 and an insulating barrier 211 of second step in the most N number of step with mask TL2, N=4) etching, the trench region Tc being positioned at contact area Rc1 and Rc2 after etching is exposed the third layer active layer 213 to (active layer 213 and an insulating barrier 211, N=4 of the 3rd step in the most N number of step).Afterwards, the mask TL2 of fine setting three-decker, to form the mask TL3 of three-decker, in the trench region Tc of contact area Rc1, Rc2 and Rc3, the active layer 213 of the 3rd step is exposed, as shown in Figure 8 A and 8 B.
Then, as shown in fig. 9 a and fig. 9b, the third layer of contact area Rc1, Rc2 and Rc3 is carried out to (active layer 213 and an insulating barrier 211 of the 3rd step in the most N number of step with mask TL3, N=4) etching, the trench region Tc being positioned at contact area Rc1, Rc2 and Rc3 after etching is to expose the 4th layer of active layer 213 to (active layer 213 and an insulating barrier 211, N=4 of the 4th step in the most N number of step).Afterwards, the mask TL3 of fine setting three-decker, to form the mask TL4 of three-decker, is the active layer 213 of the 4th step in the trench region Tc exposing contact area Rc1, Rc2, Rc3 and Rc4, as shown in figs. 10 a and 10b.Then, as seen in figs. 11a and 11b, with mask TL4 carry out the 4th layer of contact area Rc1, Rc2, Rc3 and Rc4 to etching, make the multiple structure including active layer 213 alternately and insulating barrier 211 in trench region Tc be removed completely.
After all of etching-fine setting technique completes, it is to deposit an insulant and fill up trench region Tc, the most again with flatening process such as cmp (CMP) to planarize the upper surface of insulant, and form the dielectric layer 22 as shown in Figure 12 A to Figure 12 D.Figure 12 A is the top view (x/y plane) of the part-structure of the 3 D semiconductor element of embodiment, and display is positioned at the dielectric layer 22 of contact area Rc1-Rc4.Figure 12 B is the generalized section (xz plane) along the 3 D semiconductor element depicted in the hatching 12B-12B of Figure 12 A.Figure 12 C is the generalized section (xz plane) along the 3 D semiconductor element depicted in the hatching 12C-12C of Figure 12 A.Figure 12 D is the generalized section (yz plane) along the 3 D semiconductor element depicted in the hatching 12D-12D of Figure 12 A.
Being formed after dielectric layer 22, it is by contact hole technique to concurrently form multiple structure adapter (such as 231,232,233 and 234) and base connector (such as 241,242,243 and 244), as shown in Figure 13 A to Figure 13 D.According to Figure 13 B and Figure 13 D, the base connector (such as 241,242,243 and 244) being formed at each contact area (such as Rc1, Rc2, Rc3, Rc4) is the bottom 101 downwardly extending and being connected to multiple structure (active layer 213 and insulating barrier 211 that i.e. is crisscross arranged) lower section.It is formed at the drop zone that the multiple structure adapter (such as 231,232,233 and 234) of each contact area (such as Rc1, Rc2, Rc3, Rc4) then connects the active layer 213 of each lamination, as shown in fig. 13 c.Furthermore, adjacent multiple structure adapter (such as 231/232/233/234) and base connector (such as 241/242/243/244) are to separate, as illustrated in figure 13d with dielectric layer 21 and 22.Dielectric layer 21 and 22 can be that identical or different material is made.
After contact hole technique completes, it is to deposit a conductive material (such as metal) and carry out patterning step, to form top conductor (such as 251,252,253 and 254), thus the top completing adjacent multiple structure adapter (such as 231/232/233/234) and base connector (such as 241/242/243/244) connects, as shown in Figure 14 A to Figure 14 D.In first embodiment, each multiple structure adapter such as 231,232,233 and 234 is to be electrically connected to base connector such as 241,242,243 and 244, as shown in fig. 14d by top conductor 251,252,253 and 254 respectively.The CONSTRUCTED SPECIFICATION of related elements is as it was previously stated, it is no longer repeated at this.
<the second embodiment>
Figure 15 is the generalized section of a 3 D semiconductor element of second embodiment of the invention.According to embodiment, the adapter forming contact area respectively is to downwardly extend the bottom 101 being connected to below multiple structure, and the most each adapter is that the multiple structure adapter of the drop zone with the active layer being connected each lamination is electrically connected with.In a second embodiment, being to explain as a example by ladder contact is linked to bottom, the adapter (being connected to the bottom 101 below multiple structure) wherein formed and multiple structure adapter are a single piece (integralpiece).
As shown in figure 15, adapter, such as 31,32,33 or 34, respectively include that one first conductive part such as 314,324,334 or 344 downwardly extends the bottom 101 being connected to below multiple structure, and one second conductive part such as 315,325,335 or 345 connect the first conductive part.Second conductive part such as 315,325,335 and the drop zone that 345 is the active layer 213 (laying respectively at first, second, third and fourth step) being electrically connected with corresponding secondary lamination.In Figure 15, the first conductive part the such as 314,324,334 and 344 and second conductive part such as 315,325,335 and 345 is to form four single piece (integralpieces) respectively.
According to the second embodiment, second conductive part (such as 315/325/335/345) of adapter (such as 31/32/33/34) is the drop zone of the directly active layer 213 of the secondary lamination that contact is corresponding.Furthermore, the first conductive part (such as 314/324/334/344) is to be spaced, as shown in figure 15 with these active layers 213 of a dielectric layer Ld with multiple structure.
In one embodiment, a bearing of trend (i.e. along z-direction) of the first conductive part (such as 314/324/334/344) is substantially perpendicular to a bearing of trend (i.e. along x-direction) of the second conductive part (such as 315/325/335/345).In one embodiment, the first conductive part (such as 314/324/334/344) is through multiple structure and to connect the conductor (being such as positioned at the circuit of bottom 101) below multiple structure.
The following is and propose the method for the 3 D semiconductor element of contact bottom the tool of one of which applicable manufacture the second embodiment.Figure 16 to Figure 25 illustrates a kind of manufacture method of the 3 D semiconductor element of contact bottom the tool of the second embodiment.Referring to Fig. 1 about the related elements of the 3 D semiconductor element of embodiment.Furthermore, there is on it lamination including multiple structure about the substrate 10 provided, and lamination includes multiple laminations being formed on substrate 10, it is the most corresponding with N number of step of staircase areas Rs of substrate 10 to form the content of the related elements such as contact area (such as Rc1 to Rc4) respectively, being to be described in first embodiment the most in detail, its details is not repeated at this.Consider Fig. 3 A and Fig. 3 B in light of actual conditions the most simultaneously.Figure 16 to Figure 25 is e.g. relevant to the profile angle of the hatching 3B-3B along Fig. 3 A.Manufacturing step depicted in Figure 16 to Figure 25 is to carry out in the trench region Tc defined along the step as shown in Fig. 3 A, Fig. 3 B.
Refer to Figure 16 and Figure 17, it illustrates the first patterning program of the manufacture method according to the second embodiment.As shown in figure 16, being to form a patterning photoresist PR-1 (or patterning hardmask), it has two circular cavities corresponding to the second step and the active layer 213 of the 4th step simultaneously.Afterwards, etch a pair film layer (one layer of active layer 213 of one of them step of the most N number of step and a layer insulating 211), as shown in figure 17, carry out photoresist afterwards and remove (PR-strip) step.As shown in figure 17, at trench region Tc, it is positioned at the second layer of contact area Rc2 to (active layer 213 and an insulating barrier 211 of second step in the most N number of step, and be positioned at the 4th layer of contact area Rc4 to (active layer 213 and an insulating barrier 211 of the 4th step in the most N number of step N=4), N=4), it is to be etched according to patterning photoresist PR-1 simultaneously.In Figure 17, it is to form contact hole 344h bottom the 4th.
Refer to Figure 18 and Figure 19, it illustrates the second patterning program of the manufacture method according to the second embodiment.As shown in figure 18, being to form a patterning photoresist PR-2 (or patterning hardmask), it has the two circular cavities active layer 213 corresponding to the second step simultaneously.Afterwards, etching two, to film layer (the two-layer active layer 213 of two steps of the most N number of step and dielectric layers 211), as shown in figure 19, carries out photoresist afterwards and removes (PR-strip) step.As shown in figure 19, at trench region Tc, be positioned at three layers of contact area Rc2 to and be positioned at two layers of contact area Rc3 to being removed.In Figure 19, it is to form bottom one second contact hole 334h bottom contact hole 324h and the 3rd.
Refer to Figure 20 and Figure 21, it illustrates the 3rd patterning program of the manufacture method according to the second embodiment.As shown in figure 20, being to form a patterning photoresist PR-3 (or patterning hardmask), it has the hole active layer 213 corresponding to the first step.Then, etching four, to film layer, as shown in figure 21, carries out photoresist afterwards and removes step.As shown in figure 21, at trench region Tc, it is positioned at four layers of contact area Rc1 to being removed.In Figure 21, it is to form contact hole 314h bottom one first.So far, four bottoms contact hole (i.e. 314h, 324h, 334h and 344h) have been formed.
After four bottom contact holes are formed and remove photoresist, it is to deposit a dielectric (depositional mode is e.g. with the form of the lining of contact hole bottom being formed) and perform etching to be formed dielectric layer Ld, as shown in figure 22.In Figure 22, top conductive layer (i.e. top active layer 231) by exposed out, the beneficially electric connection in subsequent technique.
Afterwards, deposit a conductor Lc, as desalinated titanium/tungsten (TiN/W) or doped silicon, and fill contact hole 314h-334h bottom first to fourth, as shown in figure 23.Then, as shown in figure 24, a patterning photoresist PR-4 (or patterning hardmask) is formed；Tropism etching (isotropicetch) such as carry out afterwards, be not patterned, to remove, the conductor linking portion that photoresist PR-4 covers.After removing patterning photoresist PR-4, then form the structure of the second embodiment, as shown in figure 25 (with the structure of Figure 15).In Figure 25 (/ Figure 15), each adapter (31/32/33/34) includes that one first conductive part (314/324/334/344) downwardly extends the bottom 101 being connected to below multiple structure, connects the first conductive part with one second conductive part (315/325/335/345) and contacts the drop zone of active layer 213 of secondary lamination of correspondence.
According to the content disclosed by above-described embodiment, it is to propose a kind of 3 D semiconductor element having bottom contact, can by arrange neighbouring multiple structure adapter and base connector and both each one be with one top conductor be electrically connected with (first embodiment), or formed there is the adapter (the second embodiment) of ladder contact site and bottom contact site and realize embodiment.The bottom contact of embodiment can be widely applied to the 3 D semiconductor element of the different kenel of many tools, such as vertical channel formula (vertical-channel, and vertical gate formula (vertical-gate VC), VG) 3 D semiconductor element, the film layer of multiple structure can be metal (metal gates), quasiconductor (polysilicon gate or bit line).The present invention is not particularly limited for the application kenel of the 3 D semiconductor element of embodiment.And the only narration of the structure of the memory cell array of said elements and staircase areas is used, the present invention is not limited to above-mentioned structure.Therefore, the those skilled in the art of association area understands, and structure and design that above-described embodiment is proposed all can be done according to the actual demand of application and suitably modify and adjust.The 3 D semiconductor element proposed according to above-described embodiment, can be with the bottom contact structure of the wider embodiment of application structure, for pursuing high Electronic Performance and the 3 D semiconductor element of characteristic, the change and progress of wider scope can be provided, for pursuing small size, easily making or the 3 D semiconductor element of more stable characteristic electron, it is as good as providing more structure probability.Furthermore, the 3 D semiconductor element of embodiment uses the technique of non-time-consuming also inexpensive, is still suitable for volume production on making.
In sum, although the present invention is disclosed above with embodiment, and so it is not limited to the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when depending on being as the criterion that appended claims scope is defined.
Claims (20)
1. a 3 D semiconductor element, including:
One substrate, has the staircase areas (staircaseregion) including N number of step (Nsteps), and wherein N is the integer more than or equal to 1；
One lamination, there is multiple structure (multi-layers) and be stacked and placed on this substrate, and this multiple structure includes active layer and crisscrosses on this substrate with insulating barrier, this lamination includes that multiple laminations (sub-stacks) are formed on this substrate, and this N number of step of these lamination and this staircase areas is correspondingly arranged to form contact area (contactregions) respectively；With
Multiple adapters (connectors), lay respectively at these contact areas of correspondence, and these adapters are to downwardly extend the bottom (bottomlayer) being connected to below this multiple structure.
3 D semiconductor element the most according to claim 1, wherein these adapters are respectively electrically connected to multiple structure adapter (multilayeredconnectors), and these multiple structure adapters are the drop zone (1andingareas) connecting respectively these active layers of this lamination respectively.
3 D semiconductor element the most according to claim 1, wherein these adapters are that base connector (bottomconnectors) downwardly extends this bottom (bottomlayer) being connected to below this multiple structure, and this element further includes:
Multiple multiple structure adapters (multilayeredconnectors), are respectively formed in these contact areas of correspondence, and these multiple structure adapters are the drop zone connecting respectively these active layers of this lamination respectively.
3 D semiconductor element the most according to claim 3, respectively this multiple structure adapter is electrically connected to corresponding respectively this base connector.
3 D semiconductor element the most according to claim 4, this multiple structure adapter being wherein disposed adjacent and this base connector are to be electrically connected with a top conductor (topconductor).
3 D semiconductor element the most according to claim 5, wherein these multiple structure adapters and these base connector are to extend parallel to each other, and the one of these top conductors extends perpendicularly to a bearing of trend of these base connector.
3 D semiconductor element the most according to claim 5, this multiple structure adapter being wherein disposed adjacent and this base connector are spaced apart with a dielectric layer (adielectriclayer).
3 D semiconductor element the most according to claim 7, wherein this dielectric layer surrounds this base connector and is covered on this multiple structure, and this top conductor is formed on this dielectric layer and connects the top surface of this multiple structure adapter and this base connector.
3 D semiconductor element the most according to claim 2, respectively this adapter includes:
One first conductive part, downwardly extends this bottom being connected to below this multiple structure；With
One second conductive part, connects this first conductive part, and this second conductive part is electrically connected with this drop zone of this active layer of this time corresponding lamination.
3 D semiconductor element the most according to claim 9, wherein this first conductive part is to be spaced with these active layers of a dielectric layer with this multiple structure.
11. 3 D semiconductor elements according to claim 9, wherein the one of this first conductive part extends perpendicularly to a bearing of trend of this second conductive part.
12. 3 D semiconductor elements according to claim 9, wherein this second conductive part of this adapter is this drop zone of directly this active layer of this lamination that contact is corresponding.
13. 3 D semiconductor elements according to claim 1, one of these adapters of at least a part of which are electrically connected to the circuit below this multiple structure.
The manufacture method of 14. 1 kinds of 3 D semiconductor elements, including:
Thering is provided a substrate, this substrate has the staircase areas including N number of step, and wherein N is the integer more than or equal to 1；
Formation has the one of multiple structure (multi-layers) and is stacked on this substrate, and this multiple structure includes active layer and interlocks with insulating barrier, this lamination includes that multiple laminations are formed on this substrate, and this N number of step of these lamination and this staircase areas is correspondingly arranged to form contact area (contactregions) respectively；With
Form multiple adapter (connectors) and lay respectively at these contact areas of correspondence, and these adapters are to downwardly extend the bottom (bottomlayer) being connected to below this multiple structure.
15. manufacture methods according to claim 14, wherein these adapters are respectively electrically connected to multiple structure adapter (multilayeredconnectors), and these multiple structure adapters are the drop zone (1andingareas) connecting respectively these active layers of this lamination respectively.
16. manufacture methods according to claim 14, further include and are electrically connected with at least one of these adapters to the conductor below this multiple structure.
17. manufacture methods according to claim 14, wherein these adapters are that base connector (bottomconnectors) downwardly extends this bottom (bottomlayer) being connected to below this multiple structure, and the method further includes:
Forming multiple multiple structure adapter (multilayeredconnectors) these contact areas respectively at correspondence, these multiple structure adapters are the drop zone connecting respectively these active layers of this lamination respectively,
Respectively this multiple structure adapter is electrically connected to corresponding respectively this base connector.
18. manufacture methods according to claim 17, this multiple structure adapter being wherein disposed adjacent and this base connector are spaced apart with a dielectric layer (adielectriclayer), and are electrically connected with a top conductor (topconductor).
19. manufacture methods according to claim 14, in the step forming these adapters, respectively this adapter includes:
One first conductive part, downwardly extends this bottom being connected to below this multiple structure；With
One second conductive part, connects this first conductive part, and this second conductive part is electrically connected with this drop zone of this active layer of this time corresponding lamination；
Wherein the one of this first conductive part extends perpendicularly to a bearing of trend of this second conductive part.
20. manufacture methods according to claim 19, further include:
Form a dielectric layer, make this first conductive part separate with these active layers of this multiple structure,
Wherein this second conductive part of this adapter is formed at above this first conductive part, and the second conductive part also directly contacts this drop zone of this active layer of this lamination of correspondence.
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| CN113725219A (en) * | 2020-05-25 | 2021-11-30 | 爱思开海力士有限公司 | Three-dimensional memory device and method of manufacturing the same |
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