TWI462278B - Semiconductor structure and manufacturing method of the same - Google Patents

Description

Semiconductor structure and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure for a memory device and a method of fabricating the same.

In recent years, the structure of semiconductor elements has been constantly changing, and the memory storage capacity of the elements has also been increasing. Memory devices are used in many products, such as MP3 players, digital cameras, computer files, and the like. As applications increase, so does the demand for memory devices toward smaller sizes and larger memory capacities. In response to this demand, it is required to manufacture a memory device having a high component density.

Therefore, designers are all committed to developing a 3D flash memory structure that not only has many stacked planes but also achieves higher memory storage capacity, has good characteristics, and reduces the cost per bit. .

The present invention relates to a semiconductor structure and a method of fabricating the same, which can be applied to a memory device. The semiconductor structure is applied to a three-dimensional memory array, which can reduce damage caused by high energy in the doping process, and also reduce the overall space and manufacturing cost of the memory array.

According to an aspect of the invention, a semiconductor structure is proposed comprising at least a substrate, a first stacked structure, and a first conductive layer. the first The stacked structure is formed on the substrate, and the first stacked structure includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. A first conductive layer is formed on the substrate and surrounds both sidewalls and a portion of the top of the first stacked structure to expose a portion of the first stacked structure.

According to another aspect of the present invention, a method of fabricating a semiconductor structure includes at least forming a first stacked structure on a substrate, including: forming an insulating structure on the substrate and providing a conductive structure adjacent to the insulating structure Forming a layer of conductive material on the substrate; and etching the layer of conductive material to form a first conductive layer and exposing a portion of the first stacked structure, wherein the first conductive layer surrounds both sidewalls and a portion of the top of the first stacked structure.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

In the embodiments disclosed herein, a semiconductor structure and a method of fabricating the same are presented. The application of the semiconductor structure to the three-dimensional memory array can reduce the damage that may be caused by the high energy in the doping process, and also reduce the overall space and manufacturing cost of the memory array. However, the detailed structure and process steps set forth in the examples are for illustrative purposes only and are not intended to limit the scope of the invention. These steps are for illustrative purposes only and are not intended to limit the invention. Those having ordinary knowledge may modify or change the steps as needed according to the actual implementation.

<Semiconductor Structure> First embodiment

Please refer to Figure 1. 1 is a schematic view of a semiconductor structure in accordance with a first embodiment of the present invention. The semiconductor structure 100 includes a substrate 110, a first stacked structure 120, and a first conductive layer 130. The first stacked structure 120 is formed on the substrate 110. The first stacked structure 120 includes a conductive structure 121 and an insulating structure 123, and the conductive structure 121 is disposed adjacent to the insulating structure 123. The first conductive layer 130 is formed on the substrate 110 and surrounds the sidewalls 120a and the portion of the top portion 120b of the first stacked structure 120 to expose a portion 120c of the first stacked structure 120. In the embodiment, the material of the conductive structure 121 includes a germanium-containing material, such as polysilicon, and the material of the insulating structure 123 is, for example, a metal oxide. However, in practical applications, the materials of the conductive structure 121 and the insulating structure 123 are also appropriately selected depending on the application conditions, and are not limited to the foregoing materials.

The first conductive layer 130 includes a first body portion 131 and a first cover portion 133 disposed above the first body portion 131. The first body portion 131 corresponds to the lower side of the first sidewall 120a. The first cover portion 133 is connected to the first body portion 131 and correspondingly covers the upper portion of the sidewalls 120a and the first stack structure 120. Top 120b. The width W1 of the first covering portion 133 is smaller than the width W2 of the corresponding side walls 120a to expose the portion 120c of the first stacked structure 120.

As shown in FIG. 1, in the embodiment, the width W3 of the first body portion 131 is substantially equal to the width W2 of each side wall 120a, and the width W1 of the first cover portion 133 is substantially smaller than the width of the first body portion 131. W3.

In an embodiment, the conductive structure 121 is, for example, a conductive layer, and the insulating structure 123 is, for example, an insulating layer, and a conductive layer is provided on the insulating layer.

As shown in FIG. 1 , the first stack structure 120 may further include a memory material layer 125 formed on the substrate 110 and covering the periphery of the conductive structure 121 and the insulating structure 123 . In an embodiment, the first conductive layer 130 covers a portion of the memory material layer 125.

In an embodiment, the first conductive layer 130 has a single material, such as polysilicon. The first conductive layer 130 may also have a composite material such as polysilicon and germanium telluride (WSi).

Second embodiment

Please refer to Figure 2. 2 is a schematic view of a semiconductor structure in accordance with a second embodiment of the present invention. In the second embodiment, the same components as the first embodiment are denoted by the same reference numerals, and the related descriptions of the same components are referred to the foregoing, and are not described herein again.

The semiconductor structure 200 includes a substrate 110, a first stacked structure 220, and a first conductive layer 130. The first stacked structure 220 is formed on the substrate 110. The first stacked structure 220 includes a conductive structure 221 and an insulating structure 223, and the conductive structure 221 is disposed adjacent to the insulating structure 223. The first conductive layer 130 is formed on the substrate 110 and surrounds the sidewalls 120a and the portion of the top portion 120b of the first stack structure 220 to expose a portion 120c of the first stack structure 120.

As shown in FIG. 2, in the embodiment, the conductive structure 221 includes a plurality of first strip-shaped conductive blocks 221a, and the insulating structure 223 includes a plurality of first strip-shaped insulating blocks 223a, a plurality of first strip-shaped conductive blocks 221a and a plurality The first strip-shaped insulating blocks 223a are alternately stacked, and each of the first strip-shaped conductive blocks 221a It is separated by the first strip insulating block 223a.

Third embodiment

Please refer to Figure 3. 3 is a schematic view showing a semiconductor structure in accordance with a third embodiment of the present invention. The same components as the first embodiment and the second embodiment in the third embodiment are denoted by the same reference numerals, and the related descriptions of the same components are referred to the foregoing, and are not described herein again.

The semiconductor structure 300 includes a substrate 110, a first stacked structure 120, and a first conductive layer 130. The first stacked structure 120 is formed on the substrate 110. The first stacked structure 120 includes a conductive structure 121 and an insulating structure 123, and the conductive structure 121 is disposed adjacent to the insulating structure 123. The first conductive layer 130 is formed on the substrate 110 and surrounds the sidewalls 120a and the portion of the top portion 120b of the first stacked structure 120 to expose a portion 120c of the first stacked structure 120.

As shown in FIG. 3 , in the embodiment, the semiconductor structure 300 further includes a second stacked structure 320 and a second conductive layer 330 . The second stack structure 320 is formed on the substrate 110 and disposed adjacent to the first stack structure 120. The second stack structure 320 includes a plurality of second strip-shaped conductive blocks 321a and a plurality of second strip-shaped insulating blocks 323a, and the plurality of second strip-shaped conductive blocks 321a and the plurality of second strip-shaped insulating blocks 323a are alternately stacked, and Each of the second strip-shaped conductive blocks 321a is separated by a second strip-shaped insulating block 323a. The second conductive layer 330 is formed on the substrate 110 and surrounds the two sidewalls 320a and the portion of the top portion 320b of the second stack structure 320 to expose a portion 320c of the second stack structure 320.

The second conductive layer 330 includes a second body portion 331 and is disposed on the second main body A second cover portion 333 above the body portion 331. The second body portion 331 is disposed below the two side walls 320a of the second stack structure 320. The second cover portion 333 is connected to the second body portion 331 and correspondingly covers the upper portion of the sidewalls 320a and the second stack structure 320. Top 320b. The width W4 of the second covering portion 333 is smaller than the width W5 of the corresponding sidewalls 320a to expose a portion 320c of the second stack structure 320.

As shown in FIG. 3, in the embodiment, the width W6 of the second main body portion 331 is substantially equal to the width W5 of each side wall 320a, and the width W4 of the second covering portion 333 is substantially smaller than the width of the second main body portion 331. W6.

In an embodiment, the second stack structure 320 further includes a memory material layer 125 formed on the substrate 110 and covering the periphery of the second strip-shaped conductive block 321a and the second strip-shaped insulating block 323a. In an embodiment, the second conductive layer 330 covers a portion of the memory material layer 125.

In an embodiment, the second conductive layer 330 has a single material, and the second conductive layer 330 may also have a composite material.

Fourth embodiment

Please refer to Figure 4. 4 is a schematic view showing a semiconductor structure in accordance with a fourth embodiment of the present invention. In the fourth embodiment, the same components as those in the foregoing third embodiment are denoted by the same reference numerals, and the related descriptions of the same components are referred to the foregoing, and are not described herein again.

The semiconductor structure 400 includes a substrate 110, a first stacked structure 120, a first conductive layer 130, a second stacked structure 320, and a second conductive layer 330.

The first stacked structure 120 is formed on the substrate 110, and the first stacked structure 120 includes a conductive structure 121 and an insulating structure 123, and the conductive structure 121 is Adjacent to the insulating structure 123. The first conductive layer 130 is formed on the substrate 110 and surrounds the sidewalls 120a and the portion of the top portion 120b of the first stacked structure 120 to expose a portion 120c of the first stacked structure 120. The second stack structure 320 is formed on the substrate 110 and disposed adjacent to the first stack structure 120. The second conductive layer 330 is formed on the substrate 110 and surrounds the two sidewalls 320a and the portion of the top portion 320b of the second stack structure 320 to expose a portion 320c of the second stack structure 320.

As shown in FIG. 4, in the embodiment, the conductive structure 121 of the first stacked structure 120 is, for example, a conductive layer, and the insulating structure 123 of the first stacked structure 120 is, for example, an insulating layer, and the conductive layer is disposed on the insulating layer. The second stack structure 320 includes a plurality of second strip-shaped conductive blocks 321a and a plurality of second strip-shaped insulating blocks 323a, and the plurality of second strip-shaped conductive blocks 321a and the plurality of second strip-shaped insulating blocks 323a are alternately stacked, and Each of the second strip-shaped conductive blocks 321a is separated by a second strip-shaped insulating block 323a.

Although the fourth embodiment is described with a first stack structure 120 including a conductive layer and an insulating layer and a second stack structure 320 including a plurality of strip-shaped conductive blocks and strip-shaped insulating blocks staggered, in practice, The first stack structure 120 and the second stack structure 320 may also include a plurality of strip-shaped conductive blocks and a plurality of strip-shaped insulating blocks, respectively, or a conductive layer and an insulating layer, respectively. The structural configurations of the first stack structure 120 and the second stack structure 320 are appropriately selected depending on the application conditions, and are not limited to the foregoing configuration.

As shown in FIG. 4, in an embodiment, the semiconductor structure 400 may further include a conductive element 440. The conductive element 440 is disposed on the first stacked structure 120 and electrically connected to the conductive structure 121. Semiconductor structure 400 of the present embodiment When applied, it can be a gate selection line of a three-dimensional memory array.

Furthermore, the first conductive layer 130 surrounds the two sidewalls 120a and the portion of the top portion 120b of the first stacked structure 120 to expose a portion 120c of the first stacked structure 120, such that the conductive element 440 has a distance from the first conductive layer 130. The conductive element 440 is less likely to come into contact with the first conductive layer 130 to cause a short circuit.

Fifth embodiment

Please refer to Figure 5. Figure 5 is a schematic view showing a semiconductor structure in accordance with a fifth embodiment of the present invention. The components of the fifth embodiment that are the same as those of the foregoing fourth embodiment are denoted by the same reference numerals, and the related descriptions of the same components are referred to the foregoing, and are not described herein again.

The semiconductor structure 500 includes a substrate 110, a first stacked structure 120, a first conductive layer 130, a second stacked structure 320, a second conductive layer 330, a conductive element 440, and a plurality of word structures WL-1 WL WL-N. The first stack structure 120 includes a conductive structure 121 and an insulating structure 123. The conductive structure 121 is disposed adjacent to the insulating structure 123. The second stack structure 320 includes a plurality of second strip-shaped conductive blocks 321a and a plurality of second strips that are alternately stacked. Insulation block 323a. The conductive element 440 is disposed on the first stacked structure 120 and electrically connected to the conductive structure 121. The word structures WL-1 to WL-N are formed on the substrate 110.

Each of the word structures WL-1 WL WL-N has at least one stacked structure similar to the second stacked structure 320 and a plurality of strip-shaped conductive blocks such that the conductive structures 121 and the second stacked structures 320 of the first stacked structure 120 Strip guide of the second strip-shaped conductive block 321a and the word structure WL-1~WL-N The electrical blocks are connected, and the word structures WL-1 WL WL-N are connected in parallel by the strip-shaped conductive blocks of the word structures WL-1 WL WL-N by the connected second strip-shaped conductive blocks 321 a The first stack structure 120 and the second stack structure 320 are disposed. In an embodiment, the semiconductor structure 500 further includes an insulating layer 640 formed in a pitch 110c between the word structures WL-1 WL WL-N. The insulating layer 640 in the pitch 110c between the word structures WL-1 WL WL-N spaces the respective word structures WL-1 WL WL-N and can reach the protection word structure WL-1 WL WL - N and the effect of preventing short circuit. In practical applications, the semiconductor structure 500 of the present embodiment may be a combination of a gate selection line and a source line of a three-dimensional vertical and three-dimensional NAND flash memory array, which can save components in the memory array. The space occupied.

<Semiconductor structure applied to memory device>

Please refer to Figure 6. FIG. 6 is a schematic diagram of a three-dimensional vertical anti-gate flash memory array. The three-dimensional vertical anti-gate flash memory array 600 has a metal layer of string selection lines ML1 and ML2, a plurality of strip-shaped conductive blocks 502-505 and 512-515 parallel to the string selection line ML1, and a plurality of vertical alignment lines. The word lines 525-1 to 525-N of ML1, and a plurality of bit lines ML3 parallel to the strip-shaped conductive blocks 502-505 and 512-515. The memory elements of the three-dimensional memory array are accessed via the plurality of strip-shaped conductive blocks 502-505 and 512-515 and the interface areas of the plurality of word lines 525-1~525-N. The stack structure of the plurality of strip-shaped conductive blocks 502-505 and 512-515 can be divided into an odd-numbered group 502-505 and an even-numbered group 512-515. The first end of the plurality of strip-shaped conductive blocks of the odd-numbered strip groups 512-515 is a plurality of ladder structures 512A-515A, through the string selection line gate structure 519, the gate selection line 526, the plurality of word lines 525-1~525-N, the gate selection line 527 to the second end of the source line 528. The first ends of the plurality of strip-shaped conductive blocks of the even-numbered groups 502-505 are the source line 528, and pass through the gate selection line 527, the plurality of word lines 525-1~525-N, and the gate selection line 526. The string selects the gate gate structure 509 to the second ends of the plurality of ladder structures 502B-505B. Since the path between the gate select line 527 and the source line 528 is longer than the path between the word lines, in order to reduce the resistance along the current path of the strip conductive block, implantation is applied to increase the gate. A doping concentration of the strip-shaped conductive block between the gate select line 527 and the source line 528, or an auxiliary gate on the strip-shaped conductive block between the gate select line 527 and the source line 528.

Referring to FIG. 4 and FIG. 6 simultaneously, taking the fourth embodiment as an example, the semiconductor structure 400 is a three-dimensional vertical gate memory device, for example, including a three-dimensional vertical anti-gate flash memory device (3D). NAND flash memory device). A metal telluride layer (not shown) may be formed on the first conductive layer 130 and the second conductive layer 330, such as tungsten telluride. In the embodiment, the semiconductor structure 400 as shown in FIG. 4 is disposed at both ends of the three-dimensional vertical inverse gate flash memory array 600 in FIG. 6 as a gate selection line, and the second strip-shaped conductive block 321a (the first 4) A stepped structure (Fig. 6) that can be extended to the end of the memory array, and a conductive element 440 (Fig. 4) is grounded at the end as a source line of the memory array.

Taking the memory array 600 of FIG. 6 as an example for further description, four semiconductor structures 400 (FIG. 4) are disposed adjacent to the memory array 600 (FIG. 6). At the first end of the ladder structures 502B-505B (Fig. 6), the other four semiconductor structures 400 (Fig. 4) are disposed in the memory array 600 (Fig. 6) adjacent to the ladder structures 512A-515A (Fig. 6). The second end. Further, in the embodiment, the semiconductor structure 400 (Fig. 4) replaces the gate selection line 527, the source line 528, and the string selection line of the first end of the structure of the original memory array 600 (Fig. 6). Gate structure 509 (Fig. 6); width W2 of first body portion 131 of first conductive layer 130 (see Fig. 1) and width W5 of second body portion 331 of second conductive layer 330 (please refer to 3) is substantially equal to or greater than the width W7 of the gate selection line 527 (Fig. 6). As a result, the gate select line 527, the source line 528, and the string select line gate structure 509 (FIG. 6) are replaced by a single semiconductor structure 400 (FIG. 4), because the gate select line 527 and the source line The resistance of the current path along the strip-shaped conductive block generated by the long path between 528 can be reduced, and at the same time, the etching process of the word line of the memory array 600 is not affected by the provision of the source line 528. Moreover, the three-dimensional memory array 600 (Fig. 6) has a multi-layer structure, so that it is required to provide high energy when applying the implant, and in the embodiment, it is not necessary to apply the implant to the strip-shaped conductive block to increase the doping concentration, thereby reducing the cause. The high energy in the doping process may cause damage to the gate selection line, and the layer-to-layer non-uniformity caused by doping the multilayer structure may be avoided, and the doping amount of the lower layer is smaller than that of the upper layer. . At the same time, the original gate select line 527, the source line 528, and the string select line gate structure 509 (Fig. 6) are replaced by a semiconductor structure 400 (Fig. 4), the original gate select line 527 and the source. The overall path length of line 528 can be reduced while also reducing the overall space and manufacturing cost of memory array 600.

<Method of Manufacturing Semiconductor Structure>

The following is a method of fabricating a semiconductor structure of the embodiments, which are for illustrative purposes only and are not intended to limit the invention. Those having ordinary knowledge may modify or change the steps as needed according to the actual implementation. Please refer to Figures 7A to 7C and Figures 8A to 8H. 7A to 7C are schematic views showing a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention. 8A to 8H are schematic views showing a method of fabricating a semiconductor structure in accordance with another embodiment of the present invention.

The manufacturing process of the semiconductor structure 100 of Fig. 1 will be described below.

Referring to FIG. 7A, a first stacked structure 120 is formed on the substrate 110. In an embodiment, the manufacturing method of the first stacked structure 120 is, for example, forming the insulating structure 123 on the substrate 110, and providing the conductive structure 121 adjacent to the insulating structure 123. In another embodiment, the manufacturing method of the first stack structure 120 further includes: forming a memory material layer 125 on the substrate 110, and the memory material layer 125 covering the periphery of the conductive structure 121 and the insulating structure 123.

Referring to FIG. 7B, a conductive material layer 630 is formed on the substrate 110. In an embodiment, the layer of conductive material 630 completely covers both sidewalls and top of the first stack 120. In an embodiment, the material of the conductive material layer 630 includes a metal such as polysilicon. However, in practical applications, the material of the conductive material layer 630 is also appropriately selected depending on the application conditions, and is not limited to the foregoing materials.

Referring to FIG. 7C, the conductive material layer 630 is etched to form the first conductive layer 130 and expose a portion 120c of the first stacked structure 120. In an embodiment, one portion 120c of the first stack structure 120 includes a memory material A portion of layer 125. The etch process has appropriate etch selectivity to the conductive material layer 630 (eg, polysilicon) and the memory material layer 125 (eg, the ONO structure), thereby etching the conductive material layer 630 without etching the memory material layer 125 of the first stacked structure 120. . The first conductive layer 130 surrounds the sidewalls 120a and the portion of the top portion 120b of the first stack structure 120. Thus far, the semiconductor structure 100 as shown in Fig. 1 is formed.

The manufacturing process of the semiconductor structure 200 of Fig. 2 will be described below. The components in the manufacturing process of the semiconductor structure 200 are the same as those in the manufacturing process of the semiconductor structure 100, and the same components and the same manufacturing process are referred to the foregoing, and will not be described herein.

In an embodiment, a first stacked structure 220 is formed on the substrate 110. In an embodiment, the manufacturing method of the first stack structure 220 is, for example, forming a plurality of first strip-shaped insulating blocks 223a on the substrate 110, and forming a plurality of first strip-shaped conductive blocks 221a, the first strip-shaped conductive blocks 221a and the first The strip-shaped insulating blocks 223a are alternately stacked, and each of the first strip-shaped conductive blocks 221a is separated by a first strip-shaped insulating block 223a. In an embodiment, the step of forming the first stacked structure 220 on the substrate 110 is performed at the same stage as the step of forming the first stacked structure 120 on the substrate 110 in the manufacturing process.

Then, a conductive material layer 630 is formed on the substrate 110, the conductive material layer 630 completely covers both sidewalls and the top of the first stacked structure 220; and the conductive material layer 630 is etched to form the first conductive layer 130 and expose the first stacked structure 220 Part of 120c. Thus far, the semiconductor structure 200 as shown in Fig. 2 is formed.

The manufacturing process of the semiconductor structure 300 of FIG. 3 will be described below.

Referring to FIG. 8A, a first stacked structure 120 is formed on the substrate 110, and a second stacked structure 320 is formed on the substrate 110 and disposed adjacent to the first stacked structure 120. In an embodiment, the step of forming the first stacked structure 120 on the substrate 110 and the step of forming the second stacked structure 320 on the substrate 110 are performed simultaneously. In an embodiment, the manufacturing method of the first stacked structure 120 is, for example, forming the insulating structure 123 on the substrate 110, and providing the conductive structure 121 adjacent to the insulating structure 123. The manufacturing method of the second stack structure 320 is, for example, forming a plurality of second strip-shaped insulating blocks 323a on the substrate 110, and forming a plurality of second strip-shaped conductive blocks 321a, a second strip-shaped conductive block 321a and a second strip-shaped insulating block. The 323a is staggered and stacked, and each of the second strip-shaped conductive blocks 321a is separated by a second strip-shaped insulating block 323a.

In another embodiment, the manufacturing method of the first stack structure 120 and the second stack structure 320 further comprises: forming a memory material layer 125 on the substrate 110, the memory material layer 125 covering the periphery of the conductive structure 121 and the insulating structure 123 and The periphery of the two strip-shaped conductive bumps 321a and the second strip-shaped insulating block 323a.

Referring to FIG. 8B, a conductive material layer 630 is formed on the substrate 110. In an embodiment, the sidewalls and the top of the first stacked structure 120 are completely covered by the conductive material layer 630, and the sidewalls and the top of the second stacked structure 320 are completely covered by the conductive material layer 630. In an embodiment, the step of completely covering the sidewalls and the top of the first stacked structure 120 with the conductive material layer 630 and the step of completely covering the sidewalls and the top of the second stacked structure 320 with the conductive material layer 630 are performed simultaneously.

Referring to FIG. 8C, the conductive material layer 630 is etched to form a first guide. The electrical layer 130 exposes a portion 120c of the first stacked structure 120 and etches the conductive material layer 630 to form the second conductive layer 330 and expose a portion 320c of the second stacked structure 320. In an embodiment, the step of etching the conductive material layer 630 to form the first conductive layer 130 and the step of etching the conductive material layer 630 to form the first conductive layer 130 are performed simultaneously. In an embodiment, the first conductive layer 130 surrounds the sidewalls 120a and the portion of the top portion 120b of the first stacked structure 120. The second conductive layer 330 surrounds the two sidewalls 320a and the portion of the top portion 320b of the second stack structure 320. So far, the semiconductor structure 300 as shown in FIG. 3 is formed.

The manufacturing process of the semiconductor structure 400 of Fig. 4 will be described below. The following description begins after etching the conductive material layer 630 to form the first conductive layer 130 and the second conductive layer 330.

Referring to FIG. 8D, an insulating layer 640 is formed on the first conductive layer 130 and on the exposed portion 120c of the first stacked structure 120. In an embodiment, the insulating layer 640 is formed on the second conductive layer 330 and the exposed portion 320c of the second stacked structure 320, and the insulating layer 640 is formed on the first conductive layer 130 and the first stacked structure 120 is exposed. The steps on part 120c are performed simultaneously. In the embodiment, the material of the insulating layer 640 is, for example, a metal oxide. However, in practical applications, the material of the insulating layer 640 is also appropriately selected depending on the application conditions, and is not limited to the foregoing materials.

Referring to FIG. 8E, the insulating layer 640 is etched to expose the upper surface 120c' of the portion 120c of the first stacked structure 120. In an embodiment, the insulating layer 640 is further etched to expose the upper portion 320c' of the portion 320c of the second stacked structure 320, and the insulating layer 640 is etched to expose the first stacked junction The steps of the upper surface 120c' of the portion 120c of the structure 120 are performed simultaneously. In the embodiment, the upper surface 130a of the first conductive layer 130 and the upper surface 330a of the second conductive layer 330 are also exposed after the insulating layer 640 is etched. In an embodiment, the etched insulating layer 640 has a surface 640a that is substantially coplanar with the upper surface 120c' and the upper surface 320c'. In an embodiment, the etch process has an appropriate etch selectivity to the insulating layer 640 (eg, metal oxide) and the memory material layer 125 (eg, the ONO structure), thereby etching the insulating layer 640 without etching the memory material layer 125. Moreover, the etching process has an appropriate etch selectivity to the insulating layer 640 (eg, metal oxide) and the first conductive layer 130 and the second conductive layer 330 (eg, polysilicon), thereby etching the insulating layer 640 without etching the first Conductive layer 130 and second conductive layer 330.

Referring to FIG. 8F, a barrier layer 650 is formed on the insulating layer 640 and the upper surface 120c' of the portion 120c of the first stacked structure 120. In an embodiment, the barrier layer 650 is further formed on the upper surface 320c' of the portion 320c of the second stacked structure 320, and the upper surface 120c' of the portion 120c of the insulating layer 640 and the first stacked structure 120 is formed. The above steps are carried out simultaneously. In the embodiment, the material of the barrier layer 650 includes a nitride such as tantalum nitride. However, in practical applications, the material of the barrier layer 650 is also appropriately selected depending on the application conditions, and is not limited to the foregoing materials.

Referring to FIG. 8G, the barrier layer 650 and the memory material layer 125 are etched to expose a portion of the upper surface 121a of the conductive structure 121. In an embodiment, the first conductive layer 130 and the second conductive layer 330 are adjacent to the sidewalls 120a of the first stacked structure 120 and the sidewalls 320a of the second stacked structure 320 and the insulating layer 640 have an abutting surface 640b, the abutting surface 640b has a height difference D from the upper surface 121a of the conductive structure 121. Height difference D The portion where the barrier layer 650 and the memory material layer 125 are etched is adjacent to the insulating layer 640 without abutting the first conductive layer 130 and the second conductive layer 330. Moreover, the etching process has an appropriate etch selectivity to the barrier layer 650 (eg, tantalum nitride) and the memory material layer 125 (eg, an ONO structure) and the insulating layer 640 (eg, a metal oxide), thereby etching the barrier layer 650 and the memory material. Layer 125 does not etch insulating layer 640.

Referring to FIG. 8H, a conductive member 440 is disposed on a portion of the upper surface 121a of the conductive structure 121. In the embodiment, since the height difference D causes the barrier layer 650 and the memory material layer 125 to be etched without etching the insulating layer 640, the conductive member 440 does not contact the first conductive layer 130 and the second conductive layer 330 without short circuit. phenomenon. Thus far, the semiconductor structure 400 as shown in FIG. 4 is formed.

The manufacturing process of the semiconductor structure 500 of Fig. 5 will be described below. The following description begins after the first stacked structure 120 and the second stacked structure 320 are formed. The same components in the manufacturing process of the semiconductor structure 400 are the same as those in the manufacturing process of the semiconductor structure 400, and the related components and the related manufacturing process are referred to the foregoing, and will not be described herein.

Referring to FIG. 5, a plurality of word structures WL-1 WL WL-N are formed on the substrate 110. In an embodiment, each of the word structures WL-1 WL WL-N has at least one stacked structure similar to the second stacked structure 320 and a plurality of strip-shaped conductive blocks forming the word structures WL-1 WL WL-N The steps of stacking the structure are performed simultaneously with the steps of forming the first stacked structure 120 and the second stacked structure 320, and the second strip-shaped conductive block 321 and the character structure The strip-shaped conductive blocks of WL-1 WL-N are connected such that the word structures WL-1 WL WL-N are arranged in parallel adjacent to the first stack structure 120 and the second stack structure 320.

In the embodiment, the insulating layer 640 is formed in the pitch structure 110c between the word structures WL-1 WL WL-N and the word structures WL-1 WL WL-N. In the embodiment, the step of forming the insulating layer 640 on the word structures WL-1 WL WL-N and the pitch 110c between the word structures WL-1 WL WL-N is to form the insulating layer 640 on the first conductive layer. The step of layer 130 and the exposed portion 120c of the first stacked structure 120, and the step of forming the insulating layer 640 on the second conductive layer 330 and the exposed portion 320c of the second stacked structure 320 are simultaneously performed.

In an embodiment, the insulating layer 640 is etched to expose the upper surface of the word structures WL-1 WL WL-N, and the step of etching the insulating layer 640 to expose the upper surface 120c ′ of the portion 120 c of the first stacked structure 120 and The step of etching the insulating layer 640 to expose the upper surface 320c' of the portion 320c of the second stacked structure 320 is performed simultaneously. In an embodiment, a portion of the insulating layer 640 is not etched away and is held in the pitch 110c between the word structures WL-1 WL WL-N to protect the word structures WL-1 WL WL -N and prevent short circuits. effect. So far, the semiconductor structure 500 as shown in FIG. 5 is formed.

The above embodiments are described in terms of a semiconductor structure and a method of manufacturing the same. In summary, the first conductive layer of the semiconductor structure proposed in the embodiment surrounds both sidewalls and a portion of the top of the first stacked structure to expose a portion of the first stacked structure, so that the conductive element is not easily generated with the first conductive layer. A short circuit occurs due to contact. Moreover, the semiconductor structure of the embodiment may be one or three The combination of the gate selection line and the source line of the vertical vertical and the gate flash memory array can save space occupied by components in the memory array. Furthermore, the semiconductor structure of the embodiment has the functions of a gate selection line, a source line, and a string selection line gate structure, which can reduce damage to components in the memory array due to high energy in the doping process. Moreover, the overall path length of the memory array is reduced, and the overall space and manufacturing cost of the memory array are also reduced.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400, 500‧‧‧ semiconductor structures

110‧‧‧Base

110c‧‧‧ spacing

120, 220‧‧‧ first stack structure

120a, 320a‧‧‧ side wall

120b, 320b‧‧‧part top

120c, 320c‧‧‧section

120c', 121a, 130a, 320c', 330a‧‧‧ upper surface

121, 221‧‧‧ conductive structure

123, 223‧‧‧ insulation structure

125‧‧‧ memory material layer

130‧‧‧First conductive layer

131‧‧‧First Main Body

133‧‧‧First Coverage

221a‧‧‧First strip of conductive block

223a‧‧‧First strip insulation block

320‧‧‧Second stacking structure

321a‧‧‧Second strip of conductive block

323a‧‧‧Second strip insulation block

330‧‧‧Second conductive layer

331‧‧‧Second Main Body

333‧‧‧Second Coverage

440‧‧‧Conductive components

502~505, 512~515‧‧‧ strip conductive blocks

502B~505B, 512A~515A‧‧‧ ladder structure

509, 519‧‧‧ string selection line gate structure

525-1~525-N‧‧‧ character line

526, 527‧‧ ‧ gate selection line

528‧‧‧Source line

630‧‧‧ Conductive material layer

640‧‧‧Insulation

640a‧‧‧ surface

640b‧‧‧ adjacency

650‧‧‧The barrier layer

D‧‧‧ height difference

ML1, ML2‧‧‧ string selection line

ML3‧‧‧ bit line

WL-1~WL-N‧‧‧ character structure

W1, W2, W3, W4, W5, W6, W7‧‧‧ width

1 is a schematic view of a semiconductor structure in accordance with a first embodiment of the present invention.

2 is a schematic view of a semiconductor structure in accordance with a second embodiment of the present invention.

3 is a schematic view showing a semiconductor structure in accordance with a third embodiment of the present invention.

4 is a schematic view showing a semiconductor structure in accordance with a fourth embodiment of the present invention.

Figure 5 is a schematic view showing a semiconductor structure in accordance with a fifth embodiment of the present invention.

FIG. 6 is a schematic diagram of a three-dimensional vertical anti-gate flash memory array.

7A to 7C are schematic views showing a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention.

8A to 8H are schematic views showing a method of fabricating a semiconductor structure in accordance with another embodiment of the present invention.

100‧‧‧Semiconductor structure

110‧‧‧Base

120‧‧‧First stack structure

120a‧‧‧ sidewall

120b‧‧‧Part top

Section 120c‧‧‧

121‧‧‧Electrical structure

123‧‧‧Insulation structure

125‧‧‧ memory material layer

130‧‧‧First conductive layer

131‧‧‧First Main Body

133‧‧‧First Coverage

W1, W2, W3‧‧‧ width

Claims (17)

A semiconductor structure comprising: a substrate; a first stacked structure formed on the substrate, wherein the first stacked structure comprises a conductive structure and an insulating structure, the conductive structure is disposed adjacent to the insulating structure; a conductive layer includes a first body portion formed on the substrate and a first cover portion disposed above the first body portion, wherein the first body portion correspondingly covers both sidewalls of the first stack structure The first cover portion is connected to the first body portion and correspondingly covers the top of the two side walls and a portion of the first stack structure, and the width of the first cover portion is smaller than the corresponding side walls. The width is to expose a portion of the first stacked structure. The semiconductor structure of claim 1, wherein the width of the first body portion is substantially equal to the width of each of the side walls. The semiconductor structure of claim 1, wherein the width of the first covering portion is substantially smaller than the width of the first body portion. The semiconductor structure of claim 1, wherein the conductive structure comprises a plurality of first strip-shaped conductive blocks, the insulating structure comprising a plurality of first strip-shaped insulating blocks, and the first strip-shaped conductive blocks and the The first strips of insulating blocks are staggered and stacked, and each of the first strips of electrically conductive blocks are separated by the first strips of insulating blocks. The semiconductor structure of claim 1, further comprising: a second stack structure formed on the substrate adjacent to the first stack The second stack structure includes a plurality of second strip-shaped conductive blocks and a plurality of second strip-shaped insulating blocks, and the second strip-shaped conductive blocks are alternately stacked with the second strip-shaped insulating blocks, and Each of the second strip-shaped conductive blocks is separated by the second strip-shaped insulating blocks; and a second conductive layer is formed on the substrate and surrounds both sidewalls and a portion of the top of the second stacked structure to A portion of the second stacked structure is exposed. The semiconductor structure of claim 1, further comprising: a conductive component disposed on the first stacked structure and electrically connected to the conductive structure. The semiconductor structure of claim 5, further comprising a plurality of word structures formed on the substrate, wherein each of the word structures comprises a plurality of strip-shaped conductive blocks, each of the strip-shaped conductive blocks being connected Corresponding to each of the second strip-shaped conductive blocks, the word structures are arranged in parallel adjacent to the first stack structure and the second stack structure. The semiconductor structure of claim 7, further comprising an insulating layer formed in a distance between each of the character structures, wherein the semiconductor structure is a gate of a three-dimensional vertical inverted gate flash memory array. Select a combination of lines and word lines. The semiconductor structure of claim 1, wherein the first stacked structure comprises a memory material layer formed on the substrate and covering the periphery of the conductive structure and the insulating structure. A method of fabricating a semiconductor structure, comprising: forming a first stacked structure on a substrate, including: Forming an insulating structure on the substrate; and providing a conductive structure adjacent to the insulating structure; forming a conductive material layer on the substrate; and etching the conductive material layer to form a first conductive layer, the first conductive layer a first body portion and a first cover portion disposed above the first body portion, the first body portion correspondingly covering the two sidewalls of the first stack structure, the first cover portion and the first cover portion a main body portion is connected to and covers a portion of the upper side of the first stacking structure and the width of the first covering portion is smaller than a width of each of the corresponding side walls to expose the first stacked structure Part of it. The method of fabricating a semiconductor structure according to claim 10, wherein the step of forming the insulating structure on the substrate comprises: forming an insulating layer on the substrate; and disposing the conductive structure adjacent to the insulating structure The step includes forming a conductive layer on the insulating layer. The method of fabricating a semiconductor structure according to claim 10, wherein the step of forming the insulating structure on the substrate comprises: forming a plurality of first strip-shaped insulating blocks on the substrate; and arranging the conductive structures adjacent thereto The step of the insulating structure includes: forming a plurality of first strip-shaped conductive blocks, the first strip-shaped conductive blocks and the first strip-shaped insulating blocks are alternately stacked, and each of the first strip-shaped conductive blocks Separated by the first strips of insulating blocks. The method for fabricating a semiconductor structure according to claim 10, further comprising: forming a second stacked structure on the substrate adjacent to the first stack The structural arrangement includes: forming a plurality of second strip-shaped insulating blocks on the substrate; and forming a plurality of second strip-shaped conductive blocks, wherein the second strip-shaped conductive blocks and the second strip-shaped insulating blocks are alternately stacked And each of the second strip-shaped conductive blocks is separated by the second strip-shaped insulating blocks; forming the conductive material layer on the substrate; and etching the conductive material layer to form a second conductive layer and exposing the A portion of the second stacked structure, wherein the second conductive layer surrounds both sidewalls and a portion of the top of the second stacked structure. The method of fabricating the semiconductor structure of claim 13, further comprising: forming a plurality of word structures on the substrate, wherein the step of forming the plurality of word structures comprises forming a plurality of strip-shaped conductive blocks thereon On the substrate, each of the strip-shaped conductive blocks is connected to the corresponding second strip-shaped conductive blocks, so that the word structures are arranged in parallel adjacent to the first stacked structure and the second stacked structure. The method for fabricating a semiconductor structure according to claim 10, further comprising: disposing a conductive element on the first stacked structure and electrically connecting the conductive structure. The method of fabricating a semiconductor structure according to claim 15, wherein the first stacked structure comprises a memory material layer formed on the substrate and covering the periphery of the conductive structure and the insulating structure, The step of disposing the conductive element on the first stack structure comprises: Forming an insulating layer on the first conductive layer and a portion exposed by the first stacked structure; etching the insulating layer to expose an upper surface of the portion of the first stacked structure; forming a resist layer on the insulating layer And an upper surface of the portion of the first stacked structure; etching the barrier layer and the memory material layer to expose a surface of a portion of the conductive structure; and disposing the conductive member on a surface of the portion of the conductive structure on. The method of fabricating a semiconductor structure according to claim 10, wherein the step of forming the first stacked structure on the substrate comprises: forming a memory material layer on the substrate, the memory material layer covering the conductive structure And the periphery of the insulating structure.