CN107293551B

CN107293551B - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN107293551B
Application number: CN201610216188.2A
Authority: CN
Inventors: 江昱维; 邱家荣
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2016-04-08
Filing date: 2016-04-08
Publication date: 2020-03-27
Anticipated expiration: 2036-04-08
Also published as: CN107293551A

Abstract

The invention discloses a semiconductor structure, which comprises a substrate, a plurality of first laminated structures and two second laminated structures. The first laminated structures are arranged on the substrate, and each first laminated structure comprises a plurality of metal layers and oxide layers which are alternately laminated. The second laminated structures are arranged on the substrate, and each second laminated structure comprises a plurality of silicon nitride layers and oxide layers which are alternately laminated. The first laminated structure is arranged between the two second laminated structures.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present invention relates to a semiconductor structure and a method for fabricating the same, and more particularly, to a semiconductor structure having a gate replacement (gate replacement) and a method for fabricating the same.

Background

Semiconductor structures are used in many products, such as MP3 players, digital cameras, computer files, and other storage devices. With the advancement of semiconductor manufacturing technology, the demand for semiconductor structures also tends to smaller size and larger storage capacity. In response to such a demand, it is required to manufacture a semiconductor structure with a high device density.

One approach designers have developed to increase the density of semiconductor structures by using three-dimensional stacked memory devices to achieve higher memory capacity while reducing the cost per bit. However, in three-dimensional stacked memory devices, especially oxide/polysilicon (OP) stacked memory devices, word line resistance (word line resistance) is a critical factor, since it affects the operating speed. Therefore, it is an important subject to manufacture a memory capable of effectively reducing the resistance of the word line.

Disclosure of Invention

The invention relates to a semiconductor structure with a gate replacement and a manufacturing method thereof. In some embodiments of the present invention, the metal layer of the semiconductor structure may reduce word line resistance and save word line metal routing (metal routing) of a Single Gate Vertical Channel (SGVC) device structure.

According to the present invention, a semiconductor structure is provided, which includes a substrate, a plurality of first stacked structures and two second stacked structures. The first laminated structures are arranged on the substrate, and each first laminated structure comprises a plurality of metal layers and oxide layers which are alternately laminated. The second laminated structures are arranged on the substrate, and each second laminated structure comprises a plurality of silicon nitride layers and oxide layers which are alternately laminated. The first laminated structure is arranged between the two second laminated structures.

According to the present invention, a method for fabricating a semiconductor structure is provided, which includes the following steps. A substrate is provided. A plurality of silicon nitride layers and oxide layers are alternately stacked. And etching the silicon nitride layer and the oxide layer to form a plurality of pre-laminated structures. A first charge trapping layer is formed on the pre-stack structure. A first channel layer is formed on the charge trapping layer. And etching part of the pre-laminated structure to form a plurality of through holes. The silicon nitride layer in the portion of the pre-stacked structure is replaced with a plurality of metal layers to form a plurality of first stacked structures. The other parts of the pre-laminated structure form two second laminated structures, and the first laminated structure is arranged between the two second structures.

In order to better understand the above and other aspects of the present invention, the following detailed description is made with reference to the accompanying drawings, in which:

drawings

Fig. 1A is a top view of a semiconductor structure 100 according to an embodiment of the invention.

FIG. 1B is a cross-sectional view of the semiconductor structure of FIG. 1A taken along line A-A'.

Fig. 2A-10 illustrate one embodiment of a semiconductor structure in accordance with one embodiment of the present invention.

[ notation ] to show

100: semiconductor structure

1: substrate

11: first laminated structure

12: second laminated structure

21: silicon nitride layer

22: metal layer

31: through hole

32. 33: space(s)

41. 42, 43: oxide layer

411: side surface of the oxide layer

44: insulating layer

60. 61, 62: charge trapping layer

601: a portion of the top surface of the charge trapping layer

80. 81, 82: channel layer

83: conductive plug

Detailed Description

The embodiments of the present invention are described in detail below with reference to the attached drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. It should be noted that the drawings are simplified to clearly illustrate the embodiments, and the dimensional ratios on the drawings are not drawn to scale according to actual products, so that the invention is not limited to the scope of the invention.

Fig. 1A is a top view of a semiconductor structure 100 according to an embodiment of the invention. FIG. 1B illustrates a cross-sectional view of the semiconductor structure 100 of FIG. 1A taken along line A-A'. It is noted that, in order to more clearly illustrate the semiconductor structure 100 according to the embodiment of the present invention, some elements may be omitted in the drawings.

In the embodiment of the invention, the semiconductor structure 100 may include a substrate 1, a plurality of first stacked structures 11 and two second stacked structures 12. The first stacked structure 11 and the second stacked structure 12 are disposed on the substrate 1. As shown in fig. 1B, each first stacked structure 11 may include a metal layer 22 and an oxide layer 41 stacked alternately, and each second stacked structure 12 may include a silicon nitride layer 21 and an oxide layer 41 stacked alternately.

In the present embodiment, the first stacked structure 11 is disposed between two second stacked structures 12. In addition, the number of the first stacked structures may be 2N, where N is a positive integer. Here, the metal layer may include tungsten (W).

As shown in fig. 1B, the semiconductor structure 100 may further include a charge trapping layer 60 and a channel layer 80, wherein the charge trapping layer 60 is disposed on the first stacked structure 11, and the channel layer 80 is disposed on the charge trapping layer 60. In one embodiment, the charge trapping layer 60 may be an oxide-nitride-oxide (ONO) structure, an oxide-nitride-oxide (ONONO) structure, or an oxide-nitride-oxide (ONONONO) structure, and the channel layer 80 may comprise polysilicon.

As shown in FIG. 1B, the charge trapping layer 60 can include a protrusion 611, and the protrusion 611 makes the top surface of the charge trapping layer 60 uneven (non-planar).

In addition, the semiconductor structure 100 may also include a plurality of conductive plugs (conductive plugs) 83 and the insulating layer 44. The conductive plug 83 is electrically connected to the channel layer 80. The insulating layer 44 may be disposed between the first stacked structures 11. In the present embodiment, the insulating layer 44 may also be disposed between the first stacked structure 11 and the second stacked structure 12.

Here, the insulating layer 44 may include oxide. In one embodiment, a portion of the insulating layer 44 and a portion of the top surface 601 of the charge trapping layer 60, each of which is located between the conductive plugs 83, may be exposed. That is, the spaces 33 may be formed between the conductive plugs 83 such that a portion of the insulating layer 44 and a portion of the top surface 601 of the charge trapping layer 60, each of which is located between the conductive plugs 83, are exposed.

Fig. 2A-10 illustrate one embodiment of a fabrication of a semiconductor structure 100 in accordance with one embodiment of the present invention. First, a substrate 1 is provided. Then, a plurality of silicon nitride layers 21 and oxide layers 41 are alternately stacked on the substrate 1. In the present embodiment, the silicon nitride layer 21 and the oxide layer 41 may be etched to form a plurality of pre-stacked structures 10.

That is, each pre-stack structure 10 may include alternating layers of silicon nitride 21 and oxide 41 as shown in fig. 2A and 2B. Fig. 2A illustrates a cross-sectional view of the semiconductor structure at this stage, and fig. 2B illustrates a perspective view of the semiconductor structure at this stage.

As shown in FIG. 3, a first charge trapping layer 61 is formed on the pre-stack structure 10, and then a first channel layer 81 is formed on the first charge trapping layer 61. In the present embodiment, the first charge trapping layer 61 may be an oxide-nitride-oxide (ONO) structure, an oxide-nitride-oxide (ONONO) structure, or an oxide-nitride-oxide (ONONONO) structure, and the first channel layer 81 may include polysilicon. However, the present invention is not limited thereto.

As shown in fig. 4, an oxide layer 42 is formed on the first channel layer 81. In the present embodiment, the remaining space between the pre-stacked structures 10 may be filled with the oxide layer 42.

As shown in fig. 5, a portion of the pre-stacked structure 10 is etched to form a plurality of through holes 31. Here, the through hole 31 may expose a portion of the top surface of the substrate 1.

As shown in fig. 6, the silicon nitride layer 21 in the etched portion of the pre-stacked structure 10 is removed to form a plurality of spaces 32 between the oxide layers 41 in the etched portion of the pre-stacked structure 10. In one embodiment, the silicon nitride layer 21 may be removed by hot phosphoric acid (H3 PO 4).

As shown in fig. 7, a plurality of metal layers 22 are formed in the plurality of spaces 32 and on the oxide layer 42. In this embodiment, the metal layer 22 may comprise tungsten (W). Next, a portion of the metal layer 22 is removed (etched) to expose the side surface 411 of the oxide layer 41 in the etched portion of the pre-stacked structure 10. That is, as shown in fig. 8, the silicon nitride layer 21 in the etched part of the pre-stacked structure 10 may be replaced by a plurality of metal layers 22 to form a plurality of first stacked structures 11, and the other part of the pre-stacked structure 10 that is not etched may form two second stacked structures 12.

As shown in FIG. 9, a second charge-trapping layer 62 is formed in the via 31 and on the oxide layer 42, and a second channel layer 82 is formed on the second charge-trapping layer 62. Next, an oxide layer 43 is formed on the second channel layer 82. Here, the oxide layer 43 may fill the via hole 31 as shown in fig. 9.

Similarly, the second charge trapping layer 62 may be an oxide-nitride-oxide (ONO) structure, an oxide-nitride-oxide (ONONO) structure, or an oxide-nitride-oxide (ONONONO) structure, while the second channel layer 82 may comprise polysilicon. However, the present invention is not limited thereto.

As shown in fig. 10, a portion of the oxide layer 43, a portion of the second charge-trapping layer 62, a portion of the second channel layer 82, and a portion of the oxide layer 42 may be removed, leaving a top surface 810 of the first channel layer 81 exposed. In some embodiments, a portion of the oxide layer 43, a portion of the second charge trapping layer 62, a portion of the second channel layer 82, and a portion of the oxide layer 42 may be removed by a chemical-mechanical planarization (CMP) process or a dry etching (dry etching) process.

In this embodiment, the top surface of the remaining oxide layer may be lower than the top surface 810 of the first channel layer 81. However, the present invention is not limited thereto.

Next, a plurality of conductive plugs 83 are formed on the first stacked structure 11, so as to form the semiconductor structure 100 shown in fig. 1B. Here, the conductive plug 83 is electrically connected to the first channel layer 81 and the second channel layer 82.

In one embodiment, the method of forming the conductive plug 83 may include the following steps. First, a polysilicon layer is deposited on the first stacked structure 11. Next, the polysilicon layer is etched to expose a portion of the first charge trapping layer 61.

It is noted that the first charge trapping layer 61 and the second charge trapping layer 62 in FIG. 10 can be regarded as the charge trapping layer 60 in FIG. 1B; the first channel layer 81 and the second channel layer 82 in fig. 10 can be regarded as the channel layer 80 in fig. 1B; the remaining oxide layer in fig. 10 can be considered as the insulating layer 44 in fig. 1B.

That is, the insulating layer 44 may be formed between the first stacked structures 11, and a portion of the insulating layer 44 between the conductive plugs 83 may be exposed.

According to the embodiments of the present invention, the metal layer is formed through the gate replacement step in the semiconductor structure manufacturing process, which can effectively reduce the word line resistance, so that the Programming Logic Array (PLA) pads only need to be formed on the right and left sides of the whole block of the semiconductor structure 100, thereby saving the word line metal wiring (routing) of the Single Gate Vertical Channel (SGVC) device structure.

In summary, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate;

a plurality of first laminated structures arranged on the substrate, wherein each first laminated structure comprises a plurality of metal layers and oxide layers which are alternately laminated;

two second laminated structures arranged on the substrate, wherein each second laminated structure comprises a plurality of silicon nitride layers and oxide layers which are alternately laminated;

a charge trapping layer including a first charge trapping layer and a second charge trapping layer, the second charge trapping layer being disposed on the plurality of first stacked structures, and portions of the first charge trapping layer being disposed on the two second stacked structures; and

a channel layer disposed on the first and second charge trapping layers;

wherein the first laminated structures are arranged between the two second laminated structures.

2. The semiconductor structure of claim 1 wherein the charge trapping layer has a protrusion such that an upper surface of the charge trapping layer is not planar.

3. The semiconductor structure of claim 1, further comprising:

and a plurality of conductive plugs electrically connected to the channel layer.

4. The semiconductor structure of claim 3, further comprising:

an insulating layer disposed between the first stacked structures;

wherein a portion of the insulating layer between the conductive plugs is exposed.

5. A method of fabricating a semiconductor structure, comprising:

providing a substrate;

alternately laminating a plurality of silicon nitride layers and oxide layers;

etching the silicon nitride layers and the oxide layers to form a plurality of pre-laminated structures;

forming a first charge trapping layer on the pre-stacked structures;

forming a first channel layer on the first charge trapping layer;

etching the parts of the pre-laminated structures to form a plurality of through holes;

replacing the silicon nitride layer in the portion of the pre-stack structures with a plurality of metal layers to form a plurality of first stack structures;

forming a second charge trapping layer in the through holes; and

forming a second channel layer on the second charge-trapping layer;

the other parts of the pre-laminated structures form two second laminated structures, the first laminated structures are arranged between the two second structures, the second charge trapping layer is arranged on the plurality of first laminated structures, and part of the first charge trapping layer is arranged on the two second laminated structures.

6. The method of manufacturing of claim 5, further comprising:

and forming a plurality of conductive plugs, wherein the conductive plugs are electrically connected with the first channel layer and the second channel layer.

7. The manufacturing method according to claim 6, wherein the step of forming the conductive plugs comprises:

depositing a polysilicon layer on the first stacked structure; and

the polysilicon layer is etched to expose portions of the first charge trapping layer.

8. The manufacturing method according to claim 5, wherein the silicon nitride layer in the portion of the pre-stacked structures is substituted for the metal layers by phosphoric acid.